Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/c1_Defs_x86.hpp @ 19749:095ddb9421d0
Merge.
author | Thomas Wuerthinger <thomas.wuerthinger@oracle.com> |
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date | Tue, 10 Mar 2015 11:33:30 +0100 |
parents | ac637b7220d1 |
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rev | line source |
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0 | 1 /* |
1972 | 2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_X86_VM_C1_DEFS_X86_HPP |
26 #define CPU_X86_VM_C1_DEFS_X86_HPP | |
27 | |
0 | 28 // native word offsets from memory address (little endian) |
29 enum { | |
30 pd_lo_word_offset_in_bytes = 0, | |
31 pd_hi_word_offset_in_bytes = BytesPerWord | |
32 }; | |
33 | |
34 // explicit rounding operations are required to implement the strictFP mode | |
35 enum { | |
36 pd_strict_fp_requires_explicit_rounding = true | |
37 }; | |
38 | |
39 | |
40 // registers | |
41 enum { | |
304 | 42 pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission |
43 pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission | |
44 pd_nof_xmm_regs_frame_map = XMMRegisterImpl::number_of_registers, // number of registers used during code emission | |
0 | 45 |
304 | 46 #ifdef _LP64 |
47 #define UNALLOCATED 4 // rsp, rbp, r15, r10 | |
48 #else | |
49 #define UNALLOCATED 2 // rsp, rbp | |
50 #endif // LP64 | |
51 | |
52 pd_nof_caller_save_cpu_regs_frame_map = pd_nof_cpu_regs_frame_map - UNALLOCATED, // number of registers killed by calls | |
53 pd_nof_caller_save_fpu_regs_frame_map = pd_nof_fpu_regs_frame_map, // number of registers killed by calls | |
54 pd_nof_caller_save_xmm_regs_frame_map = pd_nof_xmm_regs_frame_map, // number of registers killed by calls | |
55 | |
56 pd_nof_cpu_regs_reg_alloc = pd_nof_caller_save_cpu_regs_frame_map, // number of registers that are visible to register allocator | |
0 | 57 pd_nof_fpu_regs_reg_alloc = 6, // number of registers that are visible to register allocator |
58 | |
304 | 59 pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan |
60 pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan | |
61 pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan | |
0 | 62 pd_first_cpu_reg = 0, |
304 | 63 pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11), |
2002 | 64 pd_first_byte_reg = NOT_LP64(2) LP64_ONLY(0), |
65 pd_last_byte_reg = NOT_LP64(5) LP64_ONLY(11), | |
0 | 66 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map, |
67 pd_last_fpu_reg = pd_first_fpu_reg + 7, | |
68 pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map, | |
304 | 69 pd_last_xmm_reg = pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1 |
0 | 70 }; |
71 | |
72 | |
73 // encoding of float value in debug info: | |
74 enum { | |
75 pd_float_saved_as_double = true | |
76 }; | |
1972 | 77 |
78 #endif // CPU_X86_VM_C1_DEFS_X86_HPP |