Mercurial > hg > graal-compiler
annotate src/os_cpu/linux_ppc/vm/atomic_linux_ppc.inline.hpp @ 18245:137f4cf8204a
Fix AMD64AllocatorTest junit assumption.
author | Josef Eisl <josef.eisl@jku.at> |
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date | Tue, 04 Nov 2014 16:51:08 +0100 |
parents | 63c5920a038d |
children | ce8f6bb717c9 |
rev | line source |
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1 /* |
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
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3 * Copyright 2012, 2013 SAP AG. All rights reserved. |
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4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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5 * |
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6 * This code is free software; you can redistribute it and/or modify it |
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7 * under the terms of the GNU General Public License version 2 only, as |
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8 * published by the Free Software Foundation. |
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9 * |
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10 * This code is distributed in the hope that it will be useful, but WITHOUT |
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11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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13 * version 2 for more details (a copy is included in the LICENSE file that |
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14 * accompanied this code). |
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15 * |
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16 * You should have received a copy of the GNU General Public License version |
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17 * 2 along with this work; if not, write to the Free Software Foundation, |
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18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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19 * |
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20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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21 * or visit www.oracle.com if you need additional information or have any |
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22 * questions. |
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23 * |
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24 */ |
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25 |
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26 #ifndef OS_CPU_LINUX_PPC_VM_ATOMIC_LINUX_PPC_INLINE_HPP |
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27 #define OS_CPU_LINUX_PPC_VM_ATOMIC_LINUX_PPC_INLINE_HPP |
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28 |
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29 #include "orderAccess_linux_ppc.inline.hpp" |
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30 #include "runtime/atomic.hpp" |
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31 #include "runtime/os.hpp" |
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32 #include "vm_version_ppc.hpp" |
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33 |
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34 #ifndef PPC64 |
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35 #error "Atomic currently only implemented for PPC64" |
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36 #endif |
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37 |
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38 // Implementation of class atomic |
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39 |
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40 inline void Atomic::store (jbyte store_value, jbyte* dest) { *dest = store_value; } |
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41 inline void Atomic::store (jshort store_value, jshort* dest) { *dest = store_value; } |
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42 inline void Atomic::store (jint store_value, jint* dest) { *dest = store_value; } |
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43 inline void Atomic::store (jlong store_value, jlong* dest) { *dest = store_value; } |
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44 inline void Atomic::store_ptr(intptr_t store_value, intptr_t* dest) { *dest = store_value; } |
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45 inline void Atomic::store_ptr(void* store_value, void* dest) { *(void**)dest = store_value; } |
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46 |
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47 inline void Atomic::store (jbyte store_value, volatile jbyte* dest) { *dest = store_value; } |
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48 inline void Atomic::store (jshort store_value, volatile jshort* dest) { *dest = store_value; } |
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49 inline void Atomic::store (jint store_value, volatile jint* dest) { *dest = store_value; } |
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50 inline void Atomic::store (jlong store_value, volatile jlong* dest) { *dest = store_value; } |
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51 inline void Atomic::store_ptr(intptr_t store_value, volatile intptr_t* dest) { *dest = store_value; } |
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52 inline void Atomic::store_ptr(void* store_value, volatile void* dest) { *(void* volatile *)dest = store_value; } |
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53 |
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54 inline jlong Atomic::load(volatile jlong* src) { return *src; } |
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55 |
17917 | 56 // |
57 // machine barrier instructions: | |
58 // | |
59 // - sync two-way memory barrier, aka fence | |
60 // - lwsync orders Store|Store, | |
61 // Load|Store, | |
62 // Load|Load, | |
63 // but not Store|Load | |
64 // - eieio orders memory accesses for device memory (only) | |
65 // - isync invalidates speculatively executed instructions | |
66 // From the POWER ISA 2.06 documentation: | |
67 // "[...] an isync instruction prevents the execution of | |
68 // instructions following the isync until instructions | |
69 // preceding the isync have completed, [...]" | |
70 // From IBM's AIX assembler reference: | |
71 // "The isync [...] instructions causes the processor to | |
72 // refetch any instructions that might have been fetched | |
73 // prior to the isync instruction. The instruction isync | |
74 // causes the processor to wait for all previous instructions | |
75 // to complete. Then any instructions already fetched are | |
76 // discarded and instruction processing continues in the | |
77 // environment established by the previous instructions." | |
78 // | |
79 // semantic barrier instructions: | |
80 // (as defined in orderAccess.hpp) | |
81 // | |
82 // - release orders Store|Store, (maps to lwsync) | |
83 // Load|Store | |
84 // - acquire orders Load|Store, (maps to lwsync) | |
85 // Load|Load | |
86 // - fence orders Store|Store, (maps to sync) | |
87 // Load|Store, | |
88 // Load|Load, | |
89 // Store|Load | |
90 // | |
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91 |
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92 #define strasm_sync "\n sync \n" |
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93 #define strasm_lwsync "\n lwsync \n" |
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94 #define strasm_isync "\n isync \n" |
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95 #define strasm_release strasm_lwsync |
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96 #define strasm_acquire strasm_lwsync |
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97 #define strasm_fence strasm_sync |
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98 #define strasm_nobarrier "" |
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99 #define strasm_nobarrier_clobber_memory "" |
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100 |
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101 inline jint Atomic::add (jint add_value, volatile jint* dest) { |
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102 |
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103 unsigned int result; |
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104 |
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105 __asm__ __volatile__ ( |
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106 strasm_lwsync |
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107 "1: lwarx %0, 0, %2 \n" |
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108 " add %0, %0, %1 \n" |
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109 " stwcx. %0, 0, %2 \n" |
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110 " bne- 1b \n" |
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111 strasm_isync |
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112 : /*%0*/"=&r" (result) |
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113 : /*%1*/"r" (add_value), /*%2*/"r" (dest) |
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114 : "cc", "memory" ); |
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115 |
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116 return (jint) result; |
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117 } |
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118 |
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119 |
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120 inline intptr_t Atomic::add_ptr(intptr_t add_value, volatile intptr_t* dest) { |
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121 |
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122 long result; |
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123 |
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124 __asm__ __volatile__ ( |
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125 strasm_lwsync |
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126 "1: ldarx %0, 0, %2 \n" |
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127 " add %0, %0, %1 \n" |
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128 " stdcx. %0, 0, %2 \n" |
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129 " bne- 1b \n" |
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130 strasm_isync |
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131 : /*%0*/"=&r" (result) |
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132 : /*%1*/"r" (add_value), /*%2*/"r" (dest) |
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133 : "cc", "memory" ); |
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134 |
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135 return (intptr_t) result; |
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136 } |
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137 |
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138 inline void* Atomic::add_ptr(intptr_t add_value, volatile void* dest) { |
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139 return (void*)add_ptr(add_value, (volatile intptr_t*)dest); |
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140 } |
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141 |
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142 |
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143 inline void Atomic::inc (volatile jint* dest) { |
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144 |
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145 unsigned int temp; |
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146 |
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147 __asm__ __volatile__ ( |
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148 strasm_nobarrier |
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149 "1: lwarx %0, 0, %2 \n" |
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150 " addic %0, %0, 1 \n" |
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151 " stwcx. %0, 0, %2 \n" |
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152 " bne- 1b \n" |
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153 strasm_nobarrier |
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154 : /*%0*/"=&r" (temp), "=m" (*dest) |
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155 : /*%2*/"r" (dest), "m" (*dest) |
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156 : "cc" strasm_nobarrier_clobber_memory); |
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157 |
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158 } |
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159 |
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160 inline void Atomic::inc_ptr(volatile intptr_t* dest) { |
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161 |
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162 long temp; |
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163 |
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164 __asm__ __volatile__ ( |
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165 strasm_nobarrier |
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166 "1: ldarx %0, 0, %2 \n" |
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167 " addic %0, %0, 1 \n" |
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168 " stdcx. %0, 0, %2 \n" |
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169 " bne- 1b \n" |
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170 strasm_nobarrier |
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171 : /*%0*/"=&r" (temp), "=m" (*dest) |
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172 : /*%2*/"r" (dest), "m" (*dest) |
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173 : "cc" strasm_nobarrier_clobber_memory); |
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174 |
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175 } |
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176 |
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177 inline void Atomic::inc_ptr(volatile void* dest) { |
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178 inc_ptr((volatile intptr_t*)dest); |
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179 } |
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180 |
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181 |
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182 inline void Atomic::dec (volatile jint* dest) { |
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183 |
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184 unsigned int temp; |
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185 |
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186 __asm__ __volatile__ ( |
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187 strasm_nobarrier |
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188 "1: lwarx %0, 0, %2 \n" |
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189 " addic %0, %0, -1 \n" |
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190 " stwcx. %0, 0, %2 \n" |
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191 " bne- 1b \n" |
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192 strasm_nobarrier |
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193 : /*%0*/"=&r" (temp), "=m" (*dest) |
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194 : /*%2*/"r" (dest), "m" (*dest) |
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195 : "cc" strasm_nobarrier_clobber_memory); |
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196 |
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197 } |
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198 |
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199 inline void Atomic::dec_ptr(volatile intptr_t* dest) { |
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200 |
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201 long temp; |
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202 |
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203 __asm__ __volatile__ ( |
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204 strasm_nobarrier |
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205 "1: ldarx %0, 0, %2 \n" |
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206 " addic %0, %0, -1 \n" |
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207 " stdcx. %0, 0, %2 \n" |
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208 " bne- 1b \n" |
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209 strasm_nobarrier |
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210 : /*%0*/"=&r" (temp), "=m" (*dest) |
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211 : /*%2*/"r" (dest), "m" (*dest) |
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212 : "cc" strasm_nobarrier_clobber_memory); |
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213 |
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214 } |
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215 |
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216 inline void Atomic::dec_ptr(volatile void* dest) { |
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217 dec_ptr((volatile intptr_t*)dest); |
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218 } |
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219 |
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220 inline jint Atomic::xchg(jint exchange_value, volatile jint* dest) { |
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221 |
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222 // Note that xchg_ptr doesn't necessarily do an acquire |
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223 // (see synchronizer.cpp). |
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224 |
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225 unsigned int old_value; |
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226 const uint64_t zero = 0; |
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227 |
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228 __asm__ __volatile__ ( |
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229 /* lwsync */ |
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230 strasm_lwsync |
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231 /* atomic loop */ |
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232 "1: \n" |
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233 " lwarx %[old_value], %[dest], %[zero] \n" |
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234 " stwcx. %[exchange_value], %[dest], %[zero] \n" |
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235 " bne- 1b \n" |
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236 /* isync */ |
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237 strasm_sync |
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238 /* exit */ |
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239 "2: \n" |
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240 /* out */ |
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241 : [old_value] "=&r" (old_value), |
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242 "=m" (*dest) |
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243 /* in */ |
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244 : [dest] "b" (dest), |
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245 [zero] "r" (zero), |
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246 [exchange_value] "r" (exchange_value), |
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247 "m" (*dest) |
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248 /* clobber */ |
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249 : "cc", |
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250 "memory" |
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|
251 ); |
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252 |
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253 return (jint) old_value; |
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254 } |
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255 |
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256 inline intptr_t Atomic::xchg_ptr(intptr_t exchange_value, volatile intptr_t* dest) { |
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257 |
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258 // Note that xchg_ptr doesn't necessarily do an acquire |
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259 // (see synchronizer.cpp). |
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260 |
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261 long old_value; |
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262 const uint64_t zero = 0; |
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|
263 |
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264 __asm__ __volatile__ ( |
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265 /* lwsync */ |
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266 strasm_lwsync |
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267 /* atomic loop */ |
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268 "1: \n" |
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269 " ldarx %[old_value], %[dest], %[zero] \n" |
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270 " stdcx. %[exchange_value], %[dest], %[zero] \n" |
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271 " bne- 1b \n" |
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272 /* isync */ |
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273 strasm_sync |
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274 /* exit */ |
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|
275 "2: \n" |
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276 /* out */ |
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277 : [old_value] "=&r" (old_value), |
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278 "=m" (*dest) |
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279 /* in */ |
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280 : [dest] "b" (dest), |
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281 [zero] "r" (zero), |
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282 [exchange_value] "r" (exchange_value), |
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|
283 "m" (*dest) |
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|
284 /* clobber */ |
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285 : "cc", |
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286 "memory" |
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|
287 ); |
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|
288 |
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289 return (intptr_t) old_value; |
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290 } |
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|
291 |
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292 inline void* Atomic::xchg_ptr(void* exchange_value, volatile void* dest) { |
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293 return (void*)xchg_ptr((intptr_t)exchange_value, (volatile intptr_t*)dest); |
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294 } |
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295 |
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296 inline jint Atomic::cmpxchg(jint exchange_value, volatile jint* dest, jint compare_value) { |
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297 |
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298 // Note that cmpxchg guarantees a two-way memory barrier across |
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299 // the cmpxchg, so it's really a a 'fence_cmpxchg_acquire' |
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300 // (see atomic.hpp). |
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301 |
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302 unsigned int old_value; |
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303 const uint64_t zero = 0; |
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304 |
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305 __asm__ __volatile__ ( |
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306 /* fence */ |
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307 strasm_sync |
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308 /* simple guard */ |
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309 " lwz %[old_value], 0(%[dest]) \n" |
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310 " cmpw %[compare_value], %[old_value] \n" |
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311 " bne- 2f \n" |
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312 /* atomic loop */ |
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313 "1: \n" |
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314 " lwarx %[old_value], %[dest], %[zero] \n" |
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315 " cmpw %[compare_value], %[old_value] \n" |
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316 " bne- 2f \n" |
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317 " stwcx. %[exchange_value], %[dest], %[zero] \n" |
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318 " bne- 1b \n" |
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319 /* acquire */ |
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320 strasm_sync |
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321 /* exit */ |
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322 "2: \n" |
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323 /* out */ |
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324 : [old_value] "=&r" (old_value), |
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325 "=m" (*dest) |
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326 /* in */ |
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327 : [dest] "b" (dest), |
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328 [zero] "r" (zero), |
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329 [compare_value] "r" (compare_value), |
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330 [exchange_value] "r" (exchange_value), |
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331 "m" (*dest) |
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332 /* clobber */ |
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333 : "cc", |
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334 "memory" |
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335 ); |
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336 |
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337 return (jint) old_value; |
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338 } |
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339 |
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340 inline jlong Atomic::cmpxchg(jlong exchange_value, volatile jlong* dest, jlong compare_value) { |
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341 |
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342 // Note that cmpxchg guarantees a two-way memory barrier across |
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343 // the cmpxchg, so it's really a a 'fence_cmpxchg_acquire' |
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344 // (see atomic.hpp). |
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345 |
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346 long old_value; |
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347 const uint64_t zero = 0; |
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348 |
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349 __asm__ __volatile__ ( |
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350 /* fence */ |
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351 strasm_sync |
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352 /* simple guard */ |
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353 " ld %[old_value], 0(%[dest]) \n" |
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354 " cmpd %[compare_value], %[old_value] \n" |
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355 " bne- 2f \n" |
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356 /* atomic loop */ |
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357 "1: \n" |
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358 " ldarx %[old_value], %[dest], %[zero] \n" |
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359 " cmpd %[compare_value], %[old_value] \n" |
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360 " bne- 2f \n" |
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361 " stdcx. %[exchange_value], %[dest], %[zero] \n" |
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362 " bne- 1b \n" |
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363 /* acquire */ |
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364 strasm_sync |
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365 /* exit */ |
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366 "2: \n" |
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367 /* out */ |
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368 : [old_value] "=&r" (old_value), |
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369 "=m" (*dest) |
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370 /* in */ |
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371 : [dest] "b" (dest), |
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372 [zero] "r" (zero), |
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373 [compare_value] "r" (compare_value), |
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374 [exchange_value] "r" (exchange_value), |
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375 "m" (*dest) |
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376 /* clobber */ |
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377 : "cc", |
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378 "memory" |
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379 ); |
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380 |
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381 return (jlong) old_value; |
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382 } |
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383 |
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384 inline intptr_t Atomic::cmpxchg_ptr(intptr_t exchange_value, volatile intptr_t* dest, intptr_t compare_value) { |
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385 return (intptr_t)cmpxchg((jlong)exchange_value, (volatile jlong*)dest, (jlong)compare_value); |
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386 } |
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387 |
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388 inline void* Atomic::cmpxchg_ptr(void* exchange_value, volatile void* dest, void* compare_value) { |
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389 return (void*)cmpxchg((jlong)exchange_value, (volatile jlong*)dest, (jlong)compare_value); |
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390 } |
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391 |
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392 #undef strasm_sync |
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393 #undef strasm_lwsync |
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394 #undef strasm_isync |
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395 #undef strasm_release |
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396 #undef strasm_acquire |
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397 #undef strasm_fence |
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398 #undef strasm_nobarrier |
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399 #undef strasm_nobarrier_clobber_memory |
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400 |
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401 #endif // OS_CPU_LINUX_PPC_VM_ATOMIC_LINUX_PPC_INLINE_HPP |