Mercurial > hg > graal-compiler
annotate src/share/vm/c1/c1_LIRAssembler.hpp @ 1476:1f81c0d18c75
Build also release version of VM. Fix towards making SpecJVM2008 run.
author | Thomas Wuerthinger <wuerthinger@ssw.jku.at> |
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date | Fri, 26 Nov 2010 12:12:35 +0100 |
parents | 9f5b60a14736 |
children | c18cbe5936b8 61b2245abf36 |
rev | line source |
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0 | 1 /* |
1204 | 2 * Copyright 2000-2010 Sun Microsystems, Inc. All Rights Reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
21 * have any questions. | |
22 * | |
23 */ | |
24 | |
25 class Compilation; | |
26 class ScopeValue; | |
342 | 27 class BarrierSet; |
0 | 28 |
29 class LIR_Assembler: public CompilationResourceObj { | |
30 private: | |
31 C1_MacroAssembler* _masm; | |
32 CodeStubList* _slow_case_stubs; | |
342 | 33 BarrierSet* _bs; |
0 | 34 |
35 Compilation* _compilation; | |
36 FrameMap* _frame_map; | |
37 BlockBegin* _current_block; | |
38 | |
39 Instruction* _pending_non_safepoint; | |
40 int _pending_non_safepoint_offset; | |
41 | |
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42 Label _unwind_handler_entry; |
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43 |
0 | 44 #ifdef ASSERT |
45 BlockList _branch_target_blocks; | |
46 void check_no_unbound_labels(); | |
47 #endif | |
48 | |
49 FrameMap* frame_map() const { return _frame_map; } | |
50 | |
51 void set_current_block(BlockBegin* b) { _current_block = b; } | |
52 BlockBegin* current_block() const { return _current_block; } | |
53 | |
54 // non-safepoint debug info management | |
55 void flush_debug_info(int before_pc_offset) { | |
56 if (_pending_non_safepoint != NULL) { | |
57 if (_pending_non_safepoint_offset < before_pc_offset) | |
58 record_non_safepoint_debug_info(); | |
59 _pending_non_safepoint = NULL; | |
60 } | |
61 } | |
62 void process_debug_info(LIR_Op* op); | |
63 void record_non_safepoint_debug_info(); | |
64 | |
65 // unified bailout support | |
66 void bailout(const char* msg) const { compilation()->bailout(msg); } | |
67 bool bailed_out() const { return compilation()->bailed_out(); } | |
68 | |
69 // code emission patterns and accessors | |
70 void check_codespace(); | |
71 bool needs_icache(ciMethod* method) const; | |
72 | |
73 // returns offset of icache check | |
74 int check_icache(); | |
75 | |
76 void jobject2reg(jobject o, Register reg); | |
77 void jobject2reg_with_patching(Register reg, CodeEmitInfo* info); | |
78 | |
79 void emit_stubs(CodeStubList* stub_list); | |
80 | |
81 // addresses | |
304 | 82 Address as_Address(LIR_Address* addr); |
83 Address as_Address_lo(LIR_Address* addr); | |
84 Address as_Address_hi(LIR_Address* addr); | |
0 | 85 |
86 // debug information | |
1295 | 87 void add_call_info(int pc_offset, CodeEmitInfo* cinfo, bool is_method_handle_invoke = false); |
0 | 88 void add_debug_info_for_branch(CodeEmitInfo* info); |
89 void add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo); | |
90 void add_debug_info_for_div0_here(CodeEmitInfo* info); | |
91 void add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo); | |
92 void add_debug_info_for_null_check_here(CodeEmitInfo* info); | |
93 | |
94 void set_24bit_FPU(); | |
95 void reset_FPU(); | |
96 void fpop(); | |
97 void fxch(int i); | |
98 void fld(int i); | |
99 void ffree(int i); | |
100 | |
101 void breakpoint(); | |
102 void push(LIR_Opr opr); | |
103 void pop(LIR_Opr opr); | |
104 | |
105 // patching | |
106 void append_patching_stub(PatchingStub* stub); | |
107 void patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info); | |
108 | |
109 void comp_op(LIR_Condition condition, LIR_Opr src, LIR_Opr result, LIR_Op2* op); | |
110 | |
111 public: | |
112 LIR_Assembler(Compilation* c); | |
113 ~LIR_Assembler(); | |
114 C1_MacroAssembler* masm() const { return _masm; } | |
115 Compilation* compilation() const { return _compilation; } | |
116 ciMethod* method() const { return compilation()->method(); } | |
117 | |
118 CodeOffsets* offsets() const { return _compilation->offsets(); } | |
119 int code_offset() const; | |
120 address pc() const; | |
121 | |
122 int initial_frame_size_in_bytes(); | |
123 | |
124 // test for constants which can be encoded directly in instructions | |
125 static bool is_small_constant(LIR_Opr opr); | |
126 | |
127 static LIR_Opr receiverOpr(); | |
128 static LIR_Opr incomingReceiverOpr(); | |
129 static LIR_Opr osrBufferPointer(); | |
130 | |
131 // stubs | |
132 void emit_slow_case_stubs(); | |
133 void emit_static_call_stub(); | |
134 void emit_code_stub(CodeStub* op); | |
135 void add_call_info_here(CodeEmitInfo* info) { add_call_info(code_offset(), info); } | |
136 | |
137 // code patterns | |
1204 | 138 int emit_exception_handler(); |
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139 int emit_unwind_handler(); |
0 | 140 void emit_exception_entries(ExceptionInfoList* info_list); |
1204 | 141 int emit_deopt_handler(); |
0 | 142 |
143 void emit_code(BlockList* hir); | |
144 void emit_block(BlockBegin* block); | |
145 void emit_lir_list(LIR_List* list); | |
146 | |
147 // any last minute peephole optimizations are performed here. In | |
148 // particular sparc uses this for delay slot filling. | |
149 void peephole(LIR_List* list); | |
150 | |
151 void emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info); | |
152 | |
153 void return_op(LIR_Opr result); | |
154 | |
155 // returns offset of poll instruction | |
156 int safepoint_poll(LIR_Opr result, CodeEmitInfo* info); | |
157 | |
158 void const2reg (LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info); | |
159 void const2stack(LIR_Opr src, LIR_Opr dest); | |
160 void const2mem (LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info); | |
161 void reg2stack (LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack); | |
162 void reg2reg (LIR_Opr src, LIR_Opr dest); | |
163 void reg2mem (LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned); | |
164 void stack2reg (LIR_Opr src, LIR_Opr dest, BasicType type); | |
165 void stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type); | |
166 void mem2reg (LIR_Opr src, LIR_Opr dest, BasicType type, | |
167 LIR_PatchCode patch_code = lir_patch_none, | |
168 CodeEmitInfo* info = NULL, bool unaligned = false); | |
169 | |
170 void prefetchr (LIR_Opr src); | |
171 void prefetchw (LIR_Opr src); | |
172 | |
173 void shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp); | |
174 void shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest); | |
175 | |
176 void move_regs(Register from_reg, Register to_reg); | |
177 void swap_reg(Register a, Register b); | |
178 | |
179 void emit_op0(LIR_Op0* op); | |
180 void emit_op1(LIR_Op1* op); | |
181 void emit_op2(LIR_Op2* op); | |
182 void emit_op3(LIR_Op3* op); | |
183 void emit_opBranch(LIR_OpBranch* op); | |
184 void emit_opLabel(LIR_OpLabel* op); | |
185 void emit_arraycopy(LIR_OpArrayCopy* op); | |
186 void emit_opConvert(LIR_OpConvert* op); | |
187 void emit_alloc_obj(LIR_OpAllocObj* op); | |
188 void emit_alloc_array(LIR_OpAllocArray* op); | |
189 void emit_opTypeCheck(LIR_OpTypeCheck* op); | |
190 void emit_compare_and_swap(LIR_OpCompareAndSwap* op); | |
191 void emit_lock(LIR_OpLock* op); | |
192 void emit_call(LIR_OpJavaCall* op); | |
193 void emit_rtcall(LIR_OpRTCall* op); | |
194 void emit_profile_call(LIR_OpProfileCall* op); | |
195 void emit_delay(LIR_OpDelay* op); | |
196 | |
197 void arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack); | |
198 void arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info); | |
199 void intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op); | |
200 | |
201 void logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest); | |
202 | |
203 void roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack); | |
204 void move_op(LIR_Opr src, LIR_Opr result, BasicType type, | |
205 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned); | |
206 void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); | |
207 void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions | |
208 void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op); | |
209 void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result); | |
210 | |
1295 | 211 void call( LIR_OpJavaCall* op, relocInfo::relocType rtype); |
212 void ic_call( LIR_OpJavaCall* op); | |
213 void vtable_call( LIR_OpJavaCall* op); | |
214 | |
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215 // JSR 292 |
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216 void preserve_SP(LIR_OpJavaCall* op); |
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217 void restore_SP( LIR_OpJavaCall* op); |
0 | 218 |
219 void osr_entry(); | |
220 | |
221 void build_frame(); | |
222 | |
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223 void throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info); |
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224 void unwind_op(LIR_Opr exceptionOop); |
0 | 225 void monitor_address(int monitor_ix, LIR_Opr dst); |
226 | |
227 void align_backward_branch_target(); | |
228 void align_call(LIR_Code code); | |
229 | |
230 void negate(LIR_Opr left, LIR_Opr dest); | |
231 void leal(LIR_Opr left, LIR_Opr dest); | |
232 | |
233 void rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info); | |
234 | |
235 void membar(); | |
236 void membar_acquire(); | |
237 void membar_release(); | |
238 void get_thread(LIR_Opr result); | |
239 | |
240 void verify_oop_map(CodeEmitInfo* info); | |
241 | |
242 #include "incls/_c1_LIRAssembler_pd.hpp.incl" | |
243 }; |