Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/c1_LIRAssembler_x86.cpp @ 1832:22e4420d19f7
Merge
| author | kvn |
|---|---|
| date | Wed, 06 Oct 2010 14:18:32 -0700 |
| parents | 5511edd5d719 a3f7f95b0165 |
| children | c393f046f4c5 |
| rev | line source |
|---|---|
| 0 | 1 /* |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1491
diff
changeset
|
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1491
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1491
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
|
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1491
diff
changeset
|
21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 25 # include "incls/_precompiled.incl" | |
| 26 # include "incls/_c1_LIRAssembler_x86.cpp.incl" | |
| 27 | |
| 28 | |
| 29 // These masks are used to provide 128-bit aligned bitmasks to the XMM | |
| 30 // instructions, to allow sign-masking or sign-bit flipping. They allow | |
| 31 // fast versions of NegF/NegD and AbsF/AbsD. | |
| 32 | |
| 33 // Note: 'double' and 'long long' have 32-bits alignment on x86. | |
| 34 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { | |
| 35 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address | |
| 36 // of 128-bits operands for SSE instructions. | |
| 37 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); | |
| 38 // Store the value to a 128-bits operand. | |
| 39 operand[0] = lo; | |
| 40 operand[1] = hi; | |
| 41 return operand; | |
| 42 } | |
| 43 | |
| 44 // Buffer for 128-bits masks used by SSE instructions. | |
| 45 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) | |
| 46 | |
| 47 // Static initialization during VM startup. | |
| 48 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); | |
| 49 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); | |
| 50 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); | |
| 51 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); | |
| 52 | |
| 53 | |
| 54 | |
| 55 NEEDS_CLEANUP // remove this definitions ? | |
| 56 const Register IC_Klass = rax; // where the IC klass is cached | |
| 57 const Register SYNC_header = rax; // synchronization header | |
| 58 const Register SHIFT_count = rcx; // where count for shift operations must be | |
| 59 | |
| 60 #define __ _masm-> | |
| 61 | |
| 62 | |
| 63 static void select_different_registers(Register preserve, | |
| 64 Register extra, | |
| 65 Register &tmp1, | |
| 66 Register &tmp2) { | |
| 67 if (tmp1 == preserve) { | |
| 68 assert_different_registers(tmp1, tmp2, extra); | |
| 69 tmp1 = extra; | |
| 70 } else if (tmp2 == preserve) { | |
| 71 assert_different_registers(tmp1, tmp2, extra); | |
| 72 tmp2 = extra; | |
| 73 } | |
| 74 assert_different_registers(preserve, tmp1, tmp2); | |
| 75 } | |
| 76 | |
| 77 | |
| 78 | |
| 79 static void select_different_registers(Register preserve, | |
| 80 Register extra, | |
| 81 Register &tmp1, | |
| 82 Register &tmp2, | |
| 83 Register &tmp3) { | |
| 84 if (tmp1 == preserve) { | |
| 85 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
| 86 tmp1 = extra; | |
| 87 } else if (tmp2 == preserve) { | |
| 88 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
| 89 tmp2 = extra; | |
| 90 } else if (tmp3 == preserve) { | |
| 91 assert_different_registers(tmp1, tmp2, tmp3, extra); | |
| 92 tmp3 = extra; | |
| 93 } | |
| 94 assert_different_registers(preserve, tmp1, tmp2, tmp3); | |
| 95 } | |
| 96 | |
| 97 | |
| 98 | |
| 99 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { | |
| 100 if (opr->is_constant()) { | |
| 101 LIR_Const* constant = opr->as_constant_ptr(); | |
| 102 switch (constant->type()) { | |
| 103 case T_INT: { | |
| 104 return true; | |
| 105 } | |
| 106 | |
| 107 default: | |
| 108 return false; | |
| 109 } | |
| 110 } | |
| 111 return false; | |
| 112 } | |
| 113 | |
| 114 | |
| 115 LIR_Opr LIR_Assembler::receiverOpr() { | |
| 304 | 116 return FrameMap::receiver_opr; |
| 0 | 117 } |
| 118 | |
| 119 LIR_Opr LIR_Assembler::incomingReceiverOpr() { | |
| 120 return receiverOpr(); | |
| 121 } | |
| 122 | |
| 123 LIR_Opr LIR_Assembler::osrBufferPointer() { | |
| 304 | 124 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); |
| 0 | 125 } |
| 126 | |
| 127 //--------------fpu register translations----------------------- | |
| 128 | |
| 129 | |
| 130 address LIR_Assembler::float_constant(float f) { | |
| 131 address const_addr = __ float_constant(f); | |
| 132 if (const_addr == NULL) { | |
| 133 bailout("const section overflow"); | |
| 134 return __ code()->consts()->start(); | |
| 135 } else { | |
| 136 return const_addr; | |
| 137 } | |
| 138 } | |
| 139 | |
| 140 | |
| 141 address LIR_Assembler::double_constant(double d) { | |
| 142 address const_addr = __ double_constant(d); | |
| 143 if (const_addr == NULL) { | |
| 144 bailout("const section overflow"); | |
| 145 return __ code()->consts()->start(); | |
| 146 } else { | |
| 147 return const_addr; | |
| 148 } | |
| 149 } | |
| 150 | |
| 151 | |
| 152 void LIR_Assembler::set_24bit_FPU() { | |
| 153 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); | |
| 154 } | |
| 155 | |
| 156 void LIR_Assembler::reset_FPU() { | |
| 157 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 158 } | |
| 159 | |
| 160 void LIR_Assembler::fpop() { | |
| 161 __ fpop(); | |
| 162 } | |
| 163 | |
| 164 void LIR_Assembler::fxch(int i) { | |
| 165 __ fxch(i); | |
| 166 } | |
| 167 | |
| 168 void LIR_Assembler::fld(int i) { | |
| 169 __ fld_s(i); | |
| 170 } | |
| 171 | |
| 172 void LIR_Assembler::ffree(int i) { | |
| 173 __ ffree(i); | |
| 174 } | |
| 175 | |
| 176 void LIR_Assembler::breakpoint() { | |
| 177 __ int3(); | |
| 178 } | |
| 179 | |
| 180 void LIR_Assembler::push(LIR_Opr opr) { | |
| 181 if (opr->is_single_cpu()) { | |
| 182 __ push_reg(opr->as_register()); | |
| 183 } else if (opr->is_double_cpu()) { | |
| 304 | 184 NOT_LP64(__ push_reg(opr->as_register_hi())); |
| 0 | 185 __ push_reg(opr->as_register_lo()); |
| 186 } else if (opr->is_stack()) { | |
| 187 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); | |
| 188 } else if (opr->is_constant()) { | |
| 189 LIR_Const* const_opr = opr->as_constant_ptr(); | |
| 190 if (const_opr->type() == T_OBJECT) { | |
| 191 __ push_oop(const_opr->as_jobject()); | |
| 192 } else if (const_opr->type() == T_INT) { | |
| 193 __ push_jint(const_opr->as_jint()); | |
| 194 } else { | |
| 195 ShouldNotReachHere(); | |
| 196 } | |
| 197 | |
| 198 } else { | |
| 199 ShouldNotReachHere(); | |
| 200 } | |
| 201 } | |
| 202 | |
| 203 void LIR_Assembler::pop(LIR_Opr opr) { | |
| 204 if (opr->is_single_cpu()) { | |
| 304 | 205 __ pop_reg(opr->as_register()); |
| 0 | 206 } else { |
| 207 ShouldNotReachHere(); | |
| 208 } | |
| 209 } | |
| 210 | |
| 304 | 211 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { |
| 212 return addr->base()->is_illegal() && addr->index()->is_illegal(); | |
| 213 } | |
| 214 | |
| 0 | 215 //------------------------------------------- |
| 304 | 216 |
| 0 | 217 Address LIR_Assembler::as_Address(LIR_Address* addr) { |
| 304 | 218 return as_Address(addr, rscratch1); |
| 219 } | |
| 220 | |
| 221 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { | |
| 0 | 222 if (addr->base()->is_illegal()) { |
| 223 assert(addr->index()->is_illegal(), "must be illegal too"); | |
| 304 | 224 AddressLiteral laddr((address)addr->disp(), relocInfo::none); |
| 225 if (! __ reachable(laddr)) { | |
| 226 __ movptr(tmp, laddr.addr()); | |
| 227 Address res(tmp, 0); | |
| 228 return res; | |
| 229 } else { | |
| 230 return __ as_Address(laddr); | |
| 231 } | |
| 0 | 232 } |
| 233 | |
| 304 | 234 Register base = addr->base()->as_pointer_register(); |
| 0 | 235 |
| 236 if (addr->index()->is_illegal()) { | |
| 237 return Address( base, addr->disp()); | |
| 304 | 238 } else if (addr->index()->is_cpu_register()) { |
| 239 Register index = addr->index()->as_pointer_register(); | |
| 0 | 240 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); |
| 241 } else if (addr->index()->is_constant()) { | |
| 304 | 242 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); |
| 243 assert(Assembler::is_simm32(addr_offset), "must be"); | |
| 0 | 244 |
| 245 return Address(base, addr_offset); | |
| 246 } else { | |
| 247 Unimplemented(); | |
| 248 return Address(); | |
| 249 } | |
| 250 } | |
| 251 | |
| 252 | |
| 253 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { | |
| 254 Address base = as_Address(addr); | |
| 255 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); | |
| 256 } | |
| 257 | |
| 258 | |
| 259 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { | |
| 260 return as_Address(addr); | |
| 261 } | |
| 262 | |
| 263 | |
| 264 void LIR_Assembler::osr_entry() { | |
| 265 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); | |
| 266 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); | |
| 267 ValueStack* entry_state = osr_entry->state(); | |
| 268 int number_of_locks = entry_state->locks_size(); | |
| 269 | |
| 270 // we jump here if osr happens with the interpreter | |
| 271 // state set up to continue at the beginning of the | |
| 272 // loop that triggered osr - in particular, we have | |
| 273 // the following registers setup: | |
| 274 // | |
| 275 // rcx: osr buffer | |
| 276 // | |
| 277 | |
| 278 // build frame | |
| 279 ciMethod* m = compilation()->method(); | |
| 280 __ build_frame(initial_frame_size_in_bytes()); | |
| 281 | |
| 282 // OSR buffer is | |
| 283 // | |
| 284 // locals[nlocals-1..0] | |
| 285 // monitors[0..number_of_locks] | |
| 286 // | |
| 287 // locals is a direct copy of the interpreter frame so in the osr buffer | |
| 288 // so first slot in the local array is the last local from the interpreter | |
| 289 // and last slot is local[0] (receiver) from the interpreter | |
| 290 // | |
| 291 // Similarly with locks. The first lock slot in the osr buffer is the nth lock | |
| 292 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock | |
| 293 // in the interpreter frame (the method lock if a sync method) | |
| 294 | |
| 295 // Initialize monitors in the compiled activation. | |
| 296 // rcx: pointer to osr buffer | |
| 297 // | |
| 298 // All other registers are dead at this point and the locals will be | |
| 299 // copied into place by code emitted in the IR. | |
| 300 | |
| 304 | 301 Register OSR_buf = osrBufferPointer()->as_pointer_register(); |
| 0 | 302 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); |
| 303 int monitor_offset = BytesPerWord * method()->max_locals() + | |
| 1060 | 304 (2 * BytesPerWord) * (number_of_locks - 1); |
| 305 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in | |
| 306 // the OSR buffer using 2 word entries: first the lock and then | |
| 307 // the oop. | |
| 0 | 308 for (int i = 0; i < number_of_locks; i++) { |
| 1060 | 309 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); |
| 0 | 310 #ifdef ASSERT |
| 311 // verify the interpreter's monitor has a non-null object | |
| 312 { | |
| 313 Label L; | |
| 1060 | 314 __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); |
| 0 | 315 __ jcc(Assembler::notZero, L); |
| 316 __ stop("locked object is NULL"); | |
| 317 __ bind(L); | |
| 318 } | |
| 319 #endif | |
| 1060 | 320 __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); |
| 304 | 321 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); |
| 1060 | 322 __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); |
| 304 | 323 __ movptr(frame_map()->address_for_monitor_object(i), rbx); |
| 0 | 324 } |
| 325 } | |
| 326 } | |
| 327 | |
| 328 | |
| 329 // inline cache check; done before the frame is built. | |
| 330 int LIR_Assembler::check_icache() { | |
| 331 Register receiver = FrameMap::receiver_opr->as_register(); | |
| 332 Register ic_klass = IC_Klass; | |
| 304 | 333 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); |
| 0 | 334 |
| 335 if (!VerifyOops) { | |
| 336 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment | |
| 304 | 337 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { |
| 0 | 338 __ nop(); |
| 339 } | |
| 340 } | |
| 341 int offset = __ offset(); | |
| 342 __ inline_cache_check(receiver, IC_Klass); | |
| 343 assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct"); | |
| 344 if (VerifyOops) { | |
| 345 // force alignment after the cache check. | |
| 346 // It's been verified to be aligned if !VerifyOops | |
| 347 __ align(CodeEntryAlignment); | |
| 348 } | |
| 349 return offset; | |
| 350 } | |
| 351 | |
| 352 | |
| 353 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { | |
| 354 jobject o = NULL; | |
| 355 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); | |
| 356 __ movoop(reg, o); | |
| 357 patching_epilog(patch, lir_patch_normal, reg, info); | |
| 358 } | |
| 359 | |
| 360 | |
| 361 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { | |
| 362 if (exception->is_valid()) { | |
| 363 // preserve exception | |
| 364 // note: the monitor_exit runtime call is a leaf routine | |
| 365 // and cannot block => no GC can happen | |
| 366 // The slow case (MonitorAccessStub) uses the first two stack slots | |
| 367 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] | |
| 304 | 368 __ movptr (Address(rsp, 2*wordSize), exception); |
| 0 | 369 } |
| 370 | |
| 371 Register obj_reg = obj_opr->as_register(); | |
| 372 Register lock_reg = lock_opr->as_register(); | |
| 373 | |
| 374 // setup registers (lock_reg must be rax, for lock_object) | |
| 375 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); | |
| 376 Register hdr = lock_reg; | |
| 377 assert(new_hdr == SYNC_header, "wrong register"); | |
| 378 lock_reg = new_hdr; | |
| 379 // compute pointer to BasicLock | |
| 380 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); | |
| 304 | 381 __ lea(lock_reg, lock_addr); |
| 0 | 382 // unlock object |
| 383 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); | |
| 384 // _slow_case_stubs->append(slow_case); | |
| 385 // temporary fix: must be created after exceptionhandler, therefore as call stub | |
| 386 _slow_case_stubs->append(slow_case); | |
| 387 if (UseFastLocking) { | |
| 388 // try inlined fast unlocking first, revert to slow locking if it fails | |
| 389 // note: lock_reg points to the displaced header since the displaced header offset is 0! | |
| 390 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 391 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); | |
| 392 } else { | |
| 393 // always do slow unlocking | |
| 394 // note: the slow unlocking code could be inlined here, however if we use | |
| 395 // slow unlocking, speed doesn't matter anyway and this solution is | |
| 396 // simpler and requires less duplicated code - additionally, the | |
| 397 // slow unlocking code is the same in either case which simplifies | |
| 398 // debugging | |
| 399 __ jmp(*slow_case->entry()); | |
| 400 } | |
| 401 // done | |
| 402 __ bind(*slow_case->continuation()); | |
| 403 | |
| 404 if (exception->is_valid()) { | |
| 405 // restore exception | |
| 304 | 406 __ movptr (exception, Address(rsp, 2 * wordSize)); |
| 0 | 407 } |
| 408 } | |
| 409 | |
| 410 // This specifies the rsp decrement needed to build the frame | |
| 411 int LIR_Assembler::initial_frame_size_in_bytes() { | |
| 412 // if rounding, must let FrameMap know! | |
| 304 | 413 |
| 414 // The frame_map records size in slots (32bit word) | |
| 415 | |
| 416 // subtract two words to account for return address and link | |
| 417 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; | |
| 0 | 418 } |
| 419 | |
| 420 | |
| 1204 | 421 int LIR_Assembler::emit_exception_handler() { |
| 0 | 422 // if the last instruction is a call (typically to do a throw which |
| 423 // is coming at the end after block reordering) the return address | |
| 424 // must still point into the code area in order to avoid assertion | |
| 425 // failures when searching for the corresponding bci => add a nop | |
| 426 // (was bug 5/14/1999 - gri) | |
| 427 __ nop(); | |
| 428 | |
| 429 // generate code for exception handler | |
| 430 address handler_base = __ start_a_stub(exception_handler_size); | |
| 431 if (handler_base == NULL) { | |
| 432 // not enough space left for the handler | |
| 433 bailout("exception handler overflow"); | |
| 1204 | 434 return -1; |
| 0 | 435 } |
| 1204 | 436 |
| 0 | 437 int offset = code_offset(); |
| 438 | |
| 1295 | 439 // the exception oop and pc are in rax, and rdx |
| 0 | 440 // no other registers need to be preserved, so invalidate them |
| 1295 | 441 __ invalidate_registers(false, true, true, false, true, true); |
| 0 | 442 |
| 443 // check that there is really an exception | |
| 444 __ verify_not_null_oop(rax); | |
| 445 | |
| 1295 | 446 // search an exception handler (rax: exception oop, rdx: throwing pc) |
| 447 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id))); | |
| 448 | |
| 449 __ stop("should not reach here"); | |
| 450 | |
| 0 | 451 assert(code_offset() - offset <= exception_handler_size, "overflow"); |
| 452 __ end_a_stub(); | |
| 1204 | 453 |
| 454 return offset; | |
| 0 | 455 } |
| 456 | |
| 1204 | 457 |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
458 // Emit the code to remove the frame from the stack in the exception |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
459 // unwind path. |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
460 int LIR_Assembler::emit_unwind_handler() { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
461 #ifndef PRODUCT |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
462 if (CommentedAssembly) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
463 _masm->block_comment("Unwind handler"); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
464 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
465 #endif |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
466 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
467 int offset = code_offset(); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
468 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
469 // Fetch the exception from TLS and clear out exception related thread state |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
470 __ get_thread(rsi); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
471 __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset())); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
472 __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
473 __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
474 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
475 __ bind(_unwind_handler_entry); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
476 __ verify_not_null_oop(rax); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
477 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
478 __ mov(rsi, rax); // Preserve the exception |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
479 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
480 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
481 // Preform needed unlocking |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
482 MonitorExitStub* stub = NULL; |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
483 if (method()->is_synchronized()) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
484 monitor_address(0, FrameMap::rax_opr); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
485 stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
486 __ unlock_object(rdi, rbx, rax, *stub->entry()); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
487 __ bind(*stub->continuation()); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
488 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
489 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
490 if (compilation()->env()->dtrace_method_probes()) { |
|
1830
a3f7f95b0165
6988018: dtrace/hotspot/MethodInvocation/MethodInvocation002 crashes with client compiler
never
parents:
1791
diff
changeset
|
491 __ get_thread(rax); |
|
a3f7f95b0165
6988018: dtrace/hotspot/MethodInvocation/MethodInvocation002 crashes with client compiler
never
parents:
1791
diff
changeset
|
492 __ movptr(Address(rsp, 0), rax); |
|
a3f7f95b0165
6988018: dtrace/hotspot/MethodInvocation/MethodInvocation002 crashes with client compiler
never
parents:
1791
diff
changeset
|
493 __ movoop(Address(rsp, sizeof(void*)), method()->constant_encoding()); |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
494 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
495 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
496 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
497 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
498 __ mov(rax, rsi); // Restore the exception |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
499 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
500 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
501 // remove the activation and dispatch to the unwind handler |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
502 __ remove_frame(initial_frame_size_in_bytes()); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
503 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
504 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
505 // Emit the slow path assembly |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
506 if (stub != NULL) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
507 stub->emit_code(this); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
508 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
509 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
510 return offset; |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
511 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
512 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
513 |
| 1204 | 514 int LIR_Assembler::emit_deopt_handler() { |
| 0 | 515 // if the last instruction is a call (typically to do a throw which |
| 516 // is coming at the end after block reordering) the return address | |
| 517 // must still point into the code area in order to avoid assertion | |
| 518 // failures when searching for the corresponding bci => add a nop | |
| 519 // (was bug 5/14/1999 - gri) | |
| 520 __ nop(); | |
| 521 | |
| 522 // generate code for exception handler | |
| 523 address handler_base = __ start_a_stub(deopt_handler_size); | |
| 524 if (handler_base == NULL) { | |
| 525 // not enough space left for the handler | |
| 526 bailout("deopt handler overflow"); | |
| 1204 | 527 return -1; |
| 0 | 528 } |
| 1204 | 529 |
| 0 | 530 int offset = code_offset(); |
| 531 InternalAddress here(__ pc()); | |
| 1295 | 532 |
| 0 | 533 __ pushptr(here.addr()); |
| 534 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); | |
| 1295 | 535 |
| 0 | 536 assert(code_offset() - offset <= deopt_handler_size, "overflow"); |
| 537 __ end_a_stub(); | |
| 538 | |
| 1204 | 539 return offset; |
| 0 | 540 } |
| 541 | |
| 542 | |
| 543 // This is the fast version of java.lang.String.compare; it has not | |
| 544 // OSR-entry and therefore, we generate a slow version for OSR's | |
| 545 void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { | |
| 304 | 546 __ movptr (rbx, rcx); // receiver is in rcx |
| 547 __ movptr (rax, arg1->as_register()); | |
| 0 | 548 |
| 549 // Get addresses of first characters from both Strings | |
| 304 | 550 __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes())); |
| 551 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); | |
| 552 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
| 0 | 553 |
| 554 | |
| 555 // rbx, may be NULL | |
| 556 add_debug_info_for_null_check_here(info); | |
| 304 | 557 __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); |
| 558 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); | |
| 559 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); | |
| 0 | 560 |
| 561 // compute minimum length (in rax) and difference of lengths (on top of stack) | |
| 562 if (VM_Version::supports_cmov()) { | |
| 304 | 563 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
| 564 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); | |
| 565 __ mov (rcx, rbx); | |
| 566 __ subptr (rbx, rax); // subtract lengths | |
| 567 __ push (rbx); // result | |
| 568 __ cmov (Assembler::lessEqual, rax, rcx); | |
| 0 | 569 } else { |
| 570 Label L; | |
| 304 | 571 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); |
| 572 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); | |
| 573 __ mov (rax, rbx); | |
| 574 __ subptr (rbx, rcx); | |
| 575 __ push (rbx); | |
| 576 __ jcc (Assembler::lessEqual, L); | |
| 577 __ mov (rax, rcx); | |
| 0 | 578 __ bind (L); |
| 579 } | |
| 580 // is minimum length 0? | |
| 581 Label noLoop, haveResult; | |
| 304 | 582 __ testptr (rax, rax); |
| 0 | 583 __ jcc (Assembler::zero, noLoop); |
| 584 | |
| 585 // compare first characters | |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
512
diff
changeset
|
586 __ load_unsigned_short(rcx, Address(rdi, 0)); |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
512
diff
changeset
|
587 __ load_unsigned_short(rbx, Address(rsi, 0)); |
| 0 | 588 __ subl(rcx, rbx); |
| 589 __ jcc(Assembler::notZero, haveResult); | |
| 590 // starting loop | |
| 591 __ decrement(rax); // we already tested index: skip one | |
| 592 __ jcc(Assembler::zero, noLoop); | |
| 593 | |
| 594 // set rsi.edi to the end of the arrays (arrays have same length) | |
| 595 // negate the index | |
| 596 | |
| 304 | 597 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); |
| 598 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); | |
| 599 __ negptr(rax); | |
| 0 | 600 |
| 601 // compare the strings in a loop | |
| 602 | |
| 603 Label loop; | |
| 604 __ align(wordSize); | |
| 605 __ bind(loop); | |
|
622
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
512
diff
changeset
|
606 __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); |
|
56aae7be60d4
6812678: macro assembler needs delayed binding of a few constants (for 6655638)
jrose
parents:
512
diff
changeset
|
607 __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); |
| 0 | 608 __ subl(rcx, rbx); |
| 609 __ jcc(Assembler::notZero, haveResult); | |
| 610 __ increment(rax); | |
| 611 __ jcc(Assembler::notZero, loop); | |
| 612 | |
| 613 // strings are equal up to min length | |
| 614 | |
| 615 __ bind(noLoop); | |
| 304 | 616 __ pop(rax); |
| 0 | 617 return_op(LIR_OprFact::illegalOpr); |
| 618 | |
| 619 __ bind(haveResult); | |
| 620 // leave instruction is going to discard the TOS value | |
| 304 | 621 __ mov (rax, rcx); // result of call is in rax, |
| 0 | 622 } |
| 623 | |
| 624 | |
| 625 void LIR_Assembler::return_op(LIR_Opr result) { | |
| 626 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); | |
| 627 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { | |
| 628 assert(result->fpu() == 0, "result must already be on TOS"); | |
| 629 } | |
| 630 | |
| 631 // Pop the stack before the safepoint code | |
| 1295 | 632 __ remove_frame(initial_frame_size_in_bytes()); |
| 0 | 633 |
| 634 bool result_is_oop = result->is_valid() ? result->is_oop() : false; | |
| 635 | |
| 636 // Note: we do not need to round double result; float result has the right precision | |
| 637 // the poll sets the condition code, but no data registers | |
| 638 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
| 639 relocInfo::poll_return_type); | |
| 304 | 640 |
| 641 // NOTE: the requires that the polling page be reachable else the reloc | |
| 642 // goes to the movq that loads the address and not the faulting instruction | |
| 643 // which breaks the signal handler code | |
| 644 | |
| 0 | 645 __ test32(rax, polling_page); |
| 646 | |
| 647 __ ret(0); | |
| 648 } | |
| 649 | |
| 650 | |
| 651 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { | |
| 652 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), | |
| 653 relocInfo::poll_type); | |
| 654 | |
| 655 if (info != NULL) { | |
| 656 add_debug_info_for_branch(info); | |
| 657 } else { | |
| 658 ShouldNotReachHere(); | |
| 659 } | |
| 660 | |
| 661 int offset = __ offset(); | |
| 304 | 662 |
| 663 // NOTE: the requires that the polling page be reachable else the reloc | |
| 664 // goes to the movq that loads the address and not the faulting instruction | |
| 665 // which breaks the signal handler code | |
| 666 | |
| 0 | 667 __ test32(rax, polling_page); |
| 668 return offset; | |
| 669 } | |
| 670 | |
| 671 | |
| 672 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { | |
| 304 | 673 if (from_reg != to_reg) __ mov(to_reg, from_reg); |
| 0 | 674 } |
| 675 | |
| 676 void LIR_Assembler::swap_reg(Register a, Register b) { | |
| 304 | 677 __ xchgptr(a, b); |
| 0 | 678 } |
| 679 | |
| 680 | |
| 681 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { | |
| 682 assert(src->is_constant(), "should not call otherwise"); | |
| 683 assert(dest->is_register(), "should not call otherwise"); | |
| 684 LIR_Const* c = src->as_constant_ptr(); | |
| 685 | |
| 686 switch (c->type()) { | |
|
1297
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1295
diff
changeset
|
687 case T_INT: |
|
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1295
diff
changeset
|
688 case T_ADDRESS: { |
| 0 | 689 assert(patch_code == lir_patch_none, "no patching handled here"); |
| 690 __ movl(dest->as_register(), c->as_jint()); | |
| 691 break; | |
| 692 } | |
| 693 | |
| 694 case T_LONG: { | |
| 695 assert(patch_code == lir_patch_none, "no patching handled here"); | |
| 304 | 696 #ifdef _LP64 |
| 697 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); | |
| 698 #else | |
| 699 __ movptr(dest->as_register_lo(), c->as_jint_lo()); | |
| 700 __ movptr(dest->as_register_hi(), c->as_jint_hi()); | |
| 701 #endif // _LP64 | |
| 0 | 702 break; |
| 703 } | |
| 704 | |
| 705 case T_OBJECT: { | |
| 706 if (patch_code != lir_patch_none) { | |
| 707 jobject2reg_with_patching(dest->as_register(), info); | |
| 708 } else { | |
| 709 __ movoop(dest->as_register(), c->as_jobject()); | |
| 710 } | |
| 711 break; | |
| 712 } | |
| 713 | |
| 714 case T_FLOAT: { | |
| 715 if (dest->is_single_xmm()) { | |
| 716 if (c->is_zero_float()) { | |
| 717 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); | |
| 718 } else { | |
| 719 __ movflt(dest->as_xmm_float_reg(), | |
| 720 InternalAddress(float_constant(c->as_jfloat()))); | |
| 721 } | |
| 722 } else { | |
| 723 assert(dest->is_single_fpu(), "must be"); | |
| 724 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
| 725 if (c->is_zero_float()) { | |
| 726 __ fldz(); | |
| 727 } else if (c->is_one_float()) { | |
| 728 __ fld1(); | |
| 729 } else { | |
| 730 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); | |
| 731 } | |
| 732 } | |
| 733 break; | |
| 734 } | |
| 735 | |
| 736 case T_DOUBLE: { | |
| 737 if (dest->is_double_xmm()) { | |
| 738 if (c->is_zero_double()) { | |
| 739 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); | |
| 740 } else { | |
| 741 __ movdbl(dest->as_xmm_double_reg(), | |
| 742 InternalAddress(double_constant(c->as_jdouble()))); | |
| 743 } | |
| 744 } else { | |
| 745 assert(dest->is_double_fpu(), "must be"); | |
| 746 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
| 747 if (c->is_zero_double()) { | |
| 748 __ fldz(); | |
| 749 } else if (c->is_one_double()) { | |
| 750 __ fld1(); | |
| 751 } else { | |
| 752 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); | |
| 753 } | |
| 754 } | |
| 755 break; | |
| 756 } | |
| 757 | |
| 758 default: | |
| 759 ShouldNotReachHere(); | |
| 760 } | |
| 761 } | |
| 762 | |
| 763 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { | |
| 764 assert(src->is_constant(), "should not call otherwise"); | |
| 765 assert(dest->is_stack(), "should not call otherwise"); | |
| 766 LIR_Const* c = src->as_constant_ptr(); | |
| 767 | |
| 768 switch (c->type()) { | |
| 769 case T_INT: // fall through | |
| 770 case T_FLOAT: | |
|
1297
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1295
diff
changeset
|
771 case T_ADDRESS: |
| 0 | 772 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); |
| 773 break; | |
| 774 | |
| 775 case T_OBJECT: | |
| 776 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); | |
| 777 break; | |
| 778 | |
| 779 case T_LONG: // fall through | |
| 780 case T_DOUBLE: | |
| 304 | 781 #ifdef _LP64 |
| 782 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
| 783 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); | |
| 784 #else | |
| 785 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
| 786 lo_word_offset_in_bytes), c->as_jint_lo_bits()); | |
| 787 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), | |
| 788 hi_word_offset_in_bytes), c->as_jint_hi_bits()); | |
| 789 #endif // _LP64 | |
| 0 | 790 break; |
| 791 | |
| 792 default: | |
| 793 ShouldNotReachHere(); | |
| 794 } | |
| 795 } | |
| 796 | |
| 797 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { | |
| 798 assert(src->is_constant(), "should not call otherwise"); | |
| 799 assert(dest->is_address(), "should not call otherwise"); | |
| 800 LIR_Const* c = src->as_constant_ptr(); | |
| 801 LIR_Address* addr = dest->as_address_ptr(); | |
| 802 | |
| 304 | 803 int null_check_here = code_offset(); |
| 0 | 804 switch (type) { |
| 805 case T_INT: // fall through | |
| 806 case T_FLOAT: | |
|
1297
c466efa608d5
6932496: c1: deoptimization of jsr subroutine fails on sparcv9
roland
parents:
1295
diff
changeset
|
807 case T_ADDRESS: |
| 0 | 808 __ movl(as_Address(addr), c->as_jint_bits()); |
| 809 break; | |
| 810 | |
| 811 case T_OBJECT: // fall through | |
| 812 case T_ARRAY: | |
| 813 if (c->as_jobject() == NULL) { | |
|
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
xlu
parents:
321
diff
changeset
|
814 __ movptr(as_Address(addr), NULL_WORD); |
| 0 | 815 } else { |
| 304 | 816 if (is_literal_address(addr)) { |
| 817 ShouldNotReachHere(); | |
| 818 __ movoop(as_Address(addr, noreg), c->as_jobject()); | |
| 819 } else { | |
| 1060 | 820 #ifdef _LP64 |
| 821 __ movoop(rscratch1, c->as_jobject()); | |
| 822 null_check_here = code_offset(); | |
| 823 __ movptr(as_Address_lo(addr), rscratch1); | |
| 824 #else | |
| 304 | 825 __ movoop(as_Address(addr), c->as_jobject()); |
| 1060 | 826 #endif |
| 304 | 827 } |
| 0 | 828 } |
| 829 break; | |
| 830 | |
| 831 case T_LONG: // fall through | |
| 832 case T_DOUBLE: | |
| 304 | 833 #ifdef _LP64 |
| 834 if (is_literal_address(addr)) { | |
| 835 ShouldNotReachHere(); | |
| 836 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); | |
| 837 } else { | |
| 838 __ movptr(r10, (intptr_t)c->as_jlong_bits()); | |
| 839 null_check_here = code_offset(); | |
| 840 __ movptr(as_Address_lo(addr), r10); | |
| 841 } | |
| 842 #else | |
| 843 // Always reachable in 32bit so this doesn't produce useless move literal | |
| 844 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); | |
| 845 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); | |
| 846 #endif // _LP64 | |
| 0 | 847 break; |
| 848 | |
| 849 case T_BOOLEAN: // fall through | |
| 850 case T_BYTE: | |
| 851 __ movb(as_Address(addr), c->as_jint() & 0xFF); | |
| 852 break; | |
| 853 | |
| 854 case T_CHAR: // fall through | |
| 855 case T_SHORT: | |
| 856 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); | |
| 857 break; | |
| 858 | |
| 859 default: | |
| 860 ShouldNotReachHere(); | |
| 861 }; | |
| 304 | 862 |
| 863 if (info != NULL) { | |
| 864 add_debug_info_for_null_check(null_check_here, info); | |
| 865 } | |
| 0 | 866 } |
| 867 | |
| 868 | |
| 869 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { | |
| 870 assert(src->is_register(), "should not call otherwise"); | |
| 871 assert(dest->is_register(), "should not call otherwise"); | |
| 872 | |
| 873 // move between cpu-registers | |
| 874 if (dest->is_single_cpu()) { | |
| 304 | 875 #ifdef _LP64 |
| 876 if (src->type() == T_LONG) { | |
| 877 // Can do LONG -> OBJECT | |
| 878 move_regs(src->as_register_lo(), dest->as_register()); | |
| 879 return; | |
| 880 } | |
| 881 #endif | |
| 0 | 882 assert(src->is_single_cpu(), "must match"); |
| 883 if (src->type() == T_OBJECT) { | |
| 884 __ verify_oop(src->as_register()); | |
| 885 } | |
| 886 move_regs(src->as_register(), dest->as_register()); | |
| 887 | |
| 888 } else if (dest->is_double_cpu()) { | |
| 304 | 889 #ifdef _LP64 |
| 890 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { | |
| 891 // Surprising to me but we can see move of a long to t_object | |
| 892 __ verify_oop(src->as_register()); | |
| 893 move_regs(src->as_register(), dest->as_register_lo()); | |
| 894 return; | |
| 895 } | |
| 896 #endif | |
| 0 | 897 assert(src->is_double_cpu(), "must match"); |
| 898 Register f_lo = src->as_register_lo(); | |
| 899 Register f_hi = src->as_register_hi(); | |
| 900 Register t_lo = dest->as_register_lo(); | |
| 901 Register t_hi = dest->as_register_hi(); | |
| 304 | 902 #ifdef _LP64 |
| 903 assert(f_hi == f_lo, "must be same"); | |
| 904 assert(t_hi == t_lo, "must be same"); | |
| 905 move_regs(f_lo, t_lo); | |
| 906 #else | |
| 0 | 907 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); |
| 908 | |
| 304 | 909 |
| 0 | 910 if (f_lo == t_hi && f_hi == t_lo) { |
| 911 swap_reg(f_lo, f_hi); | |
| 912 } else if (f_hi == t_lo) { | |
| 913 assert(f_lo != t_hi, "overwriting register"); | |
| 914 move_regs(f_hi, t_hi); | |
| 915 move_regs(f_lo, t_lo); | |
| 916 } else { | |
| 917 assert(f_hi != t_lo, "overwriting register"); | |
| 918 move_regs(f_lo, t_lo); | |
| 919 move_regs(f_hi, t_hi); | |
| 920 } | |
| 304 | 921 #endif // LP64 |
| 0 | 922 |
| 923 // special moves from fpu-register to xmm-register | |
| 924 // necessary for method results | |
| 925 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { | |
| 926 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); | |
| 927 __ fld_s(Address(rsp, 0)); | |
| 928 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { | |
| 929 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); | |
| 930 __ fld_d(Address(rsp, 0)); | |
| 931 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { | |
| 932 __ fstp_s(Address(rsp, 0)); | |
| 933 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); | |
| 934 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { | |
| 935 __ fstp_d(Address(rsp, 0)); | |
| 936 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); | |
| 937 | |
| 938 // move between xmm-registers | |
| 939 } else if (dest->is_single_xmm()) { | |
| 940 assert(src->is_single_xmm(), "must match"); | |
| 941 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); | |
| 942 } else if (dest->is_double_xmm()) { | |
| 943 assert(src->is_double_xmm(), "must match"); | |
| 944 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); | |
| 945 | |
| 946 // move between fpu-registers (no instruction necessary because of fpu-stack) | |
| 947 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { | |
| 948 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); | |
| 949 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); | |
| 950 } else { | |
| 951 ShouldNotReachHere(); | |
| 952 } | |
| 953 } | |
| 954 | |
| 955 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { | |
| 956 assert(src->is_register(), "should not call otherwise"); | |
| 957 assert(dest->is_stack(), "should not call otherwise"); | |
| 958 | |
| 959 if (src->is_single_cpu()) { | |
| 960 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 961 if (type == T_OBJECT || type == T_ARRAY) { | |
| 962 __ verify_oop(src->as_register()); | |
| 304 | 963 __ movptr (dst, src->as_register()); |
| 964 } else { | |
| 965 __ movl (dst, src->as_register()); | |
| 0 | 966 } |
| 967 | |
| 968 } else if (src->is_double_cpu()) { | |
| 969 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); | |
| 970 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); | |
| 304 | 971 __ movptr (dstLO, src->as_register_lo()); |
| 972 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); | |
| 0 | 973 |
| 974 } else if (src->is_single_xmm()) { | |
| 975 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 976 __ movflt(dst_addr, src->as_xmm_float_reg()); | |
| 977 | |
| 978 } else if (src->is_double_xmm()) { | |
| 979 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
| 980 __ movdbl(dst_addr, src->as_xmm_double_reg()); | |
| 981 | |
| 982 } else if (src->is_single_fpu()) { | |
| 983 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
| 984 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); | |
| 985 if (pop_fpu_stack) __ fstp_s (dst_addr); | |
| 986 else __ fst_s (dst_addr); | |
| 987 | |
| 988 } else if (src->is_double_fpu()) { | |
| 989 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
| 990 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); | |
| 991 if (pop_fpu_stack) __ fstp_d (dst_addr); | |
| 992 else __ fst_d (dst_addr); | |
| 993 | |
| 994 } else { | |
| 995 ShouldNotReachHere(); | |
| 996 } | |
| 997 } | |
| 998 | |
| 999 | |
| 1000 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) { | |
| 1001 LIR_Address* to_addr = dest->as_address_ptr(); | |
| 1002 PatchingStub* patch = NULL; | |
| 1003 | |
| 1004 if (type == T_ARRAY || type == T_OBJECT) { | |
| 1005 __ verify_oop(src->as_register()); | |
| 1006 } | |
| 1007 if (patch_code != lir_patch_none) { | |
| 1008 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 304 | 1009 Address toa = as_Address(to_addr); |
| 1010 assert(toa.disp() != 0, "must have"); | |
| 0 | 1011 } |
| 1012 if (info != NULL) { | |
| 1013 add_debug_info_for_null_check_here(info); | |
| 1014 } | |
| 1015 | |
| 1016 switch (type) { | |
| 1017 case T_FLOAT: { | |
| 1018 if (src->is_single_xmm()) { | |
| 1019 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); | |
| 1020 } else { | |
| 1021 assert(src->is_single_fpu(), "must be"); | |
| 1022 assert(src->fpu_regnr() == 0, "argument must be on TOS"); | |
| 1023 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); | |
| 1024 else __ fst_s (as_Address(to_addr)); | |
| 1025 } | |
| 1026 break; | |
| 1027 } | |
| 1028 | |
| 1029 case T_DOUBLE: { | |
| 1030 if (src->is_double_xmm()) { | |
| 1031 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); | |
| 1032 } else { | |
| 1033 assert(src->is_double_fpu(), "must be"); | |
| 1034 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); | |
| 1035 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); | |
| 1036 else __ fst_d (as_Address(to_addr)); | |
| 1037 } | |
| 1038 break; | |
| 1039 } | |
| 1040 | |
| 1041 case T_ADDRESS: // fall through | |
| 1042 case T_ARRAY: // fall through | |
| 1043 case T_OBJECT: // fall through | |
| 304 | 1044 #ifdef _LP64 |
| 1045 __ movptr(as_Address(to_addr), src->as_register()); | |
| 1046 break; | |
| 1047 #endif // _LP64 | |
| 0 | 1048 case T_INT: |
| 1049 __ movl(as_Address(to_addr), src->as_register()); | |
| 1050 break; | |
| 1051 | |
| 1052 case T_LONG: { | |
| 1053 Register from_lo = src->as_register_lo(); | |
| 1054 Register from_hi = src->as_register_hi(); | |
| 304 | 1055 #ifdef _LP64 |
| 1056 __ movptr(as_Address_lo(to_addr), from_lo); | |
| 1057 #else | |
| 0 | 1058 Register base = to_addr->base()->as_register(); |
| 1059 Register index = noreg; | |
| 1060 if (to_addr->index()->is_register()) { | |
| 1061 index = to_addr->index()->as_register(); | |
| 1062 } | |
| 1063 if (base == from_lo || index == from_lo) { | |
| 1064 assert(base != from_hi, "can't be"); | |
| 1065 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); | |
| 1066 __ movl(as_Address_hi(to_addr), from_hi); | |
| 1067 if (patch != NULL) { | |
| 1068 patching_epilog(patch, lir_patch_high, base, info); | |
| 1069 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1070 patch_code = lir_patch_low; | |
| 1071 } | |
| 1072 __ movl(as_Address_lo(to_addr), from_lo); | |
| 1073 } else { | |
| 1074 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); | |
| 1075 __ movl(as_Address_lo(to_addr), from_lo); | |
| 1076 if (patch != NULL) { | |
| 1077 patching_epilog(patch, lir_patch_low, base, info); | |
| 1078 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1079 patch_code = lir_patch_high; | |
| 1080 } | |
| 1081 __ movl(as_Address_hi(to_addr), from_hi); | |
| 1082 } | |
| 304 | 1083 #endif // _LP64 |
| 0 | 1084 break; |
| 1085 } | |
| 1086 | |
| 1087 case T_BYTE: // fall through | |
| 1088 case T_BOOLEAN: { | |
| 1089 Register src_reg = src->as_register(); | |
| 1090 Address dst_addr = as_Address(to_addr); | |
| 1091 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); | |
| 1092 __ movb(dst_addr, src_reg); | |
| 1093 break; | |
| 1094 } | |
| 1095 | |
| 1096 case T_CHAR: // fall through | |
| 1097 case T_SHORT: | |
| 1098 __ movw(as_Address(to_addr), src->as_register()); | |
| 1099 break; | |
| 1100 | |
| 1101 default: | |
| 1102 ShouldNotReachHere(); | |
| 1103 } | |
| 1104 | |
| 1105 if (patch_code != lir_patch_none) { | |
| 1106 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); | |
| 1107 } | |
| 1108 } | |
| 1109 | |
| 1110 | |
| 1111 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
| 1112 assert(src->is_stack(), "should not call otherwise"); | |
| 1113 assert(dest->is_register(), "should not call otherwise"); | |
| 1114 | |
| 1115 if (dest->is_single_cpu()) { | |
| 1116 if (type == T_ARRAY || type == T_OBJECT) { | |
| 304 | 1117 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); |
| 0 | 1118 __ verify_oop(dest->as_register()); |
| 304 | 1119 } else { |
| 1120 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); | |
| 0 | 1121 } |
| 1122 | |
| 1123 } else if (dest->is_double_cpu()) { | |
| 1124 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); | |
| 1125 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); | |
| 304 | 1126 __ movptr(dest->as_register_lo(), src_addr_LO); |
| 1127 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); | |
| 0 | 1128 |
| 1129 } else if (dest->is_single_xmm()) { | |
| 1130 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1131 __ movflt(dest->as_xmm_float_reg(), src_addr); | |
| 1132 | |
| 1133 } else if (dest->is_double_xmm()) { | |
| 1134 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
| 1135 __ movdbl(dest->as_xmm_double_reg(), src_addr); | |
| 1136 | |
| 1137 } else if (dest->is_single_fpu()) { | |
| 1138 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
| 1139 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); | |
| 1140 __ fld_s(src_addr); | |
| 1141 | |
| 1142 } else if (dest->is_double_fpu()) { | |
| 1143 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
| 1144 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); | |
| 1145 __ fld_d(src_addr); | |
| 1146 | |
| 1147 } else { | |
| 1148 ShouldNotReachHere(); | |
| 1149 } | |
| 1150 } | |
| 1151 | |
| 1152 | |
| 1153 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { | |
| 1154 if (src->is_single_stack()) { | |
| 304 | 1155 if (type == T_OBJECT || type == T_ARRAY) { |
| 1156 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); | |
| 1157 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); | |
| 1158 } else { | |
| 1060 | 1159 #ifndef _LP64 |
| 304 | 1160 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); |
| 1161 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); | |
| 1060 | 1162 #else |
| 1163 //no pushl on 64bits | |
| 1164 __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); | |
| 1165 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); | |
| 1166 #endif | |
| 304 | 1167 } |
| 0 | 1168 |
| 1169 } else if (src->is_double_stack()) { | |
| 304 | 1170 #ifdef _LP64 |
| 1171 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); | |
| 1172 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); | |
| 1173 #else | |
| 0 | 1174 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); |
| 304 | 1175 // push and pop the part at src + wordSize, adding wordSize for the previous push |
|
321
6e7305abe64c
6746320: Hotspot regression test for 6512111 fails in -Xmixed mode
never
parents:
304
diff
changeset
|
1176 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); |
|
6e7305abe64c
6746320: Hotspot regression test for 6512111 fails in -Xmixed mode
never
parents:
304
diff
changeset
|
1177 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); |
| 0 | 1178 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); |
| 304 | 1179 #endif // _LP64 |
| 0 | 1180 |
| 1181 } else { | |
| 1182 ShouldNotReachHere(); | |
| 1183 } | |
| 1184 } | |
| 1185 | |
| 1186 | |
| 1187 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) { | |
| 1188 assert(src->is_address(), "should not call otherwise"); | |
| 1189 assert(dest->is_register(), "should not call otherwise"); | |
| 1190 | |
| 1191 LIR_Address* addr = src->as_address_ptr(); | |
| 1192 Address from_addr = as_Address(addr); | |
| 1193 | |
| 1194 switch (type) { | |
| 1195 case T_BOOLEAN: // fall through | |
| 1196 case T_BYTE: // fall through | |
| 1197 case T_CHAR: // fall through | |
| 1198 case T_SHORT: | |
| 1199 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { | |
| 1200 // on pre P6 processors we may get partial register stalls | |
| 1201 // so blow away the value of to_rinfo before loading a | |
| 1202 // partial word into it. Do it here so that it precedes | |
| 1203 // the potential patch point below. | |
| 304 | 1204 __ xorptr(dest->as_register(), dest->as_register()); |
| 0 | 1205 } |
| 1206 break; | |
| 1207 } | |
| 1208 | |
| 1209 PatchingStub* patch = NULL; | |
| 1210 if (patch_code != lir_patch_none) { | |
| 1211 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 304 | 1212 assert(from_addr.disp() != 0, "must have"); |
| 0 | 1213 } |
| 1214 if (info != NULL) { | |
| 1215 add_debug_info_for_null_check_here(info); | |
| 1216 } | |
| 1217 | |
| 1218 switch (type) { | |
| 1219 case T_FLOAT: { | |
| 1220 if (dest->is_single_xmm()) { | |
| 1221 __ movflt(dest->as_xmm_float_reg(), from_addr); | |
| 1222 } else { | |
| 1223 assert(dest->is_single_fpu(), "must be"); | |
| 1224 assert(dest->fpu_regnr() == 0, "dest must be TOS"); | |
| 1225 __ fld_s(from_addr); | |
| 1226 } | |
| 1227 break; | |
| 1228 } | |
| 1229 | |
| 1230 case T_DOUBLE: { | |
| 1231 if (dest->is_double_xmm()) { | |
| 1232 __ movdbl(dest->as_xmm_double_reg(), from_addr); | |
| 1233 } else { | |
| 1234 assert(dest->is_double_fpu(), "must be"); | |
| 1235 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); | |
| 1236 __ fld_d(from_addr); | |
| 1237 } | |
| 1238 break; | |
| 1239 } | |
| 1240 | |
| 1241 case T_ADDRESS: // fall through | |
| 1242 case T_OBJECT: // fall through | |
| 1243 case T_ARRAY: // fall through | |
| 304 | 1244 #ifdef _LP64 |
| 1245 __ movptr(dest->as_register(), from_addr); | |
| 1246 break; | |
| 1247 #endif // _L64 | |
| 0 | 1248 case T_INT: |
|
1398
314e17ca2c23
6946892: c1 shouldn't sign-extend to upper 32bits on x64
iveresov
parents:
1378
diff
changeset
|
1249 __ movl(dest->as_register(), from_addr); |
| 0 | 1250 break; |
| 1251 | |
| 1252 case T_LONG: { | |
| 1253 Register to_lo = dest->as_register_lo(); | |
| 1254 Register to_hi = dest->as_register_hi(); | |
| 304 | 1255 #ifdef _LP64 |
| 1256 __ movptr(to_lo, as_Address_lo(addr)); | |
| 1257 #else | |
| 0 | 1258 Register base = addr->base()->as_register(); |
| 1259 Register index = noreg; | |
| 1260 if (addr->index()->is_register()) { | |
| 1261 index = addr->index()->as_register(); | |
| 1262 } | |
| 1263 if ((base == to_lo && index == to_hi) || | |
| 1264 (base == to_hi && index == to_lo)) { | |
| 1265 // addresses with 2 registers are only formed as a result of | |
| 1266 // array access so this code will never have to deal with | |
| 1267 // patches or null checks. | |
| 1268 assert(info == NULL && patch == NULL, "must be"); | |
| 304 | 1269 __ lea(to_hi, as_Address(addr)); |
| 0 | 1270 __ movl(to_lo, Address(to_hi, 0)); |
| 1271 __ movl(to_hi, Address(to_hi, BytesPerWord)); | |
| 1272 } else if (base == to_lo || index == to_lo) { | |
| 1273 assert(base != to_hi, "can't be"); | |
| 1274 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); | |
| 1275 __ movl(to_hi, as_Address_hi(addr)); | |
| 1276 if (patch != NULL) { | |
| 1277 patching_epilog(patch, lir_patch_high, base, info); | |
| 1278 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1279 patch_code = lir_patch_low; | |
| 1280 } | |
| 1281 __ movl(to_lo, as_Address_lo(addr)); | |
| 1282 } else { | |
| 1283 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); | |
| 1284 __ movl(to_lo, as_Address_lo(addr)); | |
| 1285 if (patch != NULL) { | |
| 1286 patching_epilog(patch, lir_patch_low, base, info); | |
| 1287 patch = new PatchingStub(_masm, PatchingStub::access_field_id); | |
| 1288 patch_code = lir_patch_high; | |
| 1289 } | |
| 1290 __ movl(to_hi, as_Address_hi(addr)); | |
| 1291 } | |
| 304 | 1292 #endif // _LP64 |
| 0 | 1293 break; |
| 1294 } | |
| 1295 | |
| 1296 case T_BOOLEAN: // fall through | |
| 1297 case T_BYTE: { | |
| 1298 Register dest_reg = dest->as_register(); | |
| 1299 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
| 1300 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
| 304 | 1301 __ movsbl(dest_reg, from_addr); |
| 0 | 1302 } else { |
| 1303 __ movb(dest_reg, from_addr); | |
| 1304 __ shll(dest_reg, 24); | |
| 1305 __ sarl(dest_reg, 24); | |
| 1306 } | |
| 1307 break; | |
| 1308 } | |
| 1309 | |
| 1310 case T_CHAR: { | |
| 1311 Register dest_reg = dest->as_register(); | |
| 1312 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); | |
| 1313 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
| 304 | 1314 __ movzwl(dest_reg, from_addr); |
| 0 | 1315 } else { |
| 1316 __ movw(dest_reg, from_addr); | |
| 1317 } | |
| 1318 break; | |
| 1319 } | |
| 1320 | |
| 1321 case T_SHORT: { | |
| 1322 Register dest_reg = dest->as_register(); | |
| 1323 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { | |
| 304 | 1324 __ movswl(dest_reg, from_addr); |
| 0 | 1325 } else { |
| 1326 __ movw(dest_reg, from_addr); | |
| 1327 __ shll(dest_reg, 16); | |
| 1328 __ sarl(dest_reg, 16); | |
| 1329 } | |
| 1330 break; | |
| 1331 } | |
| 1332 | |
| 1333 default: | |
| 1334 ShouldNotReachHere(); | |
| 1335 } | |
| 1336 | |
| 1337 if (patch != NULL) { | |
| 1338 patching_epilog(patch, patch_code, addr->base()->as_register(), info); | |
| 1339 } | |
| 1340 | |
| 1341 if (type == T_ARRAY || type == T_OBJECT) { | |
| 1342 __ verify_oop(dest->as_register()); | |
| 1343 } | |
| 1344 } | |
| 1345 | |
| 1346 | |
| 1347 void LIR_Assembler::prefetchr(LIR_Opr src) { | |
| 1348 LIR_Address* addr = src->as_address_ptr(); | |
| 1349 Address from_addr = as_Address(addr); | |
| 1350 | |
| 1351 if (VM_Version::supports_sse()) { | |
| 1352 switch (ReadPrefetchInstr) { | |
| 1353 case 0: | |
| 1354 __ prefetchnta(from_addr); break; | |
| 1355 case 1: | |
| 1356 __ prefetcht0(from_addr); break; | |
| 1357 case 2: | |
| 1358 __ prefetcht2(from_addr); break; | |
| 1359 default: | |
| 1360 ShouldNotReachHere(); break; | |
| 1361 } | |
| 1362 } else if (VM_Version::supports_3dnow()) { | |
| 1363 __ prefetchr(from_addr); | |
| 1364 } | |
| 1365 } | |
| 1366 | |
| 1367 | |
| 1368 void LIR_Assembler::prefetchw(LIR_Opr src) { | |
| 1369 LIR_Address* addr = src->as_address_ptr(); | |
| 1370 Address from_addr = as_Address(addr); | |
| 1371 | |
| 1372 if (VM_Version::supports_sse()) { | |
| 1373 switch (AllocatePrefetchInstr) { | |
| 1374 case 0: | |
| 1375 __ prefetchnta(from_addr); break; | |
| 1376 case 1: | |
| 1377 __ prefetcht0(from_addr); break; | |
| 1378 case 2: | |
| 1379 __ prefetcht2(from_addr); break; | |
| 1380 case 3: | |
| 1381 __ prefetchw(from_addr); break; | |
| 1382 default: | |
| 1383 ShouldNotReachHere(); break; | |
| 1384 } | |
| 1385 } else if (VM_Version::supports_3dnow()) { | |
| 1386 __ prefetchw(from_addr); | |
| 1387 } | |
| 1388 } | |
| 1389 | |
| 1390 | |
| 1391 NEEDS_CLEANUP; // This could be static? | |
| 1392 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { | |
|
29
d5fc211aea19
6633953: type2aelembytes{T_ADDRESS} should be 8 bytes in 64 bit VM
kvn
parents:
0
diff
changeset
|
1393 int elem_size = type2aelembytes(type); |
| 0 | 1394 switch (elem_size) { |
| 1395 case 1: return Address::times_1; | |
| 1396 case 2: return Address::times_2; | |
| 1397 case 4: return Address::times_4; | |
| 1398 case 8: return Address::times_8; | |
| 1399 } | |
| 1400 ShouldNotReachHere(); | |
| 1401 return Address::no_scale; | |
| 1402 } | |
| 1403 | |
| 1404 | |
| 1405 void LIR_Assembler::emit_op3(LIR_Op3* op) { | |
| 1406 switch (op->code()) { | |
| 1407 case lir_idiv: | |
| 1408 case lir_irem: | |
| 1409 arithmetic_idiv(op->code(), | |
| 1410 op->in_opr1(), | |
| 1411 op->in_opr2(), | |
| 1412 op->in_opr3(), | |
| 1413 op->result_opr(), | |
| 1414 op->info()); | |
| 1415 break; | |
| 1416 default: ShouldNotReachHere(); break; | |
| 1417 } | |
| 1418 } | |
| 1419 | |
| 1420 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { | |
| 1421 #ifdef ASSERT | |
| 1422 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); | |
| 1423 if (op->block() != NULL) _branch_target_blocks.append(op->block()); | |
| 1424 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); | |
| 1425 #endif | |
| 1426 | |
| 1427 if (op->cond() == lir_cond_always) { | |
| 1428 if (op->info() != NULL) add_debug_info_for_branch(op->info()); | |
| 1429 __ jmp (*(op->label())); | |
| 1430 } else { | |
| 1431 Assembler::Condition acond = Assembler::zero; | |
| 1432 if (op->code() == lir_cond_float_branch) { | |
| 1433 assert(op->ublock() != NULL, "must have unordered successor"); | |
| 1434 __ jcc(Assembler::parity, *(op->ublock()->label())); | |
| 1435 switch(op->cond()) { | |
| 1436 case lir_cond_equal: acond = Assembler::equal; break; | |
| 1437 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
| 1438 case lir_cond_less: acond = Assembler::below; break; | |
| 1439 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; | |
| 1440 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; | |
| 1441 case lir_cond_greater: acond = Assembler::above; break; | |
| 1442 default: ShouldNotReachHere(); | |
| 1443 } | |
| 1444 } else { | |
| 1445 switch (op->cond()) { | |
| 1446 case lir_cond_equal: acond = Assembler::equal; break; | |
| 1447 case lir_cond_notEqual: acond = Assembler::notEqual; break; | |
| 1448 case lir_cond_less: acond = Assembler::less; break; | |
| 1449 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; | |
| 1450 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; | |
| 1451 case lir_cond_greater: acond = Assembler::greater; break; | |
| 1452 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; | |
| 1453 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; | |
| 1454 default: ShouldNotReachHere(); | |
| 1455 } | |
| 1456 } | |
| 1457 __ jcc(acond,*(op->label())); | |
| 1458 } | |
| 1459 } | |
| 1460 | |
| 1461 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { | |
| 1462 LIR_Opr src = op->in_opr(); | |
| 1463 LIR_Opr dest = op->result_opr(); | |
| 1464 | |
| 1465 switch (op->bytecode()) { | |
| 1466 case Bytecodes::_i2l: | |
| 304 | 1467 #ifdef _LP64 |
| 1468 __ movl2ptr(dest->as_register_lo(), src->as_register()); | |
| 1469 #else | |
| 0 | 1470 move_regs(src->as_register(), dest->as_register_lo()); |
| 1471 move_regs(src->as_register(), dest->as_register_hi()); | |
| 1472 __ sarl(dest->as_register_hi(), 31); | |
| 304 | 1473 #endif // LP64 |
| 0 | 1474 break; |
| 1475 | |
| 1476 case Bytecodes::_l2i: | |
| 1477 move_regs(src->as_register_lo(), dest->as_register()); | |
| 1478 break; | |
| 1479 | |
| 1480 case Bytecodes::_i2b: | |
| 1481 move_regs(src->as_register(), dest->as_register()); | |
| 1482 __ sign_extend_byte(dest->as_register()); | |
| 1483 break; | |
| 1484 | |
| 1485 case Bytecodes::_i2c: | |
| 1486 move_regs(src->as_register(), dest->as_register()); | |
| 1487 __ andl(dest->as_register(), 0xFFFF); | |
| 1488 break; | |
| 1489 | |
| 1490 case Bytecodes::_i2s: | |
| 1491 move_regs(src->as_register(), dest->as_register()); | |
| 1492 __ sign_extend_short(dest->as_register()); | |
| 1493 break; | |
| 1494 | |
| 1495 | |
| 1496 case Bytecodes::_f2d: | |
| 1497 case Bytecodes::_d2f: | |
| 1498 if (dest->is_single_xmm()) { | |
| 1499 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); | |
| 1500 } else if (dest->is_double_xmm()) { | |
| 1501 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); | |
| 1502 } else { | |
| 1503 assert(src->fpu() == dest->fpu(), "register must be equal"); | |
| 1504 // do nothing (float result is rounded later through spilling) | |
| 1505 } | |
| 1506 break; | |
| 1507 | |
| 1508 case Bytecodes::_i2f: | |
| 1509 case Bytecodes::_i2d: | |
| 1510 if (dest->is_single_xmm()) { | |
| 304 | 1511 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); |
| 0 | 1512 } else if (dest->is_double_xmm()) { |
| 304 | 1513 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); |
| 0 | 1514 } else { |
| 1515 assert(dest->fpu() == 0, "result must be on TOS"); | |
| 1516 __ movl(Address(rsp, 0), src->as_register()); | |
| 1517 __ fild_s(Address(rsp, 0)); | |
| 1518 } | |
| 1519 break; | |
| 1520 | |
| 1521 case Bytecodes::_f2i: | |
| 1522 case Bytecodes::_d2i: | |
| 1523 if (src->is_single_xmm()) { | |
| 304 | 1524 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); |
| 0 | 1525 } else if (src->is_double_xmm()) { |
| 304 | 1526 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); |
| 0 | 1527 } else { |
| 1528 assert(src->fpu() == 0, "input must be on TOS"); | |
| 1529 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); | |
| 1530 __ fist_s(Address(rsp, 0)); | |
| 1531 __ movl(dest->as_register(), Address(rsp, 0)); | |
| 1532 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); | |
| 1533 } | |
| 1534 | |
| 1535 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub | |
| 1536 assert(op->stub() != NULL, "stub required"); | |
| 1537 __ cmpl(dest->as_register(), 0x80000000); | |
| 1538 __ jcc(Assembler::equal, *op->stub()->entry()); | |
| 1539 __ bind(*op->stub()->continuation()); | |
| 1540 break; | |
| 1541 | |
| 1542 case Bytecodes::_l2f: | |
| 1543 case Bytecodes::_l2d: | |
| 1544 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); | |
| 1545 assert(dest->fpu() == 0, "result must be on TOS"); | |
| 1546 | |
| 304 | 1547 __ movptr(Address(rsp, 0), src->as_register_lo()); |
| 1548 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); | |
| 0 | 1549 __ fild_d(Address(rsp, 0)); |
| 1550 // float result is rounded later through spilling | |
| 1551 break; | |
| 1552 | |
| 1553 case Bytecodes::_f2l: | |
| 1554 case Bytecodes::_d2l: | |
| 1555 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); | |
| 1556 assert(src->fpu() == 0, "input must be on TOS"); | |
| 304 | 1557 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); |
| 0 | 1558 |
| 1559 // instruction sequence too long to inline it here | |
| 1560 { | |
| 1561 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); | |
| 1562 } | |
| 1563 break; | |
| 1564 | |
| 1565 default: ShouldNotReachHere(); | |
| 1566 } | |
| 1567 } | |
| 1568 | |
| 1569 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { | |
| 1570 if (op->init_check()) { | |
| 1571 __ cmpl(Address(op->klass()->as_register(), | |
| 1572 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), | |
| 1573 instanceKlass::fully_initialized); | |
| 1574 add_debug_info_for_null_check_here(op->stub()->info()); | |
| 1575 __ jcc(Assembler::notEqual, *op->stub()->entry()); | |
| 1576 } | |
| 1577 __ allocate_object(op->obj()->as_register(), | |
| 1578 op->tmp1()->as_register(), | |
| 1579 op->tmp2()->as_register(), | |
| 1580 op->header_size(), | |
| 1581 op->object_size(), | |
| 1582 op->klass()->as_register(), | |
| 1583 *op->stub()->entry()); | |
| 1584 __ bind(*op->stub()->continuation()); | |
| 1585 } | |
| 1586 | |
| 1587 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { | |
| 1588 if (UseSlowPath || | |
| 1589 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || | |
| 1590 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { | |
| 1591 __ jmp(*op->stub()->entry()); | |
| 1592 } else { | |
| 1593 Register len = op->len()->as_register(); | |
| 1594 Register tmp1 = op->tmp1()->as_register(); | |
| 1595 Register tmp2 = op->tmp2()->as_register(); | |
| 1596 Register tmp3 = op->tmp3()->as_register(); | |
| 1597 if (len == tmp1) { | |
| 1598 tmp1 = tmp3; | |
| 1599 } else if (len == tmp2) { | |
| 1600 tmp2 = tmp3; | |
| 1601 } else if (len == tmp3) { | |
| 1602 // everything is ok | |
| 1603 } else { | |
| 304 | 1604 __ mov(tmp3, len); |
| 0 | 1605 } |
| 1606 __ allocate_array(op->obj()->as_register(), | |
| 1607 len, | |
| 1608 tmp1, | |
| 1609 tmp2, | |
| 1610 arrayOopDesc::header_size(op->type()), | |
| 1611 array_element_size(op->type()), | |
| 1612 op->klass()->as_register(), | |
| 1613 *op->stub()->entry()); | |
| 1614 } | |
| 1615 __ bind(*op->stub()->continuation()); | |
| 1616 } | |
| 1617 | |
| 1783 | 1618 void LIR_Assembler::type_profile_helper(Register mdo, |
| 1619 ciMethodData *md, ciProfileData *data, | |
| 1620 Register recv, Label* update_done) { | |
|
1808
5511edd5d719
6988779: c1_LIRAssembler_x86.cpp crashes VS2010 compiler
iveresov
parents:
1791
diff
changeset
|
1621 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
| 1783 | 1622 Label next_test; |
| 1623 // See if the receiver is receiver[n]. | |
| 1624 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); | |
| 1625 __ jccb(Assembler::notEqual, next_test); | |
| 1626 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); | |
| 1627 __ addptr(data_addr, DataLayout::counter_increment); | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1628 __ jmp(*update_done); |
| 1783 | 1629 __ bind(next_test); |
| 1630 } | |
| 1631 | |
| 1632 // Didn't find receiver; find next empty slot and fill it in | |
|
1808
5511edd5d719
6988779: c1_LIRAssembler_x86.cpp crashes VS2010 compiler
iveresov
parents:
1791
diff
changeset
|
1633 for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { |
| 1783 | 1634 Label next_test; |
| 1635 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); | |
| 1636 __ cmpptr(recv_addr, (intptr_t)NULL_WORD); | |
| 1637 __ jccb(Assembler::notEqual, next_test); | |
| 1638 __ movptr(recv_addr, recv); | |
| 1639 __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1640 __ jmp(*update_done); |
| 1783 | 1641 __ bind(next_test); |
| 1642 } | |
| 1643 } | |
| 1644 | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1645 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { |
| 1783 | 1646 // we always need a stub for the failure case. |
| 1647 CodeStub* stub = op->stub(); | |
| 1648 Register obj = op->object()->as_register(); | |
| 1649 Register k_RInfo = op->tmp1()->as_register(); | |
| 1650 Register klass_RInfo = op->tmp2()->as_register(); | |
| 1651 Register dst = op->result_opr()->as_register(); | |
| 1652 ciKlass* k = op->klass(); | |
| 1653 Register Rtmp1 = noreg; | |
| 1654 | |
| 1655 // check if it needs to be profiled | |
| 1656 ciMethodData* md; | |
| 1657 ciProfileData* data; | |
| 1658 | |
| 1659 if (op->should_profile()) { | |
| 1660 ciMethod* method = op->profiled_method(); | |
| 1661 assert(method != NULL, "Should have method"); | |
| 1662 int bci = op->profiled_bci(); | |
| 1663 md = method->method_data(); | |
| 1664 if (md == NULL) { | |
| 1665 bailout("out of memory building methodDataOop"); | |
| 1666 return; | |
| 1667 } | |
| 1668 data = md->bci_to_data(bci); | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1669 assert(data != NULL, "need data for type check"); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1670 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
| 1783 | 1671 } |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1672 Label profile_cast_success, profile_cast_failure; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1673 Label *success_target = op->should_profile() ? &profile_cast_success : success; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1674 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; |
| 1783 | 1675 |
| 1676 if (obj == k_RInfo) { | |
| 1677 k_RInfo = dst; | |
| 1678 } else if (obj == klass_RInfo) { | |
| 1679 klass_RInfo = dst; | |
| 1680 } | |
| 1681 if (k->is_loaded()) { | |
| 1682 select_different_registers(obj, dst, k_RInfo, klass_RInfo); | |
| 1683 } else { | |
| 1684 Rtmp1 = op->tmp3()->as_register(); | |
| 1685 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); | |
| 1686 } | |
| 1687 | |
| 1688 assert_different_registers(obj, k_RInfo, klass_RInfo); | |
| 1689 if (!k->is_loaded()) { | |
| 1690 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); | |
| 1691 } else { | |
| 1692 #ifdef _LP64 | |
| 1693 __ movoop(k_RInfo, k->constant_encoding()); | |
| 1694 #endif // _LP64 | |
| 1695 } | |
| 1696 assert(obj != k_RInfo, "must be different"); | |
| 1697 | |
| 1698 __ cmpptr(obj, (int32_t)NULL_WORD); | |
| 1699 if (op->should_profile()) { | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1700 Label not_null; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1701 __ jccb(Assembler::notEqual, not_null); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1702 // Object is null; update MDO and exit |
| 1783 | 1703 Register mdo = klass_RInfo; |
| 1704 __ movoop(mdo, md->constant_encoding()); | |
| 1705 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); | |
| 1706 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); | |
| 1707 __ orl(data_addr, header_bits); | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1708 __ jmp(*obj_is_null); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1709 __ bind(not_null); |
| 1783 | 1710 } else { |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1711 __ jcc(Assembler::equal, *obj_is_null); |
| 1783 | 1712 } |
| 1713 __ verify_oop(obj); | |
| 1714 | |
| 1715 if (op->fast_check()) { | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1716 // get object class |
| 1783 | 1717 // not a safepoint as obj null check happens earlier |
| 1718 if (k->is_loaded()) { | |
| 1719 #ifdef _LP64 | |
| 1720 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
| 1721 #else | |
| 1722 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); | |
| 1723 #endif // _LP64 | |
| 1724 } else { | |
| 1725 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
| 1726 } | |
| 1727 __ jcc(Assembler::notEqual, *failure_target); | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1728 // successful cast, fall through to profile or jump |
| 1783 | 1729 } else { |
| 1730 // get object class | |
| 1731 // not a safepoint as obj null check happens earlier | |
| 1732 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); | |
| 1733 if (k->is_loaded()) { | |
| 1734 // See if we get an immediate positive hit | |
| 1735 #ifdef _LP64 | |
| 1736 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); | |
| 1737 #else | |
| 1738 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); | |
| 1739 #endif // _LP64 | |
| 1740 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { | |
| 1741 __ jcc(Assembler::notEqual, *failure_target); | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1742 // successful cast, fall through to profile or jump |
| 1783 | 1743 } else { |
| 1744 // See if we get an immediate positive hit | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1745 __ jcc(Assembler::equal, *success_target); |
| 1783 | 1746 // check for self |
| 1747 #ifdef _LP64 | |
| 1748 __ cmpptr(klass_RInfo, k_RInfo); | |
| 1749 #else | |
| 1750 __ cmpoop(klass_RInfo, k->constant_encoding()); | |
| 1751 #endif // _LP64 | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1752 __ jcc(Assembler::equal, *success_target); |
| 1783 | 1753 |
| 1754 __ push(klass_RInfo); | |
| 1755 #ifdef _LP64 | |
| 1756 __ push(k_RInfo); | |
| 1757 #else | |
| 1758 __ pushoop(k->constant_encoding()); | |
| 1759 #endif // _LP64 | |
| 1760 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
| 1761 __ pop(klass_RInfo); | |
| 1762 __ pop(klass_RInfo); | |
| 1763 // result is a boolean | |
| 1764 __ cmpl(klass_RInfo, 0); | |
| 1765 __ jcc(Assembler::equal, *failure_target); | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1766 // successful cast, fall through to profile or jump |
| 1783 | 1767 } |
| 1768 } else { | |
| 1769 // perform the fast part of the checking logic | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1770 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
| 1783 | 1771 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
| 1772 __ push(klass_RInfo); | |
| 1773 __ push(k_RInfo); | |
| 1774 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); | |
| 1775 __ pop(klass_RInfo); | |
| 1776 __ pop(k_RInfo); | |
| 1777 // result is a boolean | |
| 1778 __ cmpl(k_RInfo, 0); | |
| 1779 __ jcc(Assembler::equal, *failure_target); | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1780 // successful cast, fall through to profile or jump |
| 1783 | 1781 } |
| 1782 } | |
| 1783 if (op->should_profile()) { | |
| 1784 Register mdo = klass_RInfo, recv = k_RInfo; | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1785 __ bind(profile_cast_success); |
| 1783 | 1786 __ movoop(mdo, md->constant_encoding()); |
| 1787 __ movptr(recv, Address(obj, oopDesc::klass_offset_in_bytes())); | |
| 1788 Label update_done; | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1789 type_profile_helper(mdo, md, data, recv, success); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1790 __ jmp(*success); |
| 1783 | 1791 |
| 1792 __ bind(profile_cast_failure); | |
| 1793 __ movoop(mdo, md->constant_encoding()); | |
| 1794 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); | |
| 1795 __ subptr(counter_addr, DataLayout::counter_increment); | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1796 __ jmp(*failure); |
| 1783 | 1797 } |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1798 __ jmp(*success); |
| 1783 | 1799 } |
| 0 | 1800 |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1801 |
| 0 | 1802 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { |
| 1803 LIR_Code code = op->code(); | |
| 1804 if (code == lir_store_check) { | |
| 1805 Register value = op->object()->as_register(); | |
| 1806 Register array = op->array()->as_register(); | |
| 1807 Register k_RInfo = op->tmp1()->as_register(); | |
| 1808 Register klass_RInfo = op->tmp2()->as_register(); | |
| 1809 Register Rtmp1 = op->tmp3()->as_register(); | |
| 1810 | |
| 1811 CodeStub* stub = op->stub(); | |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1812 |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1813 // check if it needs to be profiled |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1814 ciMethodData* md; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1815 ciProfileData* data; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1816 |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1817 if (op->should_profile()) { |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1818 ciMethod* method = op->profiled_method(); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1819 assert(method != NULL, "Should have method"); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1820 int bci = op->profiled_bci(); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1821 md = method->method_data(); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1822 if (md == NULL) { |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1823 bailout("out of memory building methodDataOop"); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1824 return; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1825 } |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1826 data = md->bci_to_data(bci); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1827 assert(data != NULL, "need data for type check"); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1828 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1829 } |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1830 Label profile_cast_success, profile_cast_failure, done; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1831 Label *success_target = op->should_profile() ? &profile_cast_success : &done; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1832 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1833 |
| 304 | 1834 __ cmpptr(value, (int32_t)NULL_WORD); |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1835 if (op->should_profile()) { |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1836 Label not_null; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1837 __ jccb(Assembler::notEqual, not_null); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1838 // Object is null; update MDO and exit |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1839 Register mdo = klass_RInfo; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1840 __ movoop(mdo, md->constant_encoding()); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1841 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1842 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1843 __ orl(data_addr, header_bits); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1844 __ jmp(done); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1845 __ bind(not_null); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1846 } else { |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1847 __ jcc(Assembler::equal, done); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1848 } |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1849 |
| 0 | 1850 add_debug_info_for_null_check_here(op->info_for_exception()); |
| 304 | 1851 __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes())); |
| 1852 __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes())); | |
| 0 | 1853 |
| 1854 // get instance klass | |
| 304 | 1855 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
622
diff
changeset
|
1856 // perform the fast part of the checking logic |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1857 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
622
diff
changeset
|
1858 // call out-of-line instance of __ check_klass_subtype_slow_path(...): |
| 304 | 1859 __ push(klass_RInfo); |
| 1860 __ push(k_RInfo); | |
| 0 | 1861 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); |
| 304 | 1862 __ pop(klass_RInfo); |
| 1863 __ pop(k_RInfo); | |
| 1864 // result is a boolean | |
| 0 | 1865 __ cmpl(k_RInfo, 0); |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1866 __ jcc(Assembler::equal, *failure_target); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1867 // fall through to the success case |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1868 |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1869 if (op->should_profile()) { |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1870 Register mdo = klass_RInfo, recv = k_RInfo; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1871 __ bind(profile_cast_success); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1872 __ movoop(mdo, md->constant_encoding()); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1873 __ movptr(recv, Address(value, oopDesc::klass_offset_in_bytes())); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1874 Label update_done; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1875 type_profile_helper(mdo, md, data, recv, &done); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1876 __ jmpb(done); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1877 |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1878 __ bind(profile_cast_failure); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1879 __ movoop(mdo, md->constant_encoding()); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1880 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1881 __ subptr(counter_addr, DataLayout::counter_increment); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1882 __ jmp(*stub->entry()); |
| 0 | 1883 } |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1884 |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1885 __ bind(done); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1886 } else |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1887 if (code == lir_checkcast) { |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1888 Register obj = op->object()->as_register(); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1889 Register dst = op->result_opr()->as_register(); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1890 Label success; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1891 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1892 __ bind(success); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1893 if (dst != obj) { |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1894 __ mov(dst, obj); |
| 0 | 1895 } |
|
1791
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1896 } else |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1897 if (code == lir_instanceof) { |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1898 Register obj = op->object()->as_register(); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1899 Register dst = op->result_opr()->as_register(); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1900 Label success, failure, done; |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1901 emit_typecheck_helper(op, &success, &failure, &failure); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1902 __ bind(failure); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1903 __ xorptr(dst, dst); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1904 __ jmpb(done); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1905 __ bind(success); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1906 __ movptr(dst, 1); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1907 __ bind(done); |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1908 } else { |
|
3a294e483abc
6919069: client compiler needs to capture more profile information for tiered work
iveresov
parents:
1790
diff
changeset
|
1909 ShouldNotReachHere(); |
|
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
622
diff
changeset
|
1910 } |
| 0 | 1911 |
| 1912 } | |
| 1913 | |
| 1914 | |
| 1915 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { | |
| 304 | 1916 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { |
| 0 | 1917 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); |
| 1918 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); | |
| 1919 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); | |
| 1920 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); | |
| 1921 Register addr = op->addr()->as_register(); | |
| 1922 if (os::is_MP()) { | |
| 1923 __ lock(); | |
| 1924 } | |
| 304 | 1925 NOT_LP64(__ cmpxchg8(Address(addr, 0))); |
| 1926 | |
| 1927 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { | |
| 1928 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) | |
| 1929 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
| 0 | 1930 Register newval = op->new_value()->as_register(); |
| 1931 Register cmpval = op->cmp_value()->as_register(); | |
| 1932 assert(cmpval == rax, "wrong register"); | |
| 1933 assert(newval != NULL, "new val must be register"); | |
| 1934 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
| 1935 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
| 1936 assert(newval != addr, "new value and addr must be in different registers"); | |
| 1937 if (os::is_MP()) { | |
| 1938 __ lock(); | |
| 1939 } | |
| 304 | 1940 if ( op->code() == lir_cas_obj) { |
| 1941 __ cmpxchgptr(newval, Address(addr, 0)); | |
| 1942 } else if (op->code() == lir_cas_int) { | |
| 1943 __ cmpxchgl(newval, Address(addr, 0)); | |
| 1944 } else { | |
| 1945 LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0))); | |
| 1946 } | |
| 1947 #ifdef _LP64 | |
| 1948 } else if (op->code() == lir_cas_long) { | |
| 1949 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); | |
| 1950 Register newval = op->new_value()->as_register_lo(); | |
| 1951 Register cmpval = op->cmp_value()->as_register_lo(); | |
| 1952 assert(cmpval == rax, "wrong register"); | |
| 1953 assert(newval != NULL, "new val must be register"); | |
| 1954 assert(cmpval != newval, "cmp and new values must be in different registers"); | |
| 1955 assert(cmpval != addr, "cmp and addr must be in different registers"); | |
| 1956 assert(newval != addr, "new value and addr must be in different registers"); | |
| 1957 if (os::is_MP()) { | |
| 1958 __ lock(); | |
| 1959 } | |
| 1960 __ cmpxchgq(newval, Address(addr, 0)); | |
| 1961 #endif // _LP64 | |
| 0 | 1962 } else { |
| 1963 Unimplemented(); | |
| 1964 } | |
| 1965 } | |
| 1966 | |
| 1967 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { | |
| 1968 Assembler::Condition acond, ncond; | |
| 1969 switch (condition) { | |
| 1970 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; | |
| 1971 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; | |
| 1972 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; | |
| 1973 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; | |
| 1974 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; | |
| 1975 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; | |
| 1976 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; | |
| 1977 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; | |
| 1978 default: ShouldNotReachHere(); | |
| 1979 } | |
| 1980 | |
| 1981 if (opr1->is_cpu_register()) { | |
| 1982 reg2reg(opr1, result); | |
| 1983 } else if (opr1->is_stack()) { | |
| 1984 stack2reg(opr1, result, result->type()); | |
| 1985 } else if (opr1->is_constant()) { | |
| 1986 const2reg(opr1, result, lir_patch_none, NULL); | |
| 1987 } else { | |
| 1988 ShouldNotReachHere(); | |
| 1989 } | |
| 1990 | |
| 1991 if (VM_Version::supports_cmov() && !opr2->is_constant()) { | |
| 1992 // optimized version that does not require a branch | |
| 1993 if (opr2->is_single_cpu()) { | |
| 1994 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); | |
| 304 | 1995 __ cmov(ncond, result->as_register(), opr2->as_register()); |
| 0 | 1996 } else if (opr2->is_double_cpu()) { |
| 1997 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
| 1998 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); | |
| 304 | 1999 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); |
| 2000 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) | |
| 0 | 2001 } else if (opr2->is_single_stack()) { |
| 2002 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2003 } else if (opr2->is_double_stack()) { | |
| 304 | 2004 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); |
| 2005 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) | |
| 0 | 2006 } else { |
| 2007 ShouldNotReachHere(); | |
| 2008 } | |
| 2009 | |
| 2010 } else { | |
| 2011 Label skip; | |
| 2012 __ jcc (acond, skip); | |
| 2013 if (opr2->is_cpu_register()) { | |
| 2014 reg2reg(opr2, result); | |
| 2015 } else if (opr2->is_stack()) { | |
| 2016 stack2reg(opr2, result, result->type()); | |
| 2017 } else if (opr2->is_constant()) { | |
| 2018 const2reg(opr2, result, lir_patch_none, NULL); | |
| 2019 } else { | |
| 2020 ShouldNotReachHere(); | |
| 2021 } | |
| 2022 __ bind(skip); | |
| 2023 } | |
| 2024 } | |
| 2025 | |
| 2026 | |
| 2027 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { | |
| 2028 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); | |
| 2029 | |
| 2030 if (left->is_single_cpu()) { | |
| 2031 assert(left == dest, "left and dest must be equal"); | |
| 2032 Register lreg = left->as_register(); | |
| 2033 | |
| 2034 if (right->is_single_cpu()) { | |
| 2035 // cpu register - cpu register | |
| 2036 Register rreg = right->as_register(); | |
| 2037 switch (code) { | |
| 2038 case lir_add: __ addl (lreg, rreg); break; | |
| 2039 case lir_sub: __ subl (lreg, rreg); break; | |
| 2040 case lir_mul: __ imull(lreg, rreg); break; | |
| 2041 default: ShouldNotReachHere(); | |
| 2042 } | |
| 2043 | |
| 2044 } else if (right->is_stack()) { | |
| 2045 // cpu register - stack | |
| 2046 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2047 switch (code) { | |
| 2048 case lir_add: __ addl(lreg, raddr); break; | |
| 2049 case lir_sub: __ subl(lreg, raddr); break; | |
| 2050 default: ShouldNotReachHere(); | |
| 2051 } | |
| 2052 | |
| 2053 } else if (right->is_constant()) { | |
| 2054 // cpu register - constant | |
| 2055 jint c = right->as_constant_ptr()->as_jint(); | |
| 2056 switch (code) { | |
| 2057 case lir_add: { | |
|
1790
7f9553bedfd5
6984056: C1: incorrect code for integer constant addition on x64
iveresov
parents:
1783
diff
changeset
|
2058 __ incrementl(lreg, c); |
| 0 | 2059 break; |
| 2060 } | |
| 2061 case lir_sub: { | |
|
1790
7f9553bedfd5
6984056: C1: incorrect code for integer constant addition on x64
iveresov
parents:
1783
diff
changeset
|
2062 __ decrementl(lreg, c); |
| 0 | 2063 break; |
| 2064 } | |
| 2065 default: ShouldNotReachHere(); | |
| 2066 } | |
| 2067 | |
| 2068 } else { | |
| 2069 ShouldNotReachHere(); | |
| 2070 } | |
| 2071 | |
| 2072 } else if (left->is_double_cpu()) { | |
| 2073 assert(left == dest, "left and dest must be equal"); | |
| 2074 Register lreg_lo = left->as_register_lo(); | |
| 2075 Register lreg_hi = left->as_register_hi(); | |
| 2076 | |
| 2077 if (right->is_double_cpu()) { | |
| 2078 // cpu register - cpu register | |
| 2079 Register rreg_lo = right->as_register_lo(); | |
| 2080 Register rreg_hi = right->as_register_hi(); | |
| 304 | 2081 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); |
| 2082 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); | |
| 0 | 2083 switch (code) { |
| 2084 case lir_add: | |
| 304 | 2085 __ addptr(lreg_lo, rreg_lo); |
| 2086 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); | |
| 0 | 2087 break; |
| 2088 case lir_sub: | |
| 304 | 2089 __ subptr(lreg_lo, rreg_lo); |
| 2090 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); | |
| 0 | 2091 break; |
| 2092 case lir_mul: | |
| 304 | 2093 #ifdef _LP64 |
| 2094 __ imulq(lreg_lo, rreg_lo); | |
| 2095 #else | |
| 0 | 2096 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); |
| 2097 __ imull(lreg_hi, rreg_lo); | |
| 2098 __ imull(rreg_hi, lreg_lo); | |
| 2099 __ addl (rreg_hi, lreg_hi); | |
| 2100 __ mull (rreg_lo); | |
| 2101 __ addl (lreg_hi, rreg_hi); | |
| 304 | 2102 #endif // _LP64 |
| 0 | 2103 break; |
| 2104 default: | |
| 2105 ShouldNotReachHere(); | |
| 2106 } | |
| 2107 | |
| 2108 } else if (right->is_constant()) { | |
| 2109 // cpu register - constant | |
| 304 | 2110 #ifdef _LP64 |
| 2111 jlong c = right->as_constant_ptr()->as_jlong_bits(); | |
| 2112 __ movptr(r10, (intptr_t) c); | |
| 2113 switch (code) { | |
| 2114 case lir_add: | |
| 2115 __ addptr(lreg_lo, r10); | |
| 2116 break; | |
| 2117 case lir_sub: | |
| 2118 __ subptr(lreg_lo, r10); | |
| 2119 break; | |
| 2120 default: | |
| 2121 ShouldNotReachHere(); | |
| 2122 } | |
| 2123 #else | |
| 0 | 2124 jint c_lo = right->as_constant_ptr()->as_jint_lo(); |
| 2125 jint c_hi = right->as_constant_ptr()->as_jint_hi(); | |
| 2126 switch (code) { | |
| 2127 case lir_add: | |
| 304 | 2128 __ addptr(lreg_lo, c_lo); |
| 0 | 2129 __ adcl(lreg_hi, c_hi); |
| 2130 break; | |
| 2131 case lir_sub: | |
| 304 | 2132 __ subptr(lreg_lo, c_lo); |
| 0 | 2133 __ sbbl(lreg_hi, c_hi); |
| 2134 break; | |
| 2135 default: | |
| 2136 ShouldNotReachHere(); | |
| 2137 } | |
| 304 | 2138 #endif // _LP64 |
| 0 | 2139 |
| 2140 } else { | |
| 2141 ShouldNotReachHere(); | |
| 2142 } | |
| 2143 | |
| 2144 } else if (left->is_single_xmm()) { | |
| 2145 assert(left == dest, "left and dest must be equal"); | |
| 2146 XMMRegister lreg = left->as_xmm_float_reg(); | |
| 2147 | |
| 2148 if (right->is_single_xmm()) { | |
| 2149 XMMRegister rreg = right->as_xmm_float_reg(); | |
| 2150 switch (code) { | |
| 2151 case lir_add: __ addss(lreg, rreg); break; | |
| 2152 case lir_sub: __ subss(lreg, rreg); break; | |
| 2153 case lir_mul_strictfp: // fall through | |
| 2154 case lir_mul: __ mulss(lreg, rreg); break; | |
| 2155 case lir_div_strictfp: // fall through | |
| 2156 case lir_div: __ divss(lreg, rreg); break; | |
| 2157 default: ShouldNotReachHere(); | |
| 2158 } | |
| 2159 } else { | |
| 2160 Address raddr; | |
| 2161 if (right->is_single_stack()) { | |
| 2162 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2163 } else if (right->is_constant()) { | |
| 2164 // hack for now | |
| 2165 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); | |
| 2166 } else { | |
| 2167 ShouldNotReachHere(); | |
| 2168 } | |
| 2169 switch (code) { | |
| 2170 case lir_add: __ addss(lreg, raddr); break; | |
| 2171 case lir_sub: __ subss(lreg, raddr); break; | |
| 2172 case lir_mul_strictfp: // fall through | |
| 2173 case lir_mul: __ mulss(lreg, raddr); break; | |
| 2174 case lir_div_strictfp: // fall through | |
| 2175 case lir_div: __ divss(lreg, raddr); break; | |
| 2176 default: ShouldNotReachHere(); | |
| 2177 } | |
| 2178 } | |
| 2179 | |
| 2180 } else if (left->is_double_xmm()) { | |
| 2181 assert(left == dest, "left and dest must be equal"); | |
| 2182 | |
| 2183 XMMRegister lreg = left->as_xmm_double_reg(); | |
| 2184 if (right->is_double_xmm()) { | |
| 2185 XMMRegister rreg = right->as_xmm_double_reg(); | |
| 2186 switch (code) { | |
| 2187 case lir_add: __ addsd(lreg, rreg); break; | |
| 2188 case lir_sub: __ subsd(lreg, rreg); break; | |
| 2189 case lir_mul_strictfp: // fall through | |
| 2190 case lir_mul: __ mulsd(lreg, rreg); break; | |
| 2191 case lir_div_strictfp: // fall through | |
| 2192 case lir_div: __ divsd(lreg, rreg); break; | |
| 2193 default: ShouldNotReachHere(); | |
| 2194 } | |
| 2195 } else { | |
| 2196 Address raddr; | |
| 2197 if (right->is_double_stack()) { | |
| 2198 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
| 2199 } else if (right->is_constant()) { | |
| 2200 // hack for now | |
| 2201 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
| 2202 } else { | |
| 2203 ShouldNotReachHere(); | |
| 2204 } | |
| 2205 switch (code) { | |
| 2206 case lir_add: __ addsd(lreg, raddr); break; | |
| 2207 case lir_sub: __ subsd(lreg, raddr); break; | |
| 2208 case lir_mul_strictfp: // fall through | |
| 2209 case lir_mul: __ mulsd(lreg, raddr); break; | |
| 2210 case lir_div_strictfp: // fall through | |
| 2211 case lir_div: __ divsd(lreg, raddr); break; | |
| 2212 default: ShouldNotReachHere(); | |
| 2213 } | |
| 2214 } | |
| 2215 | |
| 2216 } else if (left->is_single_fpu()) { | |
| 2217 assert(dest->is_single_fpu(), "fpu stack allocation required"); | |
| 2218 | |
| 2219 if (right->is_single_fpu()) { | |
| 2220 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); | |
| 2221 | |
| 2222 } else { | |
| 2223 assert(left->fpu_regnr() == 0, "left must be on TOS"); | |
| 2224 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); | |
| 2225 | |
| 2226 Address raddr; | |
| 2227 if (right->is_single_stack()) { | |
| 2228 raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2229 } else if (right->is_constant()) { | |
| 2230 address const_addr = float_constant(right->as_jfloat()); | |
| 2231 assert(const_addr != NULL, "incorrect float/double constant maintainance"); | |
| 2232 // hack for now | |
| 2233 raddr = __ as_Address(InternalAddress(const_addr)); | |
| 2234 } else { | |
| 2235 ShouldNotReachHere(); | |
| 2236 } | |
| 2237 | |
| 2238 switch (code) { | |
| 2239 case lir_add: __ fadd_s(raddr); break; | |
| 2240 case lir_sub: __ fsub_s(raddr); break; | |
| 2241 case lir_mul_strictfp: // fall through | |
| 2242 case lir_mul: __ fmul_s(raddr); break; | |
| 2243 case lir_div_strictfp: // fall through | |
| 2244 case lir_div: __ fdiv_s(raddr); break; | |
| 2245 default: ShouldNotReachHere(); | |
| 2246 } | |
| 2247 } | |
| 2248 | |
| 2249 } else if (left->is_double_fpu()) { | |
| 2250 assert(dest->is_double_fpu(), "fpu stack allocation required"); | |
| 2251 | |
| 2252 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
| 2253 // Double values require special handling for strictfp mul/div on x86 | |
| 2254 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); | |
| 2255 __ fmulp(left->fpu_regnrLo() + 1); | |
| 2256 } | |
| 2257 | |
| 2258 if (right->is_double_fpu()) { | |
| 2259 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); | |
| 2260 | |
| 2261 } else { | |
| 2262 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); | |
| 2263 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); | |
| 2264 | |
| 2265 Address raddr; | |
| 2266 if (right->is_double_stack()) { | |
| 2267 raddr = frame_map()->address_for_slot(right->double_stack_ix()); | |
| 2268 } else if (right->is_constant()) { | |
| 2269 // hack for now | |
| 2270 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); | |
| 2271 } else { | |
| 2272 ShouldNotReachHere(); | |
| 2273 } | |
| 2274 | |
| 2275 switch (code) { | |
| 2276 case lir_add: __ fadd_d(raddr); break; | |
| 2277 case lir_sub: __ fsub_d(raddr); break; | |
| 2278 case lir_mul_strictfp: // fall through | |
| 2279 case lir_mul: __ fmul_d(raddr); break; | |
| 2280 case lir_div_strictfp: // fall through | |
| 2281 case lir_div: __ fdiv_d(raddr); break; | |
| 2282 default: ShouldNotReachHere(); | |
| 2283 } | |
| 2284 } | |
| 2285 | |
| 2286 if (code == lir_mul_strictfp || code == lir_div_strictfp) { | |
| 2287 // Double values require special handling for strictfp mul/div on x86 | |
| 2288 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); | |
| 2289 __ fmulp(dest->fpu_regnrLo() + 1); | |
| 2290 } | |
| 2291 | |
| 2292 } else if (left->is_single_stack() || left->is_address()) { | |
| 2293 assert(left == dest, "left and dest must be equal"); | |
| 2294 | |
| 2295 Address laddr; | |
| 2296 if (left->is_single_stack()) { | |
| 2297 laddr = frame_map()->address_for_slot(left->single_stack_ix()); | |
| 2298 } else if (left->is_address()) { | |
| 2299 laddr = as_Address(left->as_address_ptr()); | |
| 2300 } else { | |
| 2301 ShouldNotReachHere(); | |
| 2302 } | |
| 2303 | |
| 2304 if (right->is_single_cpu()) { | |
| 2305 Register rreg = right->as_register(); | |
| 2306 switch (code) { | |
| 2307 case lir_add: __ addl(laddr, rreg); break; | |
| 2308 case lir_sub: __ subl(laddr, rreg); break; | |
| 2309 default: ShouldNotReachHere(); | |
| 2310 } | |
| 2311 } else if (right->is_constant()) { | |
| 2312 jint c = right->as_constant_ptr()->as_jint(); | |
| 2313 switch (code) { | |
| 2314 case lir_add: { | |
| 304 | 2315 __ incrementl(laddr, c); |
| 0 | 2316 break; |
| 2317 } | |
| 2318 case lir_sub: { | |
| 304 | 2319 __ decrementl(laddr, c); |
| 0 | 2320 break; |
| 2321 } | |
| 2322 default: ShouldNotReachHere(); | |
| 2323 } | |
| 2324 } else { | |
| 2325 ShouldNotReachHere(); | |
| 2326 } | |
| 2327 | |
| 2328 } else { | |
| 2329 ShouldNotReachHere(); | |
| 2330 } | |
| 2331 } | |
| 2332 | |
| 2333 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { | |
| 2334 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); | |
| 2335 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); | |
| 2336 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); | |
| 2337 | |
| 2338 bool left_is_tos = (left_index == 0); | |
| 2339 bool dest_is_tos = (dest_index == 0); | |
| 2340 int non_tos_index = (left_is_tos ? right_index : left_index); | |
| 2341 | |
| 2342 switch (code) { | |
| 2343 case lir_add: | |
| 2344 if (pop_fpu_stack) __ faddp(non_tos_index); | |
| 2345 else if (dest_is_tos) __ fadd (non_tos_index); | |
| 2346 else __ fadda(non_tos_index); | |
| 2347 break; | |
| 2348 | |
| 2349 case lir_sub: | |
| 2350 if (left_is_tos) { | |
| 2351 if (pop_fpu_stack) __ fsubrp(non_tos_index); | |
| 2352 else if (dest_is_tos) __ fsub (non_tos_index); | |
| 2353 else __ fsubra(non_tos_index); | |
| 2354 } else { | |
| 2355 if (pop_fpu_stack) __ fsubp (non_tos_index); | |
| 2356 else if (dest_is_tos) __ fsubr (non_tos_index); | |
| 2357 else __ fsuba (non_tos_index); | |
| 2358 } | |
| 2359 break; | |
| 2360 | |
| 2361 case lir_mul_strictfp: // fall through | |
| 2362 case lir_mul: | |
| 2363 if (pop_fpu_stack) __ fmulp(non_tos_index); | |
| 2364 else if (dest_is_tos) __ fmul (non_tos_index); | |
| 2365 else __ fmula(non_tos_index); | |
| 2366 break; | |
| 2367 | |
| 2368 case lir_div_strictfp: // fall through | |
| 2369 case lir_div: | |
| 2370 if (left_is_tos) { | |
| 2371 if (pop_fpu_stack) __ fdivrp(non_tos_index); | |
| 2372 else if (dest_is_tos) __ fdiv (non_tos_index); | |
| 2373 else __ fdivra(non_tos_index); | |
| 2374 } else { | |
| 2375 if (pop_fpu_stack) __ fdivp (non_tos_index); | |
| 2376 else if (dest_is_tos) __ fdivr (non_tos_index); | |
| 2377 else __ fdiva (non_tos_index); | |
| 2378 } | |
| 2379 break; | |
| 2380 | |
| 2381 case lir_rem: | |
| 2382 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); | |
| 2383 __ fremr(noreg); | |
| 2384 break; | |
| 2385 | |
| 2386 default: | |
| 2387 ShouldNotReachHere(); | |
| 2388 } | |
| 2389 } | |
| 2390 | |
| 2391 | |
| 2392 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { | |
| 2393 if (value->is_double_xmm()) { | |
| 2394 switch(code) { | |
| 2395 case lir_abs : | |
| 2396 { | |
| 2397 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { | |
| 2398 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); | |
| 2399 } | |
| 2400 __ andpd(dest->as_xmm_double_reg(), | |
| 2401 ExternalAddress((address)double_signmask_pool)); | |
| 2402 } | |
| 2403 break; | |
| 2404 | |
| 2405 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; | |
| 2406 // all other intrinsics are not available in the SSE instruction set, so FPU is used | |
| 2407 default : ShouldNotReachHere(); | |
| 2408 } | |
| 2409 | |
| 2410 } else if (value->is_double_fpu()) { | |
| 2411 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); | |
| 2412 switch(code) { | |
| 2413 case lir_log : __ flog() ; break; | |
| 2414 case lir_log10 : __ flog10() ; break; | |
| 2415 case lir_abs : __ fabs() ; break; | |
| 2416 case lir_sqrt : __ fsqrt(); break; | |
| 2417 case lir_sin : | |
| 2418 // Should consider not saving rbx, if not necessary | |
| 2419 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); | |
| 2420 break; | |
| 2421 case lir_cos : | |
| 2422 // Should consider not saving rbx, if not necessary | |
| 2423 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); | |
| 2424 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); | |
| 2425 break; | |
| 2426 case lir_tan : | |
| 2427 // Should consider not saving rbx, if not necessary | |
| 2428 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); | |
| 2429 break; | |
| 2430 default : ShouldNotReachHere(); | |
| 2431 } | |
| 2432 } else { | |
| 2433 Unimplemented(); | |
| 2434 } | |
| 2435 } | |
| 2436 | |
| 2437 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { | |
| 2438 // assert(left->destroys_register(), "check"); | |
| 2439 if (left->is_single_cpu()) { | |
| 2440 Register reg = left->as_register(); | |
| 2441 if (right->is_constant()) { | |
| 2442 int val = right->as_constant_ptr()->as_jint(); | |
| 2443 switch (code) { | |
| 2444 case lir_logic_and: __ andl (reg, val); break; | |
| 2445 case lir_logic_or: __ orl (reg, val); break; | |
| 2446 case lir_logic_xor: __ xorl (reg, val); break; | |
| 2447 default: ShouldNotReachHere(); | |
| 2448 } | |
| 2449 } else if (right->is_stack()) { | |
| 2450 // added support for stack operands | |
| 2451 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); | |
| 2452 switch (code) { | |
| 2453 case lir_logic_and: __ andl (reg, raddr); break; | |
| 2454 case lir_logic_or: __ orl (reg, raddr); break; | |
| 2455 case lir_logic_xor: __ xorl (reg, raddr); break; | |
| 2456 default: ShouldNotReachHere(); | |
| 2457 } | |
| 2458 } else { | |
| 2459 Register rright = right->as_register(); | |
| 2460 switch (code) { | |
| 304 | 2461 case lir_logic_and: __ andptr (reg, rright); break; |
| 2462 case lir_logic_or : __ orptr (reg, rright); break; | |
| 2463 case lir_logic_xor: __ xorptr (reg, rright); break; | |
| 0 | 2464 default: ShouldNotReachHere(); |
| 2465 } | |
| 2466 } | |
| 2467 move_regs(reg, dst->as_register()); | |
| 2468 } else { | |
| 2469 Register l_lo = left->as_register_lo(); | |
| 2470 Register l_hi = left->as_register_hi(); | |
| 2471 if (right->is_constant()) { | |
| 304 | 2472 #ifdef _LP64 |
| 2473 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); | |
| 2474 switch (code) { | |
| 2475 case lir_logic_and: | |
| 2476 __ andq(l_lo, rscratch1); | |
| 2477 break; | |
| 2478 case lir_logic_or: | |
| 2479 __ orq(l_lo, rscratch1); | |
| 2480 break; | |
| 2481 case lir_logic_xor: | |
| 2482 __ xorq(l_lo, rscratch1); | |
| 2483 break; | |
| 2484 default: ShouldNotReachHere(); | |
| 2485 } | |
| 2486 #else | |
| 0 | 2487 int r_lo = right->as_constant_ptr()->as_jint_lo(); |
| 2488 int r_hi = right->as_constant_ptr()->as_jint_hi(); | |
| 2489 switch (code) { | |
| 2490 case lir_logic_and: | |
| 2491 __ andl(l_lo, r_lo); | |
| 2492 __ andl(l_hi, r_hi); | |
| 2493 break; | |
| 2494 case lir_logic_or: | |
| 2495 __ orl(l_lo, r_lo); | |
| 2496 __ orl(l_hi, r_hi); | |
| 2497 break; | |
| 2498 case lir_logic_xor: | |
| 2499 __ xorl(l_lo, r_lo); | |
| 2500 __ xorl(l_hi, r_hi); | |
| 2501 break; | |
| 2502 default: ShouldNotReachHere(); | |
| 2503 } | |
| 304 | 2504 #endif // _LP64 |
| 0 | 2505 } else { |
| 1572 | 2506 #ifdef _LP64 |
| 2507 Register r_lo; | |
| 2508 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { | |
| 2509 r_lo = right->as_register(); | |
| 2510 } else { | |
| 2511 r_lo = right->as_register_lo(); | |
| 2512 } | |
| 2513 #else | |
| 0 | 2514 Register r_lo = right->as_register_lo(); |
| 2515 Register r_hi = right->as_register_hi(); | |
| 2516 assert(l_lo != r_hi, "overwriting registers"); | |
| 1572 | 2517 #endif |
| 0 | 2518 switch (code) { |
| 2519 case lir_logic_and: | |
| 304 | 2520 __ andptr(l_lo, r_lo); |
| 2521 NOT_LP64(__ andptr(l_hi, r_hi);) | |
| 0 | 2522 break; |
| 2523 case lir_logic_or: | |
| 304 | 2524 __ orptr(l_lo, r_lo); |
| 2525 NOT_LP64(__ orptr(l_hi, r_hi);) | |
| 0 | 2526 break; |
| 2527 case lir_logic_xor: | |
| 304 | 2528 __ xorptr(l_lo, r_lo); |
| 2529 NOT_LP64(__ xorptr(l_hi, r_hi);) | |
| 0 | 2530 break; |
| 2531 default: ShouldNotReachHere(); | |
| 2532 } | |
| 2533 } | |
| 2534 | |
| 2535 Register dst_lo = dst->as_register_lo(); | |
| 2536 Register dst_hi = dst->as_register_hi(); | |
| 2537 | |
| 304 | 2538 #ifdef _LP64 |
| 2539 move_regs(l_lo, dst_lo); | |
| 2540 #else | |
| 0 | 2541 if (dst_lo == l_hi) { |
| 2542 assert(dst_hi != l_lo, "overwriting registers"); | |
| 2543 move_regs(l_hi, dst_hi); | |
| 2544 move_regs(l_lo, dst_lo); | |
| 2545 } else { | |
| 2546 assert(dst_lo != l_hi, "overwriting registers"); | |
| 2547 move_regs(l_lo, dst_lo); | |
| 2548 move_regs(l_hi, dst_hi); | |
| 2549 } | |
| 304 | 2550 #endif // _LP64 |
| 0 | 2551 } |
| 2552 } | |
| 2553 | |
| 2554 | |
| 2555 // we assume that rax, and rdx can be overwritten | |
| 2556 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { | |
| 2557 | |
| 2558 assert(left->is_single_cpu(), "left must be register"); | |
| 2559 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); | |
| 2560 assert(result->is_single_cpu(), "result must be register"); | |
| 2561 | |
| 2562 // assert(left->destroys_register(), "check"); | |
| 2563 // assert(right->destroys_register(), "check"); | |
| 2564 | |
| 2565 Register lreg = left->as_register(); | |
| 2566 Register dreg = result->as_register(); | |
| 2567 | |
| 2568 if (right->is_constant()) { | |
| 2569 int divisor = right->as_constant_ptr()->as_jint(); | |
| 2570 assert(divisor > 0 && is_power_of_2(divisor), "must be"); | |
| 2571 if (code == lir_idiv) { | |
| 2572 assert(lreg == rax, "must be rax,"); | |
| 2573 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
| 2574 __ cdql(); // sign extend into rdx:rax | |
| 2575 if (divisor == 2) { | |
| 2576 __ subl(lreg, rdx); | |
| 2577 } else { | |
| 2578 __ andl(rdx, divisor - 1); | |
| 2579 __ addl(lreg, rdx); | |
| 2580 } | |
| 2581 __ sarl(lreg, log2_intptr(divisor)); | |
| 2582 move_regs(lreg, dreg); | |
| 2583 } else if (code == lir_irem) { | |
| 2584 Label done; | |
| 304 | 2585 __ mov(dreg, lreg); |
| 0 | 2586 __ andl(dreg, 0x80000000 | (divisor - 1)); |
| 2587 __ jcc(Assembler::positive, done); | |
| 2588 __ decrement(dreg); | |
| 2589 __ orl(dreg, ~(divisor - 1)); | |
| 2590 __ increment(dreg); | |
| 2591 __ bind(done); | |
| 2592 } else { | |
| 2593 ShouldNotReachHere(); | |
| 2594 } | |
| 2595 } else { | |
| 2596 Register rreg = right->as_register(); | |
| 2597 assert(lreg == rax, "left register must be rax,"); | |
| 2598 assert(rreg != rdx, "right register must not be rdx"); | |
| 2599 assert(temp->as_register() == rdx, "tmp register must be rdx"); | |
| 2600 | |
| 2601 move_regs(lreg, rax); | |
| 2602 | |
| 2603 int idivl_offset = __ corrected_idivl(rreg); | |
| 2604 add_debug_info_for_div0(idivl_offset, info); | |
| 2605 if (code == lir_irem) { | |
| 2606 move_regs(rdx, dreg); // result is in rdx | |
| 2607 } else { | |
| 2608 move_regs(rax, dreg); | |
| 2609 } | |
| 2610 } | |
| 2611 } | |
| 2612 | |
| 2613 | |
| 2614 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { | |
| 2615 if (opr1->is_single_cpu()) { | |
| 2616 Register reg1 = opr1->as_register(); | |
| 2617 if (opr2->is_single_cpu()) { | |
| 2618 // cpu register - cpu register | |
| 304 | 2619 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
| 2620 __ cmpptr(reg1, opr2->as_register()); | |
| 2621 } else { | |
| 2622 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); | |
| 2623 __ cmpl(reg1, opr2->as_register()); | |
| 2624 } | |
| 0 | 2625 } else if (opr2->is_stack()) { |
| 2626 // cpu register - stack | |
| 304 | 2627 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { |
| 2628 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2629 } else { | |
| 2630 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2631 } | |
| 0 | 2632 } else if (opr2->is_constant()) { |
| 2633 // cpu register - constant | |
| 2634 LIR_Const* c = opr2->as_constant_ptr(); | |
| 2635 if (c->type() == T_INT) { | |
| 2636 __ cmpl(reg1, c->as_jint()); | |
| 304 | 2637 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
| 2638 // In 64bit oops are single register | |
| 0 | 2639 jobject o = c->as_jobject(); |
| 2640 if (o == NULL) { | |
| 304 | 2641 __ cmpptr(reg1, (int32_t)NULL_WORD); |
| 0 | 2642 } else { |
| 304 | 2643 #ifdef _LP64 |
| 2644 __ movoop(rscratch1, o); | |
| 2645 __ cmpptr(reg1, rscratch1); | |
| 2646 #else | |
| 0 | 2647 __ cmpoop(reg1, c->as_jobject()); |
| 304 | 2648 #endif // _LP64 |
| 0 | 2649 } |
| 2650 } else { | |
| 2651 ShouldNotReachHere(); | |
| 2652 } | |
| 2653 // cpu register - address | |
| 2654 } else if (opr2->is_address()) { | |
| 2655 if (op->info() != NULL) { | |
| 2656 add_debug_info_for_null_check_here(op->info()); | |
| 2657 } | |
| 2658 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); | |
| 2659 } else { | |
| 2660 ShouldNotReachHere(); | |
| 2661 } | |
| 2662 | |
| 2663 } else if(opr1->is_double_cpu()) { | |
| 2664 Register xlo = opr1->as_register_lo(); | |
| 2665 Register xhi = opr1->as_register_hi(); | |
| 2666 if (opr2->is_double_cpu()) { | |
| 304 | 2667 #ifdef _LP64 |
| 2668 __ cmpptr(xlo, opr2->as_register_lo()); | |
| 2669 #else | |
| 0 | 2670 // cpu register - cpu register |
| 2671 Register ylo = opr2->as_register_lo(); | |
| 2672 Register yhi = opr2->as_register_hi(); | |
| 2673 __ subl(xlo, ylo); | |
| 2674 __ sbbl(xhi, yhi); | |
| 2675 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { | |
| 2676 __ orl(xhi, xlo); | |
| 2677 } | |
| 304 | 2678 #endif // _LP64 |
| 0 | 2679 } else if (opr2->is_constant()) { |
| 2680 // cpu register - constant 0 | |
| 2681 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); | |
| 304 | 2682 #ifdef _LP64 |
| 2683 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); | |
| 2684 #else | |
| 0 | 2685 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); |
| 2686 __ orl(xhi, xlo); | |
| 304 | 2687 #endif // _LP64 |
| 0 | 2688 } else { |
| 2689 ShouldNotReachHere(); | |
| 2690 } | |
| 2691 | |
| 2692 } else if (opr1->is_single_xmm()) { | |
| 2693 XMMRegister reg1 = opr1->as_xmm_float_reg(); | |
| 2694 if (opr2->is_single_xmm()) { | |
| 2695 // xmm register - xmm register | |
| 2696 __ ucomiss(reg1, opr2->as_xmm_float_reg()); | |
| 2697 } else if (opr2->is_stack()) { | |
| 2698 // xmm register - stack | |
| 2699 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); | |
| 2700 } else if (opr2->is_constant()) { | |
| 2701 // xmm register - constant | |
| 2702 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); | |
| 2703 } else if (opr2->is_address()) { | |
| 2704 // xmm register - address | |
| 2705 if (op->info() != NULL) { | |
| 2706 add_debug_info_for_null_check_here(op->info()); | |
| 2707 } | |
| 2708 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); | |
| 2709 } else { | |
| 2710 ShouldNotReachHere(); | |
| 2711 } | |
| 2712 | |
| 2713 } else if (opr1->is_double_xmm()) { | |
| 2714 XMMRegister reg1 = opr1->as_xmm_double_reg(); | |
| 2715 if (opr2->is_double_xmm()) { | |
| 2716 // xmm register - xmm register | |
| 2717 __ ucomisd(reg1, opr2->as_xmm_double_reg()); | |
| 2718 } else if (opr2->is_stack()) { | |
| 2719 // xmm register - stack | |
| 2720 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); | |
| 2721 } else if (opr2->is_constant()) { | |
| 2722 // xmm register - constant | |
| 2723 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); | |
| 2724 } else if (opr2->is_address()) { | |
| 2725 // xmm register - address | |
| 2726 if (op->info() != NULL) { | |
| 2727 add_debug_info_for_null_check_here(op->info()); | |
| 2728 } | |
| 2729 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); | |
| 2730 } else { | |
| 2731 ShouldNotReachHere(); | |
| 2732 } | |
| 2733 | |
| 2734 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { | |
| 2735 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); | |
| 2736 assert(opr2->is_fpu_register(), "both must be registers"); | |
| 2737 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
| 2738 | |
| 2739 } else if (opr1->is_address() && opr2->is_constant()) { | |
| 304 | 2740 LIR_Const* c = opr2->as_constant_ptr(); |
| 2741 #ifdef _LP64 | |
| 2742 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { | |
| 2743 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); | |
| 2744 __ movoop(rscratch1, c->as_jobject()); | |
| 2745 } | |
| 2746 #endif // LP64 | |
| 0 | 2747 if (op->info() != NULL) { |
| 2748 add_debug_info_for_null_check_here(op->info()); | |
| 2749 } | |
| 2750 // special case: address - constant | |
| 2751 LIR_Address* addr = opr1->as_address_ptr(); | |
| 2752 if (c->type() == T_INT) { | |
| 2753 __ cmpl(as_Address(addr), c->as_jint()); | |
| 304 | 2754 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { |
| 2755 #ifdef _LP64 | |
| 2756 // %%% Make this explode if addr isn't reachable until we figure out a | |
| 2757 // better strategy by giving noreg as the temp for as_Address | |
| 2758 __ cmpptr(rscratch1, as_Address(addr, noreg)); | |
| 2759 #else | |
| 0 | 2760 __ cmpoop(as_Address(addr), c->as_jobject()); |
| 304 | 2761 #endif // _LP64 |
| 0 | 2762 } else { |
| 2763 ShouldNotReachHere(); | |
| 2764 } | |
| 2765 | |
| 2766 } else { | |
| 2767 ShouldNotReachHere(); | |
| 2768 } | |
| 2769 } | |
| 2770 | |
| 2771 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { | |
| 2772 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { | |
| 2773 if (left->is_single_xmm()) { | |
| 2774 assert(right->is_single_xmm(), "must match"); | |
| 2775 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
| 2776 } else if (left->is_double_xmm()) { | |
| 2777 assert(right->is_double_xmm(), "must match"); | |
| 2778 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); | |
| 2779 | |
| 2780 } else { | |
| 2781 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); | |
| 2782 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); | |
| 2783 | |
| 2784 assert(left->fpu() == 0, "left must be on TOS"); | |
| 2785 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), | |
| 2786 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); | |
| 2787 } | |
| 2788 } else { | |
| 2789 assert(code == lir_cmp_l2i, "check"); | |
| 304 | 2790 #ifdef _LP64 |
| 1369 | 2791 Label done; |
| 2792 Register dest = dst->as_register(); | |
| 2793 __ cmpptr(left->as_register_lo(), right->as_register_lo()); | |
| 2794 __ movl(dest, -1); | |
| 2795 __ jccb(Assembler::less, done); | |
| 2796 __ set_byte_if_not_zero(dest); | |
| 2797 __ movzbl(dest, dest); | |
| 2798 __ bind(done); | |
| 304 | 2799 #else |
| 0 | 2800 __ lcmp2int(left->as_register_hi(), |
| 2801 left->as_register_lo(), | |
| 2802 right->as_register_hi(), | |
| 2803 right->as_register_lo()); | |
| 2804 move_regs(left->as_register_hi(), dst->as_register()); | |
| 304 | 2805 #endif // _LP64 |
| 0 | 2806 } |
| 2807 } | |
| 2808 | |
| 2809 | |
| 2810 void LIR_Assembler::align_call(LIR_Code code) { | |
| 2811 if (os::is_MP()) { | |
| 2812 // make sure that the displacement word of the call ends up word aligned | |
| 2813 int offset = __ offset(); | |
| 2814 switch (code) { | |
| 2815 case lir_static_call: | |
| 2816 case lir_optvirtual_call: | |
| 1295 | 2817 case lir_dynamic_call: |
| 0 | 2818 offset += NativeCall::displacement_offset; |
| 2819 break; | |
| 2820 case lir_icvirtual_call: | |
| 2821 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; | |
| 2822 break; | |
| 2823 case lir_virtual_call: // currently, sparc-specific for niagara | |
| 2824 default: ShouldNotReachHere(); | |
| 2825 } | |
| 2826 while (offset++ % BytesPerWord != 0) { | |
| 2827 __ nop(); | |
| 2828 } | |
| 2829 } | |
| 2830 } | |
| 2831 | |
| 2832 | |
| 1295 | 2833 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { |
| 0 | 2834 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, |
| 2835 "must be aligned"); | |
| 1295 | 2836 __ call(AddressLiteral(op->addr(), rtype)); |
| 1564 | 2837 add_call_info(code_offset(), op->info()); |
| 0 | 2838 } |
| 2839 | |
| 2840 | |
| 1295 | 2841 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { |
| 0 | 2842 RelocationHolder rh = virtual_call_Relocation::spec(pc()); |
| 2843 __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); | |
| 2844 assert(!os::is_MP() || | |
| 2845 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, | |
| 2846 "must be aligned"); | |
| 1295 | 2847 __ call(AddressLiteral(op->addr(), rh)); |
| 1564 | 2848 add_call_info(code_offset(), op->info()); |
| 0 | 2849 } |
| 2850 | |
| 2851 | |
| 2852 /* Currently, vtable-dispatch is only enabled for sparc platforms */ | |
| 1295 | 2853 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { |
| 0 | 2854 ShouldNotReachHere(); |
| 2855 } | |
| 2856 | |
| 1295 | 2857 |
| 0 | 2858 void LIR_Assembler::emit_static_call_stub() { |
| 2859 address call_pc = __ pc(); | |
| 2860 address stub = __ start_a_stub(call_stub_size); | |
| 2861 if (stub == NULL) { | |
| 2862 bailout("static call stub overflow"); | |
| 2863 return; | |
| 2864 } | |
| 2865 | |
| 2866 int start = __ offset(); | |
| 2867 if (os::is_MP()) { | |
| 2868 // make sure that the displacement word of the call ends up word aligned | |
| 2869 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; | |
| 2870 while (offset++ % BytesPerWord != 0) { | |
| 2871 __ nop(); | |
| 2872 } | |
| 2873 } | |
| 2874 __ relocate(static_stub_Relocation::spec(call_pc)); | |
| 2875 __ movoop(rbx, (jobject)NULL); | |
| 2876 // must be set to -1 at code generation time | |
| 2877 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); | |
| 304 | 2878 // On 64bit this will die since it will take a movq & jmp, must be only a jmp |
| 2879 __ jump(RuntimeAddress(__ pc())); | |
| 0 | 2880 |
|
1489
cff162798819
6888953: some calls to function-like macros are missing semicolons
jcoomes
parents:
1378
diff
changeset
|
2881 assert(__ offset() - start <= call_stub_size, "stub too big"); |
| 0 | 2882 __ end_a_stub(); |
| 2883 } | |
| 2884 | |
| 2885 | |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2886 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { |
| 0 | 2887 assert(exceptionOop->as_register() == rax, "must match"); |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2888 assert(exceptionPC->as_register() == rdx, "must match"); |
| 0 | 2889 |
| 2890 // exception object is not added to oop map by LinearScan | |
| 2891 // (LinearScan assumes that no oops are in fixed registers) | |
| 2892 info->add_register_oop(exceptionOop); | |
| 2893 Runtime1::StubID unwind_id; | |
| 2894 | |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2895 // get current pc information |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2896 // pc is only needed if the method has an exception handler, the unwind code does not need it. |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2897 int pc_for_athrow_offset = __ offset(); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2898 InternalAddress pc_for_athrow(__ pc()); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2899 __ lea(exceptionPC->as_register(), pc_for_athrow); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2900 add_call_info(pc_for_athrow_offset, info); // for exception handler |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2901 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2902 __ verify_not_null_oop(rax); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2903 // search an exception handler (rax: exception oop, rdx: throwing pc) |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2904 if (compilation()->has_fpu_code()) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2905 unwind_id = Runtime1::handle_exception_id; |
| 0 | 2906 } else { |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2907 unwind_id = Runtime1::handle_exception_nofpu_id; |
| 0 | 2908 } |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2909 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); |
| 0 | 2910 |
| 2911 // enough room for two byte trap | |
| 2912 __ nop(); | |
| 2913 } | |
| 2914 | |
| 2915 | |
|
1378
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2916 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2917 assert(exceptionOop->as_register() == rax, "must match"); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2918 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2919 __ jmp(_unwind_handler_entry); |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2920 } |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2921 |
|
9f5b60a14736
6939930: exception unwind changes in 6919934 hurts compilation speed
never
parents:
1369
diff
changeset
|
2922 |
| 0 | 2923 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { |
| 2924 | |
| 2925 // optimized version for linear scan: | |
| 2926 // * count must be already in ECX (guaranteed by LinearScan) | |
| 2927 // * left and dest must be equal | |
| 2928 // * tmp must be unused | |
| 2929 assert(count->as_register() == SHIFT_count, "count must be in ECX"); | |
| 2930 assert(left == dest, "left and dest must be equal"); | |
| 2931 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); | |
| 2932 | |
| 2933 if (left->is_single_cpu()) { | |
| 2934 Register value = left->as_register(); | |
| 2935 assert(value != SHIFT_count, "left cannot be ECX"); | |
| 2936 | |
| 2937 switch (code) { | |
| 2938 case lir_shl: __ shll(value); break; | |
| 2939 case lir_shr: __ sarl(value); break; | |
| 2940 case lir_ushr: __ shrl(value); break; | |
| 2941 default: ShouldNotReachHere(); | |
| 2942 } | |
| 2943 } else if (left->is_double_cpu()) { | |
| 2944 Register lo = left->as_register_lo(); | |
| 2945 Register hi = left->as_register_hi(); | |
| 2946 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); | |
| 304 | 2947 #ifdef _LP64 |
| 2948 switch (code) { | |
| 2949 case lir_shl: __ shlptr(lo); break; | |
| 2950 case lir_shr: __ sarptr(lo); break; | |
| 2951 case lir_ushr: __ shrptr(lo); break; | |
| 2952 default: ShouldNotReachHere(); | |
| 2953 } | |
| 2954 #else | |
| 0 | 2955 |
| 2956 switch (code) { | |
| 2957 case lir_shl: __ lshl(hi, lo); break; | |
| 2958 case lir_shr: __ lshr(hi, lo, true); break; | |
| 2959 case lir_ushr: __ lshr(hi, lo, false); break; | |
| 2960 default: ShouldNotReachHere(); | |
| 2961 } | |
| 304 | 2962 #endif // LP64 |
| 0 | 2963 } else { |
| 2964 ShouldNotReachHere(); | |
| 2965 } | |
| 2966 } | |
| 2967 | |
| 2968 | |
| 2969 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { | |
| 2970 if (dest->is_single_cpu()) { | |
| 2971 // first move left into dest so that left is not destroyed by the shift | |
| 2972 Register value = dest->as_register(); | |
| 2973 count = count & 0x1F; // Java spec | |
| 2974 | |
| 2975 move_regs(left->as_register(), value); | |
| 2976 switch (code) { | |
| 2977 case lir_shl: __ shll(value, count); break; | |
| 2978 case lir_shr: __ sarl(value, count); break; | |
| 2979 case lir_ushr: __ shrl(value, count); break; | |
| 2980 default: ShouldNotReachHere(); | |
| 2981 } | |
| 2982 } else if (dest->is_double_cpu()) { | |
| 304 | 2983 #ifndef _LP64 |
| 0 | 2984 Unimplemented(); |
| 304 | 2985 #else |
| 2986 // first move left into dest so that left is not destroyed by the shift | |
| 2987 Register value = dest->as_register_lo(); | |
| 2988 count = count & 0x1F; // Java spec | |
| 2989 | |
| 2990 move_regs(left->as_register_lo(), value); | |
| 2991 switch (code) { | |
| 2992 case lir_shl: __ shlptr(value, count); break; | |
| 2993 case lir_shr: __ sarptr(value, count); break; | |
| 2994 case lir_ushr: __ shrptr(value, count); break; | |
| 2995 default: ShouldNotReachHere(); | |
| 2996 } | |
| 2997 #endif // _LP64 | |
| 0 | 2998 } else { |
| 2999 ShouldNotReachHere(); | |
| 3000 } | |
| 3001 } | |
| 3002 | |
| 3003 | |
| 3004 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { | |
| 3005 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
| 3006 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
| 3007 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
| 304 | 3008 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); |
| 0 | 3009 } |
| 3010 | |
| 3011 | |
| 3012 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { | |
| 3013 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
| 3014 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
| 3015 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
| 304 | 3016 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); |
| 0 | 3017 } |
| 3018 | |
| 3019 | |
| 3020 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { | |
| 3021 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); | |
| 3022 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; | |
| 3023 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); | |
| 3024 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); | |
| 3025 } | |
| 3026 | |
| 3027 | |
| 3028 // This code replaces a call to arraycopy; no exception may | |
| 3029 // be thrown in this code, they must be thrown in the System.arraycopy | |
| 3030 // activation frame; we could save some checks if this would not be the case | |
| 3031 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { | |
| 3032 ciArrayKlass* default_type = op->expected_type(); | |
| 3033 Register src = op->src()->as_register(); | |
| 3034 Register dst = op->dst()->as_register(); | |
| 3035 Register src_pos = op->src_pos()->as_register(); | |
| 3036 Register dst_pos = op->dst_pos()->as_register(); | |
| 3037 Register length = op->length()->as_register(); | |
| 3038 Register tmp = op->tmp()->as_register(); | |
| 3039 | |
| 3040 CodeStub* stub = op->stub(); | |
| 3041 int flags = op->flags(); | |
| 3042 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; | |
| 3043 if (basic_type == T_ARRAY) basic_type = T_OBJECT; | |
| 3044 | |
| 3045 // if we don't know anything or it's an object array, just go through the generic arraycopy | |
| 3046 if (default_type == NULL) { | |
| 3047 Label done; | |
| 3048 // save outgoing arguments on stack in case call to System.arraycopy is needed | |
| 3049 // HACK ALERT. This code used to push the parameters in a hardwired fashion | |
| 3050 // for interpreter calling conventions. Now we have to do it in new style conventions. | |
| 3051 // For the moment until C1 gets the new register allocator I just force all the | |
| 3052 // args to the right place (except the register args) and then on the back side | |
| 3053 // reload the register args properly if we go slow path. Yuck | |
| 3054 | |
| 3055 // These are proper for the calling convention | |
| 3056 | |
| 3057 store_parameter(length, 2); | |
| 3058 store_parameter(dst_pos, 1); | |
| 3059 store_parameter(dst, 0); | |
| 3060 | |
| 3061 // these are just temporary placements until we need to reload | |
| 3062 store_parameter(src_pos, 3); | |
| 3063 store_parameter(src, 4); | |
| 304 | 3064 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) |
| 3065 | |
| 3066 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); | |
| 0 | 3067 |
| 3068 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint | |
| 304 | 3069 #ifdef _LP64 |
| 3070 // The arguments are in java calling convention so we can trivially shift them to C | |
| 3071 // convention | |
| 3072 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
| 3073 __ mov(c_rarg0, j_rarg0); | |
| 3074 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); | |
| 3075 __ mov(c_rarg1, j_rarg1); | |
| 3076 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); | |
| 3077 __ mov(c_rarg2, j_rarg2); | |
| 3078 assert_different_registers(c_rarg3, j_rarg4); | |
| 3079 __ mov(c_rarg3, j_rarg3); | |
| 3080 #ifdef _WIN64 | |
| 3081 // Allocate abi space for args but be sure to keep stack aligned | |
| 3082 __ subptr(rsp, 6*wordSize); | |
| 3083 store_parameter(j_rarg4, 4); | |
| 3084 __ call(RuntimeAddress(entry)); | |
| 3085 __ addptr(rsp, 6*wordSize); | |
| 3086 #else | |
| 3087 __ mov(c_rarg4, j_rarg4); | |
| 3088 __ call(RuntimeAddress(entry)); | |
| 3089 #endif // _WIN64 | |
| 3090 #else | |
| 3091 __ push(length); | |
| 3092 __ push(dst_pos); | |
| 3093 __ push(dst); | |
| 3094 __ push(src_pos); | |
| 3095 __ push(src); | |
| 0 | 3096 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack |
| 3097 | |
| 304 | 3098 #endif // _LP64 |
| 3099 | |
| 0 | 3100 __ cmpl(rax, 0); |
| 3101 __ jcc(Assembler::equal, *stub->continuation()); | |
| 3102 | |
| 3103 // Reload values from the stack so they are where the stub | |
| 3104 // expects them. | |
| 304 | 3105 __ movptr (dst, Address(rsp, 0*BytesPerWord)); |
| 3106 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); | |
| 3107 __ movptr (length, Address(rsp, 2*BytesPerWord)); | |
| 3108 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); | |
| 3109 __ movptr (src, Address(rsp, 4*BytesPerWord)); | |
| 0 | 3110 __ jmp(*stub->entry()); |
| 3111 | |
| 3112 __ bind(*stub->continuation()); | |
| 3113 return; | |
| 3114 } | |
| 3115 | |
| 3116 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); | |
| 3117 | |
|
29
d5fc211aea19
6633953: type2aelembytes{T_ADDRESS} should be 8 bytes in 64 bit VM
kvn
parents:
0
diff
changeset
|
3118 int elem_size = type2aelembytes(basic_type); |
| 0 | 3119 int shift_amount; |
| 3120 Address::ScaleFactor scale; | |
| 3121 | |
| 3122 switch (elem_size) { | |
| 3123 case 1 : | |
| 3124 shift_amount = 0; | |
| 3125 scale = Address::times_1; | |
| 3126 break; | |
| 3127 case 2 : | |
| 3128 shift_amount = 1; | |
| 3129 scale = Address::times_2; | |
| 3130 break; | |
| 3131 case 4 : | |
| 3132 shift_amount = 2; | |
| 3133 scale = Address::times_4; | |
| 3134 break; | |
| 3135 case 8 : | |
| 3136 shift_amount = 3; | |
| 3137 scale = Address::times_8; | |
| 3138 break; | |
| 3139 default: | |
| 3140 ShouldNotReachHere(); | |
| 3141 } | |
| 3142 | |
| 3143 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); | |
| 3144 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); | |
| 3145 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); | |
| 3146 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); | |
| 3147 | |
| 304 | 3148 // length and pos's are all sign extended at this point on 64bit |
| 3149 | |
| 0 | 3150 // test for NULL |
| 3151 if (flags & LIR_OpArrayCopy::src_null_check) { | |
| 304 | 3152 __ testptr(src, src); |
| 0 | 3153 __ jcc(Assembler::zero, *stub->entry()); |
| 3154 } | |
| 3155 if (flags & LIR_OpArrayCopy::dst_null_check) { | |
| 304 | 3156 __ testptr(dst, dst); |
| 0 | 3157 __ jcc(Assembler::zero, *stub->entry()); |
| 3158 } | |
| 3159 | |
| 3160 // check if negative | |
| 3161 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { | |
| 3162 __ testl(src_pos, src_pos); | |
| 3163 __ jcc(Assembler::less, *stub->entry()); | |
| 3164 } | |
| 3165 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { | |
| 3166 __ testl(dst_pos, dst_pos); | |
| 3167 __ jcc(Assembler::less, *stub->entry()); | |
| 3168 } | |
| 3169 if (flags & LIR_OpArrayCopy::length_positive_check) { | |
| 3170 __ testl(length, length); | |
| 3171 __ jcc(Assembler::less, *stub->entry()); | |
| 3172 } | |
| 3173 | |
| 3174 if (flags & LIR_OpArrayCopy::src_range_check) { | |
| 304 | 3175 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); |
| 0 | 3176 __ cmpl(tmp, src_length_addr); |
| 3177 __ jcc(Assembler::above, *stub->entry()); | |
| 3178 } | |
| 3179 if (flags & LIR_OpArrayCopy::dst_range_check) { | |
| 304 | 3180 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); |
| 0 | 3181 __ cmpl(tmp, dst_length_addr); |
| 3182 __ jcc(Assembler::above, *stub->entry()); | |
| 3183 } | |
| 3184 | |
| 3185 if (flags & LIR_OpArrayCopy::type_check) { | |
| 304 | 3186 __ movptr(tmp, src_klass_addr); |
| 3187 __ cmpptr(tmp, dst_klass_addr); | |
| 0 | 3188 __ jcc(Assembler::notEqual, *stub->entry()); |
| 3189 } | |
| 3190 | |
| 3191 #ifdef ASSERT | |
| 3192 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { | |
| 3193 // Sanity check the known type with the incoming class. For the | |
| 3194 // primitive case the types must match exactly with src.klass and | |
| 3195 // dst.klass each exactly matching the default type. For the | |
| 3196 // object array case, if no type check is needed then either the | |
| 3197 // dst type is exactly the expected type and the src type is a | |
| 3198 // subtype which we can't check or src is the same array as dst | |
| 3199 // but not necessarily exactly of type default_type. | |
| 3200 Label known_ok, halt; | |
|
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
780
diff
changeset
|
3201 __ movoop(tmp, default_type->constant_encoding()); |
| 0 | 3202 if (basic_type != T_OBJECT) { |
| 304 | 3203 __ cmpptr(tmp, dst_klass_addr); |
| 0 | 3204 __ jcc(Assembler::notEqual, halt); |
| 304 | 3205 __ cmpptr(tmp, src_klass_addr); |
| 0 | 3206 __ jcc(Assembler::equal, known_ok); |
| 3207 } else { | |
| 304 | 3208 __ cmpptr(tmp, dst_klass_addr); |
| 0 | 3209 __ jcc(Assembler::equal, known_ok); |
| 304 | 3210 __ cmpptr(src, dst); |
| 0 | 3211 __ jcc(Assembler::equal, known_ok); |
| 3212 } | |
| 3213 __ bind(halt); | |
| 3214 __ stop("incorrect type information in arraycopy"); | |
| 3215 __ bind(known_ok); | |
| 3216 } | |
| 3217 #endif | |
| 3218 | |
| 304 | 3219 if (shift_amount > 0 && basic_type != T_OBJECT) { |
| 3220 __ shlptr(length, shift_amount); | |
| 3221 } | |
| 3222 | |
| 3223 #ifdef _LP64 | |
| 3224 assert_different_registers(c_rarg0, dst, dst_pos, length); | |
| 1060 | 3225 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null |
| 304 | 3226 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
| 3227 assert_different_registers(c_rarg1, length); | |
| 1060 | 3228 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null |
| 304 | 3229 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
| 3230 __ mov(c_rarg2, length); | |
| 3231 | |
| 3232 #else | |
| 3233 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); | |
| 0 | 3234 store_parameter(tmp, 0); |
| 304 | 3235 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); |
| 0 | 3236 store_parameter(tmp, 1); |
| 3237 store_parameter(length, 2); | |
| 304 | 3238 #endif // _LP64 |
| 0 | 3239 if (basic_type == T_OBJECT) { |
| 3240 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); | |
| 3241 } else { | |
| 3242 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); | |
| 3243 } | |
| 3244 | |
| 3245 __ bind(*stub->continuation()); | |
| 3246 } | |
| 3247 | |
| 3248 | |
| 3249 void LIR_Assembler::emit_lock(LIR_OpLock* op) { | |
| 3250 Register obj = op->obj_opr()->as_register(); // may not be an oop | |
| 3251 Register hdr = op->hdr_opr()->as_register(); | |
| 3252 Register lock = op->lock_opr()->as_register(); | |
| 3253 if (!UseFastLocking) { | |
| 3254 __ jmp(*op->stub()->entry()); | |
| 3255 } else if (op->code() == lir_lock) { | |
| 3256 Register scratch = noreg; | |
| 3257 if (UseBiasedLocking) { | |
| 3258 scratch = op->scratch_opr()->as_register(); | |
| 3259 } | |
| 3260 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 3261 // add debug info for NullPointerException only if one is possible | |
| 3262 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); | |
| 3263 if (op->info() != NULL) { | |
| 3264 add_debug_info_for_null_check(null_check_offset, op->info()); | |
| 3265 } | |
| 3266 // done | |
| 3267 } else if (op->code() == lir_unlock) { | |
| 3268 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); | |
| 3269 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); | |
| 3270 } else { | |
| 3271 Unimplemented(); | |
| 3272 } | |
| 3273 __ bind(*op->stub()->continuation()); | |
| 3274 } | |
| 3275 | |
| 3276 | |
| 3277 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { | |
| 3278 ciMethod* method = op->profiled_method(); | |
| 3279 int bci = op->profiled_bci(); | |
| 3280 | |
| 3281 // Update counter for all call types | |
| 3282 ciMethodData* md = method->method_data(); | |
| 3283 if (md == NULL) { | |
| 3284 bailout("out of memory building methodDataOop"); | |
| 3285 return; | |
| 3286 } | |
| 3287 ciProfileData* data = md->bci_to_data(bci); | |
| 3288 assert(data->is_CounterData(), "need CounterData for calls"); | |
| 3289 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); | |
| 3290 Register mdo = op->mdo()->as_register(); | |
|
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
780
diff
changeset
|
3291 __ movoop(mdo, md->constant_encoding()); |
| 0 | 3292 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); |
| 3293 Bytecodes::Code bc = method->java_code_at_bci(bci); | |
| 3294 // Perform additional virtual call profiling for invokevirtual and | |
| 3295 // invokeinterface bytecodes | |
| 3296 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && | |
| 1783 | 3297 C1ProfileVirtualCalls) { |
| 0 | 3298 assert(op->recv()->is_single_cpu(), "recv must be allocated"); |
| 3299 Register recv = op->recv()->as_register(); | |
| 3300 assert_different_registers(mdo, recv); | |
| 3301 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); | |
| 3302 ciKlass* known_klass = op->known_holder(); | |
| 1783 | 3303 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { |
| 0 | 3304 // We know the type that will be seen at this call site; we can |
| 3305 // statically update the methodDataOop rather than needing to do | |
| 3306 // dynamic tests on the receiver type | |
| 3307 | |
| 3308 // NOTE: we should probably put a lock around this search to | |
| 3309 // avoid collisions by concurrent compilations | |
| 3310 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; | |
| 3311 uint i; | |
| 3312 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 3313 ciKlass* receiver = vc_data->receiver(i); | |
| 3314 if (known_klass->equals(receiver)) { | |
| 3315 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); | |
| 1783 | 3316 __ addptr(data_addr, DataLayout::counter_increment); |
| 0 | 3317 return; |
| 3318 } | |
| 3319 } | |
| 3320 | |
| 3321 // Receiver type not found in profile data; select an empty slot | |
| 3322 | |
| 3323 // Note that this is less efficient than it should be because it | |
| 3324 // always does a write to the receiver part of the | |
| 3325 // VirtualCallData rather than just the first time | |
| 3326 for (i = 0; i < VirtualCallData::row_limit(); i++) { | |
| 3327 ciKlass* receiver = vc_data->receiver(i); | |
| 3328 if (receiver == NULL) { | |
| 3329 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); | |
|
989
148e5441d916
6863023: need non-perm oops in code cache for JSR 292
jrose
parents:
780
diff
changeset
|
3330 __ movoop(recv_addr, known_klass->constant_encoding()); |
| 0 | 3331 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); |
| 1783 | 3332 __ addptr(data_addr, DataLayout::counter_increment); |
| 0 | 3333 return; |
| 3334 } | |
| 3335 } | |
| 3336 } else { | |
| 304 | 3337 __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes())); |
| 0 | 3338 Label update_done; |
| 1783 | 3339 type_profile_helper(mdo, md, data, recv, &update_done); |
|
1206
87684f1a88b5
6614597: Performance variability in jvm2008 xml.validation
kvn
parents:
1204
diff
changeset
|
3340 // Receiver did not match any saved receiver and there is no empty row for it. |
|
1251
576e77447e3c
6923002: assert(false,"this call site should not be polymorphic")
kvn
parents:
1206
diff
changeset
|
3341 // Increment total counter to indicate polymorphic case. |
| 1783 | 3342 __ addptr(counter_addr, DataLayout::counter_increment); |
| 0 | 3343 |
| 3344 __ bind(update_done); | |
| 3345 } | |
|
1206
87684f1a88b5
6614597: Performance variability in jvm2008 xml.validation
kvn
parents:
1204
diff
changeset
|
3346 } else { |
|
87684f1a88b5
6614597: Performance variability in jvm2008 xml.validation
kvn
parents:
1204
diff
changeset
|
3347 // Static call |
| 1783 | 3348 __ addptr(counter_addr, DataLayout::counter_increment); |
| 0 | 3349 } |
| 3350 } | |
| 3351 | |
| 3352 void LIR_Assembler::emit_delay(LIR_OpDelay*) { | |
| 3353 Unimplemented(); | |
| 3354 } | |
| 3355 | |
| 3356 | |
| 3357 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { | |
| 304 | 3358 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); |
| 0 | 3359 } |
| 3360 | |
| 3361 | |
| 3362 void LIR_Assembler::align_backward_branch_target() { | |
| 3363 __ align(BytesPerWord); | |
| 3364 } | |
| 3365 | |
| 3366 | |
| 3367 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { | |
| 3368 if (left->is_single_cpu()) { | |
| 3369 __ negl(left->as_register()); | |
| 3370 move_regs(left->as_register(), dest->as_register()); | |
| 3371 | |
| 3372 } else if (left->is_double_cpu()) { | |
| 3373 Register lo = left->as_register_lo(); | |
| 304 | 3374 #ifdef _LP64 |
| 3375 Register dst = dest->as_register_lo(); | |
| 3376 __ movptr(dst, lo); | |
| 3377 __ negptr(dst); | |
| 3378 #else | |
| 0 | 3379 Register hi = left->as_register_hi(); |
| 3380 __ lneg(hi, lo); | |
| 3381 if (dest->as_register_lo() == hi) { | |
| 3382 assert(dest->as_register_hi() != lo, "destroying register"); | |
| 3383 move_regs(hi, dest->as_register_hi()); | |
| 3384 move_regs(lo, dest->as_register_lo()); | |
| 3385 } else { | |
| 3386 move_regs(lo, dest->as_register_lo()); | |
| 3387 move_regs(hi, dest->as_register_hi()); | |
| 3388 } | |
| 304 | 3389 #endif // _LP64 |
| 0 | 3390 |
| 3391 } else if (dest->is_single_xmm()) { | |
| 3392 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { | |
| 3393 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); | |
| 3394 } | |
| 3395 __ xorps(dest->as_xmm_float_reg(), | |
| 3396 ExternalAddress((address)float_signflip_pool)); | |
| 3397 | |
| 3398 } else if (dest->is_double_xmm()) { | |
| 3399 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { | |
| 3400 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); | |
| 3401 } | |
| 3402 __ xorpd(dest->as_xmm_double_reg(), | |
| 3403 ExternalAddress((address)double_signflip_pool)); | |
| 3404 | |
| 3405 } else if (left->is_single_fpu() || left->is_double_fpu()) { | |
| 3406 assert(left->fpu() == 0, "arg must be on TOS"); | |
| 3407 assert(dest->fpu() == 0, "dest must be TOS"); | |
| 3408 __ fchs(); | |
| 3409 | |
| 3410 } else { | |
| 3411 ShouldNotReachHere(); | |
| 3412 } | |
| 3413 } | |
| 3414 | |
| 3415 | |
| 3416 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { | |
| 3417 assert(addr->is_address() && dest->is_register(), "check"); | |
| 304 | 3418 Register reg; |
| 3419 reg = dest->as_pointer_register(); | |
| 3420 __ lea(reg, as_Address(addr->as_address_ptr())); | |
| 0 | 3421 } |
| 3422 | |
| 3423 | |
| 3424 | |
| 3425 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { | |
| 3426 assert(!tmp->is_valid(), "don't need temporary"); | |
| 3427 __ call(RuntimeAddress(dest)); | |
| 3428 if (info != NULL) { | |
| 3429 add_call_info_here(info); | |
| 3430 } | |
| 3431 } | |
| 3432 | |
| 3433 | |
| 3434 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { | |
| 3435 assert(type == T_LONG, "only for volatile long fields"); | |
| 3436 | |
| 3437 if (info != NULL) { | |
| 3438 add_debug_info_for_null_check_here(info); | |
| 3439 } | |
| 3440 | |
| 3441 if (src->is_double_xmm()) { | |
| 3442 if (dest->is_double_cpu()) { | |
| 304 | 3443 #ifdef _LP64 |
| 3444 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); | |
| 3445 #else | |
| 3446 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); | |
| 0 | 3447 __ psrlq(src->as_xmm_double_reg(), 32); |
| 304 | 3448 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); |
| 3449 #endif // _LP64 | |
| 0 | 3450 } else if (dest->is_double_stack()) { |
| 3451 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); | |
| 3452 } else if (dest->is_address()) { | |
| 3453 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); | |
| 3454 } else { | |
| 3455 ShouldNotReachHere(); | |
| 3456 } | |
| 3457 | |
| 3458 } else if (dest->is_double_xmm()) { | |
| 3459 if (src->is_double_stack()) { | |
| 3460 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); | |
| 3461 } else if (src->is_address()) { | |
| 3462 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); | |
| 3463 } else { | |
| 3464 ShouldNotReachHere(); | |
| 3465 } | |
| 3466 | |
| 3467 } else if (src->is_double_fpu()) { | |
| 3468 assert(src->fpu_regnrLo() == 0, "must be TOS"); | |
| 3469 if (dest->is_double_stack()) { | |
| 3470 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); | |
| 3471 } else if (dest->is_address()) { | |
| 3472 __ fistp_d(as_Address(dest->as_address_ptr())); | |
| 3473 } else { | |
| 3474 ShouldNotReachHere(); | |
| 3475 } | |
| 3476 | |
| 3477 } else if (dest->is_double_fpu()) { | |
| 3478 assert(dest->fpu_regnrLo() == 0, "must be TOS"); | |
| 3479 if (src->is_double_stack()) { | |
| 3480 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); | |
| 3481 } else if (src->is_address()) { | |
| 3482 __ fild_d(as_Address(src->as_address_ptr())); | |
| 3483 } else { | |
| 3484 ShouldNotReachHere(); | |
| 3485 } | |
| 3486 } else { | |
| 3487 ShouldNotReachHere(); | |
| 3488 } | |
| 3489 } | |
| 3490 | |
| 3491 | |
| 3492 void LIR_Assembler::membar() { | |
| 304 | 3493 // QQQ sparc TSO uses this, |
| 3494 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); | |
| 0 | 3495 } |
| 3496 | |
| 3497 void LIR_Assembler::membar_acquire() { | |
| 3498 // No x86 machines currently require load fences | |
| 3499 // __ load_fence(); | |
| 3500 } | |
| 3501 | |
| 3502 void LIR_Assembler::membar_release() { | |
| 3503 // No x86 machines currently require store fences | |
| 3504 // __ store_fence(); | |
| 3505 } | |
| 3506 | |
| 3507 void LIR_Assembler::get_thread(LIR_Opr result_reg) { | |
| 3508 assert(result_reg->is_register(), "check"); | |
| 304 | 3509 #ifdef _LP64 |
| 3510 // __ get_thread(result_reg->as_register_lo()); | |
| 3511 __ mov(result_reg->as_register(), r15_thread); | |
| 3512 #else | |
| 0 | 3513 __ get_thread(result_reg->as_register()); |
| 304 | 3514 #endif // _LP64 |
| 0 | 3515 } |
| 3516 | |
| 3517 | |
| 3518 void LIR_Assembler::peephole(LIR_List*) { | |
| 3519 // do nothing for now | |
| 3520 } | |
| 3521 | |
| 3522 | |
| 3523 #undef __ |