Mercurial > hg > graal-compiler
annotate src/cpu/ppc/vm/macroAssembler_ppc.inline.hpp @ 21451:24dd9af9ac26
SPARCArithmetic: add register hint for Unary2Op.
author | Josef Eisl <josef.eisl@jku.at> |
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date | Thu, 21 May 2015 15:00:11 +0200 |
parents | 58cf34613a72 |
children | 92aa6797d639 |
rev | line source |
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1 /* |
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2 * Copyright (c) 2002, 2013, Oracle and/or its affiliates. All rights reserved. |
14694 | 3 * Copyright 2012, 2014 SAP AG. All rights reserved. |
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4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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5 * |
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6 * This code is free software; you can redistribute it and/or modify it |
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7 * under the terms of the GNU General Public License version 2 only, as |
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8 * published by the Free Software Foundation. |
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9 * |
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10 * This code is distributed in the hope that it will be useful, but WITHOUT |
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11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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13 * version 2 for more details (a copy is included in the LICENSE file that |
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14 * accompanied this code). |
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15 * |
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16 * You should have received a copy of the GNU General Public License version |
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17 * 2 along with this work; if not, write to the Free Software Foundation, |
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18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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19 * |
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20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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21 * or visit www.oracle.com if you need additional information or have any |
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22 * questions. |
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23 * |
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24 */ |
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25 |
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26 #ifndef CPU_PPC_VM_MACROASSEMBLER_PPC_INLINE_HPP |
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27 #define CPU_PPC_VM_MACROASSEMBLER_PPC_INLINE_HPP |
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28 |
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29 #include "asm/assembler.inline.hpp" |
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30 #include "asm/macroAssembler.hpp" |
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31 #include "asm/codeBuffer.hpp" |
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32 #include "code/codeCache.hpp" |
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33 |
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34 inline bool MacroAssembler::is_ld_largeoffset(address a) { |
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35 const int inst1 = *(int *)a; |
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36 const int inst2 = *(int *)(a+4); |
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37 return (is_ld(inst1)) || |
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38 (is_addis(inst1) && is_ld(inst2) && inv_ra_field(inst2) == inv_rt_field(inst1)); |
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39 } |
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40 |
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41 inline int MacroAssembler::get_ld_largeoffset_offset(address a) { |
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42 assert(MacroAssembler::is_ld_largeoffset(a), "must be ld with large offset"); |
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43 |
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44 const int inst1 = *(int *)a; |
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45 if (is_ld(inst1)) { |
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46 return inv_d1_field(inst1); |
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47 } else { |
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48 const int inst2 = *(int *)(a+4); |
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49 return (inv_d1_field(inst1) << 16) + inv_d1_field(inst2); |
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50 } |
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51 } |
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52 |
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53 inline void MacroAssembler::round_to(Register r, int modulus) { |
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54 assert(is_power_of_2_long((jlong)modulus), "must be power of 2"); |
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55 addi(r, r, modulus-1); |
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56 clrrdi(r, r, log2_long((jlong)modulus)); |
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57 } |
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58 |
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59 // Move register if destination register and target register are different. |
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60 inline void MacroAssembler::mr_if_needed(Register rd, Register rs) { |
14445 | 61 if (rs != rd) mr(rd, rs); |
62 } | |
63 inline void MacroAssembler::fmr_if_needed(FloatRegister rd, FloatRegister rs) { | |
64 if (rs != rd) fmr(rd, rs); | |
65 } | |
66 inline void MacroAssembler::endgroup_if_needed(bool needed) { | |
67 if (needed) { | |
68 endgroup(); | |
69 } | |
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70 } |
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71 |
14445 | 72 inline void MacroAssembler::membar(int bits) { |
73 // TODO: use elemental_membar(bits) for Power 8 and disable optimization of acquire-release | |
74 // (Matcher::post_membar_release where we use PPC64_ONLY(xop == Op_MemBarRelease ||)) | |
75 if (bits & StoreLoad) sync(); else lwsync(); | |
76 } | |
77 inline void MacroAssembler::release() { membar(LoadStore | StoreStore); } | |
78 inline void MacroAssembler::acquire() { membar(LoadLoad | LoadStore); } | |
79 inline void MacroAssembler::fence() { membar(LoadLoad | LoadStore | StoreLoad | StoreStore); } | |
80 | |
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81 // Address of the global TOC. |
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82 inline address MacroAssembler::global_toc() { |
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83 return CodeCache::low_bound(); |
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84 } |
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85 |
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86 // Offset of given address to the global TOC. |
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87 inline int MacroAssembler::offset_to_global_toc(const address addr) { |
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88 intptr_t offset = (intptr_t)addr - (intptr_t)MacroAssembler::global_toc(); |
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89 assert(Assembler::is_simm((long)offset, 31) && offset >= 0, "must be in range"); |
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90 return (int)offset; |
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91 } |
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92 |
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93 // Address of current method's TOC. |
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94 inline address MacroAssembler::method_toc() { |
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95 return code()->consts()->start(); |
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96 } |
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97 |
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98 // Offset of given address to current method's TOC. |
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99 inline int MacroAssembler::offset_to_method_toc(address addr) { |
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100 intptr_t offset = (intptr_t)addr - (intptr_t)method_toc(); |
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101 assert(is_simm((long)offset, 31) && offset >= 0, "must be in range"); |
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102 return (int)offset; |
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103 } |
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104 |
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105 inline bool MacroAssembler::is_calculate_address_from_global_toc_at(address a, address bound) { |
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106 const address inst2_addr = a; |
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107 const int inst2 = *(int *) a; |
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108 |
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109 // The relocation points to the second instruction, the addi. |
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110 if (!is_addi(inst2)) return false; |
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111 |
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112 // The addi reads and writes the same register dst. |
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113 const int dst = inv_rt_field(inst2); |
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114 if (inv_ra_field(inst2) != dst) return false; |
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115 |
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116 // Now, find the preceding addis which writes to dst. |
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117 int inst1 = 0; |
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118 address inst1_addr = inst2_addr - BytesPerInstWord; |
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119 while (inst1_addr >= bound) { |
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120 inst1 = *(int *) inst1_addr; |
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121 if (is_addis(inst1) && inv_rt_field(inst1) == dst) { |
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122 // stop, found the addis which writes dst |
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123 break; |
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124 } |
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125 inst1_addr -= BytesPerInstWord; |
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126 } |
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127 |
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128 if (!(inst1 == 0 || inv_ra_field(inst1) == 29 /* R29 */)) return false; |
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129 return is_addis(inst1); |
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130 } |
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131 |
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132 #ifdef _LP64 |
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133 // Detect narrow oop constants. |
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134 inline bool MacroAssembler::is_set_narrow_oop(address a, address bound) { |
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135 const address inst2_addr = a; |
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136 const int inst2 = *(int *)a; |
14445 | 137 // The relocation points to the second instruction, the ori. |
138 if (!is_ori(inst2)) return false; | |
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139 |
14445 | 140 // The ori reads and writes the same register dst. |
141 const int dst = inv_rta_field(inst2); | |
142 if (inv_rs_field(inst2) != dst) return false; | |
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143 |
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144 // Now, find the preceding addis which writes to dst. |
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145 int inst1 = 0; |
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146 address inst1_addr = inst2_addr - BytesPerInstWord; |
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147 while (inst1_addr >= bound) { |
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148 inst1 = *(int *) inst1_addr; |
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149 if (is_lis(inst1) && inv_rs_field(inst1) == dst) return true; |
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150 inst1_addr -= BytesPerInstWord; |
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151 } |
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152 return false; |
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153 } |
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154 #endif |
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155 |
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156 |
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157 inline bool MacroAssembler::is_load_const_at(address a) { |
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158 const int* p_inst = (int *) a; |
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159 bool b = is_lis(*p_inst++); |
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160 if (is_ori(*p_inst)) { |
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161 p_inst++; |
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162 b = b && is_rldicr(*p_inst++); // TODO: could be made more precise: `sldi'! |
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163 b = b && is_oris(*p_inst++); |
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164 b = b && is_ori(*p_inst); |
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165 } else if (is_lis(*p_inst)) { |
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166 p_inst++; |
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167 b = b && is_ori(*p_inst++); |
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168 b = b && is_ori(*p_inst); |
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169 // TODO: could enhance reliability by adding is_insrdi |
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170 } else return false; |
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171 return b; |
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172 } |
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173 |
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174 inline void MacroAssembler::set_oop_constant(jobject obj, Register d) { |
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175 set_oop(constant_oop_address(obj), d); |
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176 } |
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177 |
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178 inline void MacroAssembler::set_oop(AddressLiteral obj_addr, Register d) { |
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179 assert(obj_addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); |
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180 load_const(d, obj_addr); |
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181 } |
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182 |
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183 inline void MacroAssembler::pd_patch_instruction(address branch, address target) { |
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184 jint& stub_inst = *(jint*) branch; |
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185 stub_inst = patched_branch(target - branch, stub_inst, 0); |
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186 } |
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187 |
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188 // Relocation of conditional far branches. |
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189 inline bool MacroAssembler::is_bc_far_variant1_at(address instruction_addr) { |
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190 // Variant 1, the 1st instruction contains the destination address: |
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191 // |
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192 // bcxx DEST |
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193 // endgroup |
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194 // |
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195 const int instruction_1 = *(int*)(instruction_addr); |
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196 const int instruction_2 = *(int*)(instruction_addr + 4); |
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197 return is_bcxx(instruction_1) && |
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198 (inv_bd_field(instruction_1, (intptr_t)instruction_addr) != (intptr_t)(instruction_addr + 2*4)) && |
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199 is_endgroup(instruction_2); |
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200 } |
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201 |
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202 // Relocation of conditional far branches. |
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203 inline bool MacroAssembler::is_bc_far_variant2_at(address instruction_addr) { |
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204 // Variant 2, the 2nd instruction contains the destination address: |
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205 // |
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206 // b!cxx SKIP |
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207 // bxx DEST |
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208 // SKIP: |
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209 // |
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210 const int instruction_1 = *(int*)(instruction_addr); |
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211 const int instruction_2 = *(int*)(instruction_addr + 4); |
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212 return is_bcxx(instruction_1) && |
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213 (inv_bd_field(instruction_1, (intptr_t)instruction_addr) == (intptr_t)(instruction_addr + 2*4)) && |
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214 is_bxx(instruction_2); |
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215 } |
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216 |
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217 // Relocation for conditional branches |
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218 inline bool MacroAssembler::is_bc_far_variant3_at(address instruction_addr) { |
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219 // Variant 3, far cond branch to the next instruction, already patched to nops: |
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220 // |
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221 // nop |
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222 // endgroup |
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223 // SKIP/DEST: |
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224 // |
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225 const int instruction_1 = *(int*)(instruction_addr); |
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226 const int instruction_2 = *(int*)(instruction_addr + 4); |
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227 return is_nop(instruction_1) && |
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228 is_endgroup(instruction_2); |
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229 } |
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230 |
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231 |
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232 // Convenience bc_far versions |
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233 inline void MacroAssembler::blt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, less), L, optimize); } |
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234 inline void MacroAssembler::bgt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, greater), L, optimize); } |
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235 inline void MacroAssembler::beq_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, equal), L, optimize); } |
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236 inline void MacroAssembler::bso_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, summary_overflow), L, optimize); } |
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237 inline void MacroAssembler::bge_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, less), L, optimize); } |
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238 inline void MacroAssembler::ble_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, greater), L, optimize); } |
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239 inline void MacroAssembler::bne_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, equal), L, optimize); } |
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240 inline void MacroAssembler::bns_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, summary_overflow), L, optimize); } |
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241 |
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242 inline address MacroAssembler::call_stub(Register function_entry) { |
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243 mtctr(function_entry); |
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244 bctrl(); |
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245 return pc(); |
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246 } |
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247 |
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248 inline void MacroAssembler::call_stub_and_return_to(Register function_entry, Register return_pc) { |
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249 assert_different_registers(function_entry, return_pc); |
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250 mtlr(return_pc); |
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251 mtctr(function_entry); |
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252 bctr(); |
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253 } |
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254 |
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255 // Get the pc where the last emitted call will return to. |
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256 inline address MacroAssembler::last_calls_return_pc() { |
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257 return _last_calls_return_pc; |
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258 } |
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259 |
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260 // Read from the polling page, its address is already in a register. |
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261 inline void MacroAssembler::load_from_polling_page(Register polling_page_address, int offset) { |
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262 ld(R0, offset, polling_page_address); |
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263 } |
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264 |
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265 // Trap-instruction-based checks. |
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266 |
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267 inline void MacroAssembler::trap_null_check(Register a, trap_to_bits cmp) { |
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268 assert(TrapBasedNullChecks, "sanity"); |
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269 tdi(cmp, a/*reg a*/, 0); |
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270 } |
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271 inline void MacroAssembler::trap_zombie_not_entrant() { |
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272 tdi(traptoUnconditional, 0/*reg 0*/, 1); |
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273 } |
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274 inline void MacroAssembler::trap_should_not_reach_here() { |
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275 tdi_unchecked(traptoUnconditional, 0/*reg 0*/, 2); |
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276 } |
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277 |
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278 inline void MacroAssembler::trap_ic_miss_check(Register a, Register b) { |
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279 td(traptoGreaterThanUnsigned | traptoLessThanUnsigned, a, b); |
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280 } |
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281 |
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282 // Do an explicit null check if access to a+offset will not raise a SIGSEGV. |
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283 // Either issue a trap instruction that raises SIGTRAP, or do a compare that |
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284 // branches to exception_entry. |
14445 | 285 // No support for compressed oops (base page of heap). Does not distinguish |
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286 // loads and stores. |
14445 | 287 inline void MacroAssembler::null_check_throw(Register a, int offset, Register temp_reg, |
288 address exception_entry) { | |
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289 if (!ImplicitNullChecks || needs_explicit_null_check(offset) || !os::zero_page_read_protected()) { |
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290 if (TrapBasedNullChecks) { |
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291 assert(UseSIGTRAP, "sanity"); |
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292 trap_null_check(a); |
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293 } else { |
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294 Label ok; |
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295 cmpdi(CCR0, a, 0); |
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296 bne(CCR0, ok); |
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297 load_const_optimized(temp_reg, exception_entry); |
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298 mtctr(temp_reg); |
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299 bctr(); |
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300 bind(ok); |
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301 } |
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302 } |
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303 } |
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304 |
14445 | 305 inline void MacroAssembler::load_with_trap_null_check(Register d, int si16, Register s1) { |
14436
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306 if (!os::zero_page_read_protected()) { |
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307 if (TrapBasedNullChecks) { |
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308 trap_null_check(s1); |
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309 } |
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310 } |
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311 ld(d, si16, s1); |
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312 } |
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313 |
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314 inline void MacroAssembler::load_heap_oop_not_null(Register d, RegisterOrConstant offs, Register s1) { |
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315 if (UseCompressedOops) { |
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316 lwz(d, offs, s1); |
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317 // Attention: no null check here! |
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318 decode_heap_oop_not_null(d); |
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319 } else { |
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320 ld(d, offs, s1); |
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321 } |
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322 } |
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323 |
14694 | 324 inline void MacroAssembler::store_heap_oop_not_null(Register d, RegisterOrConstant offs, Register s1, Register tmp) { |
325 if (UseCompressedOops) { | |
326 Register compressedOop = encode_heap_oop_not_null((tmp != noreg) ? tmp : d, d); | |
327 stw(compressedOop, offs, s1); | |
328 } else { | |
329 std(d, offs, s1); | |
330 } | |
331 } | |
332 | |
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333 inline void MacroAssembler::load_heap_oop(Register d, RegisterOrConstant offs, Register s1) { |
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334 if (UseCompressedOops) { |
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335 lwz(d, offs, s1); |
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336 decode_heap_oop(d); |
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337 } else { |
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338 ld(d, offs, s1); |
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339 } |
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340 } |
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341 |
14694 | 342 inline Register MacroAssembler::encode_heap_oop_not_null(Register d, Register src) { |
343 Register current = (src!=noreg) ? src : d; // Compressed oop is in d if no src provided. | |
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344 if (Universe::narrow_oop_base() != NULL) { |
14694 | 345 sub(d, current, R30); |
346 current = d; | |
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347 } |
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348 if (Universe::narrow_oop_shift() != 0) { |
14694 | 349 srdi(d, current, LogMinObjAlignmentInBytes); |
350 current = d; | |
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351 } |
14694 | 352 return current; // Encoded oop is in this register. |
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353 } |
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354 |
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355 inline void MacroAssembler::decode_heap_oop_not_null(Register d) { |
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356 if (Universe::narrow_oop_shift() != 0) { |
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357 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
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358 sldi(d, d, LogMinObjAlignmentInBytes); |
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359 } |
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360 if (Universe::narrow_oop_base() != NULL) { |
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361 add(d, d, R30); |
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362 } |
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363 } |
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364 |
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365 inline void MacroAssembler::decode_heap_oop(Register d) { |
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366 Label isNull; |
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367 if (Universe::narrow_oop_base() != NULL) { |
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368 cmpwi(CCR0, d, 0); |
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369 beq(CCR0, isNull); |
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370 } |
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371 if (Universe::narrow_oop_shift() != 0) { |
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372 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
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373 sldi(d, d, LogMinObjAlignmentInBytes); |
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374 } |
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375 if (Universe::narrow_oop_base() != NULL) { |
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376 add(d, d, R30); |
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377 } |
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378 bind(isNull); |
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379 } |
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380 |
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381 // SIGTRAP-based range checks for arrays. |
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382 inline void MacroAssembler::trap_range_check_l(Register a, Register b) { |
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383 tw (traptoLessThanUnsigned, a/*reg a*/, b/*reg b*/); |
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384 } |
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385 inline void MacroAssembler::trap_range_check_l(Register a, int si16) { |
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386 twi(traptoLessThanUnsigned, a/*reg a*/, si16); |
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387 } |
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388 inline void MacroAssembler::trap_range_check_le(Register a, int si16) { |
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389 twi(traptoEqual | traptoLessThanUnsigned, a/*reg a*/, si16); |
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390 } |
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391 inline void MacroAssembler::trap_range_check_g(Register a, int si16) { |
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392 twi(traptoGreaterThanUnsigned, a/*reg a*/, si16); |
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393 } |
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394 inline void MacroAssembler::trap_range_check_ge(Register a, Register b) { |
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395 tw (traptoEqual | traptoGreaterThanUnsigned, a/*reg a*/, b/*reg b*/); |
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396 } |
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397 inline void MacroAssembler::trap_range_check_ge(Register a, int si16) { |
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398 twi(traptoEqual | traptoGreaterThanUnsigned, a/*reg a*/, si16); |
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399 } |
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400 |
14684 | 401 #if defined(ABI_ELFv2) |
402 inline address MacroAssembler::function_entry() { return pc(); } | |
403 #else | |
404 inline address MacroAssembler::function_entry() { return emit_fd(); } | |
405 #endif | |
406 | |
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407 #endif // CPU_PPC_VM_MACROASSEMBLER_PPC_INLINE_HPP |