Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/assembler_x86.cpp @ 1930:2d26b0046e0d
Merge.
author | Thomas Wuerthinger <wuerthinger@ssw.jku.at> |
---|---|
date | Tue, 30 Nov 2010 14:53:30 +0100 |
parents | 3483ec571caf 2fe998383789 |
children | 06f017f7daa7 |
rev | line source |
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0 | 1 /* |
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2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
25 #include "incls/_precompiled.incl" | |
304 | 26 #include "incls/_assembler_x86.cpp.incl" |
0 | 27 |
28 // Implementation of AddressLiteral | |
29 | |
30 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { | |
31 _is_lval = false; | |
32 _target = target; | |
33 switch (rtype) { | |
34 case relocInfo::oop_type: | |
35 // Oops are a special case. Normally they would be their own section | |
36 // but in cases like icBuffer they are literals in the code stream that | |
37 // we don't have a section for. We use none so that we get a literal address | |
38 // which is always patchable. | |
39 break; | |
40 case relocInfo::external_word_type: | |
41 _rspec = external_word_Relocation::spec(target); | |
42 break; | |
43 case relocInfo::internal_word_type: | |
44 _rspec = internal_word_Relocation::spec(target); | |
45 break; | |
46 case relocInfo::opt_virtual_call_type: | |
47 _rspec = opt_virtual_call_Relocation::spec(); | |
48 break; | |
49 case relocInfo::static_call_type: | |
50 _rspec = static_call_Relocation::spec(); | |
51 break; | |
52 case relocInfo::runtime_call_type: | |
53 _rspec = runtime_call_Relocation::spec(); | |
54 break; | |
55 case relocInfo::poll_type: | |
56 case relocInfo::poll_return_type: | |
57 _rspec = Relocation::spec_simple(rtype); | |
58 break; | |
59 case relocInfo::none: | |
60 break; | |
61 default: | |
62 ShouldNotReachHere(); | |
63 break; | |
64 } | |
65 } | |
66 | |
67 // Implementation of Address | |
68 | |
304 | 69 #ifdef _LP64 |
70 | |
0 | 71 Address Address::make_array(ArrayAddress adr) { |
72 // Not implementable on 64bit machines | |
73 // Should have been handled higher up the call chain. | |
74 ShouldNotReachHere(); | |
304 | 75 return Address(); |
76 } | |
77 | |
78 // exceedingly dangerous constructor | |
79 Address::Address(int disp, address loc, relocInfo::relocType rtype) { | |
80 _base = noreg; | |
81 _index = noreg; | |
82 _scale = no_scale; | |
83 _disp = disp; | |
84 switch (rtype) { | |
85 case relocInfo::external_word_type: | |
86 _rspec = external_word_Relocation::spec(loc); | |
87 break; | |
88 case relocInfo::internal_word_type: | |
89 _rspec = internal_word_Relocation::spec(loc); | |
90 break; | |
91 case relocInfo::runtime_call_type: | |
92 // HMM | |
93 _rspec = runtime_call_Relocation::spec(); | |
94 break; | |
95 case relocInfo::poll_type: | |
96 case relocInfo::poll_return_type: | |
97 _rspec = Relocation::spec_simple(rtype); | |
98 break; | |
99 case relocInfo::none: | |
100 break; | |
101 default: | |
102 ShouldNotReachHere(); | |
103 } | |
104 } | |
105 #else // LP64 | |
106 | |
107 Address Address::make_array(ArrayAddress adr) { | |
0 | 108 AddressLiteral base = adr.base(); |
109 Address index = adr.index(); | |
110 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
111 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); | |
112 array._rspec = base._rspec; | |
113 return array; | |
304 | 114 } |
0 | 115 |
116 // exceedingly dangerous constructor | |
117 Address::Address(address loc, RelocationHolder spec) { | |
118 _base = noreg; | |
119 _index = noreg; | |
120 _scale = no_scale; | |
121 _disp = (intptr_t) loc; | |
122 _rspec = spec; | |
123 } | |
304 | 124 |
0 | 125 #endif // _LP64 |
126 | |
304 | 127 |
128 | |
0 | 129 // Convert the raw encoding form into the form expected by the constructor for |
130 // Address. An index of 4 (rsp) corresponds to having no index, so convert | |
131 // that to noreg for the Address constructor. | |
624 | 132 Address Address::make_raw(int base, int index, int scale, int disp, bool disp_is_oop) { |
133 RelocationHolder rspec; | |
134 if (disp_is_oop) { | |
135 rspec = Relocation::spec_simple(relocInfo::oop_type); | |
136 } | |
0 | 137 bool valid_index = index != rsp->encoding(); |
138 if (valid_index) { | |
139 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); | |
624 | 140 madr._rspec = rspec; |
0 | 141 return madr; |
142 } else { | |
143 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); | |
624 | 144 madr._rspec = rspec; |
0 | 145 return madr; |
146 } | |
147 } | |
148 | |
149 // Implementation of Assembler | |
150 | |
151 int AbstractAssembler::code_fill_byte() { | |
152 return (u_char)'\xF4'; // hlt | |
153 } | |
154 | |
155 // make this go away someday | |
156 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { | |
157 if (rtype == relocInfo::none) | |
158 emit_long(data); | |
159 else emit_data(data, Relocation::spec_simple(rtype), format); | |
160 } | |
161 | |
162 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { | |
304 | 163 assert(imm_operand == 0, "default format must be immediate in this file"); |
0 | 164 assert(inst_mark() != NULL, "must be inside InstructionMark"); |
165 if (rspec.type() != relocInfo::none) { | |
166 #ifdef ASSERT | |
167 check_relocation(rspec, format); | |
168 #endif | |
169 // Do not use AbstractAssembler::relocate, which is not intended for | |
170 // embedded words. Instead, relocate to the enclosing instruction. | |
171 | |
172 // hack. call32 is too wide for mask so use disp32 | |
173 if (format == call32_operand) | |
174 code_section()->relocate(inst_mark(), rspec, disp32_operand); | |
175 else | |
176 code_section()->relocate(inst_mark(), rspec, format); | |
177 } | |
178 emit_long(data); | |
179 } | |
180 | |
304 | 181 static int encode(Register r) { |
182 int enc = r->encoding(); | |
183 if (enc >= 8) { | |
184 enc -= 8; | |
185 } | |
186 return enc; | |
187 } | |
188 | |
189 static int encode(XMMRegister r) { | |
190 int enc = r->encoding(); | |
191 if (enc >= 8) { | |
192 enc -= 8; | |
193 } | |
194 return enc; | |
195 } | |
0 | 196 |
197 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { | |
198 assert(dst->has_byte_register(), "must have byte register"); | |
199 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
200 assert(isByte(imm8), "not a byte"); | |
201 assert((op1 & 0x01) == 0, "should be 8bit operation"); | |
202 emit_byte(op1); | |
304 | 203 emit_byte(op2 | encode(dst)); |
0 | 204 emit_byte(imm8); |
205 } | |
206 | |
207 | |
304 | 208 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { |
0 | 209 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
210 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
211 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
212 if (is8bit(imm32)) { | |
213 emit_byte(op1 | 0x02); // set sign bit | |
304 | 214 emit_byte(op2 | encode(dst)); |
0 | 215 emit_byte(imm32 & 0xFF); |
216 } else { | |
217 emit_byte(op1); | |
304 | 218 emit_byte(op2 | encode(dst)); |
0 | 219 emit_long(imm32); |
220 } | |
221 } | |
222 | |
223 // immediate-to-memory forms | |
304 | 224 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { |
0 | 225 assert((op1 & 0x01) == 1, "should be 32bit operation"); |
226 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
227 if (is8bit(imm32)) { | |
228 emit_byte(op1 | 0x02); // set sign bit | |
304 | 229 emit_operand(rm, adr, 1); |
0 | 230 emit_byte(imm32 & 0xFF); |
231 } else { | |
232 emit_byte(op1); | |
304 | 233 emit_operand(rm, adr, 4); |
0 | 234 emit_long(imm32); |
235 } | |
236 } | |
237 | |
238 void Assembler::emit_arith(int op1, int op2, Register dst, jobject obj) { | |
304 | 239 LP64_ONLY(ShouldNotReachHere()); |
0 | 240 assert(isByte(op1) && isByte(op2), "wrong opcode"); |
241 assert((op1 & 0x01) == 1, "should be 32bit operation"); | |
242 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); | |
243 InstructionMark im(this); | |
244 emit_byte(op1); | |
304 | 245 emit_byte(op2 | encode(dst)); |
246 emit_data((intptr_t)obj, relocInfo::oop_type, 0); | |
0 | 247 } |
248 | |
249 | |
250 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { | |
251 assert(isByte(op1) && isByte(op2), "wrong opcode"); | |
252 emit_byte(op1); | |
304 | 253 emit_byte(op2 | encode(dst) << 3 | encode(src)); |
254 } | |
255 | |
256 | |
257 void Assembler::emit_operand(Register reg, Register base, Register index, | |
258 Address::ScaleFactor scale, int disp, | |
259 RelocationHolder const& rspec, | |
260 int rip_relative_correction) { | |
0 | 261 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); |
304 | 262 |
263 // Encode the registers as needed in the fields they are used in | |
264 | |
265 int regenc = encode(reg) << 3; | |
266 int indexenc = index->is_valid() ? encode(index) << 3 : 0; | |
267 int baseenc = base->is_valid() ? encode(base) : 0; | |
268 | |
0 | 269 if (base->is_valid()) { |
270 if (index->is_valid()) { | |
271 assert(scale != Address::no_scale, "inconsistent address"); | |
272 // [base + index*scale + disp] | |
304 | 273 if (disp == 0 && rtype == relocInfo::none && |
274 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 275 // [base + index*scale] |
276 // [00 reg 100][ss index base] | |
277 assert(index != rsp, "illegal addressing mode"); | |
304 | 278 emit_byte(0x04 | regenc); |
279 emit_byte(scale << 6 | indexenc | baseenc); | |
0 | 280 } else if (is8bit(disp) && rtype == relocInfo::none) { |
281 // [base + index*scale + imm8] | |
282 // [01 reg 100][ss index base] imm8 | |
283 assert(index != rsp, "illegal addressing mode"); | |
304 | 284 emit_byte(0x44 | regenc); |
285 emit_byte(scale << 6 | indexenc | baseenc); | |
0 | 286 emit_byte(disp & 0xFF); |
287 } else { | |
304 | 288 // [base + index*scale + disp32] |
289 // [10 reg 100][ss index base] disp32 | |
0 | 290 assert(index != rsp, "illegal addressing mode"); |
304 | 291 emit_byte(0x84 | regenc); |
292 emit_byte(scale << 6 | indexenc | baseenc); | |
0 | 293 emit_data(disp, rspec, disp32_operand); |
294 } | |
304 | 295 } else if (base == rsp LP64_ONLY(|| base == r12)) { |
296 // [rsp + disp] | |
0 | 297 if (disp == 0 && rtype == relocInfo::none) { |
304 | 298 // [rsp] |
0 | 299 // [00 reg 100][00 100 100] |
304 | 300 emit_byte(0x04 | regenc); |
0 | 301 emit_byte(0x24); |
302 } else if (is8bit(disp) && rtype == relocInfo::none) { | |
304 | 303 // [rsp + imm8] |
304 // [01 reg 100][00 100 100] disp8 | |
305 emit_byte(0x44 | regenc); | |
0 | 306 emit_byte(0x24); |
307 emit_byte(disp & 0xFF); | |
308 } else { | |
304 | 309 // [rsp + imm32] |
310 // [10 reg 100][00 100 100] disp32 | |
311 emit_byte(0x84 | regenc); | |
0 | 312 emit_byte(0x24); |
313 emit_data(disp, rspec, disp32_operand); | |
314 } | |
315 } else { | |
316 // [base + disp] | |
304 | 317 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); |
318 if (disp == 0 && rtype == relocInfo::none && | |
319 base != rbp LP64_ONLY(&& base != r13)) { | |
0 | 320 // [base] |
321 // [00 reg base] | |
304 | 322 emit_byte(0x00 | regenc | baseenc); |
0 | 323 } else if (is8bit(disp) && rtype == relocInfo::none) { |
304 | 324 // [base + disp8] |
325 // [01 reg base] disp8 | |
326 emit_byte(0x40 | regenc | baseenc); | |
0 | 327 emit_byte(disp & 0xFF); |
328 } else { | |
304 | 329 // [base + disp32] |
330 // [10 reg base] disp32 | |
331 emit_byte(0x80 | regenc | baseenc); | |
0 | 332 emit_data(disp, rspec, disp32_operand); |
333 } | |
334 } | |
335 } else { | |
336 if (index->is_valid()) { | |
337 assert(scale != Address::no_scale, "inconsistent address"); | |
338 // [index*scale + disp] | |
304 | 339 // [00 reg 100][ss index 101] disp32 |
0 | 340 assert(index != rsp, "illegal addressing mode"); |
304 | 341 emit_byte(0x04 | regenc); |
342 emit_byte(scale << 6 | indexenc | 0x05); | |
0 | 343 emit_data(disp, rspec, disp32_operand); |
304 | 344 } else if (rtype != relocInfo::none ) { |
345 // [disp] (64bit) RIP-RELATIVE (32bit) abs | |
346 // [00 000 101] disp32 | |
347 | |
348 emit_byte(0x05 | regenc); | |
349 // Note that the RIP-rel. correction applies to the generated | |
350 // disp field, but _not_ to the target address in the rspec. | |
351 | |
352 // disp was created by converting the target address minus the pc | |
353 // at the start of the instruction. That needs more correction here. | |
354 // intptr_t disp = target - next_ip; | |
355 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
356 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; | |
357 int64_t adjusted = disp; | |
358 // Do rip-rel adjustment for 64bit | |
359 LP64_ONLY(adjusted -= (next_ip - inst_mark())); | |
360 assert(is_simm32(adjusted), | |
361 "must be 32bit offset (RIP relative address)"); | |
362 emit_data((int32_t) adjusted, rspec, disp32_operand); | |
363 | |
0 | 364 } else { |
304 | 365 // 32bit never did this, did everything as the rip-rel/disp code above |
366 // [disp] ABSOLUTE | |
367 // [00 reg 100][00 100 101] disp32 | |
368 emit_byte(0x04 | regenc); | |
369 emit_byte(0x25); | |
0 | 370 emit_data(disp, rspec, disp32_operand); |
371 } | |
372 } | |
373 } | |
374 | |
304 | 375 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, |
376 Address::ScaleFactor scale, int disp, | |
377 RelocationHolder const& rspec) { | |
378 emit_operand((Register)reg, base, index, scale, disp, rspec); | |
379 } | |
380 | |
0 | 381 // Secret local extension to Assembler::WhichOperand: |
382 #define end_pc_operand (_WhichOperand_limit) | |
383 | |
384 address Assembler::locate_operand(address inst, WhichOperand which) { | |
385 // Decode the given instruction, and return the address of | |
386 // an embedded 32-bit operand word. | |
387 | |
388 // If "which" is disp32_operand, selects the displacement portion | |
389 // of an effective address specifier. | |
304 | 390 // If "which" is imm64_operand, selects the trailing immediate constant. |
0 | 391 // If "which" is call32_operand, selects the displacement of a call or jump. |
392 // Caller is responsible for ensuring that there is such an operand, | |
304 | 393 // and that it is 32/64 bits wide. |
0 | 394 |
395 // If "which" is end_pc_operand, find the end of the instruction. | |
396 | |
397 address ip = inst; | |
304 | 398 bool is_64bit = false; |
399 | |
400 debug_only(bool has_disp32 = false); | |
401 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn | |
402 | |
403 again_after_prefix: | |
0 | 404 switch (0xFF & *ip++) { |
405 | |
406 // These convenience macros generate groups of "case" labels for the switch. | |
304 | 407 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 |
408 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ | |
0 | 409 case (x)+4: case (x)+5: case (x)+6: case (x)+7 |
304 | 410 #define REP16(x) REP8((x)+0): \ |
0 | 411 case REP8((x)+8) |
412 | |
413 case CS_segment: | |
414 case SS_segment: | |
415 case DS_segment: | |
416 case ES_segment: | |
417 case FS_segment: | |
418 case GS_segment: | |
304 | 419 // Seems dubious |
420 LP64_ONLY(assert(false, "shouldn't have that prefix")); | |
0 | 421 assert(ip == inst+1, "only one prefix allowed"); |
422 goto again_after_prefix; | |
423 | |
304 | 424 case 0x67: |
425 case REX: | |
426 case REX_B: | |
427 case REX_X: | |
428 case REX_XB: | |
429 case REX_R: | |
430 case REX_RB: | |
431 case REX_RX: | |
432 case REX_RXB: | |
433 NOT_LP64(assert(false, "64bit prefixes")); | |
434 goto again_after_prefix; | |
435 | |
436 case REX_W: | |
437 case REX_WB: | |
438 case REX_WX: | |
439 case REX_WXB: | |
440 case REX_WR: | |
441 case REX_WRB: | |
442 case REX_WRX: | |
443 case REX_WRXB: | |
444 NOT_LP64(assert(false, "64bit prefixes")); | |
445 is_64bit = true; | |
446 goto again_after_prefix; | |
447 | |
448 case 0xFF: // pushq a; decl a; incl a; call a; jmp a | |
0 | 449 case 0x88: // movb a, r |
450 case 0x89: // movl a, r | |
451 case 0x8A: // movb r, a | |
452 case 0x8B: // movl r, a | |
453 case 0x8F: // popl a | |
304 | 454 debug_only(has_disp32 = true); |
0 | 455 break; |
456 | |
304 | 457 case 0x68: // pushq #32 |
458 if (which == end_pc_operand) { | |
459 return ip + 4; | |
460 } | |
461 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); | |
0 | 462 return ip; // not produced by emit_operand |
463 | |
464 case 0x66: // movw ... (size prefix) | |
304 | 465 again_after_size_prefix2: |
0 | 466 switch (0xFF & *ip++) { |
304 | 467 case REX: |
468 case REX_B: | |
469 case REX_X: | |
470 case REX_XB: | |
471 case REX_R: | |
472 case REX_RB: | |
473 case REX_RX: | |
474 case REX_RXB: | |
475 case REX_W: | |
476 case REX_WB: | |
477 case REX_WX: | |
478 case REX_WXB: | |
479 case REX_WR: | |
480 case REX_WRB: | |
481 case REX_WRX: | |
482 case REX_WRXB: | |
483 NOT_LP64(assert(false, "64bit prefix found")); | |
484 goto again_after_size_prefix2; | |
0 | 485 case 0x8B: // movw r, a |
486 case 0x89: // movw a, r | |
304 | 487 debug_only(has_disp32 = true); |
0 | 488 break; |
489 case 0xC7: // movw a, #16 | |
304 | 490 debug_only(has_disp32 = true); |
0 | 491 tail_size = 2; // the imm16 |
492 break; | |
493 case 0x0F: // several SSE/SSE2 variants | |
494 ip--; // reparse the 0x0F | |
495 goto again_after_prefix; | |
496 default: | |
497 ShouldNotReachHere(); | |
498 } | |
499 break; | |
500 | |
304 | 501 case REP8(0xB8): // movl/q r, #32/#64(oop?) |
502 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); | |
503 // these asserts are somewhat nonsensical | |
504 #ifndef _LP64 | |
505 assert(which == imm_operand || which == disp32_operand, ""); | |
506 #else | |
507 assert((which == call32_operand || which == imm_operand) && is_64bit || | |
508 which == narrow_oop_operand && !is_64bit, ""); | |
509 #endif // _LP64 | |
0 | 510 return ip; |
511 | |
512 case 0x69: // imul r, a, #32 | |
513 case 0xC7: // movl a, #32(oop?) | |
514 tail_size = 4; | |
304 | 515 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 516 break; |
517 | |
518 case 0x0F: // movx..., etc. | |
519 switch (0xFF & *ip++) { | |
520 case 0x12: // movlps | |
521 case 0x28: // movaps | |
522 case 0x2E: // ucomiss | |
523 case 0x2F: // comiss | |
524 case 0x54: // andps | |
525 case 0x55: // andnps | |
526 case 0x56: // orps | |
527 case 0x57: // xorps | |
528 case 0x6E: // movd | |
529 case 0x7E: // movd | |
530 case 0xAE: // ldmxcsr a | |
304 | 531 // 64bit side says it these have both operands but that doesn't |
532 // appear to be true | |
533 debug_only(has_disp32 = true); | |
0 | 534 break; |
535 | |
536 case 0xAD: // shrd r, a, %cl | |
537 case 0xAF: // imul r, a | |
304 | 538 case 0xBE: // movsbl r, a (movsxb) |
539 case 0xBF: // movswl r, a (movsxw) | |
540 case 0xB6: // movzbl r, a (movzxb) | |
541 case 0xB7: // movzwl r, a (movzxw) | |
0 | 542 case REP16(0x40): // cmovl cc, r, a |
543 case 0xB0: // cmpxchgb | |
544 case 0xB1: // cmpxchg | |
545 case 0xC1: // xaddl | |
546 case 0xC7: // cmpxchg8 | |
547 case REP16(0x90): // setcc a | |
304 | 548 debug_only(has_disp32 = true); |
0 | 549 // fall out of the switch to decode the address |
550 break; | |
304 | 551 |
0 | 552 case 0xAC: // shrd r, a, #8 |
304 | 553 debug_only(has_disp32 = true); |
0 | 554 tail_size = 1; // the imm8 |
555 break; | |
304 | 556 |
0 | 557 case REP16(0x80): // jcc rdisp32 |
558 if (which == end_pc_operand) return ip + 4; | |
304 | 559 assert(which == call32_operand, "jcc has no disp32 or imm"); |
0 | 560 return ip; |
561 default: | |
562 ShouldNotReachHere(); | |
563 } | |
564 break; | |
565 | |
566 case 0x81: // addl a, #32; addl r, #32 | |
567 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 568 // on 32bit in the case of cmpl, the imm might be an oop |
0 | 569 tail_size = 4; |
304 | 570 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 571 break; |
572 | |
573 case 0x83: // addl a, #8; addl r, #8 | |
574 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl | |
304 | 575 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 576 tail_size = 1; |
577 break; | |
578 | |
579 case 0x9B: | |
580 switch (0xFF & *ip++) { | |
581 case 0xD9: // fnstcw a | |
304 | 582 debug_only(has_disp32 = true); |
0 | 583 break; |
584 default: | |
585 ShouldNotReachHere(); | |
586 } | |
587 break; | |
588 | |
589 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a | |
590 case REP4(0x10): // adc... | |
591 case REP4(0x20): // and... | |
592 case REP4(0x30): // xor... | |
593 case REP4(0x08): // or... | |
594 case REP4(0x18): // sbb... | |
595 case REP4(0x28): // sub... | |
304 | 596 case 0xF7: // mull a |
597 case 0x8D: // lea r, a | |
598 case 0x87: // xchg r, a | |
0 | 599 case REP4(0x38): // cmp... |
304 | 600 case 0x85: // test r, a |
601 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 602 break; |
603 | |
604 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 | |
605 case 0xC6: // movb a, #8 | |
606 case 0x80: // cmpb a, #8 | |
607 case 0x6B: // imul r, a, #8 | |
304 | 608 debug_only(has_disp32 = true); // has both kinds of operands! |
0 | 609 tail_size = 1; // the imm8 |
610 break; | |
611 | |
612 case 0xE8: // call rdisp32 | |
613 case 0xE9: // jmp rdisp32 | |
614 if (which == end_pc_operand) return ip + 4; | |
304 | 615 assert(which == call32_operand, "call has no disp32 or imm"); |
0 | 616 return ip; |
617 | |
618 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 | |
619 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl | |
620 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a | |
621 case 0xDD: // fld_d a; fst_d a; fstp_d a | |
622 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a | |
623 case 0xDF: // fild_d a; fistp_d a | |
624 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a | |
625 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a | |
626 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a | |
304 | 627 debug_only(has_disp32 = true); |
0 | 628 break; |
629 | |
420
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630 case 0xF0: // Lock |
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631 assert(os::is_MP(), "only on MP"); |
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632 goto again_after_prefix; |
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633 |
0 | 634 case 0xF3: // For SSE |
635 case 0xF2: // For SSE2 | |
304 | 636 switch (0xFF & *ip++) { |
637 case REX: | |
638 case REX_B: | |
639 case REX_X: | |
640 case REX_XB: | |
641 case REX_R: | |
642 case REX_RB: | |
643 case REX_RX: | |
644 case REX_RXB: | |
645 case REX_W: | |
646 case REX_WB: | |
647 case REX_WX: | |
648 case REX_WXB: | |
649 case REX_WR: | |
650 case REX_WRB: | |
651 case REX_WRX: | |
652 case REX_WRXB: | |
653 NOT_LP64(assert(false, "found 64bit prefix")); | |
654 ip++; | |
655 default: | |
656 ip++; | |
657 } | |
658 debug_only(has_disp32 = true); // has both kinds of operands! | |
0 | 659 break; |
660 | |
661 default: | |
662 ShouldNotReachHere(); | |
663 | |
304 | 664 #undef REP8 |
665 #undef REP16 | |
0 | 666 } |
667 | |
668 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); | |
304 | 669 #ifdef _LP64 |
670 assert(which != imm_operand, "instruction is not a movq reg, imm64"); | |
671 #else | |
672 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); | |
673 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); | |
674 #endif // LP64 | |
675 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); | |
0 | 676 |
677 // parse the output of emit_operand | |
678 int op2 = 0xFF & *ip++; | |
679 int base = op2 & 0x07; | |
680 int op3 = -1; | |
681 const int b100 = 4; | |
682 const int b101 = 5; | |
683 if (base == b100 && (op2 >> 6) != 3) { | |
684 op3 = 0xFF & *ip++; | |
685 base = op3 & 0x07; // refetch the base | |
686 } | |
687 // now ip points at the disp (if any) | |
688 | |
689 switch (op2 >> 6) { | |
690 case 0: | |
691 // [00 reg 100][ss index base] | |
304 | 692 // [00 reg 100][00 100 esp] |
0 | 693 // [00 reg base] |
694 // [00 reg 100][ss index 101][disp32] | |
695 // [00 reg 101] [disp32] | |
696 | |
697 if (base == b101) { | |
698 if (which == disp32_operand) | |
699 return ip; // caller wants the disp32 | |
700 ip += 4; // skip the disp32 | |
701 } | |
702 break; | |
703 | |
704 case 1: | |
705 // [01 reg 100][ss index base][disp8] | |
304 | 706 // [01 reg 100][00 100 esp][disp8] |
0 | 707 // [01 reg base] [disp8] |
708 ip += 1; // skip the disp8 | |
709 break; | |
710 | |
711 case 2: | |
712 // [10 reg 100][ss index base][disp32] | |
304 | 713 // [10 reg 100][00 100 esp][disp32] |
0 | 714 // [10 reg base] [disp32] |
715 if (which == disp32_operand) | |
716 return ip; // caller wants the disp32 | |
717 ip += 4; // skip the disp32 | |
718 break; | |
719 | |
720 case 3: | |
721 // [11 reg base] (not a memory addressing mode) | |
722 break; | |
723 } | |
724 | |
725 if (which == end_pc_operand) { | |
726 return ip + tail_size; | |
727 } | |
728 | |
304 | 729 #ifdef _LP64 |
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730 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); |
304 | 731 #else |
732 assert(which == imm_operand, "instruction has only an imm field"); | |
733 #endif // LP64 | |
0 | 734 return ip; |
735 } | |
736 | |
737 address Assembler::locate_next_instruction(address inst) { | |
738 // Secretly share code with locate_operand: | |
739 return locate_operand(inst, end_pc_operand); | |
740 } | |
741 | |
742 | |
743 #ifdef ASSERT | |
744 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { | |
745 address inst = inst_mark(); | |
746 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); | |
747 address opnd; | |
748 | |
749 Relocation* r = rspec.reloc(); | |
750 if (r->type() == relocInfo::none) { | |
751 return; | |
752 } else if (r->is_call() || format == call32_operand) { | |
753 // assert(format == imm32_operand, "cannot specify a nonzero format"); | |
754 opnd = locate_operand(inst, call32_operand); | |
755 } else if (r->is_data()) { | |
304 | 756 assert(format == imm_operand || format == disp32_operand |
757 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); | |
0 | 758 opnd = locate_operand(inst, (WhichOperand)format); |
759 } else { | |
304 | 760 assert(format == imm_operand, "cannot specify a format"); |
0 | 761 return; |
762 } | |
763 assert(opnd == pc(), "must put operand where relocs can find it"); | |
764 } | |
304 | 765 #endif // ASSERT |
766 | |
767 void Assembler::emit_operand32(Register reg, Address adr) { | |
768 assert(reg->encoding() < 8, "no extended registers"); | |
769 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
770 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
771 adr._rspec); | |
772 } | |
773 | |
774 void Assembler::emit_operand(Register reg, Address adr, | |
775 int rip_relative_correction) { | |
776 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
777 adr._rspec, | |
778 rip_relative_correction); | |
779 } | |
780 | |
781 void Assembler::emit_operand(XMMRegister reg, Address adr) { | |
782 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, | |
783 adr._rspec); | |
784 } | |
785 | |
786 // MMX operations | |
787 void Assembler::emit_operand(MMXRegister reg, Address adr) { | |
788 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
789 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
790 } | |
791 | |
792 // work around gcc (3.2.1-7a) bug | |
793 void Assembler::emit_operand(Address adr, MMXRegister reg) { | |
794 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); | |
795 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); | |
0 | 796 } |
797 | |
798 | |
799 void Assembler::emit_farith(int b1, int b2, int i) { | |
800 assert(isByte(b1) && isByte(b2), "wrong opcode"); | |
801 assert(0 <= i && i < 8, "illegal stack offset"); | |
802 emit_byte(b1); | |
803 emit_byte(b2 + i); | |
804 } | |
805 | |
806 | |
304 | 807 // Now the Assembler instruction (identical for 32/64 bits) |
808 | |
809 void Assembler::adcl(Register dst, int32_t imm32) { | |
810 prefix(dst); | |
0 | 811 emit_arith(0x81, 0xD0, dst, imm32); |
812 } | |
813 | |
814 void Assembler::adcl(Register dst, Address src) { | |
815 InstructionMark im(this); | |
304 | 816 prefix(src, dst); |
0 | 817 emit_byte(0x13); |
818 emit_operand(dst, src); | |
819 } | |
820 | |
821 void Assembler::adcl(Register dst, Register src) { | |
304 | 822 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 823 emit_arith(0x13, 0xC0, dst, src); |
824 } | |
825 | |
304 | 826 void Assembler::addl(Address dst, int32_t imm32) { |
827 InstructionMark im(this); | |
828 prefix(dst); | |
829 emit_arith_operand(0x81, rax, dst, imm32); | |
830 } | |
0 | 831 |
832 void Assembler::addl(Address dst, Register src) { | |
833 InstructionMark im(this); | |
304 | 834 prefix(dst, src); |
0 | 835 emit_byte(0x01); |
836 emit_operand(src, dst); | |
837 } | |
838 | |
304 | 839 void Assembler::addl(Register dst, int32_t imm32) { |
840 prefix(dst); | |
0 | 841 emit_arith(0x81, 0xC0, dst, imm32); |
842 } | |
843 | |
844 void Assembler::addl(Register dst, Address src) { | |
845 InstructionMark im(this); | |
304 | 846 prefix(src, dst); |
0 | 847 emit_byte(0x03); |
848 emit_operand(dst, src); | |
849 } | |
850 | |
851 void Assembler::addl(Register dst, Register src) { | |
304 | 852 (void) prefix_and_encode(dst->encoding(), src->encoding()); |
0 | 853 emit_arith(0x03, 0xC0, dst, src); |
854 } | |
855 | |
856 void Assembler::addr_nop_4() { | |
857 // 4 bytes: NOP DWORD PTR [EAX+0] | |
858 emit_byte(0x0F); | |
859 emit_byte(0x1F); | |
860 emit_byte(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); | |
861 emit_byte(0); // 8-bits offset (1 byte) | |
862 } | |
863 | |
864 void Assembler::addr_nop_5() { | |
865 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset | |
866 emit_byte(0x0F); | |
867 emit_byte(0x1F); | |
868 emit_byte(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); | |
869 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
870 emit_byte(0); // 8-bits offset (1 byte) | |
871 } | |
872 | |
873 void Assembler::addr_nop_7() { | |
874 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset | |
875 emit_byte(0x0F); | |
876 emit_byte(0x1F); | |
877 emit_byte(0x80); // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); | |
878 emit_long(0); // 32-bits offset (4 bytes) | |
879 } | |
880 | |
881 void Assembler::addr_nop_8() { | |
882 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset | |
883 emit_byte(0x0F); | |
884 emit_byte(0x1F); | |
885 emit_byte(0x84); // emit_rm(cbuf, 0x2, EAX_enc, 0x4); | |
886 emit_byte(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); | |
887 emit_long(0); // 32-bits offset (4 bytes) | |
888 } | |
889 | |
304 | 890 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
891 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
892 emit_byte(0xF2); | |
893 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
894 emit_byte(0x0F); | |
895 emit_byte(0x58); | |
896 emit_byte(0xC0 | encode); | |
897 } | |
898 | |
899 void Assembler::addsd(XMMRegister dst, Address src) { | |
900 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
901 InstructionMark im(this); | |
902 emit_byte(0xF2); | |
903 prefix(src, dst); | |
904 emit_byte(0x0F); | |
905 emit_byte(0x58); | |
906 emit_operand(dst, src); | |
907 } | |
908 | |
909 void Assembler::addss(XMMRegister dst, XMMRegister src) { | |
910 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
911 emit_byte(0xF3); | |
912 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
913 emit_byte(0x0F); | |
914 emit_byte(0x58); | |
915 emit_byte(0xC0 | encode); | |
916 } | |
917 | |
918 void Assembler::addss(XMMRegister dst, Address src) { | |
919 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
920 InstructionMark im(this); | |
921 emit_byte(0xF3); | |
922 prefix(src, dst); | |
923 emit_byte(0x0F); | |
924 emit_byte(0x58); | |
925 emit_operand(dst, src); | |
926 } | |
927 | |
928 void Assembler::andl(Register dst, int32_t imm32) { | |
929 prefix(dst); | |
930 emit_arith(0x81, 0xE0, dst, imm32); | |
931 } | |
932 | |
933 void Assembler::andl(Register dst, Address src) { | |
934 InstructionMark im(this); | |
935 prefix(src, dst); | |
936 emit_byte(0x23); | |
937 emit_operand(dst, src); | |
938 } | |
939 | |
940 void Assembler::andl(Register dst, Register src) { | |
941 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
942 emit_arith(0x23, 0xC0, dst, src); | |
943 } | |
944 | |
945 void Assembler::andpd(XMMRegister dst, Address src) { | |
946 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
947 InstructionMark im(this); | |
948 emit_byte(0x66); | |
949 prefix(src, dst); | |
950 emit_byte(0x0F); | |
951 emit_byte(0x54); | |
952 emit_operand(dst, src); | |
953 } | |
954 | |
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955 void Assembler::bsfl(Register dst, Register src) { |
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956 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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957 emit_byte(0x0F); |
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958 emit_byte(0xBC); |
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959 emit_byte(0xC0 | encode); |
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960 } |
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961 |
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962 void Assembler::bsrl(Register dst, Register src) { |
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963 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
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964 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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965 emit_byte(0x0F); |
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966 emit_byte(0xBD); |
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967 emit_byte(0xC0 | encode); |
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968 } |
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969 |
304 | 970 void Assembler::bswapl(Register reg) { // bswap |
971 int encode = prefix_and_encode(reg->encoding()); | |
972 emit_byte(0x0F); | |
973 emit_byte(0xC8 | encode); | |
974 } | |
975 | |
976 void Assembler::call(Label& L, relocInfo::relocType rtype) { | |
977 // suspect disp32 is always good | |
978 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); | |
979 | |
980 if (L.is_bound()) { | |
981 const int long_size = 5; | |
982 int offs = (int)( target(L) - pc() ); | |
983 assert(offs <= 0, "assembler error"); | |
984 InstructionMark im(this); | |
985 // 1110 1000 #32-bit disp | |
986 emit_byte(0xE8); | |
987 emit_data(offs - long_size, rtype, operand); | |
988 } else { | |
989 InstructionMark im(this); | |
990 // 1110 1000 #32-bit disp | |
991 L.add_patch_at(code(), locator()); | |
992 | |
993 emit_byte(0xE8); | |
994 emit_data(int(0), rtype, operand); | |
995 } | |
996 } | |
997 | |
998 void Assembler::call(Register dst) { | |
999 // This was originally using a 32bit register encoding | |
1000 // and surely we want 64bit! | |
1001 // this is a 32bit encoding but in 64bit mode the default | |
1002 // operand size is 64bit so there is no need for the | |
1003 // wide prefix. So prefix only happens if we use the | |
1004 // new registers. Much like push/pop. | |
1005 int x = offset(); | |
1006 // this may be true but dbx disassembles it as if it | |
1007 // were 32bits... | |
1008 // int encode = prefix_and_encode(dst->encoding()); | |
1009 // if (offset() != x) assert(dst->encoding() >= 8, "what?"); | |
1010 int encode = prefixq_and_encode(dst->encoding()); | |
1011 | |
1012 emit_byte(0xFF); | |
1013 emit_byte(0xD0 | encode); | |
1014 } | |
1015 | |
1016 | |
1017 void Assembler::call(Address adr) { | |
1018 InstructionMark im(this); | |
1019 prefix(adr); | |
1020 emit_byte(0xFF); | |
1021 emit_operand(rdx, adr); | |
1022 } | |
1023 | |
1024 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { | |
1025 assert(entry != NULL, "call most probably wrong"); | |
1026 InstructionMark im(this); | |
1027 emit_byte(0xE8); | |
1028 intptr_t disp = entry - (_code_pos + sizeof(int32_t)); | |
1029 assert(is_simm32(disp), "must be 32bit offset (call2)"); | |
1030 // Technically, should use call32_operand, but this format is | |
1031 // implied by the fact that we're emitting a call instruction. | |
1032 | |
1033 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); | |
1034 emit_data((int) disp, rspec, operand); | |
1035 } | |
1036 | |
1037 void Assembler::cdql() { | |
1038 emit_byte(0x99); | |
1039 } | |
1040 | |
1041 void Assembler::cmovl(Condition cc, Register dst, Register src) { | |
1042 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1043 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1044 emit_byte(0x0F); | |
1045 emit_byte(0x40 | cc); | |
1046 emit_byte(0xC0 | encode); | |
1047 } | |
1048 | |
1049 | |
1050 void Assembler::cmovl(Condition cc, Register dst, Address src) { | |
1051 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); | |
1052 prefix(src, dst); | |
1053 emit_byte(0x0F); | |
1054 emit_byte(0x40 | cc); | |
1055 emit_operand(dst, src); | |
1056 } | |
1057 | |
1058 void Assembler::cmpb(Address dst, int imm8) { | |
1059 InstructionMark im(this); | |
1060 prefix(dst); | |
1061 emit_byte(0x80); | |
1062 emit_operand(rdi, dst, 1); | |
1063 emit_byte(imm8); | |
1064 } | |
1065 | |
1066 void Assembler::cmpl(Address dst, int32_t imm32) { | |
1067 InstructionMark im(this); | |
1068 prefix(dst); | |
1069 emit_byte(0x81); | |
1070 emit_operand(rdi, dst, 4); | |
1071 emit_long(imm32); | |
1072 } | |
1073 | |
1074 void Assembler::cmpl(Register dst, int32_t imm32) { | |
1075 prefix(dst); | |
1076 emit_arith(0x81, 0xF8, dst, imm32); | |
1077 } | |
1078 | |
1079 void Assembler::cmpl(Register dst, Register src) { | |
1080 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
1081 emit_arith(0x3B, 0xC0, dst, src); | |
1082 } | |
1083 | |
1084 | |
1085 void Assembler::cmpl(Register dst, Address src) { | |
1086 InstructionMark im(this); | |
1087 prefix(src, dst); | |
1088 emit_byte(0x3B); | |
1089 emit_operand(dst, src); | |
1090 } | |
1091 | |
1092 void Assembler::cmpw(Address dst, int imm16) { | |
1093 InstructionMark im(this); | |
1094 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); | |
1095 emit_byte(0x66); | |
1096 emit_byte(0x81); | |
1097 emit_operand(rdi, dst, 2); | |
1098 emit_word(imm16); | |
1099 } | |
1100 | |
1101 // The 32-bit cmpxchg compares the value at adr with the contents of rax, | |
1102 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. | |
1103 // The ZF is set if the compared values were equal, and cleared otherwise. | |
1104 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg | |
1105 if (Atomics & 2) { | |
1106 // caveat: no instructionmark, so this isn't relocatable. | |
1107 // Emit a synthetic, non-atomic, CAS equivalent. | |
1108 // Beware. The synthetic form sets all ICCs, not just ZF. | |
1109 // cmpxchg r,[m] is equivalent to rax, = CAS (m, rax, r) | |
1110 cmpl(rax, adr); | |
1111 movl(rax, adr); | |
1112 if (reg != rax) { | |
1113 Label L ; | |
1114 jcc(Assembler::notEqual, L); | |
1115 movl(adr, reg); | |
1116 bind(L); | |
1117 } | |
1118 } else { | |
1119 InstructionMark im(this); | |
1120 prefix(adr, reg); | |
1121 emit_byte(0x0F); | |
1122 emit_byte(0xB1); | |
1123 emit_operand(reg, adr); | |
1124 } | |
1125 } | |
1126 | |
1127 void Assembler::comisd(XMMRegister dst, Address src) { | |
1128 // NOTE: dbx seems to decode this as comiss even though the | |
1129 // 0x66 is there. Strangly ucomisd comes out correct | |
1130 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1131 emit_byte(0x66); | |
1132 comiss(dst, src); | |
1133 } | |
1134 | |
1135 void Assembler::comiss(XMMRegister dst, Address src) { | |
1136 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1137 | |
1138 InstructionMark im(this); | |
1139 prefix(src, dst); | |
1140 emit_byte(0x0F); | |
1141 emit_byte(0x2F); | |
1142 emit_operand(dst, src); | |
1143 } | |
1144 | |
1145 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { | |
1146 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1147 emit_byte(0xF3); | |
1148 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1149 emit_byte(0x0F); | |
1150 emit_byte(0xE6); | |
1151 emit_byte(0xC0 | encode); | |
1152 } | |
1153 | |
1154 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { | |
1155 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1156 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1157 emit_byte(0x0F); | |
1158 emit_byte(0x5B); | |
1159 emit_byte(0xC0 | encode); | |
1160 } | |
1161 | |
1162 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | |
1163 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1164 emit_byte(0xF2); | |
1165 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1166 emit_byte(0x0F); | |
1167 emit_byte(0x5A); | |
1168 emit_byte(0xC0 | encode); | |
1169 } | |
1170 | |
1171 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { | |
1172 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1173 emit_byte(0xF2); | |
1174 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1175 emit_byte(0x0F); | |
1176 emit_byte(0x2A); | |
1177 emit_byte(0xC0 | encode); | |
1178 } | |
1179 | |
1180 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { | |
1181 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1182 emit_byte(0xF3); | |
1183 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1184 emit_byte(0x0F); | |
1185 emit_byte(0x2A); | |
1186 emit_byte(0xC0 | encode); | |
1187 } | |
1188 | |
1189 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { | |
1190 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1191 emit_byte(0xF3); | |
1192 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1193 emit_byte(0x0F); | |
1194 emit_byte(0x5A); | |
1195 emit_byte(0xC0 | encode); | |
1196 } | |
1197 | |
1198 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { | |
1199 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1200 emit_byte(0xF2); | |
1201 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1202 emit_byte(0x0F); | |
1203 emit_byte(0x2C); | |
1204 emit_byte(0xC0 | encode); | |
1205 } | |
1206 | |
1207 void Assembler::cvttss2sil(Register dst, XMMRegister src) { | |
1208 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1209 emit_byte(0xF3); | |
1210 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1211 emit_byte(0x0F); | |
1212 emit_byte(0x2C); | |
1213 emit_byte(0xC0 | encode); | |
1214 } | |
1215 | |
1216 void Assembler::decl(Address dst) { | |
1217 // Don't use it directly. Use MacroAssembler::decrement() instead. | |
1218 InstructionMark im(this); | |
1219 prefix(dst); | |
1220 emit_byte(0xFF); | |
1221 emit_operand(rcx, dst); | |
1222 } | |
1223 | |
1224 void Assembler::divsd(XMMRegister dst, Address src) { | |
1225 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1226 InstructionMark im(this); | |
1227 emit_byte(0xF2); | |
1228 prefix(src, dst); | |
1229 emit_byte(0x0F); | |
1230 emit_byte(0x5E); | |
1231 emit_operand(dst, src); | |
1232 } | |
1233 | |
1234 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | |
1235 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1236 emit_byte(0xF2); | |
1237 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1238 emit_byte(0x0F); | |
1239 emit_byte(0x5E); | |
1240 emit_byte(0xC0 | encode); | |
1241 } | |
1242 | |
1243 void Assembler::divss(XMMRegister dst, Address src) { | |
1244 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1245 InstructionMark im(this); | |
1246 emit_byte(0xF3); | |
1247 prefix(src, dst); | |
1248 emit_byte(0x0F); | |
1249 emit_byte(0x5E); | |
1250 emit_operand(dst, src); | |
1251 } | |
1252 | |
1253 void Assembler::divss(XMMRegister dst, XMMRegister src) { | |
1254 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1255 emit_byte(0xF3); | |
1256 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1257 emit_byte(0x0F); | |
1258 emit_byte(0x5E); | |
1259 emit_byte(0xC0 | encode); | |
1260 } | |
1261 | |
1262 void Assembler::emms() { | |
1263 NOT_LP64(assert(VM_Version::supports_mmx(), "")); | |
1264 emit_byte(0x0F); | |
1265 emit_byte(0x77); | |
1266 } | |
1267 | |
1268 void Assembler::hlt() { | |
1269 emit_byte(0xF4); | |
1270 } | |
1271 | |
1272 void Assembler::idivl(Register src) { | |
1273 int encode = prefix_and_encode(src->encoding()); | |
1274 emit_byte(0xF7); | |
1275 emit_byte(0xF8 | encode); | |
1276 } | |
1277 | |
1920 | 1278 void Assembler::divl(Register src) { // Unsigned |
1279 int encode = prefix_and_encode(src->encoding()); | |
1280 emit_byte(0xF7); | |
1281 emit_byte(0xF0 | encode); | |
1282 } | |
1283 | |
304 | 1284 void Assembler::imull(Register dst, Register src) { |
1285 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1286 emit_byte(0x0F); | |
1287 emit_byte(0xAF); | |
1288 emit_byte(0xC0 | encode); | |
1289 } | |
1290 | |
1291 | |
1292 void Assembler::imull(Register dst, Register src, int value) { | |
1293 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1294 if (is8bit(value)) { | |
1295 emit_byte(0x6B); | |
1296 emit_byte(0xC0 | encode); | |
1914
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1297 emit_byte(value & 0xFF); |
304 | 1298 } else { |
1299 emit_byte(0x69); | |
1300 emit_byte(0xC0 | encode); | |
1301 emit_long(value); | |
1302 } | |
1303 } | |
1304 | |
1305 void Assembler::incl(Address dst) { | |
1306 // Don't use it directly. Use MacroAssembler::increment() instead. | |
1307 InstructionMark im(this); | |
1308 prefix(dst); | |
1309 emit_byte(0xFF); | |
1310 emit_operand(rax, dst); | |
1311 } | |
1312 | |
1313 void Assembler::jcc(Condition cc, Label& L, relocInfo::relocType rtype) { | |
1314 InstructionMark im(this); | |
1315 relocate(rtype); | |
1316 assert((0 <= cc) && (cc < 16), "illegal cc"); | |
1317 if (L.is_bound()) { | |
1318 address dst = target(L); | |
1319 assert(dst != NULL, "jcc most probably wrong"); | |
1320 | |
1321 const int short_size = 2; | |
1322 const int long_size = 6; | |
1323 intptr_t offs = (intptr_t)dst - (intptr_t)_code_pos; | |
1324 if (rtype == relocInfo::none && is8bit(offs - short_size)) { | |
1325 // 0111 tttn #8-bit disp | |
1326 emit_byte(0x70 | cc); | |
1327 emit_byte((offs - short_size) & 0xFF); | |
1328 } else { | |
1329 // 0000 1111 1000 tttn #32-bit disp | |
1330 assert(is_simm32(offs - long_size), | |
1331 "must be 32bit offset (call4)"); | |
1332 emit_byte(0x0F); | |
1333 emit_byte(0x80 | cc); | |
1334 emit_long(offs - long_size); | |
1335 } | |
1336 } else { | |
1337 // Note: could eliminate cond. jumps to this jump if condition | |
1338 // is the same however, seems to be rather unlikely case. | |
1339 // Note: use jccb() if label to be bound is very close to get | |
1340 // an 8-bit displacement | |
1341 L.add_patch_at(code(), locator()); | |
1342 emit_byte(0x0F); | |
1343 emit_byte(0x80 | cc); | |
1344 emit_long(0); | |
1345 } | |
1346 } | |
1347 | |
1348 void Assembler::jccb(Condition cc, Label& L) { | |
1349 if (L.is_bound()) { | |
1350 const int short_size = 2; | |
1351 address entry = target(L); | |
1352 assert(is8bit((intptr_t)entry - ((intptr_t)_code_pos + short_size)), | |
1353 "Dispacement too large for a short jmp"); | |
1354 intptr_t offs = (intptr_t)entry - (intptr_t)_code_pos; | |
1355 // 0111 tttn #8-bit disp | |
1356 emit_byte(0x70 | cc); | |
1357 emit_byte((offs - short_size) & 0xFF); | |
1358 } else { | |
1359 InstructionMark im(this); | |
1360 L.add_patch_at(code(), locator()); | |
1361 emit_byte(0x70 | cc); | |
1362 emit_byte(0); | |
1363 } | |
1364 } | |
1365 | |
1366 void Assembler::jmp(Address adr) { | |
1367 InstructionMark im(this); | |
1368 prefix(adr); | |
1369 emit_byte(0xFF); | |
1370 emit_operand(rsp, adr); | |
1371 } | |
1372 | |
1373 void Assembler::jmp(Label& L, relocInfo::relocType rtype) { | |
1374 if (L.is_bound()) { | |
1375 address entry = target(L); | |
1376 assert(entry != NULL, "jmp most probably wrong"); | |
1377 InstructionMark im(this); | |
1378 const int short_size = 2; | |
1379 const int long_size = 5; | |
1380 intptr_t offs = entry - _code_pos; | |
1381 if (rtype == relocInfo::none && is8bit(offs - short_size)) { | |
1382 emit_byte(0xEB); | |
1383 emit_byte((offs - short_size) & 0xFF); | |
1384 } else { | |
1385 emit_byte(0xE9); | |
1386 emit_long(offs - long_size); | |
1387 } | |
1388 } else { | |
1389 // By default, forward jumps are always 32-bit displacements, since | |
1390 // we can't yet know where the label will be bound. If you're sure that | |
1391 // the forward jump will not run beyond 256 bytes, use jmpb to | |
1392 // force an 8-bit displacement. | |
1393 InstructionMark im(this); | |
1394 relocate(rtype); | |
1395 L.add_patch_at(code(), locator()); | |
1396 emit_byte(0xE9); | |
1397 emit_long(0); | |
1398 } | |
1399 } | |
1400 | |
1401 void Assembler::jmp(Register entry) { | |
1402 int encode = prefix_and_encode(entry->encoding()); | |
1403 emit_byte(0xFF); | |
1404 emit_byte(0xE0 | encode); | |
1405 } | |
1406 | |
1407 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { | |
1408 InstructionMark im(this); | |
1409 emit_byte(0xE9); | |
1410 assert(dest != NULL, "must have a target"); | |
1411 intptr_t disp = dest - (_code_pos + sizeof(int32_t)); | |
1412 assert(is_simm32(disp), "must be 32bit offset (jmp)"); | |
1413 emit_data(disp, rspec.reloc(), call32_operand); | |
1414 } | |
1415 | |
1416 void Assembler::jmpb(Label& L) { | |
1417 if (L.is_bound()) { | |
1418 const int short_size = 2; | |
1419 address entry = target(L); | |
1420 assert(is8bit((entry - _code_pos) + short_size), | |
1421 "Dispacement too large for a short jmp"); | |
1422 assert(entry != NULL, "jmp most probably wrong"); | |
1423 intptr_t offs = entry - _code_pos; | |
1424 emit_byte(0xEB); | |
1425 emit_byte((offs - short_size) & 0xFF); | |
1426 } else { | |
1427 InstructionMark im(this); | |
1428 L.add_patch_at(code(), locator()); | |
1429 emit_byte(0xEB); | |
1430 emit_byte(0); | |
1431 } | |
1432 } | |
1433 | |
1434 void Assembler::ldmxcsr( Address src) { | |
1435 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1436 InstructionMark im(this); | |
1437 prefix(src); | |
1438 emit_byte(0x0F); | |
1439 emit_byte(0xAE); | |
1440 emit_operand(as_Register(2), src); | |
1441 } | |
1442 | |
1443 void Assembler::leal(Register dst, Address src) { | |
1444 InstructionMark im(this); | |
1445 #ifdef _LP64 | |
1446 emit_byte(0x67); // addr32 | |
1447 prefix(src, dst); | |
1448 #endif // LP64 | |
1449 emit_byte(0x8D); | |
1450 emit_operand(dst, src); | |
1451 } | |
1452 | |
1453 void Assembler::lock() { | |
1454 if (Atomics & 1) { | |
1455 // Emit either nothing, a NOP, or a NOP: prefix | |
1456 emit_byte(0x90) ; | |
1457 } else { | |
1458 emit_byte(0xF0); | |
1459 } | |
1460 } | |
1461 | |
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1462 void Assembler::lzcntl(Register dst, Register src) { |
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1463 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
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1464 emit_byte(0xF3); |
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1465 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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1466 emit_byte(0x0F); |
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1467 emit_byte(0xBD); |
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1468 emit_byte(0xC0 | encode); |
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1469 } |
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1470 |
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1471 // Emit mfence instruction |
304 | 1472 void Assembler::mfence() { |
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1473 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) |
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1474 emit_byte( 0x0F ); |
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1475 emit_byte( 0xAE ); |
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1476 emit_byte( 0xF0 ); |
304 | 1477 } |
1478 | |
1479 void Assembler::mov(Register dst, Register src) { | |
1480 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
1481 } | |
1482 | |
1483 void Assembler::movapd(XMMRegister dst, XMMRegister src) { | |
1484 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1485 int dstenc = dst->encoding(); | |
1486 int srcenc = src->encoding(); | |
1487 emit_byte(0x66); | |
1488 if (dstenc < 8) { | |
1489 if (srcenc >= 8) { | |
1490 prefix(REX_B); | |
1491 srcenc -= 8; | |
1492 } | |
1493 } else { | |
1494 if (srcenc < 8) { | |
1495 prefix(REX_R); | |
1496 } else { | |
1497 prefix(REX_RB); | |
1498 srcenc -= 8; | |
1499 } | |
1500 dstenc -= 8; | |
1501 } | |
1502 emit_byte(0x0F); | |
1503 emit_byte(0x28); | |
1504 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
1505 } | |
1506 | |
1507 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | |
1508 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1509 int dstenc = dst->encoding(); | |
1510 int srcenc = src->encoding(); | |
1511 if (dstenc < 8) { | |
1512 if (srcenc >= 8) { | |
1513 prefix(REX_B); | |
1514 srcenc -= 8; | |
1515 } | |
1516 } else { | |
1517 if (srcenc < 8) { | |
1518 prefix(REX_R); | |
1519 } else { | |
1520 prefix(REX_RB); | |
1521 srcenc -= 8; | |
1522 } | |
1523 dstenc -= 8; | |
1524 } | |
1525 emit_byte(0x0F); | |
1526 emit_byte(0x28); | |
1527 emit_byte(0xC0 | dstenc << 3 | srcenc); | |
1528 } | |
1529 | |
1530 void Assembler::movb(Register dst, Address src) { | |
1531 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
1532 InstructionMark im(this); | |
1533 prefix(src, dst, true); | |
1534 emit_byte(0x8A); | |
1535 emit_operand(dst, src); | |
1536 } | |
1537 | |
1538 | |
1539 void Assembler::movb(Address dst, int imm8) { | |
1540 InstructionMark im(this); | |
1541 prefix(dst); | |
1542 emit_byte(0xC6); | |
1543 emit_operand(rax, dst, 1); | |
1544 emit_byte(imm8); | |
1545 } | |
1546 | |
1547 | |
1548 void Assembler::movb(Address dst, Register src) { | |
1549 assert(src->has_byte_register(), "must have byte register"); | |
1550 InstructionMark im(this); | |
1551 prefix(dst, src, true); | |
1552 emit_byte(0x88); | |
1553 emit_operand(src, dst); | |
1554 } | |
1555 | |
1556 void Assembler::movdl(XMMRegister dst, Register src) { | |
1557 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1558 emit_byte(0x66); | |
1559 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1560 emit_byte(0x0F); | |
1561 emit_byte(0x6E); | |
1562 emit_byte(0xC0 | encode); | |
1563 } | |
1564 | |
1565 void Assembler::movdl(Register dst, XMMRegister src) { | |
1566 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1567 emit_byte(0x66); | |
1568 // swap src/dst to get correct prefix | |
1569 int encode = prefix_and_encode(src->encoding(), dst->encoding()); | |
1570 emit_byte(0x0F); | |
1571 emit_byte(0x7E); | |
1572 emit_byte(0xC0 | encode); | |
1573 } | |
1574 | |
1575 void Assembler::movdqa(XMMRegister dst, Address src) { | |
1576 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1577 InstructionMark im(this); | |
1578 emit_byte(0x66); | |
1579 prefix(src, dst); | |
1580 emit_byte(0x0F); | |
1581 emit_byte(0x6F); | |
1582 emit_operand(dst, src); | |
1583 } | |
1584 | |
1585 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { | |
1586 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1587 emit_byte(0x66); | |
1588 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
1589 emit_byte(0x0F); | |
1590 emit_byte(0x6F); | |
1591 emit_byte(0xC0 | encode); | |
1592 } | |
1593 | |
1594 void Assembler::movdqa(Address dst, XMMRegister src) { | |
1595 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1596 InstructionMark im(this); | |
1597 emit_byte(0x66); | |
1598 prefix(dst, src); | |
1599 emit_byte(0x0F); | |
1600 emit_byte(0x7F); | |
1601 emit_operand(src, dst); | |
1602 } | |
1603 | |
405 | 1604 void Assembler::movdqu(XMMRegister dst, Address src) { |
1605 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1606 InstructionMark im(this); | |
1607 emit_byte(0xF3); | |
1608 prefix(src, dst); | |
1609 emit_byte(0x0F); | |
1610 emit_byte(0x6F); | |
1611 emit_operand(dst, src); | |
1612 } | |
1613 | |
1614 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { | |
1615 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1616 emit_byte(0xF3); | |
1617 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
1618 emit_byte(0x0F); | |
1619 emit_byte(0x6F); | |
1620 emit_byte(0xC0 | encode); | |
1621 } | |
1622 | |
1623 void Assembler::movdqu(Address dst, XMMRegister src) { | |
1624 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1625 InstructionMark im(this); | |
1626 emit_byte(0xF3); | |
1627 prefix(dst, src); | |
1628 emit_byte(0x0F); | |
1629 emit_byte(0x7F); | |
1630 emit_operand(src, dst); | |
1631 } | |
1632 | |
304 | 1633 // Uses zero extension on 64bit |
1634 | |
1635 void Assembler::movl(Register dst, int32_t imm32) { | |
1636 int encode = prefix_and_encode(dst->encoding()); | |
1637 emit_byte(0xB8 | encode); | |
1638 emit_long(imm32); | |
1639 } | |
1640 | |
1641 void Assembler::movl(Register dst, Register src) { | |
1642 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1643 emit_byte(0x8B); | |
1644 emit_byte(0xC0 | encode); | |
1645 } | |
1646 | |
1647 void Assembler::movl(Register dst, Address src) { | |
1648 InstructionMark im(this); | |
1649 prefix(src, dst); | |
1650 emit_byte(0x8B); | |
1651 emit_operand(dst, src); | |
1652 } | |
1653 | |
1654 void Assembler::movl(Address dst, int32_t imm32) { | |
1655 InstructionMark im(this); | |
1656 prefix(dst); | |
1657 emit_byte(0xC7); | |
1658 emit_operand(rax, dst, 4); | |
1659 emit_long(imm32); | |
1660 } | |
1661 | |
1662 void Assembler::movl(Address dst, Register src) { | |
1663 InstructionMark im(this); | |
1664 prefix(dst, src); | |
1665 emit_byte(0x89); | |
1666 emit_operand(src, dst); | |
1667 } | |
1668 | |
1669 // New cpus require to use movsd and movss to avoid partial register stall | |
1670 // when loading from memory. But for old Opteron use movlpd instead of movsd. | |
1671 // The selection is done in MacroAssembler::movdbl() and movflt(). | |
1672 void Assembler::movlpd(XMMRegister dst, Address src) { | |
1673 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1674 InstructionMark im(this); | |
1675 emit_byte(0x66); | |
1676 prefix(src, dst); | |
1677 emit_byte(0x0F); | |
1678 emit_byte(0x12); | |
1679 emit_operand(dst, src); | |
1680 } | |
1681 | |
1682 void Assembler::movq( MMXRegister dst, Address src ) { | |
1683 assert( VM_Version::supports_mmx(), "" ); | |
1684 emit_byte(0x0F); | |
1685 emit_byte(0x6F); | |
1686 emit_operand(dst, src); | |
1687 } | |
1688 | |
1689 void Assembler::movq( Address dst, MMXRegister src ) { | |
1690 assert( VM_Version::supports_mmx(), "" ); | |
1691 emit_byte(0x0F); | |
1692 emit_byte(0x7F); | |
1693 // workaround gcc (3.2.1-7a) bug | |
1694 // In that version of gcc with only an emit_operand(MMX, Address) | |
1695 // gcc will tail jump and try and reverse the parameters completely | |
1696 // obliterating dst in the process. By having a version available | |
1697 // that doesn't need to swap the args at the tail jump the bug is | |
1698 // avoided. | |
1699 emit_operand(dst, src); | |
1700 } | |
1701 | |
1702 void Assembler::movq(XMMRegister dst, Address src) { | |
1703 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1704 InstructionMark im(this); | |
1705 emit_byte(0xF3); | |
1706 prefix(src, dst); | |
1707 emit_byte(0x0F); | |
1708 emit_byte(0x7E); | |
1709 emit_operand(dst, src); | |
1710 } | |
1711 | |
1712 void Assembler::movq(Address dst, XMMRegister src) { | |
1713 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1714 InstructionMark im(this); | |
1715 emit_byte(0x66); | |
1716 prefix(dst, src); | |
1717 emit_byte(0x0F); | |
1718 emit_byte(0xD6); | |
1719 emit_operand(src, dst); | |
1720 } | |
1721 | |
1722 void Assembler::movsbl(Register dst, Address src) { // movsxb | |
1723 InstructionMark im(this); | |
1724 prefix(src, dst); | |
1725 emit_byte(0x0F); | |
1726 emit_byte(0xBE); | |
1727 emit_operand(dst, src); | |
1728 } | |
1729 | |
1730 void Assembler::movsbl(Register dst, Register src) { // movsxb | |
1731 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
1732 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
1733 emit_byte(0x0F); | |
1734 emit_byte(0xBE); | |
1735 emit_byte(0xC0 | encode); | |
1736 } | |
1737 | |
1738 void Assembler::movsd(XMMRegister dst, XMMRegister src) { | |
1739 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1740 emit_byte(0xF2); | |
1741 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1742 emit_byte(0x0F); | |
1743 emit_byte(0x10); | |
1744 emit_byte(0xC0 | encode); | |
1745 } | |
1746 | |
1747 void Assembler::movsd(XMMRegister dst, Address src) { | |
1748 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1749 InstructionMark im(this); | |
1750 emit_byte(0xF2); | |
1751 prefix(src, dst); | |
1752 emit_byte(0x0F); | |
1753 emit_byte(0x10); | |
1754 emit_operand(dst, src); | |
1755 } | |
1756 | |
1757 void Assembler::movsd(Address dst, XMMRegister src) { | |
1758 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1759 InstructionMark im(this); | |
1760 emit_byte(0xF2); | |
1761 prefix(dst, src); | |
1762 emit_byte(0x0F); | |
1763 emit_byte(0x11); | |
1764 emit_operand(src, dst); | |
1765 } | |
1766 | |
1767 void Assembler::movss(XMMRegister dst, XMMRegister src) { | |
1768 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1769 emit_byte(0xF3); | |
1770 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1771 emit_byte(0x0F); | |
1772 emit_byte(0x10); | |
1773 emit_byte(0xC0 | encode); | |
1774 } | |
1775 | |
1776 void Assembler::movss(XMMRegister dst, Address src) { | |
1777 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1778 InstructionMark im(this); | |
1779 emit_byte(0xF3); | |
1780 prefix(src, dst); | |
1781 emit_byte(0x0F); | |
1782 emit_byte(0x10); | |
1783 emit_operand(dst, src); | |
1784 } | |
1785 | |
1786 void Assembler::movss(Address dst, XMMRegister src) { | |
1787 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1788 InstructionMark im(this); | |
1789 emit_byte(0xF3); | |
1790 prefix(dst, src); | |
1791 emit_byte(0x0F); | |
1792 emit_byte(0x11); | |
1793 emit_operand(src, dst); | |
1794 } | |
1795 | |
1796 void Assembler::movswl(Register dst, Address src) { // movsxw | |
1797 InstructionMark im(this); | |
1798 prefix(src, dst); | |
1799 emit_byte(0x0F); | |
1800 emit_byte(0xBF); | |
1801 emit_operand(dst, src); | |
1802 } | |
1803 | |
1804 void Assembler::movswl(Register dst, Register src) { // movsxw | |
1805 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1806 emit_byte(0x0F); | |
1807 emit_byte(0xBF); | |
1808 emit_byte(0xC0 | encode); | |
1809 } | |
1810 | |
1811 void Assembler::movw(Address dst, int imm16) { | |
1812 InstructionMark im(this); | |
1813 | |
1814 emit_byte(0x66); // switch to 16-bit mode | |
1815 prefix(dst); | |
1816 emit_byte(0xC7); | |
1817 emit_operand(rax, dst, 2); | |
1818 emit_word(imm16); | |
1819 } | |
1820 | |
1821 void Assembler::movw(Register dst, Address src) { | |
1822 InstructionMark im(this); | |
1823 emit_byte(0x66); | |
1824 prefix(src, dst); | |
1825 emit_byte(0x8B); | |
1826 emit_operand(dst, src); | |
1827 } | |
1828 | |
1829 void Assembler::movw(Address dst, Register src) { | |
1830 InstructionMark im(this); | |
1831 emit_byte(0x66); | |
1832 prefix(dst, src); | |
1833 emit_byte(0x89); | |
1834 emit_operand(src, dst); | |
1835 } | |
1836 | |
1837 void Assembler::movzbl(Register dst, Address src) { // movzxb | |
1838 InstructionMark im(this); | |
1839 prefix(src, dst); | |
1840 emit_byte(0x0F); | |
1841 emit_byte(0xB6); | |
1842 emit_operand(dst, src); | |
1843 } | |
1844 | |
1845 void Assembler::movzbl(Register dst, Register src) { // movzxb | |
1846 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); | |
1847 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true); | |
1848 emit_byte(0x0F); | |
1849 emit_byte(0xB6); | |
1850 emit_byte(0xC0 | encode); | |
1851 } | |
1852 | |
1853 void Assembler::movzwl(Register dst, Address src) { // movzxw | |
1854 InstructionMark im(this); | |
1855 prefix(src, dst); | |
1856 emit_byte(0x0F); | |
1857 emit_byte(0xB7); | |
1858 emit_operand(dst, src); | |
1859 } | |
1860 | |
1861 void Assembler::movzwl(Register dst, Register src) { // movzxw | |
1862 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1863 emit_byte(0x0F); | |
1864 emit_byte(0xB7); | |
1865 emit_byte(0xC0 | encode); | |
1866 } | |
1867 | |
1868 void Assembler::mull(Address src) { | |
1869 InstructionMark im(this); | |
1870 prefix(src); | |
1871 emit_byte(0xF7); | |
1872 emit_operand(rsp, src); | |
1873 } | |
1874 | |
1875 void Assembler::mull(Register src) { | |
1876 int encode = prefix_and_encode(src->encoding()); | |
1877 emit_byte(0xF7); | |
1878 emit_byte(0xE0 | encode); | |
1879 } | |
1880 | |
1881 void Assembler::mulsd(XMMRegister dst, Address src) { | |
1882 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1883 InstructionMark im(this); | |
1884 emit_byte(0xF2); | |
1885 prefix(src, dst); | |
1886 emit_byte(0x0F); | |
1887 emit_byte(0x59); | |
1888 emit_operand(dst, src); | |
1889 } | |
1890 | |
1891 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | |
1892 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
1893 emit_byte(0xF2); | |
1894 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1895 emit_byte(0x0F); | |
1896 emit_byte(0x59); | |
1897 emit_byte(0xC0 | encode); | |
1898 } | |
1899 | |
1900 void Assembler::mulss(XMMRegister dst, Address src) { | |
1901 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1902 InstructionMark im(this); | |
1903 emit_byte(0xF3); | |
1904 prefix(src, dst); | |
1905 emit_byte(0x0F); | |
1906 emit_byte(0x59); | |
1907 emit_operand(dst, src); | |
1908 } | |
1909 | |
1910 void Assembler::mulss(XMMRegister dst, XMMRegister src) { | |
1911 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
1912 emit_byte(0xF3); | |
1913 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
1914 emit_byte(0x0F); | |
1915 emit_byte(0x59); | |
1916 emit_byte(0xC0 | encode); | |
1917 } | |
1918 | |
1919 void Assembler::negl(Register dst) { | |
1920 int encode = prefix_and_encode(dst->encoding()); | |
1921 emit_byte(0xF7); | |
1922 emit_byte(0xD8 | encode); | |
1923 } | |
1924 | |
0 | 1925 void Assembler::nop(int i) { |
304 | 1926 #ifdef ASSERT |
0 | 1927 assert(i > 0, " "); |
304 | 1928 // The fancy nops aren't currently recognized by debuggers making it a |
1929 // pain to disassemble code while debugging. If asserts are on clearly | |
1930 // speed is not an issue so simply use the single byte traditional nop | |
1931 // to do alignment. | |
1932 | |
1933 for (; i > 0 ; i--) emit_byte(0x90); | |
1934 return; | |
1935 | |
1936 #endif // ASSERT | |
1937 | |
0 | 1938 if (UseAddressNop && VM_Version::is_intel()) { |
1939 // | |
1940 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel | |
1941 // 1: 0x90 | |
1942 // 2: 0x66 0x90 | |
1943 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
1944 // 4: 0x0F 0x1F 0x40 0x00 | |
1945 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
1946 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
1947 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
1948 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1949 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1950 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1951 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
1952 | |
1953 // The rest coding is Intel specific - don't use consecutive address nops | |
1954 | |
1955 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
1956 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
1957 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
1958 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 | |
1959 | |
1960 while(i >= 15) { | |
1961 // For Intel don't generate consecutive addess nops (mix with regular nops) | |
1962 i -= 15; | |
1963 emit_byte(0x66); // size prefix | |
1964 emit_byte(0x66); // size prefix | |
1965 emit_byte(0x66); // size prefix | |
1966 addr_nop_8(); | |
1967 emit_byte(0x66); // size prefix | |
1968 emit_byte(0x66); // size prefix | |
1969 emit_byte(0x66); // size prefix | |
1970 emit_byte(0x90); // nop | |
1971 } | |
1972 switch (i) { | |
1973 case 14: | |
1974 emit_byte(0x66); // size prefix | |
1975 case 13: | |
1976 emit_byte(0x66); // size prefix | |
1977 case 12: | |
1978 addr_nop_8(); | |
1979 emit_byte(0x66); // size prefix | |
1980 emit_byte(0x66); // size prefix | |
1981 emit_byte(0x66); // size prefix | |
1982 emit_byte(0x90); // nop | |
1983 break; | |
1984 case 11: | |
1985 emit_byte(0x66); // size prefix | |
1986 case 10: | |
1987 emit_byte(0x66); // size prefix | |
1988 case 9: | |
1989 emit_byte(0x66); // size prefix | |
1990 case 8: | |
1991 addr_nop_8(); | |
1992 break; | |
1993 case 7: | |
1994 addr_nop_7(); | |
1995 break; | |
1996 case 6: | |
1997 emit_byte(0x66); // size prefix | |
1998 case 5: | |
1999 addr_nop_5(); | |
2000 break; | |
2001 case 4: | |
2002 addr_nop_4(); | |
2003 break; | |
2004 case 3: | |
2005 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
2006 emit_byte(0x66); // size prefix | |
2007 case 2: | |
2008 emit_byte(0x66); // size prefix | |
2009 case 1: | |
2010 emit_byte(0x90); // nop | |
2011 break; | |
2012 default: | |
2013 assert(i == 0, " "); | |
2014 } | |
2015 return; | |
2016 } | |
2017 if (UseAddressNop && VM_Version::is_amd()) { | |
2018 // | |
2019 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. | |
2020 // 1: 0x90 | |
2021 // 2: 0x66 0x90 | |
2022 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) | |
2023 // 4: 0x0F 0x1F 0x40 0x00 | |
2024 // 5: 0x0F 0x1F 0x44 0x00 0x00 | |
2025 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2026 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2027 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2028 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2029 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2030 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2031 | |
2032 // The rest coding is AMD specific - use consecutive address nops | |
2033 | |
2034 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2035 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 | |
2036 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2037 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 | |
2038 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 | |
2039 // Size prefixes (0x66) are added for larger sizes | |
2040 | |
2041 while(i >= 22) { | |
2042 i -= 11; | |
2043 emit_byte(0x66); // size prefix | |
2044 emit_byte(0x66); // size prefix | |
2045 emit_byte(0x66); // size prefix | |
2046 addr_nop_8(); | |
2047 } | |
2048 // Generate first nop for size between 21-12 | |
2049 switch (i) { | |
2050 case 21: | |
2051 i -= 1; | |
2052 emit_byte(0x66); // size prefix | |
2053 case 20: | |
2054 case 19: | |
2055 i -= 1; | |
2056 emit_byte(0x66); // size prefix | |
2057 case 18: | |
2058 case 17: | |
2059 i -= 1; | |
2060 emit_byte(0x66); // size prefix | |
2061 case 16: | |
2062 case 15: | |
2063 i -= 8; | |
2064 addr_nop_8(); | |
2065 break; | |
2066 case 14: | |
2067 case 13: | |
2068 i -= 7; | |
2069 addr_nop_7(); | |
2070 break; | |
2071 case 12: | |
2072 i -= 6; | |
2073 emit_byte(0x66); // size prefix | |
2074 addr_nop_5(); | |
2075 break; | |
2076 default: | |
2077 assert(i < 12, " "); | |
2078 } | |
2079 | |
2080 // Generate second nop for size between 11-1 | |
2081 switch (i) { | |
2082 case 11: | |
2083 emit_byte(0x66); // size prefix | |
2084 case 10: | |
2085 emit_byte(0x66); // size prefix | |
2086 case 9: | |
2087 emit_byte(0x66); // size prefix | |
2088 case 8: | |
2089 addr_nop_8(); | |
2090 break; | |
2091 case 7: | |
2092 addr_nop_7(); | |
2093 break; | |
2094 case 6: | |
2095 emit_byte(0x66); // size prefix | |
2096 case 5: | |
2097 addr_nop_5(); | |
2098 break; | |
2099 case 4: | |
2100 addr_nop_4(); | |
2101 break; | |
2102 case 3: | |
2103 // Don't use "0x0F 0x1F 0x00" - need patching safe padding | |
2104 emit_byte(0x66); // size prefix | |
2105 case 2: | |
2106 emit_byte(0x66); // size prefix | |
2107 case 1: | |
2108 emit_byte(0x90); // nop | |
2109 break; | |
2110 default: | |
2111 assert(i == 0, " "); | |
2112 } | |
2113 return; | |
2114 } | |
2115 | |
2116 // Using nops with size prefixes "0x66 0x90". | |
2117 // From AMD Optimization Guide: | |
2118 // 1: 0x90 | |
2119 // 2: 0x66 0x90 | |
2120 // 3: 0x66 0x66 0x90 | |
2121 // 4: 0x66 0x66 0x66 0x90 | |
2122 // 5: 0x66 0x66 0x90 0x66 0x90 | |
2123 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 | |
2124 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 | |
2125 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 | |
2126 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2127 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 | |
2128 // | |
2129 while(i > 12) { | |
2130 i -= 4; | |
2131 emit_byte(0x66); // size prefix | |
2132 emit_byte(0x66); | |
2133 emit_byte(0x66); | |
2134 emit_byte(0x90); // nop | |
2135 } | |
2136 // 1 - 12 nops | |
2137 if(i > 8) { | |
2138 if(i > 9) { | |
2139 i -= 1; | |
2140 emit_byte(0x66); | |
2141 } | |
2142 i -= 3; | |
2143 emit_byte(0x66); | |
2144 emit_byte(0x66); | |
2145 emit_byte(0x90); | |
2146 } | |
2147 // 1 - 8 nops | |
2148 if(i > 4) { | |
2149 if(i > 6) { | |
2150 i -= 1; | |
2151 emit_byte(0x66); | |
2152 } | |
2153 i -= 3; | |
2154 emit_byte(0x66); | |
2155 emit_byte(0x66); | |
2156 emit_byte(0x90); | |
2157 } | |
2158 switch (i) { | |
2159 case 4: | |
2160 emit_byte(0x66); | |
2161 case 3: | |
2162 emit_byte(0x66); | |
2163 case 2: | |
2164 emit_byte(0x66); | |
2165 case 1: | |
2166 emit_byte(0x90); | |
2167 break; | |
2168 default: | |
2169 assert(i == 0, " "); | |
2170 } | |
2171 } | |
2172 | |
304 | 2173 void Assembler::notl(Register dst) { |
2174 int encode = prefix_and_encode(dst->encoding()); | |
2175 emit_byte(0xF7); | |
2176 emit_byte(0xD0 | encode ); | |
2177 } | |
2178 | |
2179 void Assembler::orl(Address dst, int32_t imm32) { | |
2180 InstructionMark im(this); | |
2181 prefix(dst); | |
2182 emit_byte(0x81); | |
2183 emit_operand(rcx, dst, 4); | |
2184 emit_long(imm32); | |
2185 } | |
2186 | |
2187 void Assembler::orl(Register dst, int32_t imm32) { | |
2188 prefix(dst); | |
2189 emit_arith(0x81, 0xC8, dst, imm32); | |
2190 } | |
2191 | |
2192 | |
2193 void Assembler::orl(Register dst, Address src) { | |
2194 InstructionMark im(this); | |
2195 prefix(src, dst); | |
2196 emit_byte(0x0B); | |
2197 emit_operand(dst, src); | |
2198 } | |
2199 | |
2200 | |
2201 void Assembler::orl(Register dst, Register src) { | |
2202 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2203 emit_arith(0x0B, 0xC0, dst, src); | |
2204 } | |
2205 | |
681 | 2206 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { |
2207 assert(VM_Version::supports_sse4_2(), ""); | |
2208 | |
2209 InstructionMark im(this); | |
2210 emit_byte(0x66); | |
2211 prefix(src, dst); | |
2212 emit_byte(0x0F); | |
2213 emit_byte(0x3A); | |
2214 emit_byte(0x61); | |
2215 emit_operand(dst, src); | |
2216 emit_byte(imm8); | |
2217 } | |
2218 | |
2219 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { | |
2220 assert(VM_Version::supports_sse4_2(), ""); | |
2221 | |
2222 emit_byte(0x66); | |
2223 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
2224 emit_byte(0x0F); | |
2225 emit_byte(0x3A); | |
2226 emit_byte(0x61); | |
2227 emit_byte(0xC0 | encode); | |
2228 emit_byte(imm8); | |
2229 } | |
2230 | |
304 | 2231 // generic |
2232 void Assembler::pop(Register dst) { | |
2233 int encode = prefix_and_encode(dst->encoding()); | |
2234 emit_byte(0x58 | encode); | |
2235 } | |
2236 | |
643
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2237 void Assembler::popcntl(Register dst, Address src) { |
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2238 assert(VM_Version::supports_popcnt(), "must support"); |
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2239 InstructionMark im(this); |
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2240 emit_byte(0xF3); |
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2241 prefix(src, dst); |
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2242 emit_byte(0x0F); |
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2243 emit_byte(0xB8); |
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2244 emit_operand(dst, src); |
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2245 } |
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2246 |
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2247 void Assembler::popcntl(Register dst, Register src) { |
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2248 assert(VM_Version::supports_popcnt(), "must support"); |
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2249 emit_byte(0xF3); |
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2250 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
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2251 emit_byte(0x0F); |
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2252 emit_byte(0xB8); |
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2253 emit_byte(0xC0 | encode); |
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2254 } |
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2255 |
304 | 2256 void Assembler::popf() { |
2257 emit_byte(0x9D); | |
2258 } | |
2259 | |
1060 | 2260 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 2261 void Assembler::popl(Address dst) { |
2262 // NOTE: this will adjust stack by 8byte on 64bits | |
2263 InstructionMark im(this); | |
2264 prefix(dst); | |
2265 emit_byte(0x8F); | |
2266 emit_operand(rax, dst); | |
2267 } | |
1060 | 2268 #endif |
304 | 2269 |
2270 void Assembler::prefetch_prefix(Address src) { | |
2271 prefix(src); | |
2272 emit_byte(0x0F); | |
2273 } | |
2274 | |
2275 void Assembler::prefetchnta(Address src) { | |
2276 NOT_LP64(assert(VM_Version::supports_sse2(), "must support")); | |
2277 InstructionMark im(this); | |
2278 prefetch_prefix(src); | |
2279 emit_byte(0x18); | |
2280 emit_operand(rax, src); // 0, src | |
2281 } | |
2282 | |
2283 void Assembler::prefetchr(Address src) { | |
2284 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support")); | |
2285 InstructionMark im(this); | |
2286 prefetch_prefix(src); | |
2287 emit_byte(0x0D); | |
2288 emit_operand(rax, src); // 0, src | |
2289 } | |
2290 | |
2291 void Assembler::prefetcht0(Address src) { | |
2292 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2293 InstructionMark im(this); | |
2294 prefetch_prefix(src); | |
2295 emit_byte(0x18); | |
2296 emit_operand(rcx, src); // 1, src | |
2297 } | |
2298 | |
2299 void Assembler::prefetcht1(Address src) { | |
2300 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2301 InstructionMark im(this); | |
2302 prefetch_prefix(src); | |
2303 emit_byte(0x18); | |
2304 emit_operand(rdx, src); // 2, src | |
2305 } | |
2306 | |
2307 void Assembler::prefetcht2(Address src) { | |
2308 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); | |
2309 InstructionMark im(this); | |
2310 prefetch_prefix(src); | |
2311 emit_byte(0x18); | |
2312 emit_operand(rbx, src); // 3, src | |
2313 } | |
2314 | |
2315 void Assembler::prefetchw(Address src) { | |
2316 NOT_LP64(assert(VM_Version::supports_3dnow(), "must support")); | |
2317 InstructionMark im(this); | |
2318 prefetch_prefix(src); | |
2319 emit_byte(0x0D); | |
2320 emit_operand(rcx, src); // 1, src | |
2321 } | |
2322 | |
2323 void Assembler::prefix(Prefix p) { | |
2324 a_byte(p); | |
2325 } | |
2326 | |
2327 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { | |
2328 assert(isByte(mode), "invalid value"); | |
2329 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2330 | |
2331 emit_byte(0x66); | |
2332 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2333 emit_byte(0x0F); | |
2334 emit_byte(0x70); | |
2335 emit_byte(0xC0 | encode); | |
2336 emit_byte(mode & 0xFF); | |
2337 | |
2338 } | |
2339 | |
2340 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { | |
2341 assert(isByte(mode), "invalid value"); | |
2342 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2343 | |
2344 InstructionMark im(this); | |
2345 emit_byte(0x66); | |
2346 prefix(src, dst); | |
2347 emit_byte(0x0F); | |
2348 emit_byte(0x70); | |
2349 emit_operand(dst, src); | |
2350 emit_byte(mode & 0xFF); | |
2351 } | |
2352 | |
2353 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { | |
2354 assert(isByte(mode), "invalid value"); | |
2355 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2356 | |
2357 emit_byte(0xF2); | |
2358 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2359 emit_byte(0x0F); | |
2360 emit_byte(0x70); | |
2361 emit_byte(0xC0 | encode); | |
2362 emit_byte(mode & 0xFF); | |
2363 } | |
2364 | |
2365 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { | |
2366 assert(isByte(mode), "invalid value"); | |
2367 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2368 | |
2369 InstructionMark im(this); | |
2370 emit_byte(0xF2); | |
2371 prefix(src, dst); // QQ new | |
2372 emit_byte(0x0F); | |
2373 emit_byte(0x70); | |
2374 emit_operand(dst, src); | |
2375 emit_byte(mode & 0xFF); | |
2376 } | |
2377 | |
2378 void Assembler::psrlq(XMMRegister dst, int shift) { | |
2379 // HMM Table D-1 says sse2 or mmx | |
2380 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2381 | |
2382 int encode = prefixq_and_encode(xmm2->encoding(), dst->encoding()); | |
2383 emit_byte(0x66); | |
2384 emit_byte(0x0F); | |
2385 emit_byte(0x73); | |
2386 emit_byte(0xC0 | encode); | |
2387 emit_byte(shift); | |
2388 } | |
2389 | |
681 | 2390 void Assembler::ptest(XMMRegister dst, Address src) { |
2391 assert(VM_Version::supports_sse4_1(), ""); | |
2392 | |
2393 InstructionMark im(this); | |
2394 emit_byte(0x66); | |
2395 prefix(src, dst); | |
2396 emit_byte(0x0F); | |
2397 emit_byte(0x38); | |
2398 emit_byte(0x17); | |
2399 emit_operand(dst, src); | |
2400 } | |
2401 | |
2402 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | |
2403 assert(VM_Version::supports_sse4_1(), ""); | |
2404 | |
2405 emit_byte(0x66); | |
2406 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
2407 emit_byte(0x0F); | |
2408 emit_byte(0x38); | |
2409 emit_byte(0x17); | |
2410 emit_byte(0xC0 | encode); | |
2411 } | |
2412 | |
304 | 2413 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { |
2414 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2415 emit_byte(0x66); | |
2416 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2417 emit_byte(0x0F); | |
2418 emit_byte(0x60); | |
2419 emit_byte(0xC0 | encode); | |
2420 } | |
2421 | |
2422 void Assembler::push(int32_t imm32) { | |
2423 // in 64bits we push 64bits onto the stack but only | |
2424 // take a 32bit immediate | |
2425 emit_byte(0x68); | |
2426 emit_long(imm32); | |
2427 } | |
2428 | |
2429 void Assembler::push(Register src) { | |
2430 int encode = prefix_and_encode(src->encoding()); | |
2431 | |
2432 emit_byte(0x50 | encode); | |
2433 } | |
2434 | |
2435 void Assembler::pushf() { | |
2436 emit_byte(0x9C); | |
2437 } | |
2438 | |
1060 | 2439 #ifndef _LP64 // no 32bit push/pop on amd64 |
304 | 2440 void Assembler::pushl(Address src) { |
2441 // Note this will push 64bit on 64bit | |
2442 InstructionMark im(this); | |
2443 prefix(src); | |
2444 emit_byte(0xFF); | |
2445 emit_operand(rsi, src); | |
2446 } | |
1060 | 2447 #endif |
304 | 2448 |
2449 void Assembler::pxor(XMMRegister dst, Address src) { | |
2450 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2451 InstructionMark im(this); | |
2452 emit_byte(0x66); | |
2453 prefix(src, dst); | |
2454 emit_byte(0x0F); | |
2455 emit_byte(0xEF); | |
2456 emit_operand(dst, src); | |
2457 } | |
2458 | |
2459 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | |
2460 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2461 InstructionMark im(this); | |
2462 emit_byte(0x66); | |
2463 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2464 emit_byte(0x0F); | |
2465 emit_byte(0xEF); | |
2466 emit_byte(0xC0 | encode); | |
2467 } | |
2468 | |
2469 void Assembler::rcll(Register dst, int imm8) { | |
2470 assert(isShiftCount(imm8), "illegal shift count"); | |
2471 int encode = prefix_and_encode(dst->encoding()); | |
2472 if (imm8 == 1) { | |
2473 emit_byte(0xD1); | |
2474 emit_byte(0xD0 | encode); | |
2475 } else { | |
2476 emit_byte(0xC1); | |
2477 emit_byte(0xD0 | encode); | |
2478 emit_byte(imm8); | |
2479 } | |
2480 } | |
2481 | |
2482 // copies data from [esi] to [edi] using rcx pointer sized words | |
2483 // generic | |
2484 void Assembler::rep_mov() { | |
2485 emit_byte(0xF3); | |
2486 // MOVSQ | |
2487 LP64_ONLY(prefix(REX_W)); | |
2488 emit_byte(0xA5); | |
2489 } | |
2490 | |
2491 // sets rcx pointer sized words with rax, value at [edi] | |
2492 // generic | |
2493 void Assembler::rep_set() { // rep_set | |
2494 emit_byte(0xF3); | |
2495 // STOSQ | |
2496 LP64_ONLY(prefix(REX_W)); | |
2497 emit_byte(0xAB); | |
2498 } | |
2499 | |
2500 // scans rcx pointer sized words at [edi] for occurance of rax, | |
2501 // generic | |
2502 void Assembler::repne_scan() { // repne_scan | |
2503 emit_byte(0xF2); | |
2504 // SCASQ | |
2505 LP64_ONLY(prefix(REX_W)); | |
2506 emit_byte(0xAF); | |
2507 } | |
2508 | |
2509 #ifdef _LP64 | |
2510 // scans rcx 4 byte words at [edi] for occurance of rax, | |
2511 // generic | |
2512 void Assembler::repne_scanl() { // repne_scan | |
2513 emit_byte(0xF2); | |
2514 // SCASL | |
2515 emit_byte(0xAF); | |
2516 } | |
2517 #endif | |
2518 | |
0 | 2519 void Assembler::ret(int imm16) { |
2520 if (imm16 == 0) { | |
2521 emit_byte(0xC3); | |
2522 } else { | |
2523 emit_byte(0xC2); | |
2524 emit_word(imm16); | |
2525 } | |
2526 } | |
2527 | |
304 | 2528 void Assembler::sahf() { |
2529 #ifdef _LP64 | |
2530 // Not supported in 64bit mode | |
2531 ShouldNotReachHere(); | |
2532 #endif | |
2533 emit_byte(0x9E); | |
2534 } | |
2535 | |
2536 void Assembler::sarl(Register dst, int imm8) { | |
2537 int encode = prefix_and_encode(dst->encoding()); | |
2538 assert(isShiftCount(imm8), "illegal shift count"); | |
2539 if (imm8 == 1) { | |
2540 emit_byte(0xD1); | |
2541 emit_byte(0xF8 | encode); | |
2542 } else { | |
2543 emit_byte(0xC1); | |
2544 emit_byte(0xF8 | encode); | |
2545 emit_byte(imm8); | |
2546 } | |
2547 } | |
2548 | |
2549 void Assembler::sarl(Register dst) { | |
2550 int encode = prefix_and_encode(dst->encoding()); | |
2551 emit_byte(0xD3); | |
2552 emit_byte(0xF8 | encode); | |
2553 } | |
2554 | |
2555 void Assembler::sbbl(Address dst, int32_t imm32) { | |
2556 InstructionMark im(this); | |
2557 prefix(dst); | |
2558 emit_arith_operand(0x81, rbx, dst, imm32); | |
2559 } | |
2560 | |
2561 void Assembler::sbbl(Register dst, int32_t imm32) { | |
2562 prefix(dst); | |
2563 emit_arith(0x81, 0xD8, dst, imm32); | |
2564 } | |
2565 | |
2566 | |
2567 void Assembler::sbbl(Register dst, Address src) { | |
2568 InstructionMark im(this); | |
2569 prefix(src, dst); | |
2570 emit_byte(0x1B); | |
2571 emit_operand(dst, src); | |
2572 } | |
2573 | |
2574 void Assembler::sbbl(Register dst, Register src) { | |
2575 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2576 emit_arith(0x1B, 0xC0, dst, src); | |
2577 } | |
2578 | |
2579 void Assembler::setb(Condition cc, Register dst) { | |
2580 assert(0 <= cc && cc < 16, "illegal cc"); | |
2581 int encode = prefix_and_encode(dst->encoding(), true); | |
0 | 2582 emit_byte(0x0F); |
304 | 2583 emit_byte(0x90 | cc); |
2584 emit_byte(0xC0 | encode); | |
2585 } | |
2586 | |
2587 void Assembler::shll(Register dst, int imm8) { | |
2588 assert(isShiftCount(imm8), "illegal shift count"); | |
2589 int encode = prefix_and_encode(dst->encoding()); | |
2590 if (imm8 == 1 ) { | |
2591 emit_byte(0xD1); | |
2592 emit_byte(0xE0 | encode); | |
2593 } else { | |
2594 emit_byte(0xC1); | |
2595 emit_byte(0xE0 | encode); | |
2596 emit_byte(imm8); | |
2597 } | |
2598 } | |
2599 | |
2600 void Assembler::shll(Register dst) { | |
2601 int encode = prefix_and_encode(dst->encoding()); | |
2602 emit_byte(0xD3); | |
2603 emit_byte(0xE0 | encode); | |
2604 } | |
2605 | |
2606 void Assembler::shrl(Register dst, int imm8) { | |
2607 assert(isShiftCount(imm8), "illegal shift count"); | |
2608 int encode = prefix_and_encode(dst->encoding()); | |
2609 emit_byte(0xC1); | |
2610 emit_byte(0xE8 | encode); | |
2611 emit_byte(imm8); | |
2612 } | |
2613 | |
2614 void Assembler::shrl(Register dst) { | |
2615 int encode = prefix_and_encode(dst->encoding()); | |
2616 emit_byte(0xD3); | |
2617 emit_byte(0xE8 | encode); | |
2618 } | |
0 | 2619 |
2620 // copies a single word from [esi] to [edi] | |
2621 void Assembler::smovl() { | |
2622 emit_byte(0xA5); | |
2623 } | |
2624 | |
304 | 2625 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2626 // HMM Table D-1 says sse2 | |
2627 // NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2628 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2629 emit_byte(0xF2); | |
2630 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2631 emit_byte(0x0F); | |
2632 emit_byte(0x51); | |
2633 emit_byte(0xC0 | encode); | |
2634 } | |
2635 | |
2636 void Assembler::stmxcsr( Address dst) { | |
2637 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2638 InstructionMark im(this); | |
2639 prefix(dst); | |
2640 emit_byte(0x0F); | |
2641 emit_byte(0xAE); | |
2642 emit_operand(as_Register(3), dst); | |
2643 } | |
2644 | |
2645 void Assembler::subl(Address dst, int32_t imm32) { | |
2646 InstructionMark im(this); | |
2647 prefix(dst); | |
2648 if (is8bit(imm32)) { | |
2649 emit_byte(0x83); | |
2650 emit_operand(rbp, dst, 1); | |
2651 emit_byte(imm32 & 0xFF); | |
2652 } else { | |
2653 emit_byte(0x81); | |
2654 emit_operand(rbp, dst, 4); | |
2655 emit_long(imm32); | |
2656 } | |
2657 } | |
2658 | |
2659 void Assembler::subl(Register dst, int32_t imm32) { | |
2660 prefix(dst); | |
2661 emit_arith(0x81, 0xE8, dst, imm32); | |
2662 } | |
2663 | |
2664 void Assembler::subl(Address dst, Register src) { | |
2665 InstructionMark im(this); | |
2666 prefix(dst, src); | |
2667 emit_byte(0x29); | |
2668 emit_operand(src, dst); | |
2669 } | |
2670 | |
2671 void Assembler::subl(Register dst, Address src) { | |
2672 InstructionMark im(this); | |
2673 prefix(src, dst); | |
2674 emit_byte(0x2B); | |
2675 emit_operand(dst, src); | |
2676 } | |
2677 | |
2678 void Assembler::subl(Register dst, Register src) { | |
2679 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2680 emit_arith(0x2B, 0xC0, dst, src); | |
2681 } | |
2682 | |
2683 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | |
2684 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2685 emit_byte(0xF2); | |
2686 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2687 emit_byte(0x0F); | |
2688 emit_byte(0x5C); | |
2689 emit_byte(0xC0 | encode); | |
2690 } | |
2691 | |
2692 void Assembler::subsd(XMMRegister dst, Address src) { | |
2693 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2694 InstructionMark im(this); | |
2695 emit_byte(0xF2); | |
2696 prefix(src, dst); | |
2697 emit_byte(0x0F); | |
2698 emit_byte(0x5C); | |
2699 emit_operand(dst, src); | |
2700 } | |
2701 | |
2702 void Assembler::subss(XMMRegister dst, XMMRegister src) { | |
2703 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
0 | 2704 emit_byte(0xF3); |
304 | 2705 int encode = prefix_and_encode(dst->encoding(), src->encoding()); |
2706 emit_byte(0x0F); | |
2707 emit_byte(0x5C); | |
2708 emit_byte(0xC0 | encode); | |
2709 } | |
2710 | |
2711 void Assembler::subss(XMMRegister dst, Address src) { | |
2712 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2713 InstructionMark im(this); | |
2714 emit_byte(0xF3); | |
2715 prefix(src, dst); | |
2716 emit_byte(0x0F); | |
2717 emit_byte(0x5C); | |
2718 emit_operand(dst, src); | |
2719 } | |
2720 | |
2721 void Assembler::testb(Register dst, int imm8) { | |
2722 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); | |
2723 (void) prefix_and_encode(dst->encoding(), true); | |
2724 emit_arith_b(0xF6, 0xC0, dst, imm8); | |
2725 } | |
2726 | |
2727 void Assembler::testl(Register dst, int32_t imm32) { | |
2728 // not using emit_arith because test | |
2729 // doesn't support sign-extension of | |
2730 // 8bit operands | |
2731 int encode = dst->encoding(); | |
2732 if (encode == 0) { | |
2733 emit_byte(0xA9); | |
2734 } else { | |
2735 encode = prefix_and_encode(encode); | |
2736 emit_byte(0xF7); | |
2737 emit_byte(0xC0 | encode); | |
2738 } | |
2739 emit_long(imm32); | |
2740 } | |
2741 | |
2742 void Assembler::testl(Register dst, Register src) { | |
2743 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2744 emit_arith(0x85, 0xC0, dst, src); | |
2745 } | |
2746 | |
2747 void Assembler::testl(Register dst, Address src) { | |
2748 InstructionMark im(this); | |
2749 prefix(src, dst); | |
2750 emit_byte(0x85); | |
2751 emit_operand(dst, src); | |
2752 } | |
2753 | |
2754 void Assembler::ucomisd(XMMRegister dst, Address src) { | |
2755 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2756 emit_byte(0x66); | |
2757 ucomiss(dst, src); | |
2758 } | |
2759 | |
2760 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { | |
2761 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2762 emit_byte(0x66); | |
2763 ucomiss(dst, src); | |
2764 } | |
2765 | |
2766 void Assembler::ucomiss(XMMRegister dst, Address src) { | |
2767 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2768 | |
2769 InstructionMark im(this); | |
2770 prefix(src, dst); | |
2771 emit_byte(0x0F); | |
2772 emit_byte(0x2E); | |
2773 emit_operand(dst, src); | |
2774 } | |
2775 | |
2776 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { | |
2777 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2778 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2779 emit_byte(0x0F); | |
2780 emit_byte(0x2E); | |
2781 emit_byte(0xC0 | encode); | |
2782 } | |
2783 | |
2784 | |
2785 void Assembler::xaddl(Address dst, Register src) { | |
2786 InstructionMark im(this); | |
2787 prefix(dst, src); | |
0 | 2788 emit_byte(0x0F); |
304 | 2789 emit_byte(0xC1); |
2790 emit_operand(src, dst); | |
2791 } | |
2792 | |
2793 void Assembler::xchgl(Register dst, Address src) { // xchg | |
2794 InstructionMark im(this); | |
2795 prefix(src, dst); | |
2796 emit_byte(0x87); | |
2797 emit_operand(dst, src); | |
2798 } | |
2799 | |
2800 void Assembler::xchgl(Register dst, Register src) { | |
2801 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2802 emit_byte(0x87); | |
2803 emit_byte(0xc0 | encode); | |
2804 } | |
2805 | |
2806 void Assembler::xorl(Register dst, int32_t imm32) { | |
2807 prefix(dst); | |
2808 emit_arith(0x81, 0xF0, dst, imm32); | |
2809 } | |
2810 | |
2811 void Assembler::xorl(Register dst, Address src) { | |
2812 InstructionMark im(this); | |
2813 prefix(src, dst); | |
2814 emit_byte(0x33); | |
2815 emit_operand(dst, src); | |
2816 } | |
2817 | |
2818 void Assembler::xorl(Register dst, Register src) { | |
2819 (void) prefix_and_encode(dst->encoding(), src->encoding()); | |
2820 emit_arith(0x33, 0xC0, dst, src); | |
2821 } | |
2822 | |
2823 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | |
2824 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2825 emit_byte(0x66); | |
2826 xorps(dst, src); | |
2827 } | |
2828 | |
2829 void Assembler::xorpd(XMMRegister dst, Address src) { | |
2830 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
2831 InstructionMark im(this); | |
2832 emit_byte(0x66); | |
2833 prefix(src, dst); | |
2834 emit_byte(0x0F); | |
2835 emit_byte(0x57); | |
2836 emit_operand(dst, src); | |
2837 } | |
2838 | |
2839 | |
2840 void Assembler::xorps(XMMRegister dst, XMMRegister src) { | |
2841 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2842 int encode = prefix_and_encode(dst->encoding(), src->encoding()); | |
2843 emit_byte(0x0F); | |
2844 emit_byte(0x57); | |
2845 emit_byte(0xC0 | encode); | |
2846 } | |
2847 | |
2848 void Assembler::xorps(XMMRegister dst, Address src) { | |
2849 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
2850 InstructionMark im(this); | |
2851 prefix(src, dst); | |
2852 emit_byte(0x0F); | |
2853 emit_byte(0x57); | |
2854 emit_operand(dst, src); | |
2855 } | |
2856 | |
2857 #ifndef _LP64 | |
2858 // 32bit only pieces of the assembler | |
2859 | |
2860 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { | |
2861 // NO PREFIX AS NEVER 64BIT | |
2862 InstructionMark im(this); | |
2863 emit_byte(0x81); | |
2864 emit_byte(0xF8 | src1->encoding()); | |
2865 emit_data(imm32, rspec, 0); | |
2866 } | |
2867 | |
2868 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { | |
2869 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs | |
2870 InstructionMark im(this); | |
2871 emit_byte(0x81); | |
2872 emit_operand(rdi, src1); | |
2873 emit_data(imm32, rspec, 0); | |
2874 } | |
2875 | |
2876 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, | |
2877 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded | |
2878 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. | |
2879 void Assembler::cmpxchg8(Address adr) { | |
2880 InstructionMark im(this); | |
2881 emit_byte(0x0F); | |
2882 emit_byte(0xc7); | |
2883 emit_operand(rcx, adr); | |
2884 } | |
2885 | |
2886 void Assembler::decl(Register dst) { | |
2887 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
2888 emit_byte(0x48 | dst->encoding()); | |
2889 } | |
2890 | |
2891 #endif // _LP64 | |
2892 | |
2893 // 64bit typically doesn't use the x87 but needs to for the trig funcs | |
2894 | |
2895 void Assembler::fabs() { | |
2896 emit_byte(0xD9); | |
2897 emit_byte(0xE1); | |
2898 } | |
2899 | |
2900 void Assembler::fadd(int i) { | |
2901 emit_farith(0xD8, 0xC0, i); | |
2902 } | |
2903 | |
2904 void Assembler::fadd_d(Address src) { | |
2905 InstructionMark im(this); | |
2906 emit_byte(0xDC); | |
2907 emit_operand32(rax, src); | |
2908 } | |
2909 | |
2910 void Assembler::fadd_s(Address src) { | |
2911 InstructionMark im(this); | |
2912 emit_byte(0xD8); | |
2913 emit_operand32(rax, src); | |
2914 } | |
2915 | |
2916 void Assembler::fadda(int i) { | |
2917 emit_farith(0xDC, 0xC0, i); | |
2918 } | |
2919 | |
2920 void Assembler::faddp(int i) { | |
2921 emit_farith(0xDE, 0xC0, i); | |
2922 } | |
2923 | |
2924 void Assembler::fchs() { | |
2925 emit_byte(0xD9); | |
2926 emit_byte(0xE0); | |
2927 } | |
2928 | |
2929 void Assembler::fcom(int i) { | |
2930 emit_farith(0xD8, 0xD0, i); | |
2931 } | |
2932 | |
2933 void Assembler::fcomp(int i) { | |
2934 emit_farith(0xD8, 0xD8, i); | |
2935 } | |
2936 | |
2937 void Assembler::fcomp_d(Address src) { | |
2938 InstructionMark im(this); | |
2939 emit_byte(0xDC); | |
2940 emit_operand32(rbx, src); | |
2941 } | |
2942 | |
2943 void Assembler::fcomp_s(Address src) { | |
2944 InstructionMark im(this); | |
2945 emit_byte(0xD8); | |
2946 emit_operand32(rbx, src); | |
2947 } | |
2948 | |
2949 void Assembler::fcompp() { | |
2950 emit_byte(0xDE); | |
2951 emit_byte(0xD9); | |
2952 } | |
2953 | |
2954 void Assembler::fcos() { | |
2955 emit_byte(0xD9); | |
0 | 2956 emit_byte(0xFF); |
304 | 2957 } |
2958 | |
2959 void Assembler::fdecstp() { | |
2960 emit_byte(0xD9); | |
2961 emit_byte(0xF6); | |
2962 } | |
2963 | |
2964 void Assembler::fdiv(int i) { | |
2965 emit_farith(0xD8, 0xF0, i); | |
2966 } | |
2967 | |
2968 void Assembler::fdiv_d(Address src) { | |
2969 InstructionMark im(this); | |
2970 emit_byte(0xDC); | |
2971 emit_operand32(rsi, src); | |
2972 } | |
2973 | |
2974 void Assembler::fdiv_s(Address src) { | |
2975 InstructionMark im(this); | |
2976 emit_byte(0xD8); | |
2977 emit_operand32(rsi, src); | |
2978 } | |
2979 | |
2980 void Assembler::fdiva(int i) { | |
2981 emit_farith(0xDC, 0xF8, i); | |
2982 } | |
2983 | |
2984 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) | |
2985 // is erroneous for some of the floating-point instructions below. | |
2986 | |
2987 void Assembler::fdivp(int i) { | |
2988 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) | |
2989 } | |
2990 | |
2991 void Assembler::fdivr(int i) { | |
2992 emit_farith(0xD8, 0xF8, i); | |
2993 } | |
2994 | |
2995 void Assembler::fdivr_d(Address src) { | |
2996 InstructionMark im(this); | |
2997 emit_byte(0xDC); | |
2998 emit_operand32(rdi, src); | |
2999 } | |
3000 | |
3001 void Assembler::fdivr_s(Address src) { | |
3002 InstructionMark im(this); | |
3003 emit_byte(0xD8); | |
3004 emit_operand32(rdi, src); | |
3005 } | |
3006 | |
3007 void Assembler::fdivra(int i) { | |
3008 emit_farith(0xDC, 0xF0, i); | |
3009 } | |
3010 | |
3011 void Assembler::fdivrp(int i) { | |
3012 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) | |
3013 } | |
3014 | |
3015 void Assembler::ffree(int i) { | |
3016 emit_farith(0xDD, 0xC0, i); | |
3017 } | |
3018 | |
3019 void Assembler::fild_d(Address adr) { | |
3020 InstructionMark im(this); | |
3021 emit_byte(0xDF); | |
3022 emit_operand32(rbp, adr); | |
3023 } | |
3024 | |
3025 void Assembler::fild_s(Address adr) { | |
3026 InstructionMark im(this); | |
3027 emit_byte(0xDB); | |
3028 emit_operand32(rax, adr); | |
3029 } | |
3030 | |
3031 void Assembler::fincstp() { | |
3032 emit_byte(0xD9); | |
3033 emit_byte(0xF7); | |
3034 } | |
3035 | |
3036 void Assembler::finit() { | |
3037 emit_byte(0x9B); | |
3038 emit_byte(0xDB); | |
3039 emit_byte(0xE3); | |
3040 } | |
3041 | |
3042 void Assembler::fist_s(Address adr) { | |
3043 InstructionMark im(this); | |
3044 emit_byte(0xDB); | |
3045 emit_operand32(rdx, adr); | |
3046 } | |
3047 | |
3048 void Assembler::fistp_d(Address adr) { | |
3049 InstructionMark im(this); | |
3050 emit_byte(0xDF); | |
3051 emit_operand32(rdi, adr); | |
3052 } | |
3053 | |
3054 void Assembler::fistp_s(Address adr) { | |
3055 InstructionMark im(this); | |
3056 emit_byte(0xDB); | |
3057 emit_operand32(rbx, adr); | |
3058 } | |
0 | 3059 |
3060 void Assembler::fld1() { | |
3061 emit_byte(0xD9); | |
3062 emit_byte(0xE8); | |
3063 } | |
3064 | |
304 | 3065 void Assembler::fld_d(Address adr) { |
3066 InstructionMark im(this); | |
3067 emit_byte(0xDD); | |
3068 emit_operand32(rax, adr); | |
3069 } | |
0 | 3070 |
3071 void Assembler::fld_s(Address adr) { | |
3072 InstructionMark im(this); | |
3073 emit_byte(0xD9); | |
304 | 3074 emit_operand32(rax, adr); |
3075 } | |
3076 | |
3077 | |
3078 void Assembler::fld_s(int index) { | |
0 | 3079 emit_farith(0xD9, 0xC0, index); |
3080 } | |
3081 | |
3082 void Assembler::fld_x(Address adr) { | |
3083 InstructionMark im(this); | |
3084 emit_byte(0xDB); | |
304 | 3085 emit_operand32(rbp, adr); |
3086 } | |
3087 | |
3088 void Assembler::fldcw(Address src) { | |
3089 InstructionMark im(this); | |
3090 emit_byte(0xd9); | |
3091 emit_operand32(rbp, src); | |
3092 } | |
3093 | |
3094 void Assembler::fldenv(Address src) { | |
0 | 3095 InstructionMark im(this); |
3096 emit_byte(0xD9); | |
304 | 3097 emit_operand32(rsp, src); |
3098 } | |
3099 | |
3100 void Assembler::fldlg2() { | |
0 | 3101 emit_byte(0xD9); |
304 | 3102 emit_byte(0xEC); |
3103 } | |
0 | 3104 |
3105 void Assembler::fldln2() { | |
3106 emit_byte(0xD9); | |
3107 emit_byte(0xED); | |
3108 } | |
3109 | |
304 | 3110 void Assembler::fldz() { |
0 | 3111 emit_byte(0xD9); |
304 | 3112 emit_byte(0xEE); |
3113 } | |
0 | 3114 |
3115 void Assembler::flog() { | |
3116 fldln2(); | |
3117 fxch(); | |
3118 fyl2x(); | |
3119 } | |
3120 | |
3121 void Assembler::flog10() { | |
3122 fldlg2(); | |
3123 fxch(); | |
3124 fyl2x(); | |
3125 } | |
3126 | |
304 | 3127 void Assembler::fmul(int i) { |
3128 emit_farith(0xD8, 0xC8, i); | |
3129 } | |
3130 | |
3131 void Assembler::fmul_d(Address src) { | |
3132 InstructionMark im(this); | |
3133 emit_byte(0xDC); | |
3134 emit_operand32(rcx, src); | |
3135 } | |
3136 | |
3137 void Assembler::fmul_s(Address src) { | |
3138 InstructionMark im(this); | |
3139 emit_byte(0xD8); | |
3140 emit_operand32(rcx, src); | |
3141 } | |
3142 | |
3143 void Assembler::fmula(int i) { | |
3144 emit_farith(0xDC, 0xC8, i); | |
3145 } | |
3146 | |
3147 void Assembler::fmulp(int i) { | |
3148 emit_farith(0xDE, 0xC8, i); | |
3149 } | |
3150 | |
3151 void Assembler::fnsave(Address dst) { | |
3152 InstructionMark im(this); | |
3153 emit_byte(0xDD); | |
3154 emit_operand32(rsi, dst); | |
3155 } | |
3156 | |
3157 void Assembler::fnstcw(Address src) { | |
3158 InstructionMark im(this); | |
3159 emit_byte(0x9B); | |
3160 emit_byte(0xD9); | |
3161 emit_operand32(rdi, src); | |
3162 } | |
3163 | |
3164 void Assembler::fnstsw_ax() { | |
3165 emit_byte(0xdF); | |
3166 emit_byte(0xE0); | |
3167 } | |
3168 | |
3169 void Assembler::fprem() { | |
3170 emit_byte(0xD9); | |
3171 emit_byte(0xF8); | |
3172 } | |
3173 | |
3174 void Assembler::fprem1() { | |
3175 emit_byte(0xD9); | |
3176 emit_byte(0xF5); | |
3177 } | |
3178 | |
3179 void Assembler::frstor(Address src) { | |
3180 InstructionMark im(this); | |
3181 emit_byte(0xDD); | |
3182 emit_operand32(rsp, src); | |
3183 } | |
0 | 3184 |
3185 void Assembler::fsin() { | |
3186 emit_byte(0xD9); | |
3187 emit_byte(0xFE); | |
3188 } | |
3189 | |
304 | 3190 void Assembler::fsqrt() { |
3191 emit_byte(0xD9); | |
3192 emit_byte(0xFA); | |
3193 } | |
3194 | |
3195 void Assembler::fst_d(Address adr) { | |
3196 InstructionMark im(this); | |
3197 emit_byte(0xDD); | |
3198 emit_operand32(rdx, adr); | |
3199 } | |
3200 | |
3201 void Assembler::fst_s(Address adr) { | |
3202 InstructionMark im(this); | |
3203 emit_byte(0xD9); | |
3204 emit_operand32(rdx, adr); | |
3205 } | |
3206 | |
3207 void Assembler::fstp_d(Address adr) { | |
3208 InstructionMark im(this); | |
3209 emit_byte(0xDD); | |
3210 emit_operand32(rbx, adr); | |
3211 } | |
3212 | |
3213 void Assembler::fstp_d(int index) { | |
3214 emit_farith(0xDD, 0xD8, index); | |
3215 } | |
3216 | |
3217 void Assembler::fstp_s(Address adr) { | |
3218 InstructionMark im(this); | |
0 | 3219 emit_byte(0xD9); |
304 | 3220 emit_operand32(rbx, adr); |
3221 } | |
3222 | |
3223 void Assembler::fstp_x(Address adr) { | |
3224 InstructionMark im(this); | |
3225 emit_byte(0xDB); | |
3226 emit_operand32(rdi, adr); | |
3227 } | |
3228 | |
3229 void Assembler::fsub(int i) { | |
3230 emit_farith(0xD8, 0xE0, i); | |
3231 } | |
3232 | |
3233 void Assembler::fsub_d(Address src) { | |
3234 InstructionMark im(this); | |
3235 emit_byte(0xDC); | |
3236 emit_operand32(rsp, src); | |
3237 } | |
3238 | |
3239 void Assembler::fsub_s(Address src) { | |
3240 InstructionMark im(this); | |
3241 emit_byte(0xD8); | |
3242 emit_operand32(rsp, src); | |
3243 } | |
3244 | |
3245 void Assembler::fsuba(int i) { | |
3246 emit_farith(0xDC, 0xE8, i); | |
3247 } | |
3248 | |
3249 void Assembler::fsubp(int i) { | |
3250 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) | |
3251 } | |
3252 | |
3253 void Assembler::fsubr(int i) { | |
3254 emit_farith(0xD8, 0xE8, i); | |
3255 } | |
3256 | |
3257 void Assembler::fsubr_d(Address src) { | |
3258 InstructionMark im(this); | |
3259 emit_byte(0xDC); | |
3260 emit_operand32(rbp, src); | |
3261 } | |
3262 | |
3263 void Assembler::fsubr_s(Address src) { | |
3264 InstructionMark im(this); | |
3265 emit_byte(0xD8); | |
3266 emit_operand32(rbp, src); | |
3267 } | |
3268 | |
3269 void Assembler::fsubra(int i) { | |
3270 emit_farith(0xDC, 0xE0, i); | |
3271 } | |
3272 | |
3273 void Assembler::fsubrp(int i) { | |
3274 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) | |
0 | 3275 } |
3276 | |
3277 void Assembler::ftan() { | |
3278 emit_byte(0xD9); | |
3279 emit_byte(0xF2); | |
3280 emit_byte(0xDD); | |
3281 emit_byte(0xD8); | |
3282 } | |
3283 | |
304 | 3284 void Assembler::ftst() { |
0 | 3285 emit_byte(0xD9); |
304 | 3286 emit_byte(0xE4); |
3287 } | |
0 | 3288 |
3289 void Assembler::fucomi(int i) { | |
3290 // make sure the instruction is supported (introduced for P6, together with cmov) | |
3291 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
3292 emit_farith(0xDB, 0xE8, i); | |
3293 } | |
3294 | |
3295 void Assembler::fucomip(int i) { | |
3296 // make sure the instruction is supported (introduced for P6, together with cmov) | |
3297 guarantee(VM_Version::supports_cmov(), "illegal instruction"); | |
3298 emit_farith(0xDF, 0xE8, i); | |
3299 } | |
3300 | |
3301 void Assembler::fwait() { | |
3302 emit_byte(0x9B); | |
3303 } | |
3304 | |
304 | 3305 void Assembler::fxch(int i) { |
3306 emit_farith(0xD9, 0xC8, i); | |
3307 } | |
3308 | |
3309 void Assembler::fyl2x() { | |
0 | 3310 emit_byte(0xD9); |
304 | 3311 emit_byte(0xF1); |
3312 } | |
3313 | |
3314 | |
3315 #ifndef _LP64 | |
3316 | |
3317 void Assembler::incl(Register dst) { | |
3318 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
3319 emit_byte(0x40 | dst->encoding()); | |
3320 } | |
3321 | |
3322 void Assembler::lea(Register dst, Address src) { | |
3323 leal(dst, src); | |
3324 } | |
3325 | |
3326 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { | |
3327 InstructionMark im(this); | |
3328 emit_byte(0xC7); | |
3329 emit_operand(rax, dst); | |
3330 emit_data((int)imm32, rspec, 0); | |
3331 } | |
3332 | |
642
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3333 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
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3334 InstructionMark im(this); |
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3335 int encode = prefix_and_encode(dst->encoding()); |
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3336 emit_byte(0xB8 | encode); |
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3337 emit_data((int)imm32, rspec, 0); |
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|
3338 } |
304 | 3339 |
3340 void Assembler::popa() { // 32bit | |
3341 emit_byte(0x61); | |
3342 } | |
3343 | |
3344 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { | |
3345 InstructionMark im(this); | |
3346 emit_byte(0x68); | |
3347 emit_data(imm32, rspec, 0); | |
3348 } | |
3349 | |
3350 void Assembler::pusha() { // 32bit | |
3351 emit_byte(0x60); | |
3352 } | |
3353 | |
3354 void Assembler::set_byte_if_not_zero(Register dst) { | |
0 | 3355 emit_byte(0x0F); |
304 | 3356 emit_byte(0x95); |
3357 emit_byte(0xE0 | dst->encoding()); | |
3358 } | |
3359 | |
3360 void Assembler::shldl(Register dst, Register src) { | |
0 | 3361 emit_byte(0x0F); |
304 | 3362 emit_byte(0xA5); |
3363 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
3364 } | |
3365 | |
3366 void Assembler::shrdl(Register dst, Register src) { | |
0 | 3367 emit_byte(0x0F); |
304 | 3368 emit_byte(0xAD); |
3369 emit_byte(0xC0 | src->encoding() << 3 | dst->encoding()); | |
3370 } | |
3371 | |
3372 #else // LP64 | |
3373 | |
1369 | 3374 void Assembler::set_byte_if_not_zero(Register dst) { |
3375 int enc = prefix_and_encode(dst->encoding(), true); | |
3376 emit_byte(0x0F); | |
3377 emit_byte(0x95); | |
3378 emit_byte(0xE0 | enc); | |
3379 } | |
3380 | |
304 | 3381 // 64bit only pieces of the assembler |
3382 // This should only be used by 64bit instructions that can use rip-relative | |
3383 // it cannot be used by instructions that want an immediate value. | |
3384 | |
3385 bool Assembler::reachable(AddressLiteral adr) { | |
3386 int64_t disp; | |
3387 // None will force a 64bit literal to the code stream. Likely a placeholder | |
3388 // for something that will be patched later and we need to certain it will | |
3389 // always be reachable. | |
3390 if (adr.reloc() == relocInfo::none) { | |
3391 return false; | |
3392 } | |
3393 if (adr.reloc() == relocInfo::internal_word_type) { | |
3394 // This should be rip relative and easily reachable. | |
3395 return true; | |
3396 } | |
3397 if (adr.reloc() == relocInfo::virtual_call_type || | |
3398 adr.reloc() == relocInfo::opt_virtual_call_type || | |
3399 adr.reloc() == relocInfo::static_call_type || | |
3400 adr.reloc() == relocInfo::static_stub_type ) { | |
3401 // This should be rip relative within the code cache and easily | |
3402 // reachable until we get huge code caches. (At which point | |
3403 // ic code is going to have issues). | |
3404 return true; | |
3405 } | |
3406 if (adr.reloc() != relocInfo::external_word_type && | |
3407 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special | |
3408 adr.reloc() != relocInfo::poll_type && // relocs to identify them | |
3409 adr.reloc() != relocInfo::runtime_call_type ) { | |
3410 return false; | |
3411 } | |
3412 | |
3413 // Stress the correction code | |
3414 if (ForceUnreachable) { | |
3415 // Must be runtimecall reloc, see if it is in the codecache | |
3416 // Flipping stuff in the codecache to be unreachable causes issues | |
3417 // with things like inline caches where the additional instructions | |
3418 // are not handled. | |
3419 if (CodeCache::find_blob(adr._target) == NULL) { | |
3420 return false; | |
3421 } | |
3422 } | |
3423 // For external_word_type/runtime_call_type if it is reachable from where we | |
3424 // are now (possibly a temp buffer) and where we might end up | |
3425 // anywhere in the codeCache then we are always reachable. | |
3426 // This would have to change if we ever save/restore shared code | |
3427 // to be more pessimistic. | |
3428 | |
3429 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); | |
3430 if (!is_simm32(disp)) return false; | |
3431 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); | |
3432 if (!is_simm32(disp)) return false; | |
3433 | |
3434 disp = (int64_t)adr._target - ((int64_t)_code_pos + sizeof(int)); | |
3435 | |
3436 // Because rip relative is a disp + address_of_next_instruction and we | |
3437 // don't know the value of address_of_next_instruction we apply a fudge factor | |
3438 // to make sure we will be ok no matter the size of the instruction we get placed into. | |
3439 // We don't have to fudge the checks above here because they are already worst case. | |
3440 | |
3441 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal | |
3442 // + 4 because better safe than sorry. | |
3443 const int fudge = 12 + 4; | |
3444 if (disp < 0) { | |
3445 disp -= fudge; | |
3446 } else { | |
3447 disp += fudge; | |
3448 } | |
3449 return is_simm32(disp); | |
3450 } | |
3451 | |
3452 void Assembler::emit_data64(jlong data, | |
3453 relocInfo::relocType rtype, | |
3454 int format) { | |
3455 if (rtype == relocInfo::none) { | |
3456 emit_long64(data); | |
3457 } else { | |
3458 emit_data64(data, Relocation::spec_simple(rtype), format); | |
3459 } | |
3460 } | |
3461 | |
3462 void Assembler::emit_data64(jlong data, | |
3463 RelocationHolder const& rspec, | |
3464 int format) { | |
3465 assert(imm_operand == 0, "default format must be immediate in this file"); | |
3466 assert(imm_operand == format, "must be immediate"); | |
3467 assert(inst_mark() != NULL, "must be inside InstructionMark"); | |
3468 // Do not use AbstractAssembler::relocate, which is not intended for | |
3469 // embedded words. Instead, relocate to the enclosing instruction. | |
3470 code_section()->relocate(inst_mark(), rspec, format); | |
3471 #ifdef ASSERT | |
3472 check_relocation(rspec, format); | |
3473 #endif | |
3474 emit_long64(data); | |
3475 } | |
3476 | |
3477 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { | |
3478 if (reg_enc >= 8) { | |
3479 prefix(REX_B); | |
3480 reg_enc -= 8; | |
3481 } else if (byteinst && reg_enc >= 4) { | |
3482 prefix(REX); | |
3483 } | |
3484 return reg_enc; | |
3485 } | |
3486 | |
3487 int Assembler::prefixq_and_encode(int reg_enc) { | |
3488 if (reg_enc < 8) { | |
3489 prefix(REX_W); | |
3490 } else { | |
3491 prefix(REX_WB); | |
3492 reg_enc -= 8; | |
3493 } | |
3494 return reg_enc; | |
3495 } | |
3496 | |
3497 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) { | |
3498 if (dst_enc < 8) { | |
3499 if (src_enc >= 8) { | |
3500 prefix(REX_B); | |
3501 src_enc -= 8; | |
3502 } else if (byteinst && src_enc >= 4) { | |
3503 prefix(REX); | |
3504 } | |
3505 } else { | |
3506 if (src_enc < 8) { | |
3507 prefix(REX_R); | |
3508 } else { | |
3509 prefix(REX_RB); | |
3510 src_enc -= 8; | |
3511 } | |
3512 dst_enc -= 8; | |
3513 } | |
3514 return dst_enc << 3 | src_enc; | |
3515 } | |
3516 | |
3517 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { | |
3518 if (dst_enc < 8) { | |
3519 if (src_enc < 8) { | |
3520 prefix(REX_W); | |
3521 } else { | |
3522 prefix(REX_WB); | |
3523 src_enc -= 8; | |
3524 } | |
3525 } else { | |
3526 if (src_enc < 8) { | |
3527 prefix(REX_WR); | |
3528 } else { | |
3529 prefix(REX_WRB); | |
3530 src_enc -= 8; | |
3531 } | |
3532 dst_enc -= 8; | |
3533 } | |
3534 return dst_enc << 3 | src_enc; | |
3535 } | |
3536 | |
3537 void Assembler::prefix(Register reg) { | |
3538 if (reg->encoding() >= 8) { | |
3539 prefix(REX_B); | |
3540 } | |
3541 } | |
3542 | |
3543 void Assembler::prefix(Address adr) { | |
3544 if (adr.base_needs_rex()) { | |
3545 if (adr.index_needs_rex()) { | |
3546 prefix(REX_XB); | |
3547 } else { | |
3548 prefix(REX_B); | |
3549 } | |
3550 } else { | |
3551 if (adr.index_needs_rex()) { | |
3552 prefix(REX_X); | |
3553 } | |
3554 } | |
3555 } | |
3556 | |
3557 void Assembler::prefixq(Address adr) { | |
3558 if (adr.base_needs_rex()) { | |
3559 if (adr.index_needs_rex()) { | |
3560 prefix(REX_WXB); | |
3561 } else { | |
3562 prefix(REX_WB); | |
3563 } | |
3564 } else { | |
3565 if (adr.index_needs_rex()) { | |
3566 prefix(REX_WX); | |
3567 } else { | |
3568 prefix(REX_W); | |
3569 } | |
3570 } | |
3571 } | |
3572 | |
3573 | |
3574 void Assembler::prefix(Address adr, Register reg, bool byteinst) { | |
3575 if (reg->encoding() < 8) { | |
3576 if (adr.base_needs_rex()) { | |
3577 if (adr.index_needs_rex()) { | |
3578 prefix(REX_XB); | |
3579 } else { | |
3580 prefix(REX_B); | |
3581 } | |
3582 } else { | |
3583 if (adr.index_needs_rex()) { | |
3584 prefix(REX_X); | |
3585 } else if (reg->encoding() >= 4 ) { | |
3586 prefix(REX); | |
3587 } | |
3588 } | |
3589 } else { | |
3590 if (adr.base_needs_rex()) { | |
3591 if (adr.index_needs_rex()) { | |
3592 prefix(REX_RXB); | |
3593 } else { | |
3594 prefix(REX_RB); | |
3595 } | |
3596 } else { | |
3597 if (adr.index_needs_rex()) { | |
3598 prefix(REX_RX); | |
3599 } else { | |
3600 prefix(REX_R); | |
3601 } | |
3602 } | |
3603 } | |
3604 } | |
3605 | |
3606 void Assembler::prefixq(Address adr, Register src) { | |
3607 if (src->encoding() < 8) { | |
3608 if (adr.base_needs_rex()) { | |
3609 if (adr.index_needs_rex()) { | |
3610 prefix(REX_WXB); | |
3611 } else { | |
3612 prefix(REX_WB); | |
3613 } | |
3614 } else { | |
3615 if (adr.index_needs_rex()) { | |
3616 prefix(REX_WX); | |
3617 } else { | |
3618 prefix(REX_W); | |
3619 } | |
3620 } | |
3621 } else { | |
3622 if (adr.base_needs_rex()) { | |
3623 if (adr.index_needs_rex()) { | |
3624 prefix(REX_WRXB); | |
3625 } else { | |
3626 prefix(REX_WRB); | |
3627 } | |
3628 } else { | |
3629 if (adr.index_needs_rex()) { | |
3630 prefix(REX_WRX); | |
3631 } else { | |
3632 prefix(REX_WR); | |
3633 } | |
3634 } | |
3635 } | |
3636 } | |
3637 | |
3638 void Assembler::prefix(Address adr, XMMRegister reg) { | |
3639 if (reg->encoding() < 8) { | |
3640 if (adr.base_needs_rex()) { | |
3641 if (adr.index_needs_rex()) { | |
3642 prefix(REX_XB); | |
3643 } else { | |
3644 prefix(REX_B); | |
3645 } | |
3646 } else { | |
3647 if (adr.index_needs_rex()) { | |
3648 prefix(REX_X); | |
3649 } | |
3650 } | |
3651 } else { | |
3652 if (adr.base_needs_rex()) { | |
3653 if (adr.index_needs_rex()) { | |
3654 prefix(REX_RXB); | |
3655 } else { | |
3656 prefix(REX_RB); | |
3657 } | |
3658 } else { | |
3659 if (adr.index_needs_rex()) { | |
3660 prefix(REX_RX); | |
3661 } else { | |
3662 prefix(REX_R); | |
3663 } | |
3664 } | |
3665 } | |
3666 } | |
3667 | |
3668 void Assembler::adcq(Register dst, int32_t imm32) { | |
3669 (void) prefixq_and_encode(dst->encoding()); | |
3670 emit_arith(0x81, 0xD0, dst, imm32); | |
3671 } | |
3672 | |
3673 void Assembler::adcq(Register dst, Address src) { | |
3674 InstructionMark im(this); | |
3675 prefixq(src, dst); | |
3676 emit_byte(0x13); | |
3677 emit_operand(dst, src); | |
3678 } | |
3679 | |
3680 void Assembler::adcq(Register dst, Register src) { | |
3681 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
3682 emit_arith(0x13, 0xC0, dst, src); | |
3683 } | |
3684 | |
3685 void Assembler::addq(Address dst, int32_t imm32) { | |
3686 InstructionMark im(this); | |
3687 prefixq(dst); | |
3688 emit_arith_operand(0x81, rax, dst,imm32); | |
3689 } | |
3690 | |
3691 void Assembler::addq(Address dst, Register src) { | |
3692 InstructionMark im(this); | |
3693 prefixq(dst, src); | |
3694 emit_byte(0x01); | |
3695 emit_operand(src, dst); | |
3696 } | |
3697 | |
3698 void Assembler::addq(Register dst, int32_t imm32) { | |
3699 (void) prefixq_and_encode(dst->encoding()); | |
3700 emit_arith(0x81, 0xC0, dst, imm32); | |
3701 } | |
3702 | |
3703 void Assembler::addq(Register dst, Address src) { | |
3704 InstructionMark im(this); | |
3705 prefixq(src, dst); | |
3706 emit_byte(0x03); | |
3707 emit_operand(dst, src); | |
3708 } | |
3709 | |
3710 void Assembler::addq(Register dst, Register src) { | |
3711 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
3712 emit_arith(0x03, 0xC0, dst, src); | |
3713 } | |
3714 | |
3715 void Assembler::andq(Register dst, int32_t imm32) { | |
3716 (void) prefixq_and_encode(dst->encoding()); | |
3717 emit_arith(0x81, 0xE0, dst, imm32); | |
3718 } | |
3719 | |
3720 void Assembler::andq(Register dst, Address src) { | |
3721 InstructionMark im(this); | |
3722 prefixq(src, dst); | |
3723 emit_byte(0x23); | |
3724 emit_operand(dst, src); | |
3725 } | |
3726 | |
3727 void Assembler::andq(Register dst, Register src) { | |
3728 (int) prefixq_and_encode(dst->encoding(), src->encoding()); | |
3729 emit_arith(0x23, 0xC0, dst, src); | |
3730 } | |
3731 | |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3732 void Assembler::bsfq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3733 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3734 emit_byte(0x0F); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3735 emit_byte(0xBC); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3736 emit_byte(0xC0 | encode); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
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diff
changeset
|
3737 } |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3738 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3739 void Assembler::bsrq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
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diff
changeset
|
3740 assert(!VM_Version::supports_lzcnt(), "encoding is treated as LZCNT"); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3741 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
changeset
|
3742 emit_byte(0x0F); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
710
diff
changeset
|
3743 emit_byte(0xBD); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
3744 emit_byte(0xC0 | encode); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
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diff
changeset
|
3745 } |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
3746 |
304 | 3747 void Assembler::bswapq(Register reg) { |
3748 int encode = prefixq_and_encode(reg->encoding()); | |
3749 emit_byte(0x0F); | |
3750 emit_byte(0xC8 | encode); | |
3751 } | |
3752 | |
3753 void Assembler::cdqq() { | |
3754 prefix(REX_W); | |
3755 emit_byte(0x99); | |
3756 } | |
3757 | |
3758 void Assembler::clflush(Address adr) { | |
3759 prefix(adr); | |
3760 emit_byte(0x0F); | |
3761 emit_byte(0xAE); | |
3762 emit_operand(rdi, adr); | |
3763 } | |
3764 | |
3765 void Assembler::cmovq(Condition cc, Register dst, Register src) { | |
3766 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3767 emit_byte(0x0F); | |
3768 emit_byte(0x40 | cc); | |
3769 emit_byte(0xC0 | encode); | |
3770 } | |
3771 | |
3772 void Assembler::cmovq(Condition cc, Register dst, Address src) { | |
3773 InstructionMark im(this); | |
3774 prefixq(src, dst); | |
3775 emit_byte(0x0F); | |
3776 emit_byte(0x40 | cc); | |
3777 emit_operand(dst, src); | |
3778 } | |
3779 | |
3780 void Assembler::cmpq(Address dst, int32_t imm32) { | |
3781 InstructionMark im(this); | |
3782 prefixq(dst); | |
3783 emit_byte(0x81); | |
3784 emit_operand(rdi, dst, 4); | |
3785 emit_long(imm32); | |
3786 } | |
3787 | |
3788 void Assembler::cmpq(Register dst, int32_t imm32) { | |
3789 (void) prefixq_and_encode(dst->encoding()); | |
3790 emit_arith(0x81, 0xF8, dst, imm32); | |
3791 } | |
3792 | |
3793 void Assembler::cmpq(Address dst, Register src) { | |
3794 InstructionMark im(this); | |
3795 prefixq(dst, src); | |
3796 emit_byte(0x3B); | |
3797 emit_operand(src, dst); | |
3798 } | |
3799 | |
3800 void Assembler::cmpq(Register dst, Register src) { | |
3801 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
3802 emit_arith(0x3B, 0xC0, dst, src); | |
3803 } | |
3804 | |
3805 void Assembler::cmpq(Register dst, Address src) { | |
3806 InstructionMark im(this); | |
3807 prefixq(src, dst); | |
3808 emit_byte(0x3B); | |
3809 emit_operand(dst, src); | |
3810 } | |
3811 | |
3812 void Assembler::cmpxchgq(Register reg, Address adr) { | |
3813 InstructionMark im(this); | |
3814 prefixq(adr, reg); | |
3815 emit_byte(0x0F); | |
3816 emit_byte(0xB1); | |
3817 emit_operand(reg, adr); | |
3818 } | |
3819 | |
3820 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { | |
3821 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3822 emit_byte(0xF2); | |
3823 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3824 emit_byte(0x0F); | |
3825 emit_byte(0x2A); | |
3826 emit_byte(0xC0 | encode); | |
3827 } | |
3828 | |
3829 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { | |
3830 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
3831 emit_byte(0xF3); | |
3832 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3833 emit_byte(0x0F); | |
3834 emit_byte(0x2A); | |
3835 emit_byte(0xC0 | encode); | |
3836 } | |
3837 | |
3838 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { | |
3839 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
3840 emit_byte(0xF2); | |
3841 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3842 emit_byte(0x0F); | |
3843 emit_byte(0x2C); | |
3844 emit_byte(0xC0 | encode); | |
3845 } | |
3846 | |
3847 void Assembler::cvttss2siq(Register dst, XMMRegister src) { | |
3848 NOT_LP64(assert(VM_Version::supports_sse(), "")); | |
3849 emit_byte(0xF3); | |
3850 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3851 emit_byte(0x0F); | |
3852 emit_byte(0x2C); | |
3853 emit_byte(0xC0 | encode); | |
3854 } | |
3855 | |
3856 void Assembler::decl(Register dst) { | |
3857 // Don't use it directly. Use MacroAssembler::decrementl() instead. | |
3858 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) | |
3859 int encode = prefix_and_encode(dst->encoding()); | |
3860 emit_byte(0xFF); | |
3861 emit_byte(0xC8 | encode); | |
3862 } | |
3863 | |
3864 void Assembler::decq(Register dst) { | |
3865 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
3866 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
3867 int encode = prefixq_and_encode(dst->encoding()); | |
3868 emit_byte(0xFF); | |
3869 emit_byte(0xC8 | encode); | |
3870 } | |
3871 | |
3872 void Assembler::decq(Address dst) { | |
3873 // Don't use it directly. Use MacroAssembler::decrementq() instead. | |
3874 InstructionMark im(this); | |
3875 prefixq(dst); | |
3876 emit_byte(0xFF); | |
3877 emit_operand(rcx, dst); | |
3878 } | |
3879 | |
3880 void Assembler::fxrstor(Address src) { | |
3881 prefixq(src); | |
3882 emit_byte(0x0F); | |
3883 emit_byte(0xAE); | |
3884 emit_operand(as_Register(1), src); | |
3885 } | |
3886 | |
3887 void Assembler::fxsave(Address dst) { | |
3888 prefixq(dst); | |
3889 emit_byte(0x0F); | |
3890 emit_byte(0xAE); | |
3891 emit_operand(as_Register(0), dst); | |
3892 } | |
3893 | |
3894 void Assembler::idivq(Register src) { | |
3895 int encode = prefixq_and_encode(src->encoding()); | |
3896 emit_byte(0xF7); | |
3897 emit_byte(0xF8 | encode); | |
3898 } | |
3899 | |
3900 void Assembler::imulq(Register dst, Register src) { | |
3901 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3902 emit_byte(0x0F); | |
3903 emit_byte(0xAF); | |
3904 emit_byte(0xC0 | encode); | |
3905 } | |
3906 | |
3907 void Assembler::imulq(Register dst, Register src, int value) { | |
3908 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
3909 if (is8bit(value)) { | |
3910 emit_byte(0x6B); | |
3911 emit_byte(0xC0 | encode); | |
1914
ae065c367d93
6987135: Performance regression on Intel platform with 32-bits edition between 6u13 and 6u14.
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1846
diff
changeset
|
3912 emit_byte(value & 0xFF); |
304 | 3913 } else { |
3914 emit_byte(0x69); | |
3915 emit_byte(0xC0 | encode); | |
3916 emit_long(value); | |
3917 } | |
3918 } | |
3919 | |
3920 void Assembler::incl(Register dst) { | |
3921 // Don't use it directly. Use MacroAssembler::incrementl() instead. | |
3922 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
3923 int encode = prefix_and_encode(dst->encoding()); | |
3924 emit_byte(0xFF); | |
3925 emit_byte(0xC0 | encode); | |
3926 } | |
3927 | |
3928 void Assembler::incq(Register dst) { | |
3929 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
3930 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) | |
3931 int encode = prefixq_and_encode(dst->encoding()); | |
3932 emit_byte(0xFF); | |
3933 emit_byte(0xC0 | encode); | |
3934 } | |
3935 | |
3936 void Assembler::incq(Address dst) { | |
3937 // Don't use it directly. Use MacroAssembler::incrementq() instead. | |
3938 InstructionMark im(this); | |
3939 prefixq(dst); | |
3940 emit_byte(0xFF); | |
3941 emit_operand(rax, dst); | |
3942 } | |
3943 | |
3944 void Assembler::lea(Register dst, Address src) { | |
3945 leaq(dst, src); | |
3946 } | |
3947 | |
3948 void Assembler::leaq(Register dst, Address src) { | |
3949 InstructionMark im(this); | |
3950 prefixq(src, dst); | |
3951 emit_byte(0x8D); | |
3952 emit_operand(dst, src); | |
3953 } | |
3954 | |
3955 void Assembler::mov64(Register dst, int64_t imm64) { | |
3956 InstructionMark im(this); | |
3957 int encode = prefixq_and_encode(dst->encoding()); | |
3958 emit_byte(0xB8 | encode); | |
3959 emit_long64(imm64); | |
3960 } | |
3961 | |
3962 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { | |
3963 InstructionMark im(this); | |
3964 int encode = prefixq_and_encode(dst->encoding()); | |
3965 emit_byte(0xB8 | encode); | |
3966 emit_data64(imm64, rspec); | |
3967 } | |
3968 | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
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|
3969 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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diff
changeset
|
3970 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3971 int encode = prefix_and_encode(dst->encoding()); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
3972 emit_byte(0xB8 | encode); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3973 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
3974 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3975 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
3976 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3977 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3978 prefix(dst); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3979 emit_byte(0xC7); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3980 emit_operand(rax, dst, 4); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3981 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3982 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3983 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3984 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3985 InstructionMark im(this); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3986 int encode = prefix_and_encode(src1->encoding()); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
3987 emit_byte(0x81); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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parents:
624
diff
changeset
|
3988 emit_byte(0xF8 | encode); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3989 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
3990 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
3991 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
3992 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
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|
3993 InstructionMark im(this); |
660978a2a31a
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kvn
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624
diff
changeset
|
3994 prefix(src1); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
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624
diff
changeset
|
3995 emit_byte(0x81); |
660978a2a31a
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624
diff
changeset
|
3996 emit_operand(rax, src1, 4); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
changeset
|
3997 emit_data((int)imm32, rspec, narrow_oop_operand); |
660978a2a31a
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kvn
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624
diff
changeset
|
3998 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
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624
diff
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|
3999 |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4000 void Assembler::lzcntq(Register dst, Register src) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4001 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
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|
4002 emit_byte(0xF3); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4003 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4004 emit_byte(0x0F); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4005 emit_byte(0xBD); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4006 emit_byte(0xC0 | encode); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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710
diff
changeset
|
4007 } |
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twisti
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diff
changeset
|
4008 |
304 | 4009 void Assembler::movdq(XMMRegister dst, Register src) { |
4010 // table D-1 says MMX/SSE2 | |
4011 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
0 | 4012 emit_byte(0x66); |
304 | 4013 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
0 | 4014 emit_byte(0x0F); |
304 | 4015 emit_byte(0x6E); |
4016 emit_byte(0xC0 | encode); | |
4017 } | |
4018 | |
4019 void Assembler::movdq(Register dst, XMMRegister src) { | |
4020 // table D-1 says MMX/SSE2 | |
4021 NOT_LP64(assert(VM_Version::supports_sse2() || VM_Version::supports_mmx(), "")); | |
0 | 4022 emit_byte(0x66); |
304 | 4023 // swap src/dst to get correct prefix |
4024 int encode = prefixq_and_encode(src->encoding(), dst->encoding()); | |
0 | 4025 emit_byte(0x0F); |
4026 emit_byte(0x7E); | |
304 | 4027 emit_byte(0xC0 | encode); |
4028 } | |
4029 | |
4030 void Assembler::movq(Register dst, Register src) { | |
4031 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4032 emit_byte(0x8B); | |
4033 emit_byte(0xC0 | encode); | |
4034 } | |
4035 | |
4036 void Assembler::movq(Register dst, Address src) { | |
4037 InstructionMark im(this); | |
4038 prefixq(src, dst); | |
4039 emit_byte(0x8B); | |
4040 emit_operand(dst, src); | |
4041 } | |
4042 | |
4043 void Assembler::movq(Address dst, Register src) { | |
4044 InstructionMark im(this); | |
4045 prefixq(dst, src); | |
4046 emit_byte(0x89); | |
4047 emit_operand(src, dst); | |
4048 } | |
4049 | |
624 | 4050 void Assembler::movsbq(Register dst, Address src) { |
4051 InstructionMark im(this); | |
4052 prefixq(src, dst); | |
4053 emit_byte(0x0F); | |
4054 emit_byte(0xBE); | |
4055 emit_operand(dst, src); | |
4056 } | |
4057 | |
4058 void Assembler::movsbq(Register dst, Register src) { | |
4059 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4060 emit_byte(0x0F); | |
4061 emit_byte(0xBE); | |
4062 emit_byte(0xC0 | encode); | |
4063 } | |
4064 | |
304 | 4065 void Assembler::movslq(Register dst, int32_t imm32) { |
4066 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) | |
4067 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) | |
4068 // as a result we shouldn't use until tested at runtime... | |
4069 ShouldNotReachHere(); | |
4070 InstructionMark im(this); | |
4071 int encode = prefixq_and_encode(dst->encoding()); | |
4072 emit_byte(0xC7 | encode); | |
4073 emit_long(imm32); | |
4074 } | |
4075 | |
4076 void Assembler::movslq(Address dst, int32_t imm32) { | |
4077 assert(is_simm32(imm32), "lost bits"); | |
4078 InstructionMark im(this); | |
4079 prefixq(dst); | |
4080 emit_byte(0xC7); | |
4081 emit_operand(rax, dst, 4); | |
4082 emit_long(imm32); | |
4083 } | |
4084 | |
4085 void Assembler::movslq(Register dst, Address src) { | |
4086 InstructionMark im(this); | |
4087 prefixq(src, dst); | |
4088 emit_byte(0x63); | |
4089 emit_operand(dst, src); | |
4090 } | |
4091 | |
4092 void Assembler::movslq(Register dst, Register src) { | |
4093 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4094 emit_byte(0x63); | |
4095 emit_byte(0xC0 | encode); | |
4096 } | |
4097 | |
624 | 4098 void Assembler::movswq(Register dst, Address src) { |
4099 InstructionMark im(this); | |
4100 prefixq(src, dst); | |
4101 emit_byte(0x0F); | |
4102 emit_byte(0xBF); | |
4103 emit_operand(dst, src); | |
4104 } | |
4105 | |
4106 void Assembler::movswq(Register dst, Register src) { | |
4107 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4108 emit_byte(0x0F); | |
4109 emit_byte(0xBF); | |
4110 emit_byte(0xC0 | encode); | |
4111 } | |
4112 | |
4113 void Assembler::movzbq(Register dst, Address src) { | |
4114 InstructionMark im(this); | |
4115 prefixq(src, dst); | |
4116 emit_byte(0x0F); | |
4117 emit_byte(0xB6); | |
4118 emit_operand(dst, src); | |
4119 } | |
4120 | |
4121 void Assembler::movzbq(Register dst, Register src) { | |
4122 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4123 emit_byte(0x0F); | |
4124 emit_byte(0xB6); | |
4125 emit_byte(0xC0 | encode); | |
4126 } | |
4127 | |
4128 void Assembler::movzwq(Register dst, Address src) { | |
4129 InstructionMark im(this); | |
4130 prefixq(src, dst); | |
4131 emit_byte(0x0F); | |
4132 emit_byte(0xB7); | |
4133 emit_operand(dst, src); | |
4134 } | |
4135 | |
4136 void Assembler::movzwq(Register dst, Register src) { | |
4137 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4138 emit_byte(0x0F); | |
4139 emit_byte(0xB7); | |
4140 emit_byte(0xC0 | encode); | |
4141 } | |
4142 | |
304 | 4143 void Assembler::negq(Register dst) { |
4144 int encode = prefixq_and_encode(dst->encoding()); | |
4145 emit_byte(0xF7); | |
4146 emit_byte(0xD8 | encode); | |
4147 } | |
4148 | |
4149 void Assembler::notq(Register dst) { | |
4150 int encode = prefixq_and_encode(dst->encoding()); | |
4151 emit_byte(0xF7); | |
4152 emit_byte(0xD0 | encode); | |
4153 } | |
4154 | |
4155 void Assembler::orq(Address dst, int32_t imm32) { | |
4156 InstructionMark im(this); | |
4157 prefixq(dst); | |
4158 emit_byte(0x81); | |
4159 emit_operand(rcx, dst, 4); | |
4160 emit_long(imm32); | |
4161 } | |
4162 | |
4163 void Assembler::orq(Register dst, int32_t imm32) { | |
4164 (void) prefixq_and_encode(dst->encoding()); | |
4165 emit_arith(0x81, 0xC8, dst, imm32); | |
4166 } | |
4167 | |
4168 void Assembler::orq(Register dst, Address src) { | |
4169 InstructionMark im(this); | |
4170 prefixq(src, dst); | |
4171 emit_byte(0x0B); | |
4172 emit_operand(dst, src); | |
4173 } | |
4174 | |
4175 void Assembler::orq(Register dst, Register src) { | |
4176 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4177 emit_arith(0x0B, 0xC0, dst, src); | |
4178 } | |
4179 | |
4180 void Assembler::popa() { // 64bit | |
4181 movq(r15, Address(rsp, 0)); | |
4182 movq(r14, Address(rsp, wordSize)); | |
4183 movq(r13, Address(rsp, 2 * wordSize)); | |
4184 movq(r12, Address(rsp, 3 * wordSize)); | |
4185 movq(r11, Address(rsp, 4 * wordSize)); | |
4186 movq(r10, Address(rsp, 5 * wordSize)); | |
4187 movq(r9, Address(rsp, 6 * wordSize)); | |
4188 movq(r8, Address(rsp, 7 * wordSize)); | |
4189 movq(rdi, Address(rsp, 8 * wordSize)); | |
4190 movq(rsi, Address(rsp, 9 * wordSize)); | |
4191 movq(rbp, Address(rsp, 10 * wordSize)); | |
4192 // skip rsp | |
4193 movq(rbx, Address(rsp, 12 * wordSize)); | |
4194 movq(rdx, Address(rsp, 13 * wordSize)); | |
4195 movq(rcx, Address(rsp, 14 * wordSize)); | |
4196 movq(rax, Address(rsp, 15 * wordSize)); | |
4197 | |
4198 addq(rsp, 16 * wordSize); | |
4199 } | |
4200 | |
643
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4201 void Assembler::popcntq(Register dst, Address src) { |
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4202 assert(VM_Version::supports_popcnt(), "must support"); |
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4203 InstructionMark im(this); |
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4204 emit_byte(0xF3); |
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4205 prefixq(src, dst); |
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4206 emit_byte(0x0F); |
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4207 emit_byte(0xB8); |
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4208 emit_operand(dst, src); |
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4209 } |
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4210 |
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4211 void Assembler::popcntq(Register dst, Register src) { |
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4212 assert(VM_Version::supports_popcnt(), "must support"); |
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4213 emit_byte(0xF3); |
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4214 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); |
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4215 emit_byte(0x0F); |
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4216 emit_byte(0xB8); |
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4217 emit_byte(0xC0 | encode); |
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4218 } |
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4219 |
304 | 4220 void Assembler::popq(Address dst) { |
4221 InstructionMark im(this); | |
4222 prefixq(dst); | |
4223 emit_byte(0x8F); | |
4224 emit_operand(rax, dst); | |
4225 } | |
4226 | |
4227 void Assembler::pusha() { // 64bit | |
4228 // we have to store original rsp. ABI says that 128 bytes | |
4229 // below rsp are local scratch. | |
4230 movq(Address(rsp, -5 * wordSize), rsp); | |
4231 | |
4232 subq(rsp, 16 * wordSize); | |
4233 | |
4234 movq(Address(rsp, 15 * wordSize), rax); | |
4235 movq(Address(rsp, 14 * wordSize), rcx); | |
4236 movq(Address(rsp, 13 * wordSize), rdx); | |
4237 movq(Address(rsp, 12 * wordSize), rbx); | |
4238 // skip rsp | |
4239 movq(Address(rsp, 10 * wordSize), rbp); | |
4240 movq(Address(rsp, 9 * wordSize), rsi); | |
4241 movq(Address(rsp, 8 * wordSize), rdi); | |
4242 movq(Address(rsp, 7 * wordSize), r8); | |
4243 movq(Address(rsp, 6 * wordSize), r9); | |
4244 movq(Address(rsp, 5 * wordSize), r10); | |
4245 movq(Address(rsp, 4 * wordSize), r11); | |
4246 movq(Address(rsp, 3 * wordSize), r12); | |
4247 movq(Address(rsp, 2 * wordSize), r13); | |
4248 movq(Address(rsp, wordSize), r14); | |
4249 movq(Address(rsp, 0), r15); | |
4250 } | |
4251 | |
4252 void Assembler::pushq(Address src) { | |
4253 InstructionMark im(this); | |
4254 prefixq(src); | |
4255 emit_byte(0xFF); | |
4256 emit_operand(rsi, src); | |
4257 } | |
4258 | |
4259 void Assembler::rclq(Register dst, int imm8) { | |
4260 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
4261 int encode = prefixq_and_encode(dst->encoding()); | |
4262 if (imm8 == 1) { | |
4263 emit_byte(0xD1); | |
4264 emit_byte(0xD0 | encode); | |
4265 } else { | |
4266 emit_byte(0xC1); | |
4267 emit_byte(0xD0 | encode); | |
4268 emit_byte(imm8); | |
4269 } | |
4270 } | |
4271 void Assembler::sarq(Register dst, int imm8) { | |
4272 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
4273 int encode = prefixq_and_encode(dst->encoding()); | |
4274 if (imm8 == 1) { | |
4275 emit_byte(0xD1); | |
4276 emit_byte(0xF8 | encode); | |
4277 } else { | |
4278 emit_byte(0xC1); | |
4279 emit_byte(0xF8 | encode); | |
4280 emit_byte(imm8); | |
4281 } | |
4282 } | |
4283 | |
4284 void Assembler::sarq(Register dst) { | |
4285 int encode = prefixq_and_encode(dst->encoding()); | |
4286 emit_byte(0xD3); | |
4287 emit_byte(0xF8 | encode); | |
4288 } | |
4289 void Assembler::sbbq(Address dst, int32_t imm32) { | |
4290 InstructionMark im(this); | |
4291 prefixq(dst); | |
4292 emit_arith_operand(0x81, rbx, dst, imm32); | |
4293 } | |
4294 | |
4295 void Assembler::sbbq(Register dst, int32_t imm32) { | |
4296 (void) prefixq_and_encode(dst->encoding()); | |
4297 emit_arith(0x81, 0xD8, dst, imm32); | |
4298 } | |
4299 | |
4300 void Assembler::sbbq(Register dst, Address src) { | |
4301 InstructionMark im(this); | |
4302 prefixq(src, dst); | |
4303 emit_byte(0x1B); | |
4304 emit_operand(dst, src); | |
4305 } | |
4306 | |
4307 void Assembler::sbbq(Register dst, Register src) { | |
4308 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4309 emit_arith(0x1B, 0xC0, dst, src); | |
4310 } | |
4311 | |
4312 void Assembler::shlq(Register dst, int imm8) { | |
4313 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
4314 int encode = prefixq_and_encode(dst->encoding()); | |
4315 if (imm8 == 1) { | |
4316 emit_byte(0xD1); | |
4317 emit_byte(0xE0 | encode); | |
4318 } else { | |
4319 emit_byte(0xC1); | |
4320 emit_byte(0xE0 | encode); | |
4321 emit_byte(imm8); | |
4322 } | |
4323 } | |
4324 | |
4325 void Assembler::shlq(Register dst) { | |
4326 int encode = prefixq_and_encode(dst->encoding()); | |
4327 emit_byte(0xD3); | |
4328 emit_byte(0xE0 | encode); | |
4329 } | |
4330 | |
4331 void Assembler::shrq(Register dst, int imm8) { | |
4332 assert(isShiftCount(imm8 >> 1), "illegal shift count"); | |
4333 int encode = prefixq_and_encode(dst->encoding()); | |
4334 emit_byte(0xC1); | |
4335 emit_byte(0xE8 | encode); | |
4336 emit_byte(imm8); | |
4337 } | |
4338 | |
4339 void Assembler::shrq(Register dst) { | |
4340 int encode = prefixq_and_encode(dst->encoding()); | |
4341 emit_byte(0xD3); | |
4342 emit_byte(0xE8 | encode); | |
4343 } | |
4344 | |
4345 void Assembler::sqrtsd(XMMRegister dst, Address src) { | |
4346 NOT_LP64(assert(VM_Version::supports_sse2(), "")); | |
0 | 4347 InstructionMark im(this); |
4348 emit_byte(0xF2); | |
304 | 4349 prefix(src, dst); |
0 | 4350 emit_byte(0x0F); |
304 | 4351 emit_byte(0x51); |
4352 emit_operand(dst, src); | |
4353 } | |
4354 | |
4355 void Assembler::subq(Address dst, int32_t imm32) { | |
4356 InstructionMark im(this); | |
4357 prefixq(dst); | |
4358 if (is8bit(imm32)) { | |
4359 emit_byte(0x83); | |
4360 emit_operand(rbp, dst, 1); | |
4361 emit_byte(imm32 & 0xFF); | |
4362 } else { | |
4363 emit_byte(0x81); | |
4364 emit_operand(rbp, dst, 4); | |
4365 emit_long(imm32); | |
4366 } | |
4367 } | |
4368 | |
4369 void Assembler::subq(Register dst, int32_t imm32) { | |
4370 (void) prefixq_and_encode(dst->encoding()); | |
4371 emit_arith(0x81, 0xE8, dst, imm32); | |
4372 } | |
4373 | |
4374 void Assembler::subq(Address dst, Register src) { | |
4375 InstructionMark im(this); | |
4376 prefixq(dst, src); | |
4377 emit_byte(0x29); | |
4378 emit_operand(src, dst); | |
4379 } | |
4380 | |
4381 void Assembler::subq(Register dst, Address src) { | |
4382 InstructionMark im(this); | |
4383 prefixq(src, dst); | |
4384 emit_byte(0x2B); | |
4385 emit_operand(dst, src); | |
4386 } | |
4387 | |
4388 void Assembler::subq(Register dst, Register src) { | |
4389 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4390 emit_arith(0x2B, 0xC0, dst, src); | |
4391 } | |
4392 | |
4393 void Assembler::testq(Register dst, int32_t imm32) { | |
4394 // not using emit_arith because test | |
4395 // doesn't support sign-extension of | |
4396 // 8bit operands | |
4397 int encode = dst->encoding(); | |
4398 if (encode == 0) { | |
4399 prefix(REX_W); | |
4400 emit_byte(0xA9); | |
4401 } else { | |
4402 encode = prefixq_and_encode(encode); | |
4403 emit_byte(0xF7); | |
4404 emit_byte(0xC0 | encode); | |
4405 } | |
4406 emit_long(imm32); | |
4407 } | |
4408 | |
4409 void Assembler::testq(Register dst, Register src) { | |
4410 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4411 emit_arith(0x85, 0xC0, dst, src); | |
4412 } | |
4413 | |
4414 void Assembler::xaddq(Address dst, Register src) { | |
4415 InstructionMark im(this); | |
4416 prefixq(dst, src); | |
71 | 4417 emit_byte(0x0F); |
304 | 4418 emit_byte(0xC1); |
4419 emit_operand(src, dst); | |
4420 } | |
4421 | |
4422 void Assembler::xchgq(Register dst, Address src) { | |
4423 InstructionMark im(this); | |
4424 prefixq(src, dst); | |
4425 emit_byte(0x87); | |
4426 emit_operand(dst, src); | |
4427 } | |
4428 | |
4429 void Assembler::xchgq(Register dst, Register src) { | |
4430 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); | |
4431 emit_byte(0x87); | |
4432 emit_byte(0xc0 | encode); | |
4433 } | |
4434 | |
4435 void Assembler::xorq(Register dst, Register src) { | |
4436 (void) prefixq_and_encode(dst->encoding(), src->encoding()); | |
4437 emit_arith(0x33, 0xC0, dst, src); | |
4438 } | |
4439 | |
4440 void Assembler::xorq(Register dst, Address src) { | |
4441 InstructionMark im(this); | |
4442 prefixq(src, dst); | |
4443 emit_byte(0x33); | |
4444 emit_operand(dst, src); | |
4445 } | |
4446 | |
4447 #endif // !LP64 | |
4448 | |
4449 static Assembler::Condition reverse[] = { | |
4450 Assembler::noOverflow /* overflow = 0x0 */ , | |
4451 Assembler::overflow /* noOverflow = 0x1 */ , | |
4452 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , | |
4453 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , | |
4454 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , | |
4455 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , | |
4456 Assembler::above /* belowEqual = 0x6 */ , | |
4457 Assembler::belowEqual /* above = 0x7 */ , | |
4458 Assembler::positive /* negative = 0x8 */ , | |
4459 Assembler::negative /* positive = 0x9 */ , | |
4460 Assembler::noParity /* parity = 0xa */ , | |
4461 Assembler::parity /* noParity = 0xb */ , | |
4462 Assembler::greaterEqual /* less = 0xc */ , | |
4463 Assembler::less /* greaterEqual = 0xd */ , | |
4464 Assembler::greater /* lessEqual = 0xe */ , | |
4465 Assembler::lessEqual /* greater = 0xf, */ | |
4466 | |
4467 }; | |
4468 | |
0 | 4469 |
4470 // Implementation of MacroAssembler | |
4471 | |
304 | 4472 // First all the versions that have distinct versions depending on 32/64 bit |
4473 // Unless the difference is trivial (1 line or so). | |
4474 | |
4475 #ifndef _LP64 | |
4476 | |
4477 // 32bit versions | |
4478 | |
0 | 4479 Address MacroAssembler::as_Address(AddressLiteral adr) { |
4480 return Address(adr.target(), adr.rspec()); | |
4481 } | |
4482 | |
4483 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
4484 return Address::make_array(adr); | |
4485 } | |
4486 | |
304 | 4487 int MacroAssembler::biased_locking_enter(Register lock_reg, |
4488 Register obj_reg, | |
4489 Register swap_reg, | |
4490 Register tmp_reg, | |
4491 bool swap_reg_contains_mark, | |
4492 Label& done, | |
4493 Label* slow_case, | |
4494 BiasedLockingCounters* counters) { | |
4495 assert(UseBiasedLocking, "why call this otherwise?"); | |
4496 assert(swap_reg == rax, "swap_reg must be rax, for cmpxchg"); | |
4497 assert_different_registers(lock_reg, obj_reg, swap_reg); | |
4498 | |
4499 if (PrintBiasedLockingStatistics && counters == NULL) | |
4500 counters = BiasedLocking::counters(); | |
4501 | |
4502 bool need_tmp_reg = false; | |
4503 if (tmp_reg == noreg) { | |
4504 need_tmp_reg = true; | |
4505 tmp_reg = lock_reg; | |
4506 } else { | |
4507 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
4508 } | |
4509 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
4510 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
4511 Address klass_addr (obj_reg, oopDesc::klass_offset_in_bytes()); | |
4512 Address saved_mark_addr(lock_reg, 0); | |
4513 | |
4514 // Biased locking | |
4515 // See whether the lock is currently biased toward our thread and | |
4516 // whether the epoch is still valid | |
4517 // Note that the runtime guarantees sufficient alignment of JavaThread | |
4518 // pointers to allow age to be placed into low bits | |
4519 // First check to see whether biasing is even enabled for this object | |
4520 Label cas_label; | |
4521 int null_check_offset = -1; | |
4522 if (!swap_reg_contains_mark) { | |
4523 null_check_offset = offset(); | |
4524 movl(swap_reg, mark_addr); | |
4525 } | |
4526 if (need_tmp_reg) { | |
4527 push(tmp_reg); | |
4528 } | |
4529 movl(tmp_reg, swap_reg); | |
4530 andl(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
4531 cmpl(tmp_reg, markOopDesc::biased_lock_pattern); | |
4532 if (need_tmp_reg) { | |
4533 pop(tmp_reg); | |
4534 } | |
4535 jcc(Assembler::notEqual, cas_label); | |
4536 // The bias pattern is present in the object's header. Need to check | |
4537 // whether the bias owner and the epoch are both still current. | |
4538 // Note that because there is no current thread register on x86 we | |
4539 // need to store off the mark word we read out of the object to | |
4540 // avoid reloading it and needing to recheck invariants below. This | |
4541 // store is unfortunate but it makes the overall code shorter and | |
4542 // simpler. | |
4543 movl(saved_mark_addr, swap_reg); | |
4544 if (need_tmp_reg) { | |
4545 push(tmp_reg); | |
4546 } | |
4547 get_thread(tmp_reg); | |
4548 xorl(swap_reg, tmp_reg); | |
4549 if (swap_reg_contains_mark) { | |
4550 null_check_offset = offset(); | |
4551 } | |
4552 movl(tmp_reg, klass_addr); | |
4553 xorl(swap_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
4554 andl(swap_reg, ~((int) markOopDesc::age_mask_in_place)); | |
4555 if (need_tmp_reg) { | |
4556 pop(tmp_reg); | |
4557 } | |
4558 if (counters != NULL) { | |
4559 cond_inc32(Assembler::zero, | |
4560 ExternalAddress((address)counters->biased_lock_entry_count_addr())); | |
4561 } | |
4562 jcc(Assembler::equal, done); | |
4563 | |
4564 Label try_revoke_bias; | |
4565 Label try_rebias; | |
4566 | |
4567 // At this point we know that the header has the bias pattern and | |
4568 // that we are not the bias owner in the current epoch. We need to | |
4569 // figure out more details about the state of the header in order to | |
4570 // know what operations can be legally performed on the object's | |
4571 // header. | |
4572 | |
4573 // If the low three bits in the xor result aren't clear, that means | |
4574 // the prototype header is no longer biased and we have to revoke | |
4575 // the bias on this object. | |
4576 testl(swap_reg, markOopDesc::biased_lock_mask_in_place); | |
4577 jcc(Assembler::notZero, try_revoke_bias); | |
4578 | |
4579 // Biasing is still enabled for this data type. See whether the | |
4580 // epoch of the current bias is still valid, meaning that the epoch | |
4581 // bits of the mark word are equal to the epoch bits of the | |
4582 // prototype header. (Note that the prototype header's epoch bits | |
4583 // only change at a safepoint.) If not, attempt to rebias the object | |
4584 // toward the current thread. Note that we must be absolutely sure | |
4585 // that the current epoch is invalid in order to do this because | |
4586 // otherwise the manipulations it performs on the mark word are | |
4587 // illegal. | |
4588 testl(swap_reg, markOopDesc::epoch_mask_in_place); | |
4589 jcc(Assembler::notZero, try_rebias); | |
4590 | |
4591 // The epoch of the current bias is still valid but we know nothing | |
4592 // about the owner; it might be set or it might be clear. Try to | |
4593 // acquire the bias of the object using an atomic operation. If this | |
4594 // fails we will go in to the runtime to revoke the object's bias. | |
4595 // Note that we first construct the presumed unbiased header so we | |
4596 // don't accidentally blow away another thread's valid bias. | |
4597 movl(swap_reg, saved_mark_addr); | |
4598 andl(swap_reg, | |
4599 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
4600 if (need_tmp_reg) { | |
4601 push(tmp_reg); | |
4602 } | |
4603 get_thread(tmp_reg); | |
4604 orl(tmp_reg, swap_reg); | |
4605 if (os::is_MP()) { | |
4606 lock(); | |
4607 } | |
4608 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
4609 if (need_tmp_reg) { | |
4610 pop(tmp_reg); | |
4611 } | |
4612 // If the biasing toward our thread failed, this means that | |
4613 // another thread succeeded in biasing it toward itself and we | |
4614 // need to revoke that bias. The revocation will occur in the | |
4615 // interpreter runtime in the slow case. | |
4616 if (counters != NULL) { | |
4617 cond_inc32(Assembler::zero, | |
4618 ExternalAddress((address)counters->anonymously_biased_lock_entry_count_addr())); | |
4619 } | |
4620 if (slow_case != NULL) { | |
4621 jcc(Assembler::notZero, *slow_case); | |
4622 } | |
4623 jmp(done); | |
4624 | |
4625 bind(try_rebias); | |
4626 // At this point we know the epoch has expired, meaning that the | |
4627 // current "bias owner", if any, is actually invalid. Under these | |
4628 // circumstances _only_, we are allowed to use the current header's | |
4629 // value as the comparison value when doing the cas to acquire the | |
4630 // bias in the current epoch. In other words, we allow transfer of | |
4631 // the bias from one thread to another directly in this situation. | |
4632 // | |
4633 // FIXME: due to a lack of registers we currently blow away the age | |
4634 // bits in this situation. Should attempt to preserve them. | |
4635 if (need_tmp_reg) { | |
4636 push(tmp_reg); | |
4637 } | |
4638 get_thread(tmp_reg); | |
4639 movl(swap_reg, klass_addr); | |
4640 orl(tmp_reg, Address(swap_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
4641 movl(swap_reg, saved_mark_addr); | |
4642 if (os::is_MP()) { | |
4643 lock(); | |
4644 } | |
4645 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
4646 if (need_tmp_reg) { | |
4647 pop(tmp_reg); | |
4648 } | |
4649 // If the biasing toward our thread failed, then another thread | |
4650 // succeeded in biasing it toward itself and we need to revoke that | |
4651 // bias. The revocation will occur in the runtime in the slow case. | |
4652 if (counters != NULL) { | |
4653 cond_inc32(Assembler::zero, | |
4654 ExternalAddress((address)counters->rebiased_lock_entry_count_addr())); | |
4655 } | |
4656 if (slow_case != NULL) { | |
4657 jcc(Assembler::notZero, *slow_case); | |
4658 } | |
4659 jmp(done); | |
4660 | |
4661 bind(try_revoke_bias); | |
4662 // The prototype mark in the klass doesn't have the bias bit set any | |
4663 // more, indicating that objects of this data type are not supposed | |
4664 // to be biased any more. We are going to try to reset the mark of | |
4665 // this object to the prototype value and fall through to the | |
4666 // CAS-based locking scheme. Note that if our CAS fails, it means | |
4667 // that another thread raced us for the privilege of revoking the | |
4668 // bias of this particular object, so it's okay to continue in the | |
4669 // normal locking code. | |
4670 // | |
4671 // FIXME: due to a lack of registers we currently blow away the age | |
4672 // bits in this situation. Should attempt to preserve them. | |
4673 movl(swap_reg, saved_mark_addr); | |
4674 if (need_tmp_reg) { | |
4675 push(tmp_reg); | |
4676 } | |
4677 movl(tmp_reg, klass_addr); | |
4678 movl(tmp_reg, Address(tmp_reg, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); | |
4679 if (os::is_MP()) { | |
4680 lock(); | |
4681 } | |
4682 cmpxchgptr(tmp_reg, Address(obj_reg, 0)); | |
4683 if (need_tmp_reg) { | |
4684 pop(tmp_reg); | |
4685 } | |
4686 // Fall through to the normal CAS-based lock, because no matter what | |
4687 // the result of the above CAS, some thread must have succeeded in | |
4688 // removing the bias bit from the object's header. | |
4689 if (counters != NULL) { | |
4690 cond_inc32(Assembler::zero, | |
4691 ExternalAddress((address)counters->revoked_lock_entry_count_addr())); | |
4692 } | |
4693 | |
4694 bind(cas_label); | |
4695 | |
4696 return null_check_offset; | |
4697 } | |
4698 void MacroAssembler::call_VM_leaf_base(address entry_point, | |
4699 int number_of_arguments) { | |
4700 call(RuntimeAddress(entry_point)); | |
4701 increment(rsp, number_of_arguments * wordSize); | |
4702 } | |
4703 | |
4704 void MacroAssembler::cmpoop(Address src1, jobject obj) { | |
4705 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4706 } | |
4707 | |
4708 void MacroAssembler::cmpoop(Register src1, jobject obj) { | |
4709 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4710 } | |
4711 | |
4712 void MacroAssembler::extend_sign(Register hi, Register lo) { | |
4713 // According to Intel Doc. AP-526, "Integer Divide", p.18. | |
4714 if (VM_Version::is_P6() && hi == rdx && lo == rax) { | |
4715 cdql(); | |
4716 } else { | |
4717 movl(hi, lo); | |
4718 sarl(hi, 31); | |
4719 } | |
4720 } | |
4721 | |
0 | 4722 void MacroAssembler::fat_nop() { |
4723 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
4724 emit_byte(0x26); // es: | |
4725 emit_byte(0x2e); // cs: | |
4726 emit_byte(0x64); // fs: | |
4727 emit_byte(0x65); // gs: | |
4728 emit_byte(0x90); | |
4729 } | |
4730 | |
304 | 4731 void MacroAssembler::jC2(Register tmp, Label& L) { |
4732 // set parity bit if FPU flag C2 is set (via rax) | |
4733 save_rax(tmp); | |
4734 fwait(); fnstsw_ax(); | |
4735 sahf(); | |
4736 restore_rax(tmp); | |
4737 // branch | |
4738 jcc(Assembler::parity, L); | |
4739 } | |
4740 | |
4741 void MacroAssembler::jnC2(Register tmp, Label& L) { | |
4742 // set parity bit if FPU flag C2 is set (via rax) | |
4743 save_rax(tmp); | |
4744 fwait(); fnstsw_ax(); | |
4745 sahf(); | |
4746 restore_rax(tmp); | |
4747 // branch | |
4748 jcc(Assembler::noParity, L); | |
4749 } | |
4750 | |
0 | 4751 // 32bit can do a case table jump in one instruction but we no longer allow the base |
4752 // to be installed in the Address class | |
4753 void MacroAssembler::jump(ArrayAddress entry) { | |
4754 jmp(as_Address(entry)); | |
4755 } | |
4756 | |
304 | 4757 // Note: y_lo will be destroyed |
4758 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
4759 // Long compare for Java (semantics as described in JVM spec.) | |
4760 Label high, low, done; | |
4761 | |
4762 cmpl(x_hi, y_hi); | |
4763 jcc(Assembler::less, low); | |
4764 jcc(Assembler::greater, high); | |
4765 // x_hi is the return register | |
4766 xorl(x_hi, x_hi); | |
4767 cmpl(x_lo, y_lo); | |
4768 jcc(Assembler::below, low); | |
4769 jcc(Assembler::equal, done); | |
4770 | |
4771 bind(high); | |
4772 xorl(x_hi, x_hi); | |
4773 increment(x_hi); | |
4774 jmp(done); | |
4775 | |
4776 bind(low); | |
4777 xorl(x_hi, x_hi); | |
4778 decrementl(x_hi); | |
4779 | |
4780 bind(done); | |
4781 } | |
4782 | |
4783 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
4784 mov_literal32(dst, (int32_t)src.target(), src.rspec()); | |
0 | 4785 } |
4786 | |
4787 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
4788 // leal(dst, as_Address(adr)); | |
304 | 4789 // see note in movl as to why we must use a move |
0 | 4790 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); |
4791 } | |
4792 | |
4793 void MacroAssembler::leave() { | |
304 | 4794 mov(rsp, rbp); |
4795 pop(rbp); | |
4796 } | |
0 | 4797 |
4798 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { | |
4799 // Multiplication of two Java long values stored on the stack | |
4800 // as illustrated below. Result is in rdx:rax. | |
4801 // | |
4802 // rsp ---> [ ?? ] \ \ | |
4803 // .... | y_rsp_offset | | |
4804 // [ y_lo ] / (in bytes) | x_rsp_offset | |
4805 // [ y_hi ] | (in bytes) | |
4806 // .... | | |
4807 // [ x_lo ] / | |
4808 // [ x_hi ] | |
4809 // .... | |
4810 // | |
4811 // Basic idea: lo(result) = lo(x_lo * y_lo) | |
4812 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) | |
4813 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); | |
4814 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); | |
4815 Label quick; | |
4816 // load x_hi, y_hi and check if quick | |
4817 // multiplication is possible | |
4818 movl(rbx, x_hi); | |
4819 movl(rcx, y_hi); | |
4820 movl(rax, rbx); | |
4821 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 | |
4822 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply | |
4823 // do full multiplication | |
4824 // 1st step | |
4825 mull(y_lo); // x_hi * y_lo | |
4826 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, | |
4827 // 2nd step | |
4828 movl(rax, x_lo); | |
4829 mull(rcx); // x_lo * y_hi | |
4830 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, | |
4831 // 3rd step | |
4832 bind(quick); // note: rbx, = 0 if quick multiply! | |
4833 movl(rax, x_lo); | |
4834 mull(y_lo); // x_lo * y_lo | |
4835 addl(rdx, rbx); // correct hi(x_lo * y_lo) | |
4836 } | |
4837 | |
304 | 4838 void MacroAssembler::lneg(Register hi, Register lo) { |
4839 negl(lo); | |
4840 adcl(hi, 0); | |
4841 negl(hi); | |
4842 } | |
0 | 4843 |
4844 void MacroAssembler::lshl(Register hi, Register lo) { | |
4845 // Java shift left long support (semantics as described in JVM spec., p.305) | |
4846 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) | |
4847 // shift value is in rcx ! | |
4848 assert(hi != rcx, "must not use rcx"); | |
4849 assert(lo != rcx, "must not use rcx"); | |
4850 const Register s = rcx; // shift count | |
4851 const int n = BitsPerWord; | |
4852 Label L; | |
4853 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
4854 cmpl(s, n); // if (s < n) | |
4855 jcc(Assembler::less, L); // else (s >= n) | |
4856 movl(hi, lo); // x := x << n | |
4857 xorl(lo, lo); | |
4858 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
4859 bind(L); // s (mod n) < n | |
4860 shldl(hi, lo); // x := x << s | |
4861 shll(lo); | |
4862 } | |
4863 | |
4864 | |
4865 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { | |
4866 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) | |
4867 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) | |
4868 assert(hi != rcx, "must not use rcx"); | |
4869 assert(lo != rcx, "must not use rcx"); | |
4870 const Register s = rcx; // shift count | |
4871 const int n = BitsPerWord; | |
4872 Label L; | |
4873 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) | |
4874 cmpl(s, n); // if (s < n) | |
4875 jcc(Assembler::less, L); // else (s >= n) | |
4876 movl(lo, hi); // x := x >> n | |
4877 if (sign_extension) sarl(hi, 31); | |
4878 else xorl(hi, hi); | |
4879 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! | |
4880 bind(L); // s (mod n) < n | |
4881 shrdl(lo, hi); // x := x >> s | |
4882 if (sign_extension) sarl(hi); | |
4883 else shrl(hi); | |
4884 } | |
4885 | |
304 | 4886 void MacroAssembler::movoop(Register dst, jobject obj) { |
4887 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4888 } | |
4889 | |
4890 void MacroAssembler::movoop(Address dst, jobject obj) { | |
4891 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4892 } | |
4893 | |
4894 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
4895 if (src.is_lval()) { | |
4896 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); | |
4897 } else { | |
4898 movl(dst, as_Address(src)); | |
4899 } | |
4900 } | |
4901 | |
4902 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
4903 movl(as_Address(dst), src); | |
4904 } | |
4905 | |
4906 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
4907 movl(dst, as_Address(src)); | |
4908 } | |
4909 | |
4910 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
4911 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
4912 movl(dst, src); | |
4913 } | |
4914 | |
4915 | |
4916 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { | |
4917 movsd(dst, as_Address(src)); | |
4918 } | |
4919 | |
4920 void MacroAssembler::pop_callee_saved_registers() { | |
4921 pop(rcx); | |
4922 pop(rdx); | |
4923 pop(rdi); | |
4924 pop(rsi); | |
4925 } | |
4926 | |
4927 void MacroAssembler::pop_fTOS() { | |
4928 fld_d(Address(rsp, 0)); | |
4929 addl(rsp, 2 * wordSize); | |
4930 } | |
4931 | |
4932 void MacroAssembler::push_callee_saved_registers() { | |
4933 push(rsi); | |
4934 push(rdi); | |
4935 push(rdx); | |
4936 push(rcx); | |
4937 } | |
4938 | |
4939 void MacroAssembler::push_fTOS() { | |
4940 subl(rsp, 2 * wordSize); | |
4941 fstp_d(Address(rsp, 0)); | |
4942 } | |
4943 | |
4944 | |
4945 void MacroAssembler::pushoop(jobject obj) { | |
4946 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); | |
4947 } | |
4948 | |
4949 | |
4950 void MacroAssembler::pushptr(AddressLiteral src) { | |
4951 if (src.is_lval()) { | |
4952 push_literal32((int32_t)src.target(), src.rspec()); | |
4953 } else { | |
4954 pushl(as_Address(src)); | |
4955 } | |
4956 } | |
4957 | |
4958 void MacroAssembler::set_word_if_not_zero(Register dst) { | |
4959 xorl(dst, dst); | |
4960 set_byte_if_not_zero(dst); | |
4961 } | |
4962 | |
4963 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
4964 masm->push(arg); | |
4965 } | |
4966 | |
4967 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
4968 masm->push(arg); | |
4969 } | |
4970 | |
4971 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
4972 masm->push(arg); | |
4973 } | |
4974 | |
4975 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
4976 masm->push(arg); | |
4977 } | |
4978 | |
4979 #ifndef PRODUCT | |
4980 extern "C" void findpc(intptr_t x); | |
4981 #endif | |
4982 | |
4983 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { | |
4984 // In order to get locks to work, we need to fake a in_VM state | |
4985 JavaThread* thread = JavaThread::current(); | |
4986 JavaThreadState saved_state = thread->thread_state(); | |
4987 thread->set_thread_state(_thread_in_vm); | |
4988 if (ShowMessageBoxOnError) { | |
4989 JavaThread* thread = JavaThread::current(); | |
4990 JavaThreadState saved_state = thread->thread_state(); | |
4991 thread->set_thread_state(_thread_in_vm); | |
4992 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
4993 ttyLocker ttyl; | |
4994 BytecodeCounter::print(); | |
4995 } | |
4996 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
4997 // This is the value of eip which points to where verify_oop will return. | |
4998 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
4999 ttyLocker ttyl; | |
5000 tty->print_cr("eip = 0x%08x", eip); | |
5001 #ifndef PRODUCT | |
1793
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|
5002 if ((WizardMode || Verbose) && PrintMiscellaneous) { |
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diff
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|
5003 tty->cr(); |
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diff
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|
5004 findpc(eip); |
d257356e35f0
6939224: MethodHandle.invokeGeneric needs to perform the correct set of conversions
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diff
changeset
|
5005 tty->cr(); |
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diff
changeset
|
5006 } |
304 | 5007 #endif |
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|
5008 tty->print_cr("rax = 0x%08x", rax); |
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diff
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|
5009 tty->print_cr("rbx = 0x%08x", rbx); |
304 | 5010 tty->print_cr("rcx = 0x%08x", rcx); |
5011 tty->print_cr("rdx = 0x%08x", rdx); | |
5012 tty->print_cr("rdi = 0x%08x", rdi); | |
5013 tty->print_cr("rsi = 0x%08x", rsi); | |
1793
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diff
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|
5014 tty->print_cr("rbp = 0x%08x", rbp); |
304 | 5015 tty->print_cr("rsp = 0x%08x", rsp); |
5016 BREAKPOINT; | |
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diff
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|
5017 assert(false, "start up GDB"); |
304 | 5018 } |
5019 } else { | |
5020 ttyLocker ttyl; | |
5021 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
5022 assert(false, "DEBUG MESSAGE"); | |
5023 } | |
5024 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); | |
5025 } | |
5026 | |
5027 void MacroAssembler::stop(const char* msg) { | |
5028 ExternalAddress message((address)msg); | |
5029 // push address of message | |
5030 pushptr(message.addr()); | |
5031 { Label L; call(L, relocInfo::none); bind(L); } // push eip | |
5032 pusha(); // push registers | |
5033 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); | |
5034 hlt(); | |
5035 } | |
5036 | |
5037 void MacroAssembler::warn(const char* msg) { | |
5038 push_CPU_state(); | |
5039 | |
5040 ExternalAddress message((address) msg); | |
5041 // push address of message | |
5042 pushptr(message.addr()); | |
5043 | |
5044 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); | |
5045 addl(rsp, wordSize); // discard argument | |
5046 pop_CPU_state(); | |
5047 } | |
5048 | |
5049 #else // _LP64 | |
5050 | |
5051 // 64 bit versions | |
5052 | |
5053 Address MacroAssembler::as_Address(AddressLiteral adr) { | |
5054 // amd64 always does this as a pc-rel | |
5055 // we can be absolute or disp based on the instruction type | |
5056 // jmp/call are displacements others are absolute | |
5057 assert(!adr.is_lval(), "must be rval"); | |
5058 assert(reachable(adr), "must be"); | |
5059 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); | |
5060 | |
5061 } | |
5062 | |
5063 Address MacroAssembler::as_Address(ArrayAddress adr) { | |
5064 AddressLiteral base = adr.base(); | |
5065 lea(rscratch1, base); | |
5066 Address index = adr.index(); | |
5067 assert(index._disp == 0, "must not have disp"); // maybe it can? | |
5068 Address array(rscratch1, index._index, index._scale, index._disp); | |
5069 return array; | |
5070 } | |
5071 | |
5072 int MacroAssembler::biased_locking_enter(Register lock_reg, | |
5073 Register obj_reg, | |
5074 Register swap_reg, | |
5075 Register tmp_reg, | |
5076 bool swap_reg_contains_mark, | |
5077 Label& done, | |
5078 Label* slow_case, | |
5079 BiasedLockingCounters* counters) { | |
5080 assert(UseBiasedLocking, "why call this otherwise?"); | |
5081 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); | |
5082 assert(tmp_reg != noreg, "tmp_reg must be supplied"); | |
5083 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); | |
5084 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
5085 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); | |
5086 Address saved_mark_addr(lock_reg, 0); | |
5087 | |
5088 if (PrintBiasedLockingStatistics && counters == NULL) | |
5089 counters = BiasedLocking::counters(); | |
5090 | |
5091 // Biased locking | |
5092 // See whether the lock is currently biased toward our thread and | |
5093 // whether the epoch is still valid | |
5094 // Note that the runtime guarantees sufficient alignment of JavaThread | |
5095 // pointers to allow age to be placed into low bits | |
5096 // First check to see whether biasing is even enabled for this object | |
5097 Label cas_label; | |
5098 int null_check_offset = -1; | |
5099 if (!swap_reg_contains_mark) { | |
5100 null_check_offset = offset(); | |
5101 movq(swap_reg, mark_addr); | |
5102 } | |
5103 movq(tmp_reg, swap_reg); | |
5104 andq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
5105 cmpq(tmp_reg, markOopDesc::biased_lock_pattern); | |
5106 jcc(Assembler::notEqual, cas_label); | |
5107 // The bias pattern is present in the object's header. Need to check | |
5108 // whether the bias owner and the epoch are both still current. | |
5109 load_prototype_header(tmp_reg, obj_reg); | |
5110 orq(tmp_reg, r15_thread); | |
5111 xorq(tmp_reg, swap_reg); | |
5112 andq(tmp_reg, ~((int) markOopDesc::age_mask_in_place)); | |
5113 if (counters != NULL) { | |
5114 cond_inc32(Assembler::zero, | |
5115 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
5116 } | |
0 | 5117 jcc(Assembler::equal, done); |
5118 | |
304 | 5119 Label try_revoke_bias; |
5120 Label try_rebias; | |
5121 | |
5122 // At this point we know that the header has the bias pattern and | |
5123 // that we are not the bias owner in the current epoch. We need to | |
5124 // figure out more details about the state of the header in order to | |
5125 // know what operations can be legally performed on the object's | |
5126 // header. | |
5127 | |
5128 // If the low three bits in the xor result aren't clear, that means | |
5129 // the prototype header is no longer biased and we have to revoke | |
5130 // the bias on this object. | |
5131 testq(tmp_reg, markOopDesc::biased_lock_mask_in_place); | |
5132 jcc(Assembler::notZero, try_revoke_bias); | |
5133 | |
5134 // Biasing is still enabled for this data type. See whether the | |
5135 // epoch of the current bias is still valid, meaning that the epoch | |
5136 // bits of the mark word are equal to the epoch bits of the | |
5137 // prototype header. (Note that the prototype header's epoch bits | |
5138 // only change at a safepoint.) If not, attempt to rebias the object | |
5139 // toward the current thread. Note that we must be absolutely sure | |
5140 // that the current epoch is invalid in order to do this because | |
5141 // otherwise the manipulations it performs on the mark word are | |
5142 // illegal. | |
5143 testq(tmp_reg, markOopDesc::epoch_mask_in_place); | |
5144 jcc(Assembler::notZero, try_rebias); | |
5145 | |
5146 // The epoch of the current bias is still valid but we know nothing | |
5147 // about the owner; it might be set or it might be clear. Try to | |
5148 // acquire the bias of the object using an atomic operation. If this | |
5149 // fails we will go in to the runtime to revoke the object's bias. | |
5150 // Note that we first construct the presumed unbiased header so we | |
5151 // don't accidentally blow away another thread's valid bias. | |
5152 andq(swap_reg, | |
5153 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); | |
5154 movq(tmp_reg, swap_reg); | |
5155 orq(tmp_reg, r15_thread); | |
5156 if (os::is_MP()) { | |
5157 lock(); | |
5158 } | |
5159 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
5160 // If the biasing toward our thread failed, this means that | |
5161 // another thread succeeded in biasing it toward itself and we | |
5162 // need to revoke that bias. The revocation will occur in the | |
5163 // interpreter runtime in the slow case. | |
5164 if (counters != NULL) { | |
5165 cond_inc32(Assembler::zero, | |
5166 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); | |
5167 } | |
5168 if (slow_case != NULL) { | |
5169 jcc(Assembler::notZero, *slow_case); | |
5170 } | |
0 | 5171 jmp(done); |
5172 | |
304 | 5173 bind(try_rebias); |
5174 // At this point we know the epoch has expired, meaning that the | |
5175 // current "bias owner", if any, is actually invalid. Under these | |
5176 // circumstances _only_, we are allowed to use the current header's | |
5177 // value as the comparison value when doing the cas to acquire the | |
5178 // bias in the current epoch. In other words, we allow transfer of | |
5179 // the bias from one thread to another directly in this situation. | |
5180 // | |
5181 // FIXME: due to a lack of registers we currently blow away the age | |
5182 // bits in this situation. Should attempt to preserve them. | |
5183 load_prototype_header(tmp_reg, obj_reg); | |
5184 orq(tmp_reg, r15_thread); | |
5185 if (os::is_MP()) { | |
5186 lock(); | |
5187 } | |
5188 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
5189 // If the biasing toward our thread failed, then another thread | |
5190 // succeeded in biasing it toward itself and we need to revoke that | |
5191 // bias. The revocation will occur in the runtime in the slow case. | |
5192 if (counters != NULL) { | |
5193 cond_inc32(Assembler::zero, | |
5194 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); | |
5195 } | |
5196 if (slow_case != NULL) { | |
5197 jcc(Assembler::notZero, *slow_case); | |
0 | 5198 } |
5199 jmp(done); | |
5200 | |
304 | 5201 bind(try_revoke_bias); |
5202 // The prototype mark in the klass doesn't have the bias bit set any | |
5203 // more, indicating that objects of this data type are not supposed | |
5204 // to be biased any more. We are going to try to reset the mark of | |
5205 // this object to the prototype value and fall through to the | |
5206 // CAS-based locking scheme. Note that if our CAS fails, it means | |
5207 // that another thread raced us for the privilege of revoking the | |
5208 // bias of this particular object, so it's okay to continue in the | |
5209 // normal locking code. | |
5210 // | |
5211 // FIXME: due to a lack of registers we currently blow away the age | |
5212 // bits in this situation. Should attempt to preserve them. | |
5213 load_prototype_header(tmp_reg, obj_reg); | |
5214 if (os::is_MP()) { | |
5215 lock(); | |
5216 } | |
5217 cmpxchgq(tmp_reg, Address(obj_reg, 0)); | |
5218 // Fall through to the normal CAS-based lock, because no matter what | |
5219 // the result of the above CAS, some thread must have succeeded in | |
5220 // removing the bias bit from the object's header. | |
5221 if (counters != NULL) { | |
5222 cond_inc32(Assembler::zero, | |
5223 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); | |
5224 } | |
5225 | |
5226 bind(cas_label); | |
5227 | |
5228 return null_check_offset; | |
5229 } | |
5230 | |
5231 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { | |
5232 Label L, E; | |
5233 | |
5234 #ifdef _WIN64 | |
5235 // Windows always allocates space for it's register args | |
5236 assert(num_args <= 4, "only register arguments supported"); | |
5237 subq(rsp, frame::arg_reg_save_area_bytes); | |
5238 #endif | |
5239 | |
5240 // Align stack if necessary | |
5241 testl(rsp, 15); | |
5242 jcc(Assembler::zero, L); | |
5243 | |
5244 subq(rsp, 8); | |
5245 { | |
5246 call(RuntimeAddress(entry_point)); | |
5247 } | |
5248 addq(rsp, 8); | |
5249 jmp(E); | |
5250 | |
5251 bind(L); | |
5252 { | |
5253 call(RuntimeAddress(entry_point)); | |
5254 } | |
5255 | |
5256 bind(E); | |
5257 | |
5258 #ifdef _WIN64 | |
5259 // restore stack pointer | |
5260 addq(rsp, frame::arg_reg_save_area_bytes); | |
5261 #endif | |
5262 | |
5263 } | |
5264 | |
5265 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { | |
5266 assert(!src2.is_lval(), "should use cmpptr"); | |
5267 | |
5268 if (reachable(src2)) { | |
5269 cmpq(src1, as_Address(src2)); | |
5270 } else { | |
5271 lea(rscratch1, src2); | |
5272 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
5273 } | |
5274 } | |
5275 | |
5276 int MacroAssembler::corrected_idivq(Register reg) { | |
5277 // Full implementation of Java ldiv and lrem; checks for special | |
5278 // case as described in JVM spec., p.243 & p.271. The function | |
5279 // returns the (pc) offset of the idivl instruction - may be needed | |
5280 // for implicit exceptions. | |
5281 // | |
5282 // normal case special case | |
5283 // | |
5284 // input : rax: dividend min_long | |
5285 // reg: divisor (may not be eax/edx) -1 | |
5286 // | |
5287 // output: rax: quotient (= rax idiv reg) min_long | |
5288 // rdx: remainder (= rax irem reg) 0 | |
5289 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); | |
5290 static const int64_t min_long = 0x8000000000000000; | |
5291 Label normal_case, special_case; | |
5292 | |
5293 // check for special case | |
5294 cmp64(rax, ExternalAddress((address) &min_long)); | |
5295 jcc(Assembler::notEqual, normal_case); | |
5296 xorl(rdx, rdx); // prepare rdx for possible special case (where | |
5297 // remainder = 0) | |
5298 cmpq(reg, -1); | |
5299 jcc(Assembler::equal, special_case); | |
5300 | |
5301 // handle normal case | |
5302 bind(normal_case); | |
5303 cdqq(); | |
5304 int idivq_offset = offset(); | |
5305 idivq(reg); | |
5306 | |
5307 // normal and special case exit | |
5308 bind(special_case); | |
5309 | |
5310 return idivq_offset; | |
5311 } | |
5312 | |
5313 void MacroAssembler::decrementq(Register reg, int value) { | |
5314 if (value == min_jint) { subq(reg, value); return; } | |
5315 if (value < 0) { incrementq(reg, -value); return; } | |
5316 if (value == 0) { ; return; } | |
5317 if (value == 1 && UseIncDec) { decq(reg) ; return; } | |
5318 /* else */ { subq(reg, value) ; return; } | |
5319 } | |
5320 | |
5321 void MacroAssembler::decrementq(Address dst, int value) { | |
5322 if (value == min_jint) { subq(dst, value); return; } | |
5323 if (value < 0) { incrementq(dst, -value); return; } | |
5324 if (value == 0) { ; return; } | |
5325 if (value == 1 && UseIncDec) { decq(dst) ; return; } | |
5326 /* else */ { subq(dst, value) ; return; } | |
5327 } | |
5328 | |
5329 void MacroAssembler::fat_nop() { | |
5330 // A 5 byte nop that is safe for patching (see patch_verified_entry) | |
5331 // Recommened sequence from 'Software Optimization Guide for the AMD | |
5332 // Hammer Processor' | |
5333 emit_byte(0x66); | |
5334 emit_byte(0x66); | |
5335 emit_byte(0x90); | |
5336 emit_byte(0x66); | |
5337 emit_byte(0x90); | |
5338 } | |
5339 | |
5340 void MacroAssembler::incrementq(Register reg, int value) { | |
5341 if (value == min_jint) { addq(reg, value); return; } | |
5342 if (value < 0) { decrementq(reg, -value); return; } | |
5343 if (value == 0) { ; return; } | |
5344 if (value == 1 && UseIncDec) { incq(reg) ; return; } | |
5345 /* else */ { addq(reg, value) ; return; } | |
5346 } | |
5347 | |
5348 void MacroAssembler::incrementq(Address dst, int value) { | |
5349 if (value == min_jint) { addq(dst, value); return; } | |
5350 if (value < 0) { decrementq(dst, -value); return; } | |
5351 if (value == 0) { ; return; } | |
5352 if (value == 1 && UseIncDec) { incq(dst) ; return; } | |
5353 /* else */ { addq(dst, value) ; return; } | |
5354 } | |
5355 | |
5356 // 32bit can do a case table jump in one instruction but we no longer allow the base | |
5357 // to be installed in the Address class | |
5358 void MacroAssembler::jump(ArrayAddress entry) { | |
5359 lea(rscratch1, entry.base()); | |
5360 Address dispatch = entry.index(); | |
5361 assert(dispatch._base == noreg, "must be"); | |
5362 dispatch._base = rscratch1; | |
5363 jmp(dispatch); | |
5364 } | |
5365 | |
5366 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { | |
5367 ShouldNotReachHere(); // 64bit doesn't use two regs | |
5368 cmpq(x_lo, y_lo); | |
5369 } | |
5370 | |
5371 void MacroAssembler::lea(Register dst, AddressLiteral src) { | |
5372 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
5373 } | |
5374 | |
5375 void MacroAssembler::lea(Address dst, AddressLiteral adr) { | |
5376 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); | |
5377 movptr(dst, rscratch1); | |
5378 } | |
5379 | |
5380 void MacroAssembler::leave() { | |
5381 // %%% is this really better? Why not on 32bit too? | |
5382 emit_byte(0xC9); // LEAVE | |
5383 } | |
5384 | |
5385 void MacroAssembler::lneg(Register hi, Register lo) { | |
5386 ShouldNotReachHere(); // 64bit doesn't use two regs | |
5387 negq(lo); | |
5388 } | |
5389 | |
5390 void MacroAssembler::movoop(Register dst, jobject obj) { | |
5391 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
5392 } | |
5393 | |
5394 void MacroAssembler::movoop(Address dst, jobject obj) { | |
5395 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); | |
5396 movq(dst, rscratch1); | |
5397 } | |
5398 | |
5399 void MacroAssembler::movptr(Register dst, AddressLiteral src) { | |
5400 if (src.is_lval()) { | |
5401 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); | |
5402 } else { | |
5403 if (reachable(src)) { | |
5404 movq(dst, as_Address(src)); | |
5405 } else { | |
5406 lea(rscratch1, src); | |
5407 movq(dst, Address(rscratch1,0)); | |
0 | 5408 } |
304 | 5409 } |
5410 } | |
5411 | |
5412 void MacroAssembler::movptr(ArrayAddress dst, Register src) { | |
5413 movq(as_Address(dst), src); | |
5414 } | |
5415 | |
5416 void MacroAssembler::movptr(Register dst, ArrayAddress src) { | |
5417 movq(dst, as_Address(src)); | |
5418 } | |
5419 | |
5420 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
5421 void MacroAssembler::movptr(Address dst, intptr_t src) { | |
5422 mov64(rscratch1, src); | |
5423 movq(dst, rscratch1); | |
5424 } | |
5425 | |
5426 // These are mostly for initializing NULL | |
5427 void MacroAssembler::movptr(Address dst, int32_t src) { | |
5428 movslq(dst, src); | |
5429 } | |
5430 | |
5431 void MacroAssembler::movptr(Register dst, int32_t src) { | |
5432 mov64(dst, (intptr_t)src); | |
5433 } | |
5434 | |
5435 void MacroAssembler::pushoop(jobject obj) { | |
5436 movoop(rscratch1, obj); | |
5437 push(rscratch1); | |
5438 } | |
5439 | |
5440 void MacroAssembler::pushptr(AddressLiteral src) { | |
5441 lea(rscratch1, src); | |
5442 if (src.is_lval()) { | |
5443 push(rscratch1); | |
5444 } else { | |
5445 pushq(Address(rscratch1, 0)); | |
5446 } | |
5447 } | |
5448 | |
5449 void MacroAssembler::reset_last_Java_frame(bool clear_fp, | |
5450 bool clear_pc) { | |
5451 // we must set sp to zero to clear frame | |
512
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diff
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|
5452 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
304 | 5453 // must clear fp, so that compiled frames are not confused; it is |
5454 // possible that we need it only for debugging | |
5455 if (clear_fp) { | |
512
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diff
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|
5456 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
304 | 5457 } |
5458 | |
5459 if (clear_pc) { | |
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|
5460 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
304 | 5461 } |
5462 } | |
5463 | |
5464 void MacroAssembler::set_last_Java_frame(Register last_java_sp, | |
5465 Register last_java_fp, | |
5466 address last_java_pc) { | |
5467 // determine last_java_sp register | |
5468 if (!last_java_sp->is_valid()) { | |
5469 last_java_sp = rsp; | |
5470 } | |
5471 | |
5472 // last_java_fp is optional | |
5473 if (last_java_fp->is_valid()) { | |
5474 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), | |
5475 last_java_fp); | |
5476 } | |
5477 | |
5478 // last_java_pc is optional | |
5479 if (last_java_pc != NULL) { | |
5480 Address java_pc(r15_thread, | |
5481 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); | |
5482 lea(rscratch1, InternalAddress(last_java_pc)); | |
5483 movptr(java_pc, rscratch1); | |
5484 } | |
5485 | |
5486 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
5487 } | |
5488 | |
5489 static void pass_arg0(MacroAssembler* masm, Register arg) { | |
5490 if (c_rarg0 != arg ) { | |
5491 masm->mov(c_rarg0, arg); | |
5492 } | |
5493 } | |
5494 | |
5495 static void pass_arg1(MacroAssembler* masm, Register arg) { | |
5496 if (c_rarg1 != arg ) { | |
5497 masm->mov(c_rarg1, arg); | |
5498 } | |
5499 } | |
5500 | |
5501 static void pass_arg2(MacroAssembler* masm, Register arg) { | |
5502 if (c_rarg2 != arg ) { | |
5503 masm->mov(c_rarg2, arg); | |
5504 } | |
5505 } | |
5506 | |
5507 static void pass_arg3(MacroAssembler* masm, Register arg) { | |
5508 if (c_rarg3 != arg ) { | |
5509 masm->mov(c_rarg3, arg); | |
5510 } | |
5511 } | |
5512 | |
5513 void MacroAssembler::stop(const char* msg) { | |
5514 address rip = pc(); | |
5515 pusha(); // get regs on stack | |
5516 lea(c_rarg0, ExternalAddress((address) msg)); | |
5517 lea(c_rarg1, InternalAddress(rip)); | |
5518 movq(c_rarg2, rsp); // pass pointer to regs array | |
5519 andq(rsp, -16); // align stack as required by ABI | |
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|
5520 mov64(rax, 0); |
304 | 5521 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); |
5522 hlt(); | |
5523 } | |
5524 | |
5525 void MacroAssembler::warn(const char* msg) { | |
5526 push(r12); | |
5527 movq(r12, rsp); | |
5528 andq(rsp, -16); // align stack as required by push_CPU_state and call | |
5529 | |
5530 push_CPU_state(); // keeps alignment at 16 bytes | |
5531 lea(c_rarg0, ExternalAddress((address) msg)); | |
1422
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* using reflected objects instead of oops
Lukas Stadler <lukas.stadler@oracle.com>
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diff
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|
5532 mov64(rax, 0); |
304 | 5533 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); |
5534 pop_CPU_state(); | |
5535 | |
5536 movq(rsp, r12); | |
5537 pop(r12); | |
5538 } | |
5539 | |
5540 #ifndef PRODUCT | |
5541 extern "C" void findpc(intptr_t x); | |
5542 #endif | |
5543 | |
5544 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { | |
5545 // In order to get locks to work, we need to fake a in_VM state | |
5546 if (ShowMessageBoxOnError ) { | |
5547 JavaThread* thread = JavaThread::current(); | |
5548 JavaThreadState saved_state = thread->thread_state(); | |
5549 thread->set_thread_state(_thread_in_vm); | |
5550 #ifndef PRODUCT | |
5551 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
5552 ttyLocker ttyl; | |
5553 BytecodeCounter::print(); | |
0 | 5554 } |
304 | 5555 #endif |
5556 // To see where a verify_oop failed, get $ebx+40/X for this frame. | |
5557 // XXX correct this offset for amd64 | |
5558 // This is the value of eip which points to where verify_oop will return. | |
5559 if (os::message_box(msg, "Execution stopped, print registers?")) { | |
5560 ttyLocker ttyl; | |
5561 tty->print_cr("rip = 0x%016lx", pc); | |
5562 #ifndef PRODUCT | |
5563 tty->cr(); | |
5564 findpc(pc); | |
5565 tty->cr(); | |
5566 #endif | |
5567 tty->print_cr("rax = 0x%016lx", regs[15]); | |
5568 tty->print_cr("rbx = 0x%016lx", regs[12]); | |
5569 tty->print_cr("rcx = 0x%016lx", regs[14]); | |
5570 tty->print_cr("rdx = 0x%016lx", regs[13]); | |
5571 tty->print_cr("rdi = 0x%016lx", regs[8]); | |
5572 tty->print_cr("rsi = 0x%016lx", regs[9]); | |
5573 tty->print_cr("rbp = 0x%016lx", regs[10]); | |
5574 tty->print_cr("rsp = 0x%016lx", regs[11]); | |
5575 tty->print_cr("r8 = 0x%016lx", regs[7]); | |
5576 tty->print_cr("r9 = 0x%016lx", regs[6]); | |
5577 tty->print_cr("r10 = 0x%016lx", regs[5]); | |
5578 tty->print_cr("r11 = 0x%016lx", regs[4]); | |
5579 tty->print_cr("r12 = 0x%016lx", regs[3]); | |
5580 tty->print_cr("r13 = 0x%016lx", regs[2]); | |
5581 tty->print_cr("r14 = 0x%016lx", regs[1]); | |
5582 tty->print_cr("r15 = 0x%016lx", regs[0]); | |
5583 BREAKPOINT; | |
0 | 5584 } |
304 | 5585 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); |
5586 } else { | |
5587 ttyLocker ttyl; | |
5588 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", | |
5589 msg); | |
5590 } | |
5591 } | |
5592 | |
5593 #endif // _LP64 | |
5594 | |
5595 // Now versions that are common to 32/64 bit | |
5596 | |
5597 void MacroAssembler::addptr(Register dst, int32_t imm32) { | |
5598 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); | |
5599 } | |
5600 | |
5601 void MacroAssembler::addptr(Register dst, Register src) { | |
5602 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
5603 } | |
5604 | |
5605 void MacroAssembler::addptr(Address dst, Register src) { | |
5606 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); | |
5607 } | |
5608 | |
5609 void MacroAssembler::align(int modulus) { | |
5610 if (offset() % modulus != 0) { | |
5611 nop(modulus - (offset() % modulus)); | |
5612 } | |
5613 } | |
5614 | |
5615 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { | |
1060 | 5616 if (reachable(src)) { |
5617 andpd(dst, as_Address(src)); | |
5618 } else { | |
5619 lea(rscratch1, src); | |
5620 andpd(dst, Address(rscratch1, 0)); | |
5621 } | |
304 | 5622 } |
5623 | |
5624 void MacroAssembler::andptr(Register dst, int32_t imm32) { | |
5625 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); | |
5626 } | |
5627 | |
5628 void MacroAssembler::atomic_incl(AddressLiteral counter_addr) { | |
5629 pushf(); | |
5630 if (os::is_MP()) | |
5631 lock(); | |
5632 incrementl(counter_addr); | |
5633 popf(); | |
5634 } | |
5635 | |
5636 // Writes to stack successive pages until offset reached to check for | |
5637 // stack overflow + shadow pages. This clobbers tmp. | |
5638 void MacroAssembler::bang_stack_size(Register size, Register tmp) { | |
5639 movptr(tmp, rsp); | |
5640 // Bang stack for total size given plus shadow page size. | |
5641 // Bang one page at a time because large size can bang beyond yellow and | |
5642 // red zones. | |
5643 Label loop; | |
5644 bind(loop); | |
5645 movl(Address(tmp, (-os::vm_page_size())), size ); | |
5646 subptr(tmp, os::vm_page_size()); | |
5647 subl(size, os::vm_page_size()); | |
5648 jcc(Assembler::greater, loop); | |
5649 | |
5650 // Bang down shadow pages too. | |
5651 // The -1 because we already subtracted 1 page. | |
5652 for (int i = 0; i< StackShadowPages-1; i++) { | |
5653 // this could be any sized move but this is can be a debugging crumb | |
5654 // so the bigger the better. | |
5655 movptr(Address(tmp, (-i*os::vm_page_size())), size ); | |
5656 } | |
5657 } | |
5658 | |
5659 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { | |
5660 assert(UseBiasedLocking, "why call this otherwise?"); | |
5661 | |
5662 // Check for biased locking unlock case, which is a no-op | |
5663 // Note: we do not have to check the thread ID for two reasons. | |
5664 // First, the interpreter checks for IllegalMonitorStateException at | |
5665 // a higher level. Second, if the bias was revoked while we held the | |
5666 // lock, the object could not be rebiased toward another thread, so | |
5667 // the bias bit would be clear. | |
5668 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); | |
5669 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); | |
5670 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); | |
5671 jcc(Assembler::equal, done); | |
5672 } | |
5673 | |
5674 void MacroAssembler::c2bool(Register x) { | |
5675 // implements x == 0 ? 0 : 1 | |
5676 // note: must only look at least-significant byte of x | |
5677 // since C-style booleans are stored in one byte | |
5678 // only! (was bug) | |
5679 andl(x, 0xFF); | |
5680 setb(Assembler::notZero, x); | |
5681 } | |
5682 | |
5683 // Wouldn't need if AddressLiteral version had new name | |
5684 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { | |
5685 Assembler::call(L, rtype); | |
5686 } | |
5687 | |
5688 void MacroAssembler::call(Register entry) { | |
5689 Assembler::call(entry); | |
5690 } | |
5691 | |
5692 void MacroAssembler::call(AddressLiteral entry) { | |
5693 if (reachable(entry)) { | |
5694 Assembler::call_literal(entry.target(), entry.rspec()); | |
5695 } else { | |
5696 lea(rscratch1, entry); | |
5697 Assembler::call(rscratch1); | |
5698 } | |
5699 } | |
5700 | |
5701 // Implementation of call_VM versions | |
5702 | |
5703 void MacroAssembler::call_VM(Register oop_result, | |
5704 address entry_point, | |
5705 bool check_exceptions) { | |
5706 Label C, E; | |
5707 call(C, relocInfo::none); | |
5708 jmp(E); | |
5709 | |
5710 bind(C); | |
5711 call_VM_helper(oop_result, entry_point, 0, check_exceptions); | |
5712 ret(0); | |
5713 | |
5714 bind(E); | |
5715 } | |
5716 | |
5717 void MacroAssembler::call_VM(Register oop_result, | |
5718 address entry_point, | |
5719 Register arg_1, | |
5720 bool check_exceptions) { | |
5721 Label C, E; | |
5722 call(C, relocInfo::none); | |
5723 jmp(E); | |
5724 | |
5725 bind(C); | |
5726 pass_arg1(this, arg_1); | |
5727 call_VM_helper(oop_result, entry_point, 1, check_exceptions); | |
5728 ret(0); | |
5729 | |
5730 bind(E); | |
5731 } | |
5732 | |
5733 void MacroAssembler::call_VM(Register oop_result, | |
5734 address entry_point, | |
5735 Register arg_1, | |
5736 Register arg_2, | |
5737 bool check_exceptions) { | |
5738 Label C, E; | |
5739 call(C, relocInfo::none); | |
5740 jmp(E); | |
5741 | |
5742 bind(C); | |
5743 | |
5744 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5745 | |
5746 pass_arg2(this, arg_2); | |
5747 pass_arg1(this, arg_1); | |
5748 call_VM_helper(oop_result, entry_point, 2, check_exceptions); | |
5749 ret(0); | |
5750 | |
5751 bind(E); | |
5752 } | |
5753 | |
5754 void MacroAssembler::call_VM(Register oop_result, | |
5755 address entry_point, | |
5756 Register arg_1, | |
5757 Register arg_2, | |
5758 Register arg_3, | |
5759 bool check_exceptions) { | |
5760 Label C, E; | |
5761 call(C, relocInfo::none); | |
5762 jmp(E); | |
5763 | |
5764 bind(C); | |
5765 | |
5766 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
5767 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
5768 pass_arg3(this, arg_3); | |
5769 | |
5770 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5771 pass_arg2(this, arg_2); | |
5772 | |
5773 pass_arg1(this, arg_1); | |
5774 call_VM_helper(oop_result, entry_point, 3, check_exceptions); | |
5775 ret(0); | |
5776 | |
5777 bind(E); | |
5778 } | |
5779 | |
5780 void MacroAssembler::call_VM(Register oop_result, | |
5781 Register last_java_sp, | |
5782 address entry_point, | |
5783 int number_of_arguments, | |
5784 bool check_exceptions) { | |
5785 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); | |
5786 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
5787 } | |
5788 | |
5789 void MacroAssembler::call_VM(Register oop_result, | |
5790 Register last_java_sp, | |
5791 address entry_point, | |
5792 Register arg_1, | |
5793 bool check_exceptions) { | |
5794 pass_arg1(this, arg_1); | |
5795 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
5796 } | |
5797 | |
5798 void MacroAssembler::call_VM(Register oop_result, | |
5799 Register last_java_sp, | |
5800 address entry_point, | |
5801 Register arg_1, | |
5802 Register arg_2, | |
5803 bool check_exceptions) { | |
5804 | |
5805 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5806 pass_arg2(this, arg_2); | |
5807 pass_arg1(this, arg_1); | |
5808 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
5809 } | |
5810 | |
5811 void MacroAssembler::call_VM(Register oop_result, | |
5812 Register last_java_sp, | |
5813 address entry_point, | |
5814 Register arg_1, | |
5815 Register arg_2, | |
5816 Register arg_3, | |
5817 bool check_exceptions) { | |
5818 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); | |
5819 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); | |
5820 pass_arg3(this, arg_3); | |
5821 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5822 pass_arg2(this, arg_2); | |
5823 pass_arg1(this, arg_1); | |
5824 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
5825 } | |
5826 | |
5827 void MacroAssembler::call_VM_base(Register oop_result, | |
5828 Register java_thread, | |
5829 Register last_java_sp, | |
5830 address entry_point, | |
5831 int number_of_arguments, | |
5832 bool check_exceptions) { | |
5833 // determine java_thread register | |
5834 if (!java_thread->is_valid()) { | |
5835 #ifdef _LP64 | |
5836 java_thread = r15_thread; | |
5837 #else | |
5838 java_thread = rdi; | |
5839 get_thread(java_thread); | |
5840 #endif // LP64 | |
5841 } | |
5842 // determine last_java_sp register | |
5843 if (!last_java_sp->is_valid()) { | |
5844 last_java_sp = rsp; | |
5845 } | |
5846 // debugging support | |
5847 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
5848 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); | |
5849 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); | |
5850 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); | |
5851 | |
5852 // push java thread (becomes first argument of C function) | |
5853 | |
5854 NOT_LP64(push(java_thread); number_of_arguments++); | |
5855 LP64_ONLY(mov(c_rarg0, r15_thread)); | |
5856 | |
5857 // set last Java frame before call | |
5858 assert(last_java_sp != rbp, "can't use ebp/rbp"); | |
5859 | |
5860 // Only interpreter should have to set fp | |
5861 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); | |
5862 | |
5863 // do the call, remove parameters | |
5864 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); | |
5865 | |
5866 // restore the thread (cannot use the pushed argument since arguments | |
5867 // may be overwritten by C code generated by an optimizing compiler); | |
5868 // however can use the register value directly if it is callee saved. | |
5869 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { | |
5870 // rdi & rsi (also r15) are callee saved -> nothing to do | |
5871 #ifdef ASSERT | |
5872 guarantee(java_thread != rax, "change this code"); | |
5873 push(rax); | |
5874 { Label L; | |
5875 get_thread(rax); | |
5876 cmpptr(java_thread, rax); | |
5877 jcc(Assembler::equal, L); | |
5878 stop("MacroAssembler::call_VM_base: rdi not callee saved?"); | |
5879 bind(L); | |
0 | 5880 } |
304 | 5881 pop(rax); |
5882 #endif | |
5883 } else { | |
5884 get_thread(java_thread); | |
5885 } | |
5886 // reset last Java frame | |
5887 // Only interpreter should have to clear fp | |
5888 reset_last_Java_frame(java_thread, true, false); | |
5889 | |
5890 #ifndef CC_INTERP | |
5891 // C++ interp handles this in the interpreter | |
5892 check_and_handle_popframe(java_thread); | |
5893 check_and_handle_earlyret(java_thread); | |
5894 #endif /* CC_INTERP */ | |
5895 | |
5896 if (check_exceptions) { | |
5897 // check for pending exceptions (java_thread is set upon return) | |
5898 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); | |
5899 #ifndef _LP64 | |
5900 jump_cc(Assembler::notEqual, | |
5901 RuntimeAddress(StubRoutines::forward_exception_entry())); | |
5902 #else | |
5903 // This used to conditionally jump to forward_exception however it is | |
5904 // possible if we relocate that the branch will not reach. So we must jump | |
5905 // around so we can always reach | |
5906 | |
5907 Label ok; | |
5908 jcc(Assembler::equal, ok); | |
5909 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); | |
5910 bind(ok); | |
5911 #endif // LP64 | |
5912 } | |
5913 | |
5914 // get oop result if there is one and reset the value in the thread | |
5915 if (oop_result->is_valid()) { | |
5916 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); | |
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changeset
|
5917 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); |
304 | 5918 verify_oop(oop_result, "broken oop in call_VM_base"); |
5919 } | |
5920 } | |
5921 | |
5922 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
5923 | |
5924 // Calculate the value for last_Java_sp | |
5925 // somewhat subtle. call_VM does an intermediate call | |
5926 // which places a return address on the stack just under the | |
5927 // stack pointer as the user finsihed with it. This allows | |
5928 // use to retrieve last_Java_pc from last_Java_sp[-1]. | |
5929 // On 32bit we then have to push additional args on the stack to accomplish | |
5930 // the actual requested call. On 64bit call_VM only can use register args | |
5931 // so the only extra space is the return address that call_VM created. | |
5932 // This hopefully explains the calculations here. | |
5933 | |
5934 #ifdef _LP64 | |
5935 // We've pushed one address, correct last_Java_sp | |
5936 lea(rax, Address(rsp, wordSize)); | |
5937 #else | |
5938 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); | |
5939 #endif // LP64 | |
5940 | |
5941 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); | |
5942 | |
5943 } | |
5944 | |
5945 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { | |
5946 call_VM_leaf_base(entry_point, number_of_arguments); | |
5947 } | |
5948 | |
5949 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { | |
5950 pass_arg0(this, arg_0); | |
5951 call_VM_leaf(entry_point, 1); | |
5952 } | |
5953 | |
5954 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { | |
5955 | |
5956 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
5957 pass_arg1(this, arg_1); | |
5958 pass_arg0(this, arg_0); | |
5959 call_VM_leaf(entry_point, 2); | |
5960 } | |
5961 | |
5962 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { | |
5963 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); | |
5964 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); | |
5965 pass_arg2(this, arg_2); | |
5966 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); | |
5967 pass_arg1(this, arg_1); | |
5968 pass_arg0(this, arg_0); | |
5969 call_VM_leaf(entry_point, 3); | |
5970 } | |
5971 | |
5972 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { | |
5973 } | |
5974 | |
5975 void MacroAssembler::check_and_handle_popframe(Register java_thread) { | |
5976 } | |
5977 | |
5978 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { | |
5979 if (reachable(src1)) { | |
5980 cmpl(as_Address(src1), imm); | |
5981 } else { | |
5982 lea(rscratch1, src1); | |
5983 cmpl(Address(rscratch1, 0), imm); | |
5984 } | |
5985 } | |
5986 | |
5987 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { | |
5988 assert(!src2.is_lval(), "use cmpptr"); | |
5989 if (reachable(src2)) { | |
5990 cmpl(src1, as_Address(src2)); | |
5991 } else { | |
5992 lea(rscratch1, src2); | |
5993 cmpl(src1, Address(rscratch1, 0)); | |
5994 } | |
5995 } | |
5996 | |
5997 void MacroAssembler::cmp32(Register src1, int32_t imm) { | |
5998 Assembler::cmpl(src1, imm); | |
5999 } | |
6000 | |
6001 void MacroAssembler::cmp32(Register src1, Address src2) { | |
6002 Assembler::cmpl(src1, src2); | |
6003 } | |
6004 | |
6005 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
6006 ucomisd(opr1, opr2); | |
6007 | |
6008 Label L; | |
6009 if (unordered_is_less) { | |
6010 movl(dst, -1); | |
6011 jcc(Assembler::parity, L); | |
6012 jcc(Assembler::below , L); | |
6013 movl(dst, 0); | |
6014 jcc(Assembler::equal , L); | |
6015 increment(dst); | |
6016 } else { // unordered is greater | |
6017 movl(dst, 1); | |
6018 jcc(Assembler::parity, L); | |
6019 jcc(Assembler::above , L); | |
6020 movl(dst, 0); | |
6021 jcc(Assembler::equal , L); | |
6022 decrementl(dst); | |
6023 } | |
6024 bind(L); | |
6025 } | |
6026 | |
6027 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { | |
6028 ucomiss(opr1, opr2); | |
6029 | |
6030 Label L; | |
6031 if (unordered_is_less) { | |
6032 movl(dst, -1); | |
6033 jcc(Assembler::parity, L); | |
6034 jcc(Assembler::below , L); | |
6035 movl(dst, 0); | |
6036 jcc(Assembler::equal , L); | |
6037 increment(dst); | |
6038 } else { // unordered is greater | |
6039 movl(dst, 1); | |
6040 jcc(Assembler::parity, L); | |
6041 jcc(Assembler::above , L); | |
6042 movl(dst, 0); | |
6043 jcc(Assembler::equal , L); | |
6044 decrementl(dst); | |
6045 } | |
6046 bind(L); | |
6047 } | |
6048 | |
6049 | |
6050 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { | |
6051 if (reachable(src1)) { | |
6052 cmpb(as_Address(src1), imm); | |
6053 } else { | |
6054 lea(rscratch1, src1); | |
6055 cmpb(Address(rscratch1, 0), imm); | |
6056 } | |
6057 } | |
6058 | |
6059 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { | |
6060 #ifdef _LP64 | |
6061 if (src2.is_lval()) { | |
6062 movptr(rscratch1, src2); | |
6063 Assembler::cmpq(src1, rscratch1); | |
6064 } else if (reachable(src2)) { | |
6065 cmpq(src1, as_Address(src2)); | |
6066 } else { | |
6067 lea(rscratch1, src2); | |
6068 Assembler::cmpq(src1, Address(rscratch1, 0)); | |
6069 } | |
6070 #else | |
6071 if (src2.is_lval()) { | |
6072 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
6073 } else { | |
6074 cmpl(src1, as_Address(src2)); | |
6075 } | |
6076 #endif // _LP64 | |
6077 } | |
6078 | |
6079 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { | |
6080 assert(src2.is_lval(), "not a mem-mem compare"); | |
6081 #ifdef _LP64 | |
6082 // moves src2's literal address | |
6083 movptr(rscratch1, src2); | |
6084 Assembler::cmpq(src1, rscratch1); | |
6085 #else | |
6086 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); | |
6087 #endif // _LP64 | |
6088 } | |
6089 | |
6090 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { | |
6091 if (reachable(adr)) { | |
6092 if (os::is_MP()) | |
6093 lock(); | |
6094 cmpxchgptr(reg, as_Address(adr)); | |
6095 } else { | |
6096 lea(rscratch1, adr); | |
6097 if (os::is_MP()) | |
6098 lock(); | |
6099 cmpxchgptr(reg, Address(rscratch1, 0)); | |
6100 } | |
6101 } | |
6102 | |
6103 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { | |
6104 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); | |
6105 } | |
6106 | |
6107 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { | |
1060 | 6108 if (reachable(src)) { |
6109 comisd(dst, as_Address(src)); | |
6110 } else { | |
6111 lea(rscratch1, src); | |
6112 comisd(dst, Address(rscratch1, 0)); | |
6113 } | |
304 | 6114 } |
6115 | |
6116 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { | |
1060 | 6117 if (reachable(src)) { |
6118 comiss(dst, as_Address(src)); | |
6119 } else { | |
6120 lea(rscratch1, src); | |
6121 comiss(dst, Address(rscratch1, 0)); | |
6122 } | |
304 | 6123 } |
6124 | |
6125 | |
6126 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { | |
6127 Condition negated_cond = negate_condition(cond); | |
6128 Label L; | |
6129 jcc(negated_cond, L); | |
6130 atomic_incl(counter_addr); | |
6131 bind(L); | |
6132 } | |
6133 | |
6134 int MacroAssembler::corrected_idivl(Register reg) { | |
6135 // Full implementation of Java idiv and irem; checks for | |
6136 // special case as described in JVM spec., p.243 & p.271. | |
6137 // The function returns the (pc) offset of the idivl | |
6138 // instruction - may be needed for implicit exceptions. | |
6139 // | |
6140 // normal case special case | |
6141 // | |
6142 // input : rax,: dividend min_int | |
6143 // reg: divisor (may not be rax,/rdx) -1 | |
6144 // | |
6145 // output: rax,: quotient (= rax, idiv reg) min_int | |
6146 // rdx: remainder (= rax, irem reg) 0 | |
6147 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); | |
6148 const int min_int = 0x80000000; | |
6149 Label normal_case, special_case; | |
6150 | |
6151 // check for special case | |
6152 cmpl(rax, min_int); | |
6153 jcc(Assembler::notEqual, normal_case); | |
6154 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) | |
6155 cmpl(reg, -1); | |
6156 jcc(Assembler::equal, special_case); | |
6157 | |
6158 // handle normal case | |
6159 bind(normal_case); | |
6160 cdql(); | |
6161 int idivl_offset = offset(); | |
6162 idivl(reg); | |
6163 | |
6164 // normal and special case exit | |
6165 bind(special_case); | |
6166 | |
6167 return idivl_offset; | |
6168 } | |
6169 | |
6170 | |
6171 | |
6172 void MacroAssembler::decrementl(Register reg, int value) { | |
6173 if (value == min_jint) {subl(reg, value) ; return; } | |
6174 if (value < 0) { incrementl(reg, -value); return; } | |
6175 if (value == 0) { ; return; } | |
6176 if (value == 1 && UseIncDec) { decl(reg) ; return; } | |
6177 /* else */ { subl(reg, value) ; return; } | |
6178 } | |
6179 | |
6180 void MacroAssembler::decrementl(Address dst, int value) { | |
6181 if (value == min_jint) {subl(dst, value) ; return; } | |
6182 if (value < 0) { incrementl(dst, -value); return; } | |
6183 if (value == 0) { ; return; } | |
6184 if (value == 1 && UseIncDec) { decl(dst) ; return; } | |
6185 /* else */ { subl(dst, value) ; return; } | |
6186 } | |
6187 | |
6188 void MacroAssembler::division_with_shift (Register reg, int shift_value) { | |
6189 assert (shift_value > 0, "illegal shift value"); | |
6190 Label _is_positive; | |
6191 testl (reg, reg); | |
6192 jcc (Assembler::positive, _is_positive); | |
6193 int offset = (1 << shift_value) - 1 ; | |
6194 | |
6195 if (offset == 1) { | |
6196 incrementl(reg); | |
6197 } else { | |
6198 addl(reg, offset); | |
6199 } | |
6200 | |
6201 bind (_is_positive); | |
6202 sarl(reg, shift_value); | |
6203 } | |
6204 | |
6205 // !defined(COMPILER2) is because of stupid core builds | |
6206 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) | |
6207 void MacroAssembler::empty_FPU_stack() { | |
6208 if (VM_Version::supports_mmx()) { | |
6209 emms(); | |
6210 } else { | |
6211 for (int i = 8; i-- > 0; ) ffree(i); | |
6212 } | |
6213 } | |
6214 #endif // !LP64 || C1 || !C2 | |
6215 | |
6216 | |
6217 // Defines obj, preserves var_size_in_bytes | |
6218 void MacroAssembler::eden_allocate(Register obj, | |
6219 Register var_size_in_bytes, | |
6220 int con_size_in_bytes, | |
6221 Register t1, | |
6222 Label& slow_case) { | |
6223 assert(obj == rax, "obj must be in rax, for cmpxchg"); | |
6224 assert_different_registers(obj, var_size_in_bytes, t1); | |
362 | 6225 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
6226 jmp(slow_case); | |
304 | 6227 } else { |
362 | 6228 Register end = t1; |
6229 Label retry; | |
6230 bind(retry); | |
6231 ExternalAddress heap_top((address) Universe::heap()->top_addr()); | |
6232 movptr(obj, heap_top); | |
6233 if (var_size_in_bytes == noreg) { | |
6234 lea(end, Address(obj, con_size_in_bytes)); | |
6235 } else { | |
6236 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
6237 } | |
6238 // if end < obj then we wrapped around => object too long => slow case | |
6239 cmpptr(end, obj); | |
6240 jcc(Assembler::below, slow_case); | |
6241 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); | |
6242 jcc(Assembler::above, slow_case); | |
6243 // Compare obj with the top addr, and if still equal, store the new top addr in | |
6244 // end at the address of the top addr pointer. Sets ZF if was equal, and clears | |
6245 // it otherwise. Use lock prefix for atomicity on MPs. | |
6246 locked_cmpxchgptr(end, heap_top); | |
6247 jcc(Assembler::notEqual, retry); | |
6248 } | |
304 | 6249 } |
6250 | |
6251 void MacroAssembler::enter() { | |
6252 push(rbp); | |
6253 mov(rbp, rsp); | |
6254 } | |
0 | 6255 |
6256 void MacroAssembler::fcmp(Register tmp) { | |
6257 fcmp(tmp, 1, true, true); | |
6258 } | |
6259 | |
6260 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { | |
6261 assert(!pop_right || pop_left, "usage error"); | |
6262 if (VM_Version::supports_cmov()) { | |
6263 assert(tmp == noreg, "unneeded temp"); | |
6264 if (pop_left) { | |
6265 fucomip(index); | |
6266 } else { | |
6267 fucomi(index); | |
6268 } | |
6269 if (pop_right) { | |
6270 fpop(); | |
6271 } | |
6272 } else { | |
6273 assert(tmp != noreg, "need temp"); | |
6274 if (pop_left) { | |
6275 if (pop_right) { | |
6276 fcompp(); | |
6277 } else { | |
6278 fcomp(index); | |
6279 } | |
6280 } else { | |
6281 fcom(index); | |
6282 } | |
6283 // convert FPU condition into eflags condition via rax, | |
6284 save_rax(tmp); | |
6285 fwait(); fnstsw_ax(); | |
6286 sahf(); | |
6287 restore_rax(tmp); | |
6288 } | |
6289 // condition codes set as follows: | |
6290 // | |
6291 // CF (corresponds to C0) if x < y | |
6292 // PF (corresponds to C2) if unordered | |
6293 // ZF (corresponds to C3) if x = y | |
6294 } | |
6295 | |
6296 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { | |
6297 fcmp2int(dst, unordered_is_less, 1, true, true); | |
6298 } | |
6299 | |
6300 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { | |
6301 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); | |
6302 Label L; | |
6303 if (unordered_is_less) { | |
6304 movl(dst, -1); | |
6305 jcc(Assembler::parity, L); | |
6306 jcc(Assembler::below , L); | |
6307 movl(dst, 0); | |
6308 jcc(Assembler::equal , L); | |
6309 increment(dst); | |
6310 } else { // unordered is greater | |
6311 movl(dst, 1); | |
6312 jcc(Assembler::parity, L); | |
6313 jcc(Assembler::above , L); | |
6314 movl(dst, 0); | |
6315 jcc(Assembler::equal , L); | |
304 | 6316 decrementl(dst); |
0 | 6317 } |
6318 bind(L); | |
6319 } | |
6320 | |
304 | 6321 void MacroAssembler::fld_d(AddressLiteral src) { |
6322 fld_d(as_Address(src)); | |
6323 } | |
6324 | |
6325 void MacroAssembler::fld_s(AddressLiteral src) { | |
6326 fld_s(as_Address(src)); | |
6327 } | |
6328 | |
6329 void MacroAssembler::fld_x(AddressLiteral src) { | |
6330 Assembler::fld_x(as_Address(src)); | |
6331 } | |
6332 | |
6333 void MacroAssembler::fldcw(AddressLiteral src) { | |
6334 Assembler::fldcw(as_Address(src)); | |
6335 } | |
0 | 6336 |
6337 void MacroAssembler::fpop() { | |
6338 ffree(); | |
6339 fincstp(); | |
6340 } | |
6341 | |
304 | 6342 void MacroAssembler::fremr(Register tmp) { |
6343 save_rax(tmp); | |
6344 { Label L; | |
6345 bind(L); | |
6346 fprem(); | |
6347 fwait(); fnstsw_ax(); | |
6348 #ifdef _LP64 | |
6349 testl(rax, 0x400); | |
6350 jcc(Assembler::notEqual, L); | |
6351 #else | |
6352 sahf(); | |
6353 jcc(Assembler::parity, L); | |
6354 #endif // _LP64 | |
6355 } | |
6356 restore_rax(tmp); | |
6357 // Result is in ST0. | |
6358 // Note: fxch & fpop to get rid of ST1 | |
6359 // (otherwise FPU stack could overflow eventually) | |
6360 fxch(1); | |
6361 fpop(); | |
6362 } | |
6363 | |
6364 | |
6365 void MacroAssembler::incrementl(AddressLiteral dst) { | |
6366 if (reachable(dst)) { | |
6367 incrementl(as_Address(dst)); | |
0 | 6368 } else { |
304 | 6369 lea(rscratch1, dst); |
6370 incrementl(Address(rscratch1, 0)); | |
6371 } | |
6372 } | |
6373 | |
6374 void MacroAssembler::incrementl(ArrayAddress dst) { | |
6375 incrementl(as_Address(dst)); | |
6376 } | |
6377 | |
6378 void MacroAssembler::incrementl(Register reg, int value) { | |
6379 if (value == min_jint) {addl(reg, value) ; return; } | |
6380 if (value < 0) { decrementl(reg, -value); return; } | |
6381 if (value == 0) { ; return; } | |
6382 if (value == 1 && UseIncDec) { incl(reg) ; return; } | |
6383 /* else */ { addl(reg, value) ; return; } | |
6384 } | |
6385 | |
6386 void MacroAssembler::incrementl(Address dst, int value) { | |
6387 if (value == min_jint) {addl(dst, value) ; return; } | |
6388 if (value < 0) { decrementl(dst, -value); return; } | |
6389 if (value == 0) { ; return; } | |
6390 if (value == 1 && UseIncDec) { incl(dst) ; return; } | |
6391 /* else */ { addl(dst, value) ; return; } | |
6392 } | |
6393 | |
6394 void MacroAssembler::jump(AddressLiteral dst) { | |
6395 if (reachable(dst)) { | |
6396 jmp_literal(dst.target(), dst.rspec()); | |
6397 } else { | |
6398 lea(rscratch1, dst); | |
6399 jmp(rscratch1); | |
6400 } | |
6401 } | |
6402 | |
6403 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { | |
6404 if (reachable(dst)) { | |
6405 InstructionMark im(this); | |
6406 relocate(dst.reloc()); | |
6407 const int short_size = 2; | |
6408 const int long_size = 6; | |
6409 int offs = (intptr_t)dst.target() - ((intptr_t)_code_pos); | |
6410 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { | |
6411 // 0111 tttn #8-bit disp | |
6412 emit_byte(0x70 | cc); | |
6413 emit_byte((offs - short_size) & 0xFF); | |
6414 } else { | |
6415 // 0000 1111 1000 tttn #32-bit disp | |
6416 emit_byte(0x0F); | |
6417 emit_byte(0x80 | cc); | |
6418 emit_long(offs - long_size); | |
6419 } | |
0 | 6420 } else { |
304 | 6421 #ifdef ASSERT |
6422 warning("reversing conditional branch"); | |
6423 #endif /* ASSERT */ | |
6424 Label skip; | |
6425 jccb(reverse[cc], skip); | |
6426 lea(rscratch1, dst); | |
6427 Assembler::jmp(rscratch1); | |
6428 bind(skip); | |
6429 } | |
6430 } | |
6431 | |
6432 void MacroAssembler::ldmxcsr(AddressLiteral src) { | |
6433 if (reachable(src)) { | |
6434 Assembler::ldmxcsr(as_Address(src)); | |
6435 } else { | |
6436 lea(rscratch1, src); | |
6437 Assembler::ldmxcsr(Address(rscratch1, 0)); | |
6438 } | |
6439 } | |
6440 | |
6441 int MacroAssembler::load_signed_byte(Register dst, Address src) { | |
6442 int off; | |
6443 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
6444 off = offset(); | |
6445 movsbl(dst, src); // movsxb | |
6446 } else { | |
6447 off = load_unsigned_byte(dst, src); | |
6448 shll(dst, 24); | |
6449 sarl(dst, 24); | |
6450 } | |
6451 return off; | |
6452 } | |
6453 | |
622
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6454 // Note: load_signed_short used to be called load_signed_word. |
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6455 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler |
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6456 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. |
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6457 // The term "word" in HotSpot means a 32- or 64-bit machine word. |
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6458 int MacroAssembler::load_signed_short(Register dst, Address src) { |
304 | 6459 int off; |
6460 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
6461 // This is dubious to me since it seems safe to do a signed 16 => 64 bit | |
6462 // version but this is what 64bit has always done. This seems to imply | |
6463 // that users are only using 32bits worth. | |
6464 off = offset(); | |
6465 movswl(dst, src); // movsxw | |
6466 } else { | |
622
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6467 off = load_unsigned_short(dst, src); |
304 | 6468 shll(dst, 16); |
6469 sarl(dst, 16); | |
6470 } | |
6471 return off; | |
6472 } | |
6473 | |
6474 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { | |
6475 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, | |
6476 // and "3.9 Partial Register Penalties", p. 22). | |
6477 int off; | |
6478 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { | |
6479 off = offset(); | |
6480 movzbl(dst, src); // movzxb | |
6481 } else { | |
6482 xorl(dst, dst); | |
6483 off = offset(); | |
6484 movb(dst, src); | |
6485 } | |
6486 return off; | |
6487 } | |
6488 | |
622
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6489 // Note: load_unsigned_short used to be called load_unsigned_word. |
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6490 int MacroAssembler::load_unsigned_short(Register dst, Address src) { |
304 | 6491 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, |
6492 // and "3.9 Partial Register Penalties", p. 22). | |
6493 int off; | |
6494 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { | |
6495 off = offset(); | |
6496 movzwl(dst, src); // movzxw | |
6497 } else { | |
6498 xorl(dst, dst); | |
6499 off = offset(); | |
6500 movw(dst, src); | |
6501 } | |
6502 return off; | |
6503 } | |
6504 | |
622
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6505 void MacroAssembler::load_sized_value(Register dst, Address src, |
1503 | 6506 size_t size_in_bytes, bool is_signed) { |
6507 switch (size_in_bytes) { | |
622
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6508 #ifndef _LP64 |
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6509 // For case 8, caller is responsible for manually loading |
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6510 // the second word into another register. |
1503 | 6511 case 8: movl(dst, src); break; |
622
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6512 #else |
1503 | 6513 case 8: movq(dst, src); break; |
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6514 #endif |
1503 | 6515 case 4: movl(dst, src); break; |
6516 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; | |
6517 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; | |
6518 default: ShouldNotReachHere(); | |
622
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6519 } |
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6520 } |
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6521 |
304 | 6522 void MacroAssembler::mov32(AddressLiteral dst, Register src) { |
6523 if (reachable(dst)) { | |
6524 movl(as_Address(dst), src); | |
6525 } else { | |
6526 lea(rscratch1, dst); | |
6527 movl(Address(rscratch1, 0), src); | |
6528 } | |
6529 } | |
6530 | |
6531 void MacroAssembler::mov32(Register dst, AddressLiteral src) { | |
6532 if (reachable(src)) { | |
6533 movl(dst, as_Address(src)); | |
6534 } else { | |
6535 lea(rscratch1, src); | |
6536 movl(dst, Address(rscratch1, 0)); | |
6537 } | |
0 | 6538 } |
6539 | |
6540 // C++ bool manipulation | |
6541 | |
6542 void MacroAssembler::movbool(Register dst, Address src) { | |
6543 if(sizeof(bool) == 1) | |
6544 movb(dst, src); | |
6545 else if(sizeof(bool) == 2) | |
6546 movw(dst, src); | |
6547 else if(sizeof(bool) == 4) | |
6548 movl(dst, src); | |
6549 else | |
6550 // unsupported | |
6551 ShouldNotReachHere(); | |
6552 } | |
6553 | |
6554 void MacroAssembler::movbool(Address dst, bool boolconst) { | |
6555 if(sizeof(bool) == 1) | |
6556 movb(dst, (int) boolconst); | |
6557 else if(sizeof(bool) == 2) | |
6558 movw(dst, (int) boolconst); | |
6559 else if(sizeof(bool) == 4) | |
6560 movl(dst, (int) boolconst); | |
6561 else | |
6562 // unsupported | |
6563 ShouldNotReachHere(); | |
6564 } | |
6565 | |
6566 void MacroAssembler::movbool(Address dst, Register src) { | |
6567 if(sizeof(bool) == 1) | |
6568 movb(dst, src); | |
6569 else if(sizeof(bool) == 2) | |
6570 movw(dst, src); | |
6571 else if(sizeof(bool) == 4) | |
6572 movl(dst, src); | |
6573 else | |
6574 // unsupported | |
6575 ShouldNotReachHere(); | |
6576 } | |
6577 | |
304 | 6578 void MacroAssembler::movbyte(ArrayAddress dst, int src) { |
6579 movb(as_Address(dst), src); | |
6580 } | |
6581 | |
6582 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { | |
6583 if (reachable(src)) { | |
6584 if (UseXmmLoadAndClearUpper) { | |
6585 movsd (dst, as_Address(src)); | |
6586 } else { | |
6587 movlpd(dst, as_Address(src)); | |
6588 } | |
6589 } else { | |
6590 lea(rscratch1, src); | |
6591 if (UseXmmLoadAndClearUpper) { | |
6592 movsd (dst, Address(rscratch1, 0)); | |
6593 } else { | |
6594 movlpd(dst, Address(rscratch1, 0)); | |
6595 } | |
6596 } | |
6597 } | |
6598 | |
6599 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { | |
6600 if (reachable(src)) { | |
6601 movss(dst, as_Address(src)); | |
6602 } else { | |
6603 lea(rscratch1, src); | |
6604 movss(dst, Address(rscratch1, 0)); | |
6605 } | |
6606 } | |
6607 | |
6608 void MacroAssembler::movptr(Register dst, Register src) { | |
6609 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
6610 } | |
6611 | |
6612 void MacroAssembler::movptr(Register dst, Address src) { | |
6613 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
6614 } | |
6615 | |
6616 // src should NEVER be a real pointer. Use AddressLiteral for true pointers | |
6617 void MacroAssembler::movptr(Register dst, intptr_t src) { | |
6618 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); | |
6619 } | |
6620 | |
6621 void MacroAssembler::movptr(Address dst, Register src) { | |
6622 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); | |
6623 } | |
6624 | |
6625 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { | |
6626 if (reachable(src)) { | |
6627 movss(dst, as_Address(src)); | |
6628 } else { | |
6629 lea(rscratch1, src); | |
6630 movss(dst, Address(rscratch1, 0)); | |
6631 } | |
6632 } | |
6633 | |
6634 void MacroAssembler::null_check(Register reg, int offset) { | |
6635 if (needs_explicit_null_check(offset)) { | |
6636 // provoke OS NULL exception if reg = NULL by | |
6637 // accessing M[reg] w/o changing any (non-CC) registers | |
6638 // NOTE: cmpl is plenty here to provoke a segv | |
6639 cmpptr(rax, Address(reg, 0)); | |
6640 // Note: should probably use testl(rax, Address(reg, 0)); | |
6641 // may be shorter code (however, this version of | |
6642 // testl needs to be implemented first) | |
6643 } else { | |
6644 // nothing to do, (later) access of M[reg + offset] | |
6645 // will provoke OS NULL exception if reg = NULL | |
6646 } | |
6647 } | |
6648 | |
6649 void MacroAssembler::os_breakpoint() { | |
6650 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability | |
6651 // (e.g., MSVC can't call ps() otherwise) | |
6652 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); | |
6653 } | |
6654 | |
6655 void MacroAssembler::pop_CPU_state() { | |
6656 pop_FPU_state(); | |
6657 pop_IU_state(); | |
6658 } | |
6659 | |
6660 void MacroAssembler::pop_FPU_state() { | |
6661 NOT_LP64(frstor(Address(rsp, 0));) | |
6662 LP64_ONLY(fxrstor(Address(rsp, 0));) | |
6663 addptr(rsp, FPUStateSizeInWords * wordSize); | |
6664 } | |
6665 | |
6666 void MacroAssembler::pop_IU_state() { | |
6667 popa(); | |
6668 LP64_ONLY(addq(rsp, 8)); | |
6669 popf(); | |
6670 } | |
6671 | |
6672 // Save Integer and Float state | |
6673 // Warning: Stack must be 16 byte aligned (64bit) | |
6674 void MacroAssembler::push_CPU_state() { | |
6675 push_IU_state(); | |
6676 push_FPU_state(); | |
6677 } | |
6678 | |
6679 void MacroAssembler::push_FPU_state() { | |
6680 subptr(rsp, FPUStateSizeInWords * wordSize); | |
6681 #ifndef _LP64 | |
6682 fnsave(Address(rsp, 0)); | |
6683 fwait(); | |
6684 #else | |
6685 fxsave(Address(rsp, 0)); | |
6686 #endif // LP64 | |
6687 } | |
6688 | |
6689 void MacroAssembler::push_IU_state() { | |
6690 // Push flags first because pusha kills them | |
6691 pushf(); | |
6692 // Make sure rsp stays 16-byte aligned | |
6693 LP64_ONLY(subq(rsp, 8)); | |
6694 pusha(); | |
6695 } | |
6696 | |
6697 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { | |
6698 // determine java_thread register | |
6699 if (!java_thread->is_valid()) { | |
6700 java_thread = rdi; | |
6701 get_thread(java_thread); | |
6702 } | |
6703 // we must set sp to zero to clear frame | |
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
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420
diff
changeset
|
6704 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); |
304 | 6705 if (clear_fp) { |
512
db4caa99ef11
6787106: Hotspot 32 bit build fails on platforms having different definitions for intptr_t & int32_t
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420
diff
changeset
|
6706 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); |
304 | 6707 } |
6708 | |
6709 if (clear_pc) | |
512
db4caa99ef11
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diff
changeset
|
6710 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); |
304 | 6711 |
6712 } | |
6713 | |
6714 void MacroAssembler::restore_rax(Register tmp) { | |
6715 if (tmp == noreg) pop(rax); | |
6716 else if (tmp != rax) mov(rax, tmp); | |
6717 } | |
6718 | |
6719 void MacroAssembler::round_to(Register reg, int modulus) { | |
6720 addptr(reg, modulus - 1); | |
6721 andptr(reg, -modulus); | |
6722 } | |
6723 | |
6724 void MacroAssembler::save_rax(Register tmp) { | |
6725 if (tmp == noreg) push(rax); | |
6726 else if (tmp != rax) mov(tmp, rax); | |
6727 } | |
6728 | |
6729 // Write serialization page so VM thread can do a pseudo remote membar. | |
6730 // We use the current thread pointer to calculate a thread specific | |
6731 // offset to write to within the page. This minimizes bus traffic | |
6732 // due to cache line collision. | |
6733 void MacroAssembler::serialize_memory(Register thread, Register tmp) { | |
6734 movl(tmp, thread); | |
6735 shrl(tmp, os::get_serialize_page_shift_count()); | |
6736 andl(tmp, (os::vm_page_size() - sizeof(int))); | |
6737 | |
6738 Address index(noreg, tmp, Address::times_1); | |
6739 ExternalAddress page(os::get_memory_serialize_page()); | |
6740 | |
606
19962e74284f
6811384: MacroAssembler::serialize_memory may touch next page on amd64
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parents:
520
diff
changeset
|
6741 // Size of store must match masking code above |
19962e74284f
6811384: MacroAssembler::serialize_memory may touch next page on amd64
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parents:
520
diff
changeset
|
6742 movl(as_Address(ArrayAddress(page, index)), tmp); |
304 | 6743 } |
6744 | |
6745 // Calls to C land | |
6746 // | |
6747 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded | |
6748 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp | |
6749 // has to be reset to 0. This is required to allow proper stack traversal. | |
6750 void MacroAssembler::set_last_Java_frame(Register java_thread, | |
6751 Register last_java_sp, | |
6752 Register last_java_fp, | |
6753 address last_java_pc) { | |
6754 // determine java_thread register | |
6755 if (!java_thread->is_valid()) { | |
6756 java_thread = rdi; | |
6757 get_thread(java_thread); | |
6758 } | |
6759 // determine last_java_sp register | |
6760 if (!last_java_sp->is_valid()) { | |
6761 last_java_sp = rsp; | |
6762 } | |
6763 | |
6764 // last_java_fp is optional | |
6765 | |
6766 if (last_java_fp->is_valid()) { | |
6767 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); | |
6768 } | |
6769 | |
6770 // last_java_pc is optional | |
6771 | |
6772 if (last_java_pc != NULL) { | |
6773 lea(Address(java_thread, | |
6774 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), | |
6775 InternalAddress(last_java_pc)); | |
6776 | |
6777 } | |
6778 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); | |
6779 } | |
6780 | |
6781 void MacroAssembler::shlptr(Register dst, int imm8) { | |
6782 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); | |
6783 } | |
6784 | |
6785 void MacroAssembler::shrptr(Register dst, int imm8) { | |
6786 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); | |
6787 } | |
6788 | |
6789 void MacroAssembler::sign_extend_byte(Register reg) { | |
6790 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { | |
6791 movsbl(reg, reg); // movsxb | |
6792 } else { | |
6793 shll(reg, 24); | |
6794 sarl(reg, 24); | |
6795 } | |
6796 } | |
6797 | |
6798 void MacroAssembler::sign_extend_short(Register reg) { | |
6799 if (LP64_ONLY(true ||) VM_Version::is_P6()) { | |
6800 movswl(reg, reg); // movsxw | |
6801 } else { | |
6802 shll(reg, 16); | |
6803 sarl(reg, 16); | |
6804 } | |
6805 } | |
6806 | |
362 | 6807 ////////////////////////////////////////////////////////////////////////////////// |
6808 #ifndef SERIALGC | |
6809 | |
6810 void MacroAssembler::g1_write_barrier_pre(Register obj, | |
6811 #ifndef _LP64 | |
6812 Register thread, | |
6813 #endif | |
6814 Register tmp, | |
6815 Register tmp2, | |
6816 bool tosca_live) { | |
6817 LP64_ONLY(Register thread = r15_thread;) | |
6818 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
6819 PtrQueue::byte_offset_of_active())); | |
6820 | |
6821 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
6822 PtrQueue::byte_offset_of_index())); | |
6823 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + | |
6824 PtrQueue::byte_offset_of_buf())); | |
6825 | |
6826 | |
6827 Label done; | |
6828 Label runtime; | |
6829 | |
6830 // if (!marking_in_progress) goto done; | |
6831 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { | |
6832 cmpl(in_progress, 0); | |
6833 } else { | |
6834 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption"); | |
6835 cmpb(in_progress, 0); | |
6836 } | |
6837 jcc(Assembler::equal, done); | |
6838 | |
6839 // if (x.f == NULL) goto done; | |
845
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6840 #ifdef _LP64 |
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
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parents:
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diff
changeset
|
6841 load_heap_oop(tmp2, Address(obj, 0)); |
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6842 #else |
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6843 movptr(tmp2, Address(obj, 0)); |
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6844 #endif |
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
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parents:
775
diff
changeset
|
6845 cmpptr(tmp2, (int32_t) NULL_WORD); |
362 | 6846 jcc(Assembler::equal, done); |
6847 | |
6848 // Can we store original value in the thread's buffer? | |
6849 | |
6850 #ifdef _LP64 | |
845
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6851 movslq(tmp, index); |
362 | 6852 cmpq(tmp, 0); |
6853 #else | |
6854 cmpl(index, 0); | |
6855 #endif | |
6856 jcc(Assembler::equal, runtime); | |
6857 #ifdef _LP64 | |
6858 subq(tmp, wordSize); | |
6859 movl(index, tmp); | |
6860 addq(tmp, buffer); | |
6861 #else | |
6862 subl(index, wordSize); | |
6863 movl(tmp, buffer); | |
6864 addl(tmp, index); | |
6865 #endif | |
6866 movptr(Address(tmp, 0), tmp2); | |
6867 jmp(done); | |
6868 bind(runtime); | |
6869 // save the live input values | |
6870 if(tosca_live) push(rax); | |
6871 push(obj); | |
6872 #ifdef _LP64 | |
845
df6caf649ff7
6700789: G1: Enable use of compressed oops with G1 heaps
ysr
parents:
775
diff
changeset
|
6873 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, r15_thread); |
362 | 6874 #else |
6875 push(thread); | |
6876 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), tmp2, thread); | |
6877 pop(thread); | |
6878 #endif | |
6879 pop(obj); | |
6880 if(tosca_live) pop(rax); | |
6881 bind(done); | |
6882 | |
6883 } | |
6884 | |
6885 void MacroAssembler::g1_write_barrier_post(Register store_addr, | |
6886 Register new_val, | |
6887 #ifndef _LP64 | |
6888 Register thread, | |
6889 #endif | |
6890 Register tmp, | |
6891 Register tmp2) { | |
6892 | |
6893 LP64_ONLY(Register thread = r15_thread;) | |
6894 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
6895 PtrQueue::byte_offset_of_index())); | |
6896 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + | |
6897 PtrQueue::byte_offset_of_buf())); | |
6898 BarrierSet* bs = Universe::heap()->barrier_set(); | |
6899 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
6900 Label done; | |
6901 Label runtime; | |
6902 | |
6903 // Does store cross heap regions? | |
6904 | |
6905 movptr(tmp, store_addr); | |
6906 xorptr(tmp, new_val); | |
6907 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); | |
6908 jcc(Assembler::equal, done); | |
6909 | |
6910 // crosses regions, storing NULL? | |
6911 | |
6912 cmpptr(new_val, (int32_t) NULL_WORD); | |
6913 jcc(Assembler::equal, done); | |
6914 | |
6915 // storing region crossing non-NULL, is card already dirty? | |
6916 | |
6917 ExternalAddress cardtable((address) ct->byte_map_base); | |
6918 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
6919 #ifdef _LP64 | |
6920 const Register card_addr = tmp; | |
6921 | |
6922 movq(card_addr, store_addr); | |
6923 shrq(card_addr, CardTableModRefBS::card_shift); | |
6924 | |
6925 lea(tmp2, cardtable); | |
6926 | |
6927 // get the address of the card | |
6928 addq(card_addr, tmp2); | |
6929 #else | |
6930 const Register card_index = tmp; | |
6931 | |
6932 movl(card_index, store_addr); | |
6933 shrl(card_index, CardTableModRefBS::card_shift); | |
6934 | |
6935 Address index(noreg, card_index, Address::times_1); | |
6936 const Register card_addr = tmp; | |
6937 lea(card_addr, as_Address(ArrayAddress(cardtable, index))); | |
6938 #endif | |
6939 cmpb(Address(card_addr, 0), 0); | |
6940 jcc(Assembler::equal, done); | |
6941 | |
6942 // storing a region crossing, non-NULL oop, card is clean. | |
6943 // dirty card and log. | |
6944 | |
6945 movb(Address(card_addr, 0), 0); | |
6946 | |
6947 cmpl(queue_index, 0); | |
6948 jcc(Assembler::equal, runtime); | |
6949 subl(queue_index, wordSize); | |
6950 movptr(tmp2, buffer); | |
6951 #ifdef _LP64 | |
6952 movslq(rscratch1, queue_index); | |
6953 addq(tmp2, rscratch1); | |
6954 movq(Address(tmp2, 0), card_addr); | |
6955 #else | |
6956 addl(tmp2, queue_index); | |
6957 movl(Address(tmp2, 0), card_index); | |
6958 #endif | |
6959 jmp(done); | |
6960 | |
6961 bind(runtime); | |
6962 // save the live input values | |
6963 push(store_addr); | |
6964 push(new_val); | |
6965 #ifdef _LP64 | |
6966 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); | |
6967 #else | |
6968 push(thread); | |
6969 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); | |
6970 pop(thread); | |
6971 #endif | |
6972 pop(new_val); | |
6973 pop(store_addr); | |
6974 | |
6975 bind(done); | |
6976 | |
6977 } | |
6978 | |
6979 #endif // SERIALGC | |
6980 ////////////////////////////////////////////////////////////////////////////////// | |
6981 | |
6982 | |
304 | 6983 void MacroAssembler::store_check(Register obj) { |
6984 // Does a store check for the oop in register obj. The content of | |
6985 // register obj is destroyed afterwards. | |
6986 store_check_part_1(obj); | |
6987 store_check_part_2(obj); | |
6988 } | |
6989 | |
6990 void MacroAssembler::store_check(Register obj, Address dst) { | |
6991 store_check(obj); | |
6992 } | |
6993 | |
6994 | |
6995 // split the store check operation so that other instructions can be scheduled inbetween | |
6996 void MacroAssembler::store_check_part_1(Register obj) { | |
6997 BarrierSet* bs = Universe::heap()->barrier_set(); | |
6998 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
6999 shrptr(obj, CardTableModRefBS::card_shift); | |
7000 } | |
7001 | |
7002 void MacroAssembler::store_check_part_2(Register obj) { | |
7003 BarrierSet* bs = Universe::heap()->barrier_set(); | |
7004 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); | |
7005 CardTableModRefBS* ct = (CardTableModRefBS*)bs; | |
7006 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); | |
7007 | |
7008 // The calculation for byte_map_base is as follows: | |
7009 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); | |
7010 // So this essentially converts an address to a displacement and | |
7011 // it will never need to be relocated. On 64bit however the value may be too | |
7012 // large for a 32bit displacement | |
7013 | |
7014 intptr_t disp = (intptr_t) ct->byte_map_base; | |
7015 if (is_simm32(disp)) { | |
7016 Address cardtable(noreg, obj, Address::times_1, disp); | |
7017 movb(cardtable, 0); | |
7018 } else { | |
7019 // By doing it as an ExternalAddress disp could be converted to a rip-relative | |
7020 // displacement and done in a single instruction given favorable mapping and | |
7021 // a smarter version of as_Address. Worst case it is two instructions which | |
7022 // is no worse off then loading disp into a register and doing as a simple | |
7023 // Address() as above. | |
7024 // We can't do as ExternalAddress as the only style since if disp == 0 we'll | |
7025 // assert since NULL isn't acceptable in a reloci (see 6644928). In any case | |
7026 // in some cases we'll get a single instruction version. | |
7027 | |
7028 ExternalAddress cardtable((address)disp); | |
7029 Address index(noreg, obj, Address::times_1); | |
7030 movb(as_Address(ArrayAddress(cardtable, index)), 0); | |
7031 } | |
7032 } | |
7033 | |
7034 void MacroAssembler::subptr(Register dst, int32_t imm32) { | |
7035 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); | |
7036 } | |
7037 | |
7038 void MacroAssembler::subptr(Register dst, Register src) { | |
7039 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); | |
7040 } | |
7041 | |
7042 void MacroAssembler::test32(Register src1, AddressLiteral src2) { | |
7043 // src2 must be rval | |
7044 | |
7045 if (reachable(src2)) { | |
7046 testl(src1, as_Address(src2)); | |
7047 } else { | |
7048 lea(rscratch1, src2); | |
7049 testl(src1, Address(rscratch1, 0)); | |
7050 } | |
7051 } | |
7052 | |
7053 // C++ bool manipulation | |
0 | 7054 void MacroAssembler::testbool(Register dst) { |
7055 if(sizeof(bool) == 1) | |
304 | 7056 testb(dst, 0xff); |
0 | 7057 else if(sizeof(bool) == 2) { |
7058 // testw implementation needed for two byte bools | |
7059 ShouldNotReachHere(); | |
7060 } else if(sizeof(bool) == 4) | |
7061 testl(dst, dst); | |
7062 else | |
7063 // unsupported | |
7064 ShouldNotReachHere(); | |
7065 } | |
7066 | |
304 | 7067 void MacroAssembler::testptr(Register dst, Register src) { |
7068 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); | |
7069 } | |
7070 | |
7071 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. | |
7072 void MacroAssembler::tlab_allocate(Register obj, | |
7073 Register var_size_in_bytes, | |
7074 int con_size_in_bytes, | |
7075 Register t1, | |
7076 Register t2, | |
7077 Label& slow_case) { | |
7078 assert_different_registers(obj, t1, t2); | |
7079 assert_different_registers(obj, var_size_in_bytes, t1); | |
7080 Register end = t2; | |
7081 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); | |
7082 | |
7083 verify_tlab(); | |
7084 | |
7085 NOT_LP64(get_thread(thread)); | |
7086 | |
7087 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); | |
7088 if (var_size_in_bytes == noreg) { | |
7089 lea(end, Address(obj, con_size_in_bytes)); | |
7090 } else { | |
7091 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); | |
7092 } | |
7093 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); | |
7094 jcc(Assembler::above, slow_case); | |
7095 | |
7096 // update the tlab top pointer | |
7097 movptr(Address(thread, JavaThread::tlab_top_offset()), end); | |
7098 | |
7099 // recover var_size_in_bytes if necessary | |
7100 if (var_size_in_bytes == end) { | |
7101 subptr(var_size_in_bytes, obj); | |
7102 } | |
7103 verify_tlab(); | |
7104 } | |
7105 | |
7106 // Preserves rbx, and rdx. | |
7107 void MacroAssembler::tlab_refill(Label& retry, | |
7108 Label& try_eden, | |
7109 Label& slow_case) { | |
7110 Register top = rax; | |
7111 Register t1 = rcx; | |
7112 Register t2 = rsi; | |
7113 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); | |
7114 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); | |
7115 Label do_refill, discard_tlab; | |
7116 | |
7117 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
7118 // No allocation in the shared eden. | |
7119 jmp(slow_case); | |
7120 } | |
7121 | |
7122 NOT_LP64(get_thread(thread_reg)); | |
7123 | |
7124 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
7125 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
7126 | |
7127 // calculate amount of free space | |
7128 subptr(t1, top); | |
7129 shrptr(t1, LogHeapWordSize); | |
7130 | |
7131 // Retain tlab and allocate object in shared space if | |
7132 // the amount free in the tlab is too large to discard. | |
7133 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); | |
7134 jcc(Assembler::lessEqual, discard_tlab); | |
7135 | |
7136 // Retain | |
7137 // %%% yuck as movptr... | |
7138 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); | |
7139 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); | |
7140 if (TLABStats) { | |
7141 // increment number of slow_allocations | |
7142 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); | |
7143 } | |
7144 jmp(try_eden); | |
7145 | |
7146 bind(discard_tlab); | |
7147 if (TLABStats) { | |
7148 // increment number of refills | |
7149 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); | |
7150 // accumulate wastage -- t1 is amount free in tlab | |
7151 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); | |
7152 } | |
7153 | |
7154 // if tlab is currently allocated (top or end != null) then | |
7155 // fill [top, end + alignment_reserve) with array object | |
7156 testptr (top, top); | |
7157 jcc(Assembler::zero, do_refill); | |
7158 | |
7159 // set up the mark word | |
7160 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); | |
7161 // set the length to the remaining space | |
7162 subptr(t1, typeArrayOopDesc::header_size(T_INT)); | |
7163 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); | |
7164 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); | |
1690 | 7165 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); |
304 | 7166 // set klass to intArrayKlass |
7167 // dubious reloc why not an oop reloc? | |
7168 movptr(t1, ExternalAddress((address) Universe::intArrayKlassObj_addr())); | |
7169 // store klass last. concurrent gcs assumes klass length is valid if | |
7170 // klass field is not null. | |
7171 store_klass(top, t1); | |
7172 | |
7173 // refill the tlab with an eden allocation | |
7174 bind(do_refill); | |
7175 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
7176 shlptr(t1, LogHeapWordSize); | |
7177 // add object_size ?? | |
7178 eden_allocate(top, t1, 0, t2, slow_case); | |
7179 | |
7180 // Check that t1 was preserved in eden_allocate. | |
7181 #ifdef ASSERT | |
7182 if (UseTLAB) { | |
7183 Label ok; | |
7184 Register tsize = rsi; | |
7185 assert_different_registers(tsize, thread_reg, t1); | |
7186 push(tsize); | |
7187 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); | |
7188 shlptr(tsize, LogHeapWordSize); | |
7189 cmpptr(t1, tsize); | |
7190 jcc(Assembler::equal, ok); | |
7191 stop("assert(t1 != tlab size)"); | |
7192 should_not_reach_here(); | |
7193 | |
7194 bind(ok); | |
7195 pop(tsize); | |
7196 } | |
7197 #endif | |
7198 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); | |
7199 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); | |
7200 addptr(top, t1); | |
7201 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); | |
7202 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); | |
7203 verify_tlab(); | |
7204 jmp(retry); | |
7205 } | |
7206 | |
7207 static const double pi_4 = 0.7853981633974483; | |
7208 | |
7209 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { | |
7210 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) | |
7211 // was attempted in this code; unfortunately it appears that the | |
7212 // switch to 80-bit precision and back causes this to be | |
7213 // unprofitable compared with simply performing a runtime call if | |
7214 // the argument is out of the (-pi/4, pi/4) range. | |
7215 | |
7216 Register tmp = noreg; | |
7217 if (!VM_Version::supports_cmov()) { | |
7218 // fcmp needs a temporary so preserve rbx, | |
7219 tmp = rbx; | |
7220 push(tmp); | |
7221 } | |
7222 | |
7223 Label slow_case, done; | |
7224 | |
520
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6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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|
7225 ExternalAddress pi4_adr = (address)&pi_4; |
52a431267315
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|
7226 if (reachable(pi4_adr)) { |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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|
7227 // x ?<= pi/4 |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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|
7228 fld_d(pi4_adr); |
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6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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|
7229 fld_s(1); // Stack: X PI/4 X |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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|
7230 fabs(); // Stack: |X| PI/4 X |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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diff
changeset
|
7231 fcmp(tmp); |
52a431267315
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|
7232 jcc(Assembler::above, slow_case); |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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diff
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|
7233 |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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|
7234 // fastest case: -pi/4 <= x <= pi/4 |
52a431267315
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|
7235 switch(trig) { |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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|
7236 case 's': |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
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diff
changeset
|
7237 fsin(); |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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|
7238 break; |
52a431267315
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diff
changeset
|
7239 case 'c': |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
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diff
changeset
|
7240 fcos(); |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
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diff
changeset
|
7241 break; |
52a431267315
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diff
changeset
|
7242 case 't': |
52a431267315
6791168: Fix invalid code in bytecodeInterpreter that can cause gcc ICE
coleenp
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diff
changeset
|
7243 ftan(); |
52a431267315
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changeset
|
7244 break; |
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diff
changeset
|
7245 default: |
52a431267315
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diff
changeset
|
7246 assert(false, "bad intrinsic"); |
52a431267315
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diff
changeset
|
7247 break; |
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diff
changeset
|
7248 } |
52a431267315
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diff
changeset
|
7249 jmp(done); |
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|
7250 } |
304 | 7251 |
7252 // slow case: runtime call | |
7253 bind(slow_case); | |
7254 // Preserve registers across runtime call | |
7255 pusha(); | |
7256 int incoming_argument_and_return_value_offset = -1; | |
7257 if (num_fpu_regs_in_use > 1) { | |
7258 // Must preserve all other FPU regs (could alternatively convert | |
7259 // SharedRuntime::dsin and dcos into assembly routines known not to trash | |
7260 // FPU state, but can not trust C compiler) | |
7261 NEEDS_CLEANUP; | |
7262 // NOTE that in this case we also push the incoming argument to | |
7263 // the stack and restore it later; we also use this stack slot to | |
7264 // hold the return value from dsin or dcos. | |
7265 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
7266 subptr(rsp, sizeof(jdouble)); | |
7267 fstp_d(Address(rsp, 0)); | |
7268 } | |
7269 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); | |
7270 fld_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
7271 } | |
7272 subptr(rsp, sizeof(jdouble)); | |
7273 fstp_d(Address(rsp, 0)); | |
7274 #ifdef _LP64 | |
7275 movdbl(xmm0, Address(rsp, 0)); | |
7276 #endif // _LP64 | |
7277 | |
7278 // NOTE: we must not use call_VM_leaf here because that requires a | |
7279 // complete interpreter frame in debug mode -- same bug as 4387334 | |
7280 // MacroAssembler::call_VM_leaf_base is perfectly safe and will | |
7281 // do proper 64bit abi | |
7282 | |
7283 NEEDS_CLEANUP; | |
7284 // Need to add stack banging before this runtime call if it needs to | |
7285 // be taken; however, there is no generic stack banging routine at | |
7286 // the MacroAssembler level | |
7287 switch(trig) { | |
7288 case 's': | |
7289 { | |
7290 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 0); | |
7291 } | |
7292 break; | |
7293 case 'c': | |
7294 { | |
7295 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 0); | |
7296 } | |
7297 break; | |
7298 case 't': | |
7299 { | |
7300 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 0); | |
7301 } | |
7302 break; | |
7303 default: | |
7304 assert(false, "bad intrinsic"); | |
7305 break; | |
7306 } | |
7307 #ifdef _LP64 | |
7308 movsd(Address(rsp, 0), xmm0); | |
7309 fld_d(Address(rsp, 0)); | |
7310 #endif // _LP64 | |
7311 addptr(rsp, sizeof(jdouble)); | |
7312 if (num_fpu_regs_in_use > 1) { | |
7313 // Must save return value to stack and then restore entire FPU stack | |
7314 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); | |
7315 for (int i = 0; i < num_fpu_regs_in_use; i++) { | |
7316 fld_d(Address(rsp, 0)); | |
7317 addptr(rsp, sizeof(jdouble)); | |
7318 } | |
7319 } | |
7320 popa(); | |
7321 | |
7322 // Come here with result in F-TOS | |
7323 bind(done); | |
7324 | |
7325 if (tmp != noreg) { | |
7326 pop(tmp); | |
7327 } | |
7328 } | |
7329 | |
7330 | |
623
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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|
7331 // Look up the method for a megamorphic invokeinterface call. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7332 // The target method is determined by <intf_klass, itable_index>. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7333 // The receiver klass is in recv_klass. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7334 // On success, the result will be in method_result, and execution falls through. |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7335 // On failure, execution transfers to the given label. |
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|
7336 void MacroAssembler::lookup_interface_method(Register recv_klass, |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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|
7337 Register intf_klass, |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
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647
diff
changeset
|
7338 RegisterOrConstant itable_index, |
623
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7339 Register method_result, |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7340 Register scan_temp, |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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diff
changeset
|
7341 Label& L_no_such_interface) { |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7342 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7343 assert(itable_index.is_constant() || itable_index.as_register() == method_result, |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7344 "caller must use same register for non-constant itable index as for method"); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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changeset
|
7345 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7346 // Compute start of first itableOffsetEntry (which is at the end of the vtable) |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7347 int vtable_base = instanceKlass::vtable_start_offset() * wordSize; |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7348 int itentry_off = itableMethodEntry::method_offset_in_bytes(); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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|
7349 int scan_step = itableOffsetEntry::size() * wordSize; |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7350 int vte_size = vtableEntry::size() * wordSize; |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7351 Address::ScaleFactor times_vte_scale = Address::times_ptr; |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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|
7352 assert(vte_size == wordSize, "else adjust times_vte_scale"); |
9adddb8c0fc8
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|
7353 |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7354 movl(scan_temp, Address(recv_klass, instanceKlass::vtable_length_offset() * wordSize)); |
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6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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|
7355 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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changeset
|
7356 // %%% Could store the aligned, prescaled offset in the klassoop. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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diff
changeset
|
7357 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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changeset
|
7358 if (HeapWordsPerLong > 1) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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diff
changeset
|
7359 // Round up to align_object_offset boundary |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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diff
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|
7360 // see code for instanceKlass::start_of_itable! |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
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changeset
|
7361 round_to(scan_temp, BytesPerLong); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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diff
changeset
|
7362 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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diff
changeset
|
7363 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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diff
changeset
|
7364 // Adjust recv_klass by scaled itable_index, so we can free itable_index. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
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diff
changeset
|
7365 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
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changeset
|
7366 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); |
9adddb8c0fc8
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changeset
|
7367 |
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622
diff
changeset
|
7368 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7369 // if (scan->interface() == intf) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7370 // result = (klass + scan->offset() + itable_index); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7371 // } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7372 // } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7373 Label search, found_method; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7374 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7375 for (int peel = 1; peel >= 0; peel--) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7376 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7377 cmpptr(intf_klass, method_result); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7378 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7379 if (peel) { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7380 jccb(Assembler::equal, found_method); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7381 } else { |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7382 jccb(Assembler::notEqual, search); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7383 // (invert the test to fall through to found_method...) |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7384 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7385 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7386 if (!peel) break; |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7387 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7388 bind(search); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7389 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7390 // Check that the previous entry is non-null. A null entry means that |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7391 // the receiver class doesn't implement the interface, and wasn't the |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7392 // same as when the caller was compiled. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7393 testptr(method_result, method_result); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7394 jcc(Assembler::zero, L_no_such_interface); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7395 addptr(scan_temp, scan_step); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7396 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7397 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7398 bind(found_method); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7399 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7400 // Got a hit. |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7401 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7402 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7403 } |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7404 |
9adddb8c0fc8
6812831: factor duplicated assembly code for megamorphic invokeinterface (for 6655638)
jrose
parents:
622
diff
changeset
|
7405 |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7406 void MacroAssembler::check_klass_subtype(Register sub_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7407 Register super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7408 Register temp_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7409 Label& L_success) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7410 Label L_failure; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7411 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7412 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7413 bind(L_failure); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7414 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7415 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7416 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7417 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7418 Register super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7419 Register temp_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7420 Label* L_success, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7421 Label* L_failure, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7422 Label* L_slow_path, |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7423 RegisterOrConstant super_check_offset) { |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7424 assert_different_registers(sub_klass, super_klass, temp_reg); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7425 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7426 if (super_check_offset.is_register()) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7427 assert_different_registers(sub_klass, super_klass, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7428 super_check_offset.as_register()); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7429 } else if (must_load_sco) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7430 assert(temp_reg != noreg, "supply either a temp or a register offset"); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7431 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7432 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7433 Label L_fallthrough; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7434 int label_nulls = 0; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7435 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7436 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7437 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7438 assert(label_nulls <= 1, "at most one NULL in the batch"); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7439 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7440 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7441 Klass::secondary_super_cache_offset_in_bytes()); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7442 int sco_offset = (klassOopDesc::header_size() * HeapWordSize + |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7443 Klass::super_check_offset_offset_in_bytes()); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7444 Address super_check_offset_addr(super_klass, sco_offset); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7445 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7446 // Hacked jcc, which "knows" that L_fallthrough, at least, is in |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7447 // range of a jccb. If this routine grows larger, reconsider at |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7448 // least some of these. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7449 #define local_jcc(assembler_cond, label) \ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7450 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7451 else jcc( assembler_cond, label) /*omit semi*/ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7452 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7453 // Hacked jmp, which may only be used just before L_fallthrough. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7454 #define final_jmp(label) \ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7455 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7456 else jmp(label) /*omit semi*/ |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7457 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7458 // If the pointers are equal, we are done (e.g., String[] elements). |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7459 // This self-check enables sharing of secondary supertype arrays among |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7460 // non-primary types such as array-of-interface. Otherwise, each such |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7461 // type would need its own customized SSA. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7462 // We move this check to the front of the fast path because many |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7463 // type checks are in fact trivially successful in this manner, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7464 // so we get a nicely predicted branch right at the start of the check. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7465 cmpptr(sub_klass, super_klass); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7466 local_jcc(Assembler::equal, *L_success); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7467 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7468 // Check the supertype display: |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7469 if (must_load_sco) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7470 // Positive movl does right thing on LP64. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7471 movl(temp_reg, super_check_offset_addr); |
665
c89f86385056
6814659: separable cleanups and subroutines for 6655638
jrose
parents:
647
diff
changeset
|
7472 super_check_offset = RegisterOrConstant(temp_reg); |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7473 } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7474 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7475 cmpptr(super_klass, super_check_addr); // load displayed supertype |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7476 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7477 // This check has worked decisively for primary supers. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7478 // Secondary supers are sought in the super_cache ('super_cache_addr'). |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7479 // (Secondary supers are interfaces and very deeply nested subtypes.) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7480 // This works in the same check above because of a tricky aliasing |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7481 // between the super_cache and the primary super display elements. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7482 // (The 'super_check_addr' can address either, as the case requires.) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7483 // Note that the cache is updated below if it does not help us find |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7484 // what we need immediately. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7485 // So if it was a primary super, we can just fail immediately. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7486 // Otherwise, it's the slow path for us (no success at this point). |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7487 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7488 if (super_check_offset.is_register()) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7489 local_jcc(Assembler::equal, *L_success); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7490 cmpl(super_check_offset.as_register(), sc_offset); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7491 if (L_failure == &L_fallthrough) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7492 local_jcc(Assembler::equal, *L_slow_path); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7493 } else { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7494 local_jcc(Assembler::notEqual, *L_failure); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7495 final_jmp(*L_slow_path); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7496 } |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7497 } else if (super_check_offset.as_constant() == sc_offset) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7498 // Need a slow path; fast failure is impossible. |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7499 if (L_slow_path == &L_fallthrough) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7500 local_jcc(Assembler::equal, *L_success); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7501 } else { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7502 local_jcc(Assembler::notEqual, *L_slow_path); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7503 final_jmp(*L_success); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7504 } |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7505 } else { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7506 // No slow path; it's a fast decision. |
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diff
changeset
|
7507 if (L_failure == &L_fallthrough) { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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diff
changeset
|
7508 local_jcc(Assembler::equal, *L_success); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7509 } else { |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7510 local_jcc(Assembler::notEqual, *L_failure); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7511 final_jmp(*L_success); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7512 } |
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643
diff
changeset
|
7513 } |
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643
diff
changeset
|
7514 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7515 bind(L_fallthrough); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7516 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7517 #undef local_jcc |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7518 #undef final_jmp |
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parents:
643
diff
changeset
|
7519 } |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7520 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7521 |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7522 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7523 Register super_klass, |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7524 Register temp_reg, |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7525 Register temp2_reg, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7526 Label* L_success, |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7527 Label* L_failure, |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7528 bool set_cond_codes) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7529 assert_different_registers(sub_klass, super_klass, temp_reg); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7530 if (temp2_reg != noreg) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7531 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7532 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7533 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7534 Label L_fallthrough; |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7535 int label_nulls = 0; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7536 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7537 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7538 assert(label_nulls <= 1, "at most one NULL in the batch"); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7539 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7540 // a couple of useful fields in sub_klass: |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7541 int ss_offset = (klassOopDesc::header_size() * HeapWordSize + |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7542 Klass::secondary_supers_offset_in_bytes()); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7543 int sc_offset = (klassOopDesc::header_size() * HeapWordSize + |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7544 Klass::secondary_super_cache_offset_in_bytes()); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7545 Address secondary_supers_addr(sub_klass, ss_offset); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7546 Address super_cache_addr( sub_klass, sc_offset); |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7547 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7548 // Do a linear scan of the secondary super-klass chain. |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7549 // This code is rarely used, so simplicity is a virtue here. |
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parents:
643
diff
changeset
|
7550 // The repne_scan instruction uses fixed registers, which we must spill. |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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643
diff
changeset
|
7551 // Don't worry too much about pre-existing connections with the input regs. |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7552 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7553 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7554 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) |
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parents:
643
diff
changeset
|
7555 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7556 // Get super_klass value into rax (even if it was in rdi or rcx). |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7557 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7558 if (super_klass != rax || UseCompressedOops) { |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7559 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7560 mov(rax, super_klass); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7561 } |
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6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7562 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7563 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7564 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7565 #ifndef PRODUCT |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7566 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7567 ExternalAddress pst_counter_addr((address) pst_counter); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7568 NOT_LP64( incrementl(pst_counter_addr) ); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7569 LP64_ONLY( lea(rcx, pst_counter_addr) ); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7570 LP64_ONLY( incrementl(Address(rcx, 0)) ); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7571 #endif //PRODUCT |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7572 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7573 // We will consult the secondary-super array. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7574 movptr(rdi, secondary_supers_addr); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7575 // Load the array length. (Positive movl does right thing on LP64.) |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7576 movl(rcx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7577 // Skip to start of data. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7578 addptr(rdi, arrayOopDesc::base_offset_in_bytes(T_OBJECT)); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7579 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7580 // Scan RCX words at [RDI] for an occurrence of RAX. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7581 // Set NZ/Z based on last compare. |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7582 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7583 // not change flags (only scas instruction which is repeated sets flags). |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7584 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7585 #ifdef _LP64 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7586 // This part is tricky, as values in supers array could be 32 or 64 bit wide |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7587 // and we store values in objArrays always encoded, thus we need to encode |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7588 // the value of rax before repne. Note that rax is dead after the repne. |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7589 if (UseCompressedOops) { |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7590 encode_heap_oop_not_null(rax); // Changes flags. |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7591 // The superclass is never null; it would be a basic system error if a null |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7592 // pointer were to sneak in here. Note that we have already loaded the |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7593 // Klass::super_check_offset from the super_klass in the fast path, |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7594 // so if there is a null in that register, we are already in the afterlife. |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7595 testl(rax,rax); // Set Z = 0 |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7596 repne_scanl(); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7597 } else |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7598 #endif // _LP64 |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7599 { |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7600 testptr(rax,rax); // Set Z = 0 |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
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643
diff
changeset
|
7601 repne_scan(); |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
7602 } |
644
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7603 // Unspill the temp. registers: |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7604 if (pushed_rdi) pop(rdi); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7605 if (pushed_rcx) pop(rcx); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7606 if (pushed_rax) pop(rax); |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
jrose
parents:
643
diff
changeset
|
7607 |
c517646eef23
6813212: factor duplicated assembly code for general subclass check (for 6655638)
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parents:
643
diff
changeset
|
7608 if (set_cond_codes) { |
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7609 // Special hack for the AD files: rdi is guaranteed non-zero. |
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7610 assert(!pushed_rdi, "rdi must be left non-NULL"); |
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7611 // Also, the condition codes are properly set Z/NZ on succeed/failure. |
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7612 } |
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|
7613 |
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|
7614 if (L_failure == &L_fallthrough) |
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7615 jccb(Assembler::notEqual, *L_failure); |
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7616 else jcc(Assembler::notEqual, *L_failure); |
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7617 |
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7618 // Success. Cache the super we found and proceed in triumph. |
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7619 movptr(super_cache_addr, super_klass); |
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7620 |
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7621 if (L_success != &L_fallthrough) { |
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7622 jmp(*L_success); |
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|
7623 } |
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7624 |
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|
7625 #undef IS_A_TEMP |
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7626 |
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7627 bind(L_fallthrough); |
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|
7628 } |
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7629 |
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7630 |
304 | 7631 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { |
7632 ucomisd(dst, as_Address(src)); | |
7633 } | |
7634 | |
7635 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { | |
7636 ucomiss(dst, as_Address(src)); | |
7637 } | |
7638 | |
7639 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { | |
7640 if (reachable(src)) { | |
7641 xorpd(dst, as_Address(src)); | |
7642 } else { | |
7643 lea(rscratch1, src); | |
7644 xorpd(dst, Address(rscratch1, 0)); | |
7645 } | |
7646 } | |
7647 | |
7648 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { | |
7649 if (reachable(src)) { | |
7650 xorps(dst, as_Address(src)); | |
7651 } else { | |
7652 lea(rscratch1, src); | |
7653 xorps(dst, Address(rscratch1, 0)); | |
7654 } | |
7655 } | |
7656 | |
0 | 7657 void MacroAssembler::verify_oop(Register reg, const char* s) { |
7658 if (!VerifyOops) return; | |
304 | 7659 |
0 | 7660 // Pass register number to verify_oop_subroutine |
7661 char* b = new char[strlen(s) + 50]; | |
7662 sprintf(b, "verify_oop: %s: %s", reg->name(), s); | |
1583 | 7663 #ifdef _LP64 |
7664 push(rscratch1); // save r10, trashed by movptr() | |
7665 #endif | |
304 | 7666 push(rax); // save rax, |
7667 push(reg); // pass register argument | |
0 | 7668 ExternalAddress buffer((address) b); |
304 | 7669 // avoid using pushptr, as it modifies scratch registers |
7670 // and our contract is not to modify anything | |
7671 movptr(rax, buffer.addr()); | |
7672 push(rax); | |
0 | 7673 // call indirectly to solve generation ordering problem |
7674 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
7675 call(rax); | |
1583 | 7676 // Caller pops the arguments (oop, message) and restores rax, r10 |
0 | 7677 } |
7678 | |
7679 | |
665
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7680 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, |
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7681 Register tmp, |
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7682 int offset) { |
622
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7683 intptr_t value = *delayed_value_addr; |
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7684 if (value != 0) |
665
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7685 return RegisterOrConstant(value + offset); |
622
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7686 |
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7687 // load indirectly to solve generation ordering problem |
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7688 movptr(tmp, ExternalAddress((address) delayed_value_addr)); |
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7689 |
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7690 #ifdef ASSERT |
1793
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7691 { Label L; |
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7692 testptr(tmp, tmp); |
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|
7693 if (WizardMode) { |
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7694 jcc(Assembler::notZero, L); |
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7695 char* buf = new char[40]; |
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|
7696 sprintf(buf, "DelayedValue="INTPTR_FORMAT, delayed_value_addr[1]); |
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7697 stop(buf); |
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|
7698 } else { |
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|
7699 jccb(Assembler::notZero, L); |
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|
7700 hlt(); |
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|
7701 } |
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|
7702 bind(L); |
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7703 } |
622
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7704 #endif |
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7705 |
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7706 if (offset != 0) |
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7707 addptr(tmp, offset); |
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7708 |
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7709 return RegisterOrConstant(tmp); |
622
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7710 } |
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7711 |
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7712 |
710 | 7713 // registers on entry: |
7714 // - rax ('check' register): required MethodType | |
7715 // - rcx: method handle | |
7716 // - rdx, rsi, or ?: killable temp | |
7717 void MacroAssembler::check_method_handle_type(Register mtype_reg, Register mh_reg, | |
7718 Register temp_reg, | |
7719 Label& wrong_method_type) { | |
1846 | 7720 Address type_addr(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg)); |
710 | 7721 // compare method type against that of the receiver |
1846 | 7722 if (UseCompressedOops) { |
7723 load_heap_oop(temp_reg, type_addr); | |
7724 cmpptr(mtype_reg, temp_reg); | |
7725 } else { | |
7726 cmpptr(mtype_reg, type_addr); | |
7727 } | |
710 | 7728 jcc(Assembler::notEqual, wrong_method_type); |
7729 } | |
7730 | |
7731 | |
7732 // A method handle has a "vmslots" field which gives the size of its | |
7733 // argument list in JVM stack slots. This field is either located directly | |
7734 // in every method handle, or else is indirectly accessed through the | |
7735 // method handle's MethodType. This macro hides the distinction. | |
7736 void MacroAssembler::load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, | |
7737 Register temp_reg) { | |
1503 | 7738 assert_different_registers(vmslots_reg, mh_reg, temp_reg); |
710 | 7739 // load mh.type.form.vmslots |
7740 if (java_dyn_MethodHandle::vmslots_offset_in_bytes() != 0) { | |
7741 // hoist vmslots into every mh to avoid dependent load chain | |
7742 movl(vmslots_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmslots_offset_in_bytes, temp_reg))); | |
7743 } else { | |
7744 Register temp2_reg = vmslots_reg; | |
1846 | 7745 load_heap_oop(temp2_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::type_offset_in_bytes, temp_reg))); |
7746 load_heap_oop(temp2_reg, Address(temp2_reg, delayed_value(java_dyn_MethodType::form_offset_in_bytes, temp_reg))); | |
710 | 7747 movl(vmslots_reg, Address(temp2_reg, delayed_value(java_dyn_MethodTypeForm::vmslots_offset_in_bytes, temp_reg))); |
7748 } | |
7749 } | |
7750 | |
7751 | |
7752 // registers on entry: | |
7753 // - rcx: method handle | |
7754 // - rdx: killable temp (interpreted only) | |
7755 // - rax: killable temp (compiled only) | |
7756 void MacroAssembler::jump_to_method_handle_entry(Register mh_reg, Register temp_reg) { | |
7757 assert(mh_reg == rcx, "caller must put MH object in rcx"); | |
7758 assert_different_registers(mh_reg, temp_reg); | |
7759 | |
7760 // pick out the interpreted side of the handler | |
1846 | 7761 // NOTE: vmentry is not an oop! |
710 | 7762 movptr(temp_reg, Address(mh_reg, delayed_value(java_dyn_MethodHandle::vmentry_offset_in_bytes, temp_reg))); |
7763 | |
7764 // off we go... | |
7765 jmp(Address(temp_reg, MethodHandleEntry::from_interpreted_entry_offset_in_bytes())); | |
7766 | |
7767 // for the various stubs which take control at this point, | |
7768 // see MethodHandles::generate_method_handle_stub | |
7769 } | |
7770 | |
7771 | |
7772 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, | |
7773 int extra_slot_offset) { | |
7774 // cf. TemplateTable::prepare_invoke(), if (load_receiver). | |
1506 | 7775 int stackElementSize = Interpreter::stackElementSize; |
710 | 7776 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); |
7777 #ifdef ASSERT | |
7778 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); | |
7779 assert(offset1 - offset == stackElementSize, "correct arithmetic"); | |
7780 #endif | |
7781 Register scale_reg = noreg; | |
7782 Address::ScaleFactor scale_factor = Address::no_scale; | |
7783 if (arg_slot.is_constant()) { | |
7784 offset += arg_slot.as_constant() * stackElementSize; | |
7785 } else { | |
7786 scale_reg = arg_slot.as_register(); | |
7787 scale_factor = Address::times(stackElementSize); | |
7788 } | |
7789 offset += wordSize; // return PC is on stack | |
7790 return Address(rsp, scale_reg, scale_factor, offset); | |
7791 } | |
7792 | |
7793 | |
0 | 7794 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { |
7795 if (!VerifyOops) return; | |
304 | 7796 |
0 | 7797 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); |
7798 // Pass register number to verify_oop_subroutine | |
7799 char* b = new char[strlen(s) + 50]; | |
7800 sprintf(b, "verify_oop_addr: %s", s); | |
304 | 7801 |
1583 | 7802 #ifdef _LP64 |
7803 push(rscratch1); // save r10, trashed by movptr() | |
7804 #endif | |
304 | 7805 push(rax); // save rax, |
0 | 7806 // addr may contain rsp so we will have to adjust it based on the push |
7807 // we just did | |
304 | 7808 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which |
7809 // stores rax into addr which is backwards of what was intended. | |
0 | 7810 if (addr.uses(rsp)) { |
304 | 7811 lea(rax, addr); |
7812 pushptr(Address(rax, BytesPerWord)); | |
0 | 7813 } else { |
304 | 7814 pushptr(addr); |
7815 } | |
7816 | |
0 | 7817 ExternalAddress buffer((address) b); |
7818 // pass msg argument | |
304 | 7819 // avoid using pushptr, as it modifies scratch registers |
7820 // and our contract is not to modify anything | |
7821 movptr(rax, buffer.addr()); | |
7822 push(rax); | |
7823 | |
0 | 7824 // call indirectly to solve generation ordering problem |
7825 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); | |
7826 call(rax); | |
1583 | 7827 // Caller pops the arguments (addr, message) and restores rax, r10. |
0 | 7828 } |
7829 | |
304 | 7830 void MacroAssembler::verify_tlab() { |
7831 #ifdef ASSERT | |
7832 if (UseTLAB && VerifyOops) { | |
7833 Label next, ok; | |
7834 Register t1 = rsi; | |
7835 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); | |
7836 | |
7837 push(t1); | |
7838 NOT_LP64(push(thread_reg)); | |
7839 NOT_LP64(get_thread(thread_reg)); | |
7840 | |
7841 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
7842 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); | |
7843 jcc(Assembler::aboveEqual, next); | |
7844 stop("assert(top >= start)"); | |
7845 should_not_reach_here(); | |
7846 | |
7847 bind(next); | |
7848 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); | |
7849 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); | |
7850 jcc(Assembler::aboveEqual, ok); | |
7851 stop("assert(top <= end)"); | |
7852 should_not_reach_here(); | |
7853 | |
7854 bind(ok); | |
7855 NOT_LP64(pop(thread_reg)); | |
7856 pop(t1); | |
7857 } | |
7858 #endif | |
7859 } | |
0 | 7860 |
7861 class ControlWord { | |
7862 public: | |
7863 int32_t _value; | |
7864 | |
7865 int rounding_control() const { return (_value >> 10) & 3 ; } | |
7866 int precision_control() const { return (_value >> 8) & 3 ; } | |
7867 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
7868 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
7869 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
7870 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
7871 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
7872 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
7873 | |
7874 void print() const { | |
7875 // rounding control | |
7876 const char* rc; | |
7877 switch (rounding_control()) { | |
7878 case 0: rc = "round near"; break; | |
7879 case 1: rc = "round down"; break; | |
7880 case 2: rc = "round up "; break; | |
7881 case 3: rc = "chop "; break; | |
7882 }; | |
7883 // precision control | |
7884 const char* pc; | |
7885 switch (precision_control()) { | |
7886 case 0: pc = "24 bits "; break; | |
7887 case 1: pc = "reserved"; break; | |
7888 case 2: pc = "53 bits "; break; | |
7889 case 3: pc = "64 bits "; break; | |
7890 }; | |
7891 // flags | |
7892 char f[9]; | |
7893 f[0] = ' '; | |
7894 f[1] = ' '; | |
7895 f[2] = (precision ()) ? 'P' : 'p'; | |
7896 f[3] = (underflow ()) ? 'U' : 'u'; | |
7897 f[4] = (overflow ()) ? 'O' : 'o'; | |
7898 f[5] = (zero_divide ()) ? 'Z' : 'z'; | |
7899 f[6] = (denormalized()) ? 'D' : 'd'; | |
7900 f[7] = (invalid ()) ? 'I' : 'i'; | |
7901 f[8] = '\x0'; | |
7902 // output | |
7903 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); | |
7904 } | |
7905 | |
7906 }; | |
7907 | |
7908 class StatusWord { | |
7909 public: | |
7910 int32_t _value; | |
7911 | |
7912 bool busy() const { return ((_value >> 15) & 1) != 0; } | |
7913 bool C3() const { return ((_value >> 14) & 1) != 0; } | |
7914 bool C2() const { return ((_value >> 10) & 1) != 0; } | |
7915 bool C1() const { return ((_value >> 9) & 1) != 0; } | |
7916 bool C0() const { return ((_value >> 8) & 1) != 0; } | |
7917 int top() const { return (_value >> 11) & 7 ; } | |
7918 bool error_status() const { return ((_value >> 7) & 1) != 0; } | |
7919 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } | |
7920 bool precision() const { return ((_value >> 5) & 1) != 0; } | |
7921 bool underflow() const { return ((_value >> 4) & 1) != 0; } | |
7922 bool overflow() const { return ((_value >> 3) & 1) != 0; } | |
7923 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } | |
7924 bool denormalized() const { return ((_value >> 1) & 1) != 0; } | |
7925 bool invalid() const { return ((_value >> 0) & 1) != 0; } | |
7926 | |
7927 void print() const { | |
7928 // condition codes | |
7929 char c[5]; | |
7930 c[0] = (C3()) ? '3' : '-'; | |
7931 c[1] = (C2()) ? '2' : '-'; | |
7932 c[2] = (C1()) ? '1' : '-'; | |
7933 c[3] = (C0()) ? '0' : '-'; | |
7934 c[4] = '\x0'; | |
7935 // flags | |
7936 char f[9]; | |
7937 f[0] = (error_status()) ? 'E' : '-'; | |
7938 f[1] = (stack_fault ()) ? 'S' : '-'; | |
7939 f[2] = (precision ()) ? 'P' : '-'; | |
7940 f[3] = (underflow ()) ? 'U' : '-'; | |
7941 f[4] = (overflow ()) ? 'O' : '-'; | |
7942 f[5] = (zero_divide ()) ? 'Z' : '-'; | |
7943 f[6] = (denormalized()) ? 'D' : '-'; | |
7944 f[7] = (invalid ()) ? 'I' : '-'; | |
7945 f[8] = '\x0'; | |
7946 // output | |
7947 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); | |
7948 } | |
7949 | |
7950 }; | |
7951 | |
7952 class TagWord { | |
7953 public: | |
7954 int32_t _value; | |
7955 | |
7956 int tag_at(int i) const { return (_value >> (i*2)) & 3; } | |
7957 | |
7958 void print() const { | |
7959 printf("%04x", _value & 0xFFFF); | |
7960 } | |
7961 | |
7962 }; | |
7963 | |
7964 class FPU_Register { | |
7965 public: | |
7966 int32_t _m0; | |
7967 int32_t _m1; | |
7968 int16_t _ex; | |
7969 | |
7970 bool is_indefinite() const { | |
7971 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; | |
7972 } | |
7973 | |
7974 void print() const { | |
7975 char sign = (_ex < 0) ? '-' : '+'; | |
7976 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; | |
7977 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); | |
7978 }; | |
7979 | |
7980 }; | |
7981 | |
7982 class FPU_State { | |
7983 public: | |
7984 enum { | |
7985 register_size = 10, | |
7986 number_of_registers = 8, | |
7987 register_mask = 7 | |
7988 }; | |
7989 | |
7990 ControlWord _control_word; | |
7991 StatusWord _status_word; | |
7992 TagWord _tag_word; | |
7993 int32_t _error_offset; | |
7994 int32_t _error_selector; | |
7995 int32_t _data_offset; | |
7996 int32_t _data_selector; | |
7997 int8_t _register[register_size * number_of_registers]; | |
7998 | |
7999 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } | |
8000 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } | |
8001 | |
8002 const char* tag_as_string(int tag) const { | |
8003 switch (tag) { | |
8004 case 0: return "valid"; | |
8005 case 1: return "zero"; | |
8006 case 2: return "special"; | |
8007 case 3: return "empty"; | |
8008 } | |
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8009 ShouldNotReachHere(); |
0 | 8010 return NULL; |
8011 } | |
8012 | |
8013 void print() const { | |
8014 // print computation registers | |
8015 { int t = _status_word.top(); | |
8016 for (int i = 0; i < number_of_registers; i++) { | |
8017 int j = (i - t) & register_mask; | |
8018 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); | |
8019 st(j)->print(); | |
8020 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); | |
8021 } | |
8022 } | |
8023 printf("\n"); | |
8024 // print control registers | |
8025 printf("ctrl = "); _control_word.print(); printf("\n"); | |
8026 printf("stat = "); _status_word .print(); printf("\n"); | |
8027 printf("tags = "); _tag_word .print(); printf("\n"); | |
8028 } | |
8029 | |
8030 }; | |
8031 | |
8032 class Flag_Register { | |
8033 public: | |
8034 int32_t _value; | |
8035 | |
8036 bool overflow() const { return ((_value >> 11) & 1) != 0; } | |
8037 bool direction() const { return ((_value >> 10) & 1) != 0; } | |
8038 bool sign() const { return ((_value >> 7) & 1) != 0; } | |
8039 bool zero() const { return ((_value >> 6) & 1) != 0; } | |
8040 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } | |
8041 bool parity() const { return ((_value >> 2) & 1) != 0; } | |
8042 bool carry() const { return ((_value >> 0) & 1) != 0; } | |
8043 | |
8044 void print() const { | |
8045 // flags | |
8046 char f[8]; | |
8047 f[0] = (overflow ()) ? 'O' : '-'; | |
8048 f[1] = (direction ()) ? 'D' : '-'; | |
8049 f[2] = (sign ()) ? 'S' : '-'; | |
8050 f[3] = (zero ()) ? 'Z' : '-'; | |
8051 f[4] = (auxiliary_carry()) ? 'A' : '-'; | |
8052 f[5] = (parity ()) ? 'P' : '-'; | |
8053 f[6] = (carry ()) ? 'C' : '-'; | |
8054 f[7] = '\x0'; | |
8055 // output | |
8056 printf("%08x flags = %s", _value, f); | |
8057 } | |
8058 | |
8059 }; | |
8060 | |
8061 class IU_Register { | |
8062 public: | |
8063 int32_t _value; | |
8064 | |
8065 void print() const { | |
8066 printf("%08x %11d", _value, _value); | |
8067 } | |
8068 | |
8069 }; | |
8070 | |
8071 class IU_State { | |
8072 public: | |
8073 Flag_Register _eflags; | |
8074 IU_Register _rdi; | |
8075 IU_Register _rsi; | |
8076 IU_Register _rbp; | |
8077 IU_Register _rsp; | |
8078 IU_Register _rbx; | |
8079 IU_Register _rdx; | |
8080 IU_Register _rcx; | |
8081 IU_Register _rax; | |
8082 | |
8083 void print() const { | |
8084 // computation registers | |
8085 printf("rax, = "); _rax.print(); printf("\n"); | |
8086 printf("rbx, = "); _rbx.print(); printf("\n"); | |
8087 printf("rcx = "); _rcx.print(); printf("\n"); | |
8088 printf("rdx = "); _rdx.print(); printf("\n"); | |
8089 printf("rdi = "); _rdi.print(); printf("\n"); | |
8090 printf("rsi = "); _rsi.print(); printf("\n"); | |
8091 printf("rbp, = "); _rbp.print(); printf("\n"); | |
8092 printf("rsp = "); _rsp.print(); printf("\n"); | |
8093 printf("\n"); | |
8094 // control registers | |
8095 printf("flgs = "); _eflags.print(); printf("\n"); | |
8096 } | |
8097 }; | |
8098 | |
8099 | |
8100 class CPU_State { | |
8101 public: | |
8102 FPU_State _fpu_state; | |
8103 IU_State _iu_state; | |
8104 | |
8105 void print() const { | |
8106 printf("--------------------------------------------------\n"); | |
8107 _iu_state .print(); | |
8108 printf("\n"); | |
8109 _fpu_state.print(); | |
8110 printf("--------------------------------------------------\n"); | |
8111 } | |
8112 | |
8113 }; | |
8114 | |
8115 | |
8116 static void _print_CPU_state(CPU_State* state) { | |
8117 state->print(); | |
8118 }; | |
8119 | |
8120 | |
8121 void MacroAssembler::print_CPU_state() { | |
8122 push_CPU_state(); | |
304 | 8123 push(rsp); // pass CPU state |
0 | 8124 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); |
304 | 8125 addptr(rsp, wordSize); // discard argument |
0 | 8126 pop_CPU_state(); |
8127 } | |
8128 | |
8129 | |
8130 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { | |
8131 static int counter = 0; | |
8132 FPU_State* fs = &state->_fpu_state; | |
8133 counter++; | |
8134 // For leaf calls, only verify that the top few elements remain empty. | |
8135 // We only need 1 empty at the top for C2 code. | |
8136 if( stack_depth < 0 ) { | |
8137 if( fs->tag_for_st(7) != 3 ) { | |
8138 printf("FPR7 not empty\n"); | |
8139 state->print(); | |
8140 assert(false, "error"); | |
8141 return false; | |
8142 } | |
8143 return true; // All other stack states do not matter | |
8144 } | |
8145 | |
8146 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, | |
8147 "bad FPU control word"); | |
8148 | |
8149 // compute stack depth | |
8150 int i = 0; | |
8151 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; | |
8152 int d = i; | |
8153 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; | |
8154 // verify findings | |
8155 if (i != FPU_State::number_of_registers) { | |
8156 // stack not contiguous | |
8157 printf("%s: stack not contiguous at ST%d\n", s, i); | |
8158 state->print(); | |
8159 assert(false, "error"); | |
8160 return false; | |
8161 } | |
8162 // check if computed stack depth corresponds to expected stack depth | |
8163 if (stack_depth < 0) { | |
8164 // expected stack depth is -stack_depth or less | |
8165 if (d > -stack_depth) { | |
8166 // too many elements on the stack | |
8167 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); | |
8168 state->print(); | |
8169 assert(false, "error"); | |
8170 return false; | |
8171 } | |
8172 } else { | |
8173 // expected stack depth is stack_depth | |
8174 if (d != stack_depth) { | |
8175 // wrong stack depth | |
8176 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); | |
8177 state->print(); | |
8178 assert(false, "error"); | |
8179 return false; | |
8180 } | |
8181 } | |
8182 // everything is cool | |
8183 return true; | |
8184 } | |
8185 | |
8186 | |
8187 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
8188 if (!VerifyFPU) return; | |
8189 push_CPU_state(); | |
304 | 8190 push(rsp); // pass CPU state |
0 | 8191 ExternalAddress msg((address) s); |
8192 // pass message string s | |
8193 pushptr(msg.addr()); | |
304 | 8194 push(stack_depth); // pass stack depth |
0 | 8195 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); |
304 | 8196 addptr(rsp, 3 * wordSize); // discard arguments |
0 | 8197 // check for error |
8198 { Label L; | |
8199 testl(rax, rax); | |
8200 jcc(Assembler::notZero, L); | |
8201 int3(); // break if error condition | |
8202 bind(L); | |
8203 } | |
8204 pop_CPU_state(); | |
8205 } | |
8206 | |
304 | 8207 void MacroAssembler::load_klass(Register dst, Register src) { |
8208 #ifdef _LP64 | |
8209 if (UseCompressedOops) { | |
8210 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
8211 decode_heap_oop_not_null(dst); | |
8212 } else | |
8213 #endif | |
8214 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); | |
8215 } | |
8216 | |
8217 void MacroAssembler::load_prototype_header(Register dst, Register src) { | |
8218 #ifdef _LP64 | |
8219 if (UseCompressedOops) { | |
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8220 assert (Universe::heap() != NULL, "java heap should be initialized"); |
304 | 8221 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
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8222 if (Universe::narrow_oop_shift() != 0) { |
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8223 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
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8224 if (LogMinObjAlignmentInBytes == Address::times_8) { |
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8225 movq(dst, Address(r12_heapbase, dst, Address::times_8, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
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8226 } else { |
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8227 // OK to use shift since we don't need to preserve flags. |
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8228 shlq(dst, LogMinObjAlignmentInBytes); |
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8229 movq(dst, Address(r12_heapbase, dst, Address::times_1, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
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8230 } |
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8231 } else { |
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8232 movq(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
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8233 } |
304 | 8234 } else |
8235 #endif | |
642
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8236 { |
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8237 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); |
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8238 movptr(dst, Address(dst, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes())); |
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8239 } |
304 | 8240 } |
8241 | |
8242 void MacroAssembler::store_klass(Register dst, Register src) { | |
8243 #ifdef _LP64 | |
8244 if (UseCompressedOops) { | |
8245 encode_heap_oop_not_null(src); | |
8246 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
8247 } else | |
8248 #endif | |
8249 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); | |
8250 } | |
8251 | |
1846 | 8252 void MacroAssembler::load_heap_oop(Register dst, Address src) { |
8253 #ifdef _LP64 | |
8254 if (UseCompressedOops) { | |
8255 movl(dst, src); | |
8256 decode_heap_oop(dst); | |
8257 } else | |
8258 #endif | |
8259 movptr(dst, src); | |
8260 } | |
8261 | |
8262 void MacroAssembler::store_heap_oop(Address dst, Register src) { | |
8263 #ifdef _LP64 | |
8264 if (UseCompressedOops) { | |
8265 assert(!dst.uses(src), "not enough registers"); | |
8266 encode_heap_oop(src); | |
8267 movl(dst, src); | |
8268 } else | |
8269 #endif | |
8270 movptr(dst, src); | |
8271 } | |
8272 | |
8273 // Used for storing NULLs. | |
8274 void MacroAssembler::store_heap_oop_null(Address dst) { | |
8275 #ifdef _LP64 | |
8276 if (UseCompressedOops) { | |
8277 movl(dst, (int32_t)NULL_WORD); | |
8278 } else { | |
8279 movslq(dst, (int32_t)NULL_WORD); | |
8280 } | |
8281 #else | |
8282 movl(dst, (int32_t)NULL_WORD); | |
8283 #endif | |
8284 } | |
8285 | |
304 | 8286 #ifdef _LP64 |
8287 void MacroAssembler::store_klass_gap(Register dst, Register src) { | |
8288 if (UseCompressedOops) { | |
8289 // Store to klass gap in destination | |
8290 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); | |
8291 } | |
8292 } | |
8293 | |
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8294 #ifdef ASSERT |
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8295 void MacroAssembler::verify_heapbase(const char* msg) { |
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8296 assert (UseCompressedOops, "should be compressed"); |
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8297 assert (Universe::heap() != NULL, "java heap should be initialized"); |
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8298 if (CheckCompressedOops) { |
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8299 Label ok; |
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8300 push(rscratch1); // cmpptr trashes rscratch1 |
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|
8301 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
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8302 jcc(Assembler::equal, ok); |
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|
8303 stop(msg); |
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|
8304 bind(ok); |
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8305 pop(rscratch1); |
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|
8306 } |
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|
8307 } |
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|
8308 #endif |
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8309 |
304 | 8310 // Algorithm must match oop.inline.hpp encode_heap_oop. |
8311 void MacroAssembler::encode_heap_oop(Register r) { | |
1684
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8312 #ifdef ASSERT |
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|
8313 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); |
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|
8314 #endif |
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|
8315 verify_oop(r, "broken oop in encode_heap_oop"); |
642
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8316 if (Universe::narrow_oop_base() == NULL) { |
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8317 if (Universe::narrow_oop_shift() != 0) { |
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8318 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
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|
8319 shrq(r, LogMinObjAlignmentInBytes); |
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|
8320 } |
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|
8321 return; |
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|
8322 } |
304 | 8323 testq(r, r); |
8324 cmovq(Assembler::equal, r, r12_heapbase); | |
8325 subq(r, r12_heapbase); | |
8326 shrq(r, LogMinObjAlignmentInBytes); | |
8327 } | |
8328 | |
8329 void MacroAssembler::encode_heap_oop_not_null(Register r) { | |
0 | 8330 #ifdef ASSERT |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8331 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); |
304 | 8332 if (CheckCompressedOops) { |
0 | 8333 Label ok; |
304 | 8334 testq(r, r); |
8335 jcc(Assembler::notEqual, ok); | |
8336 stop("null oop passed to encode_heap_oop_not_null"); | |
0 | 8337 bind(ok); |
304 | 8338 } |
8339 #endif | |
8340 verify_oop(r, "broken oop in encode_heap_oop_not_null"); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8341 if (Universe::narrow_oop_base() != NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8342 subq(r, r12_heapbase); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8343 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8344 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8345 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8346 shrq(r, LogMinObjAlignmentInBytes); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8347 } |
304 | 8348 } |
8349 | |
8350 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { | |
8351 #ifdef ASSERT | |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8352 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); |
304 | 8353 if (CheckCompressedOops) { |
8354 Label ok; | |
8355 testq(src, src); | |
8356 jcc(Assembler::notEqual, ok); | |
8357 stop("null oop passed to encode_heap_oop_not_null2"); | |
8358 bind(ok); | |
0 | 8359 } |
8360 #endif | |
304 | 8361 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); |
8362 if (dst != src) { | |
8363 movq(dst, src); | |
8364 } | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8365 if (Universe::narrow_oop_base() != NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8366 subq(dst, r12_heapbase); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8367 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8368 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8369 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8370 shrq(dst, LogMinObjAlignmentInBytes); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8371 } |
304 | 8372 } |
8373 | |
8374 void MacroAssembler::decode_heap_oop(Register r) { | |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8375 #ifdef ASSERT |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8376 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8377 #endif |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8378 if (Universe::narrow_oop_base() == NULL) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8379 if (Universe::narrow_oop_shift() != 0) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8380 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8381 shlq(r, LogMinObjAlignmentInBytes); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8382 } |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8383 } else { |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8384 Label done; |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8385 shlq(r, LogMinObjAlignmentInBytes); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8386 jccb(Assembler::equal, done); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8387 addq(r, r12_heapbase); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8388 bind(done); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8389 } |
304 | 8390 verify_oop(r, "broken oop in decode_heap_oop"); |
8391 } | |
8392 | |
8393 void MacroAssembler::decode_heap_oop_not_null(Register r) { | |
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8394 // Note: it will change flags |
304 | 8395 assert (UseCompressedOops, "should only be used for compressed headers"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8396 assert (Universe::heap() != NULL, "java heap should be initialized"); |
304 | 8397 // Cannot assert, unverified entry point counts instructions (see .ad file) |
8398 // vtableStubs also counts instructions in pd_code_size_limit. | |
8399 // Also do not verify_oop as this is called by verify_oop. | |
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8400 if (Universe::narrow_oop_shift() != 0) { |
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8401 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8402 shlq(r, LogMinObjAlignmentInBytes); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8403 if (Universe::narrow_oop_base() != NULL) { |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8404 addq(r, r12_heapbase); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8405 } |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8406 } else { |
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8407 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8408 } |
304 | 8409 } |
8410 | |
8411 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { | |
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8412 // Note: it will change flags |
304 | 8413 assert (UseCompressedOops, "should only be used for compressed headers"); |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8414 assert (Universe::heap() != NULL, "java heap should be initialized"); |
304 | 8415 // Cannot assert, unverified entry point counts instructions (see .ad file) |
8416 // vtableStubs also counts instructions in pd_code_size_limit. | |
8417 // Also do not verify_oop as this is called by verify_oop. | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8418 if (Universe::narrow_oop_shift() != 0) { |
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8419 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8420 if (LogMinObjAlignmentInBytes == Address::times_8) { |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8421 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8422 } else { |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8423 if (dst != src) { |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8424 movq(dst, src); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8425 } |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8426 shlq(dst, LogMinObjAlignmentInBytes); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8427 if (Universe::narrow_oop_base() != NULL) { |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8428 addq(dst, r12_heapbase); |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8429 } |
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1513
diff
changeset
|
8430 } |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8431 } else { |
898
60fea60a6db5
6864914: SPECjvm2008 produces invalid result with zero based Compressed Oops
kvn
parents:
845
diff
changeset
|
8432 assert (Universe::narrow_oop_base() == NULL, "sanity"); |
1684
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8433 if (dst != src) { |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8434 movq(dst, src); |
66c5dadb4d61
6973308: Missing zero length check before repne scas in check_klass_subtype_slow_path()
kvn
parents:
1583
diff
changeset
|
8435 } |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8436 } |
304 | 8437 } |
8438 | |
8439 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8440 assert (UseCompressedOops, "should only be used for compressed headers"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8441 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8442 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8443 int oop_index = oop_recorder()->find_index(obj); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8444 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8445 mov_narrow_oop(dst, oop_index, rspec); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8446 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8447 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8448 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8449 assert (UseCompressedOops, "should only be used for compressed headers"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8450 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8451 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
304 | 8452 int oop_index = oop_recorder()->find_index(obj); |
8453 RelocationHolder rspec = oop_Relocation::spec(oop_index); | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8454 mov_narrow_oop(dst, oop_index, rspec); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8455 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8456 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8457 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8458 assert (UseCompressedOops, "should only be used for compressed headers"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8459 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8460 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8461 int oop_index = oop_recorder()->find_index(obj); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8462 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8463 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8464 } |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8465 |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8466 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8467 assert (UseCompressedOops, "should only be used for compressed headers"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8468 assert (Universe::heap() != NULL, "java heap should be initialized"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8469 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8470 int oop_index = oop_recorder()->find_index(obj); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8471 RelocationHolder rspec = oop_Relocation::spec(oop_index); |
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8472 Assembler::cmp_narrow_oop(dst, oop_index, rspec); |
304 | 8473 } |
8474 | |
8475 void MacroAssembler::reinit_heapbase() { | |
8476 if (UseCompressedOops) { | |
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
8477 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_oop_base_addr())); |
304 | 8478 } |
8479 } | |
8480 #endif // _LP64 | |
0 | 8481 |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8482 // IndexOf substring. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8483 void MacroAssembler::string_indexof(Register str1, Register str2, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8484 Register cnt1, Register cnt2, Register result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8485 XMMRegister vec, Register tmp) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8486 assert(UseSSE42Intrinsics, "SSE4.2 is required"); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8487 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8488 Label RELOAD_SUBSTR, PREP_FOR_SCAN, SCAN_TO_SUBSTR, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8489 SCAN_SUBSTR, RET_NOT_FOUND, CLEANUP; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8490 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8491 push(str1); // string addr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8492 push(str2); // substr addr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8493 push(cnt2); // substr count |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8494 jmpb(PREP_FOR_SCAN); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8495 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8496 // Substr count saved at sp |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8497 // Substr saved at sp+1*wordSize |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8498 // String saved at sp+2*wordSize |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8499 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8500 // Reload substr for rescan |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8501 bind(RELOAD_SUBSTR); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8502 movl(cnt2, Address(rsp, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8503 movptr(str2, Address(rsp, wordSize)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8504 // We came here after the beginninig of the substring was |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8505 // matched but the rest of it was not so we need to search |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8506 // again. Start from the next element after the previous match. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8507 subptr(str1, result); // Restore counter |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8508 shrl(str1, 1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8509 addl(cnt1, str1); |
1302
2484f4d6a54e
6935535: String.indexOf() returns incorrect result on x86 with SSE4.2
kvn
parents:
1108
diff
changeset
|
8510 decrementl(cnt1); |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8511 lea(str1, Address(result, 2)); // Reload string |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8512 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8513 // Load substr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8514 bind(PREP_FOR_SCAN); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8515 movdqu(vec, Address(str2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8516 addl(cnt1, 8); // prime the loop |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8517 subptr(str1, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8518 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8519 // Scan string for substr in 16-byte vectors |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8520 bind(SCAN_TO_SUBSTR); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8521 subl(cnt1, 8); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8522 addptr(str1, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8523 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8524 // pcmpestri |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8525 // inputs: |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8526 // xmm - substring |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8527 // rax - substring length (elements count) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8528 // mem - scaned string |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8529 // rdx - string length (elements count) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8530 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8531 // outputs: |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8532 // rcx - matched index in string |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8533 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8534 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8535 pcmpestri(vec, Address(str1, 0), 0x0d); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8536 jcc(Assembler::above, SCAN_TO_SUBSTR); // CF == 0 && ZF == 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8537 jccb(Assembler::aboveEqual, RET_NOT_FOUND); // CF == 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8538 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8539 // Fallthrough: found a potential substr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8540 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8541 // Make sure string is still long enough |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8542 subl(cnt1, tmp); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8543 cmpl(cnt1, cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8544 jccb(Assembler::negative, RET_NOT_FOUND); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8545 // Compute start addr of substr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8546 lea(str1, Address(str1, tmp, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8547 movptr(result, str1); // save |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8548 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8549 // Compare potential substr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8550 addl(cnt1, 8); // prime the loop |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8551 addl(cnt2, 8); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8552 subptr(str1, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8553 subptr(str2, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8554 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8555 // Scan 16-byte vectors of string and substr |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8556 bind(SCAN_SUBSTR); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8557 subl(cnt1, 8); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8558 subl(cnt2, 8); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8559 addptr(str1, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8560 addptr(str2, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8561 movdqu(vec, Address(str2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8562 pcmpestri(vec, Address(str1, 0), 0x0d); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8563 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8564 jcc(Assembler::positive, SCAN_SUBSTR); // SF == 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8565 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8566 // Compute substr offset |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8567 subptr(result, Address(rsp, 2*wordSize)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8568 shrl(result, 1); // index |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8569 jmpb(CLEANUP); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8570 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8571 bind(RET_NOT_FOUND); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8572 movl(result, -1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8573 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8574 bind(CLEANUP); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8575 addptr(rsp, 3*wordSize); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8576 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8577 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8578 // Compare strings. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8579 void MacroAssembler::string_compare(Register str1, Register str2, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8580 Register cnt1, Register cnt2, Register result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8581 XMMRegister vec1, XMMRegister vec2) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8582 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8583 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8584 // Compute the minimum of the string lengths and the |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8585 // difference of the string lengths (stack). |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8586 // Do the conditional move stuff |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8587 movl(result, cnt1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8588 subl(cnt1, cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8589 push(cnt1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8590 if (VM_Version::supports_cmov()) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8591 cmovl(Assembler::lessEqual, cnt2, result); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8592 } else { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8593 Label GT_LABEL; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8594 jccb(Assembler::greater, GT_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8595 movl(cnt2, result); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8596 bind(GT_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8597 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8598 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8599 // Is the minimum length zero? |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8600 testl(cnt2, cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8601 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8602 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8603 // Load first characters |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8604 load_unsigned_short(result, Address(str1, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8605 load_unsigned_short(cnt1, Address(str2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8606 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8607 // Compare first characters |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8608 subl(result, cnt1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8609 jcc(Assembler::notZero, POP_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8610 decrementl(cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8611 jcc(Assembler::zero, LENGTH_DIFF_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8612 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8613 { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8614 // Check after comparing first character to see if strings are equivalent |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8615 Label LSkip2; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8616 // Check if the strings start at same location |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8617 cmpptr(str1, str2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8618 jccb(Assembler::notEqual, LSkip2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8619 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8620 // Check if the length difference is zero (from stack) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8621 cmpl(Address(rsp, 0), 0x0); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8622 jcc(Assembler::equal, LENGTH_DIFF_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8623 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8624 // Strings might not be equivalent |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8625 bind(LSkip2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8626 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8627 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8628 // Advance to next character |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8629 addptr(str1, 2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8630 addptr(str2, 2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8631 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8632 if (UseSSE42Intrinsics) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8633 // With SSE4.2, use double quad vector compare |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8634 Label COMPARE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8635 // Setup to compare 16-byte vectors |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8636 movl(cnt1, cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8637 andl(cnt2, 0xfffffff8); // cnt2 holds the vector count |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8638 andl(cnt1, 0x00000007); // cnt1 holds the tail count |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8639 testl(cnt2, cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8640 jccb(Assembler::zero, COMPARE_TAIL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8641 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8642 lea(str2, Address(str2, cnt2, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8643 lea(str1, Address(str1, cnt2, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8644 negptr(cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8645 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8646 bind(COMPARE_VECTORS); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8647 movdqu(vec1, Address(str1, cnt2, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8648 movdqu(vec2, Address(str2, cnt2, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8649 pxor(vec1, vec2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8650 ptest(vec1, vec1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8651 jccb(Assembler::notZero, VECTOR_NOT_EQUAL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8652 addptr(cnt2, 8); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8653 jcc(Assembler::notZero, COMPARE_VECTORS); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8654 jmpb(COMPARE_TAIL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8655 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8656 // Mismatched characters in the vectors |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8657 bind(VECTOR_NOT_EQUAL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8658 lea(str1, Address(str1, cnt2, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8659 lea(str2, Address(str2, cnt2, Address::times_2)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8660 movl(cnt1, 8); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8661 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8662 // Compare tail (< 8 chars), or rescan last vectors to |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8663 // find 1st mismatched characters |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8664 bind(COMPARE_TAIL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8665 testl(cnt1, cnt1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8666 jccb(Assembler::zero, LENGTH_DIFF_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8667 movl(cnt2, cnt1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8668 // Fallthru to tail compare |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8669 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8670 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8671 // Shift str2 and str1 to the end of the arrays, negate min |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8672 lea(str1, Address(str1, cnt2, Address::times_2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8673 lea(str2, Address(str2, cnt2, Address::times_2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8674 negptr(cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8675 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8676 // Compare the rest of the characters |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8677 bind(WHILE_HEAD_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8678 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8679 load_unsigned_short(cnt1, Address(str2, cnt2, Address::times_2, 0)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8680 subl(result, cnt1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8681 jccb(Assembler::notZero, POP_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8682 increment(cnt2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8683 jcc(Assembler::notZero, WHILE_HEAD_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8684 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8685 // Strings are equal up to min length. Return the length difference. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8686 bind(LENGTH_DIFF_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8687 pop(result); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8688 jmpb(DONE_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8689 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8690 // Discard the stored length difference |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8691 bind(POP_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8692 addptr(rsp, wordSize); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8693 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8694 // That's it |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8695 bind(DONE_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8696 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8697 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8698 // Compare char[] arrays aligned to 4 bytes or substrings. |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8699 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8700 Register limit, Register result, Register chr, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8701 XMMRegister vec1, XMMRegister vec2) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8702 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8703 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8704 int length_offset = arrayOopDesc::length_offset_in_bytes(); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8705 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8706 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8707 // Check the input args |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8708 cmpptr(ary1, ary2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8709 jcc(Assembler::equal, TRUE_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8710 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8711 if (is_array_equ) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8712 // Need additional checks for arrays_equals. |
1016 | 8713 testptr(ary1, ary1); |
8714 jcc(Assembler::zero, FALSE_LABEL); | |
8715 testptr(ary2, ary2); | |
8716 jcc(Assembler::zero, FALSE_LABEL); | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8717 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8718 // Check the lengths |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8719 movl(limit, Address(ary1, length_offset)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8720 cmpl(limit, Address(ary2, length_offset)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8721 jcc(Assembler::notEqual, FALSE_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8722 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8723 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8724 // count == 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8725 testl(limit, limit); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8726 jcc(Assembler::zero, TRUE_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8727 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8728 if (is_array_equ) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8729 // Load array address |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8730 lea(ary1, Address(ary1, base_offset)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8731 lea(ary2, Address(ary2, base_offset)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8732 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8733 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8734 shll(limit, 1); // byte count != 0 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8735 movl(result, limit); // copy |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8736 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8737 if (UseSSE42Intrinsics) { |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8738 // With SSE4.2, use double quad vector compare |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8739 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8740 // Compare 16-byte vectors |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8741 andl(result, 0x0000000e); // tail count (in bytes) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8742 andl(limit, 0xfffffff0); // vector count (in bytes) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8743 jccb(Assembler::zero, COMPARE_TAIL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8744 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8745 lea(ary1, Address(ary1, limit, Address::times_1)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8746 lea(ary2, Address(ary2, limit, Address::times_1)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8747 negptr(limit); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8748 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8749 bind(COMPARE_WIDE_VECTORS); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8750 movdqu(vec1, Address(ary1, limit, Address::times_1)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8751 movdqu(vec2, Address(ary2, limit, Address::times_1)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8752 pxor(vec1, vec2); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8753 ptest(vec1, vec1); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8754 jccb(Assembler::notZero, FALSE_LABEL); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8755 addptr(limit, 16); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8756 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8757 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8758 bind(COMPARE_TAIL); // limit is zero |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8759 movl(limit, result); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8760 // Fallthru to tail compare |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8761 } |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8762 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8763 // Compare 4-byte vectors |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8764 andl(limit, 0xfffffffc); // vector count (in bytes) |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8765 jccb(Assembler::zero, COMPARE_CHAR); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8766 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8767 lea(ary1, Address(ary1, limit, Address::times_1)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8768 lea(ary2, Address(ary2, limit, Address::times_1)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8769 negptr(limit); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8770 |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8771 bind(COMPARE_VECTORS); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
diff
changeset
|
8772 movl(chr, Address(ary1, limit, Address::times_1)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
kvn
parents:
898
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8773 cmpl(chr, Address(ary2, limit, Address::times_1)); |
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8774 jccb(Assembler::notEqual, FALSE_LABEL); |
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8775 addptr(limit, 4); |
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8776 jcc(Assembler::notZero, COMPARE_VECTORS); |
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8777 |
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8778 // Compare trailing char (final 2 bytes), if any |
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8779 bind(COMPARE_CHAR); |
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8780 testl(result, 0x2); // tail char |
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8781 jccb(Assembler::zero, TRUE_LABEL); |
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8782 load_unsigned_short(chr, Address(ary1, 0)); |
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8783 load_unsigned_short(limit, Address(ary2, 0)); |
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8784 cmpl(chr, limit); |
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8785 jccb(Assembler::notEqual, FALSE_LABEL); |
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8786 |
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8787 bind(TRUE_LABEL); |
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8788 movl(result, 1); // return true |
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8789 jmpb(DONE); |
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8790 |
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8791 bind(FALSE_LABEL); |
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8792 xorl(result, result); // return false |
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8793 |
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8794 // That's it |
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8795 bind(DONE); |
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8796 } |
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8797 |
1763 | 8798 #ifdef PRODUCT |
8799 #define BLOCK_COMMENT(str) /* nothing */ | |
8800 #else | |
8801 #define BLOCK_COMMENT(str) block_comment(str) | |
8802 #endif | |
8803 | |
8804 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") | |
8805 void MacroAssembler::generate_fill(BasicType t, bool aligned, | |
8806 Register to, Register value, Register count, | |
8807 Register rtmp, XMMRegister xtmp) { | |
8808 assert_different_registers(to, value, count, rtmp); | |
8809 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; | |
8810 Label L_fill_2_bytes, L_fill_4_bytes; | |
8811 | |
8812 int shift = -1; | |
8813 switch (t) { | |
8814 case T_BYTE: | |
8815 shift = 2; | |
8816 break; | |
8817 case T_SHORT: | |
8818 shift = 1; | |
8819 break; | |
8820 case T_INT: | |
8821 shift = 0; | |
8822 break; | |
8823 default: ShouldNotReachHere(); | |
8824 } | |
8825 | |
8826 if (t == T_BYTE) { | |
8827 andl(value, 0xff); | |
8828 movl(rtmp, value); | |
8829 shll(rtmp, 8); | |
8830 orl(value, rtmp); | |
8831 } | |
8832 if (t == T_SHORT) { | |
8833 andl(value, 0xffff); | |
8834 } | |
8835 if (t == T_BYTE || t == T_SHORT) { | |
8836 movl(rtmp, value); | |
8837 shll(rtmp, 16); | |
8838 orl(value, rtmp); | |
8839 } | |
8840 | |
8841 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element | |
8842 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp | |
8843 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { | |
8844 // align source address at 4 bytes address boundary | |
8845 if (t == T_BYTE) { | |
8846 // One byte misalignment happens only for byte arrays | |
8847 testptr(to, 1); | |
8848 jccb(Assembler::zero, L_skip_align1); | |
8849 movb(Address(to, 0), value); | |
8850 increment(to); | |
8851 decrement(count); | |
8852 BIND(L_skip_align1); | |
8853 } | |
8854 // Two bytes misalignment happens only for byte and short (char) arrays | |
8855 testptr(to, 2); | |
8856 jccb(Assembler::zero, L_skip_align2); | |
8857 movw(Address(to, 0), value); | |
8858 addptr(to, 2); | |
8859 subl(count, 1<<(shift-1)); | |
8860 BIND(L_skip_align2); | |
8861 } | |
8862 if (UseSSE < 2) { | |
8863 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
8864 // Fill 32-byte chunks | |
8865 subl(count, 8 << shift); | |
8866 jcc(Assembler::less, L_check_fill_8_bytes); | |
8867 align(16); | |
8868 | |
8869 BIND(L_fill_32_bytes_loop); | |
8870 | |
8871 for (int i = 0; i < 32; i += 4) { | |
8872 movl(Address(to, i), value); | |
8873 } | |
8874 | |
8875 addptr(to, 32); | |
8876 subl(count, 8 << shift); | |
8877 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
8878 BIND(L_check_fill_8_bytes); | |
8879 addl(count, 8 << shift); | |
8880 jccb(Assembler::zero, L_exit); | |
8881 jmpb(L_fill_8_bytes); | |
8882 | |
8883 // | |
8884 // length is too short, just fill qwords | |
8885 // | |
8886 BIND(L_fill_8_bytes_loop); | |
8887 movl(Address(to, 0), value); | |
8888 movl(Address(to, 4), value); | |
8889 addptr(to, 8); | |
8890 BIND(L_fill_8_bytes); | |
8891 subl(count, 1 << (shift + 1)); | |
8892 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
8893 // fall through to fill 4 bytes | |
8894 } else { | |
8895 Label L_fill_32_bytes; | |
8896 if (!UseUnalignedLoadStores) { | |
8897 // align to 8 bytes, we know we are 4 byte aligned to start | |
8898 testptr(to, 4); | |
8899 jccb(Assembler::zero, L_fill_32_bytes); | |
8900 movl(Address(to, 0), value); | |
8901 addptr(to, 4); | |
8902 subl(count, 1<<shift); | |
8903 } | |
8904 BIND(L_fill_32_bytes); | |
8905 { | |
8906 assert( UseSSE >= 2, "supported cpu only" ); | |
8907 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; | |
8908 // Fill 32-byte chunks | |
8909 movdl(xtmp, value); | |
8910 pshufd(xtmp, xtmp, 0); | |
8911 | |
8912 subl(count, 8 << shift); | |
8913 jcc(Assembler::less, L_check_fill_8_bytes); | |
8914 align(16); | |
8915 | |
8916 BIND(L_fill_32_bytes_loop); | |
8917 | |
8918 if (UseUnalignedLoadStores) { | |
8919 movdqu(Address(to, 0), xtmp); | |
8920 movdqu(Address(to, 16), xtmp); | |
8921 } else { | |
8922 movq(Address(to, 0), xtmp); | |
8923 movq(Address(to, 8), xtmp); | |
8924 movq(Address(to, 16), xtmp); | |
8925 movq(Address(to, 24), xtmp); | |
8926 } | |
8927 | |
8928 addptr(to, 32); | |
8929 subl(count, 8 << shift); | |
8930 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); | |
8931 BIND(L_check_fill_8_bytes); | |
8932 addl(count, 8 << shift); | |
8933 jccb(Assembler::zero, L_exit); | |
8934 jmpb(L_fill_8_bytes); | |
8935 | |
8936 // | |
8937 // length is too short, just fill qwords | |
8938 // | |
8939 BIND(L_fill_8_bytes_loop); | |
8940 movq(Address(to, 0), xtmp); | |
8941 addptr(to, 8); | |
8942 BIND(L_fill_8_bytes); | |
8943 subl(count, 1 << (shift + 1)); | |
8944 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); | |
8945 } | |
8946 } | |
8947 // fill trailing 4 bytes | |
8948 BIND(L_fill_4_bytes); | |
8949 testl(count, 1<<shift); | |
8950 jccb(Assembler::zero, L_fill_2_bytes); | |
8951 movl(Address(to, 0), value); | |
8952 if (t == T_BYTE || t == T_SHORT) { | |
8953 addptr(to, 4); | |
8954 BIND(L_fill_2_bytes); | |
8955 // fill trailing 2 bytes | |
8956 testl(count, 1<<(shift-1)); | |
8957 jccb(Assembler::zero, L_fill_byte); | |
8958 movw(Address(to, 0), value); | |
8959 if (t == T_BYTE) { | |
8960 addptr(to, 2); | |
8961 BIND(L_fill_byte); | |
8962 // fill trailing byte | |
8963 testl(count, 1); | |
8964 jccb(Assembler::zero, L_exit); | |
8965 movb(Address(to, 0), value); | |
8966 } else { | |
8967 BIND(L_fill_byte); | |
8968 } | |
8969 } else { | |
8970 BIND(L_fill_2_bytes); | |
8971 } | |
8972 BIND(L_exit); | |
8973 } | |
8974 #undef BIND | |
8975 #undef BLOCK_COMMENT | |
8976 | |
8977 | |
0 | 8978 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { |
8979 switch (cond) { | |
8980 // Note some conditions are synonyms for others | |
8981 case Assembler::zero: return Assembler::notZero; | |
8982 case Assembler::notZero: return Assembler::zero; | |
8983 case Assembler::less: return Assembler::greaterEqual; | |
8984 case Assembler::lessEqual: return Assembler::greater; | |
8985 case Assembler::greater: return Assembler::lessEqual; | |
8986 case Assembler::greaterEqual: return Assembler::less; | |
8987 case Assembler::below: return Assembler::aboveEqual; | |
8988 case Assembler::belowEqual: return Assembler::above; | |
8989 case Assembler::above: return Assembler::belowEqual; | |
8990 case Assembler::aboveEqual: return Assembler::below; | |
8991 case Assembler::overflow: return Assembler::noOverflow; | |
8992 case Assembler::noOverflow: return Assembler::overflow; | |
8993 case Assembler::negative: return Assembler::positive; | |
8994 case Assembler::positive: return Assembler::negative; | |
8995 case Assembler::parity: return Assembler::noParity; | |
8996 case Assembler::noParity: return Assembler::parity; | |
8997 } | |
8998 ShouldNotReachHere(); return Assembler::overflow; | |
8999 } | |
9000 | |
9001 SkipIfEqual::SkipIfEqual( | |
9002 MacroAssembler* masm, const bool* flag_addr, bool value) { | |
9003 _masm = masm; | |
9004 _masm->cmp8(ExternalAddress((address)flag_addr), value); | |
9005 _masm->jcc(Assembler::equal, _label); | |
9006 } | |
9007 | |
9008 SkipIfEqual::~SkipIfEqual() { | |
9009 _masm->bind(_label); | |
9010 } |