Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/assembler_sparc.cpp @ 342:37f87013dfd8
6711316: Open source the Garbage-First garbage collector
Summary: First mercurial integration of the code for the Garbage-First garbage collector.
Reviewed-by: apetrusenko, iveresov, jmasa, sgoldman, tonyp, ysr
author | ysr |
---|---|
date | Thu, 05 Jun 2008 15:57:56 -0700 |
parents | b130b98db9cf |
children | 6aae2f9d0294 |
rev | line source |
---|---|
0 | 1 /* |
2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved. | |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
21 * have any questions. | |
22 * | |
23 */ | |
24 | |
25 #include "incls/_precompiled.incl" | |
26 #include "incls/_assembler_sparc.cpp.incl" | |
27 | |
28 // Implementation of Address | |
29 | |
30 Address::Address( addr_type t, int which ) { | |
31 switch (t) { | |
32 case extra_in_argument: | |
33 case extra_out_argument: | |
34 _base = t == extra_in_argument ? FP : SP; | |
35 _hi = 0; | |
36 // Warning: In LP64 mode, _disp will occupy more than 10 bits. | |
37 // This is inconsistent with the other constructors but op | |
38 // codes such as ld or ldx, only access disp() to get their | |
39 // simm13 argument. | |
40 _disp = ((which - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS; | |
41 break; | |
42 default: | |
43 ShouldNotReachHere(); | |
44 break; | |
45 } | |
46 } | |
47 | |
48 static const char* argumentNames[][2] = { | |
49 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"}, | |
50 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"}, | |
51 {"A(n>9)","P(n>9)"} | |
52 }; | |
53 | |
54 const char* Argument::name() const { | |
55 int nofArgs = sizeof argumentNames / sizeof argumentNames[0]; | |
56 int num = number(); | |
57 if (num >= nofArgs) num = nofArgs - 1; | |
58 return argumentNames[num][is_in() ? 1 : 0]; | |
59 } | |
60 | |
61 void Assembler::print_instruction(int inst) { | |
62 const char* s; | |
63 switch (inv_op(inst)) { | |
64 default: s = "????"; break; | |
65 case call_op: s = "call"; break; | |
66 case branch_op: | |
67 switch (inv_op2(inst)) { | |
68 case bpr_op2: s = "bpr"; break; | |
69 case fb_op2: s = "fb"; break; | |
70 case fbp_op2: s = "fbp"; break; | |
71 case br_op2: s = "br"; break; | |
72 case bp_op2: s = "bp"; break; | |
73 case cb_op2: s = "cb"; break; | |
74 default: s = "????"; break; | |
75 } | |
76 } | |
77 ::tty->print("%s", s); | |
78 } | |
79 | |
80 | |
81 // Patch instruction inst at offset inst_pos to refer to dest_pos | |
82 // and return the resulting instruction. | |
83 // We should have pcs, not offsets, but since all is relative, it will work out | |
84 // OK. | |
85 int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) { | |
86 | |
87 int m; // mask for displacement field | |
88 int v; // new value for displacement field | |
89 const int word_aligned_ones = -4; | |
90 switch (inv_op(inst)) { | |
91 default: ShouldNotReachHere(); | |
92 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break; | |
93 case branch_op: | |
94 switch (inv_op2(inst)) { | |
95 case bpr_op2: m = wdisp16(word_aligned_ones, 0); v = wdisp16(dest_pos, inst_pos); break; | |
96 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; | |
97 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; | |
98 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; | |
99 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; | |
100 case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; | |
101 default: ShouldNotReachHere(); | |
102 } | |
103 } | |
104 return inst & ~m | v; | |
105 } | |
106 | |
107 // Return the offset of the branch destionation of instruction inst | |
108 // at offset pos. | |
109 // Should have pcs, but since all is relative, it works out. | |
110 int Assembler::branch_destination(int inst, int pos) { | |
111 int r; | |
112 switch (inv_op(inst)) { | |
113 default: ShouldNotReachHere(); | |
114 case call_op: r = inv_wdisp(inst, pos, 30); break; | |
115 case branch_op: | |
116 switch (inv_op2(inst)) { | |
117 case bpr_op2: r = inv_wdisp16(inst, pos); break; | |
118 case fbp_op2: r = inv_wdisp( inst, pos, 19); break; | |
119 case bp_op2: r = inv_wdisp( inst, pos, 19); break; | |
120 case fb_op2: r = inv_wdisp( inst, pos, 22); break; | |
121 case br_op2: r = inv_wdisp( inst, pos, 22); break; | |
122 case cb_op2: r = inv_wdisp( inst, pos, 22); break; | |
123 default: ShouldNotReachHere(); | |
124 } | |
125 } | |
126 return r; | |
127 } | |
128 | |
129 int AbstractAssembler::code_fill_byte() { | |
130 return 0x00; // illegal instruction 0x00000000 | |
131 } | |
132 | |
342
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133 Assembler::Condition Assembler::reg_cond_to_cc_cond(Assembler::RCondition in) { |
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134 switch (in) { |
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135 case rc_z: return equal; |
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136 case rc_lez: return lessEqual; |
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137 case rc_lz: return less; |
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138 case rc_nz: return notEqual; |
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139 case rc_gz: return greater; |
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140 case rc_gez: return greaterEqual; |
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141 default: |
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142 ShouldNotReachHere(); |
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143 } |
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144 return equal; |
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145 } |
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146 |
0 | 147 // Generate a bunch 'o stuff (including v9's |
148 #ifndef PRODUCT | |
149 void Assembler::test_v9() { | |
150 add( G0, G1, G2 ); | |
151 add( G3, 0, G4 ); | |
152 | |
153 addcc( G5, G6, G7 ); | |
154 addcc( I0, 1, I1 ); | |
155 addc( I2, I3, I4 ); | |
156 addc( I5, -1, I6 ); | |
157 addccc( I7, L0, L1 ); | |
158 addccc( L2, (1 << 12) - 2, L3 ); | |
159 | |
160 Label lbl1, lbl2, lbl3; | |
161 | |
162 bind(lbl1); | |
163 | |
164 bpr( rc_z, true, pn, L4, pc(), relocInfo::oop_type ); | |
165 delayed()->nop(); | |
166 bpr( rc_lez, false, pt, L5, lbl1); | |
167 delayed()->nop(); | |
168 | |
169 fb( f_never, true, pc() + 4, relocInfo::none); | |
170 delayed()->nop(); | |
171 fb( f_notEqual, false, lbl2 ); | |
172 delayed()->nop(); | |
173 | |
174 fbp( f_notZero, true, fcc0, pn, pc() - 4, relocInfo::none); | |
175 delayed()->nop(); | |
176 fbp( f_lessOrGreater, false, fcc1, pt, lbl3 ); | |
177 delayed()->nop(); | |
178 | |
179 br( equal, true, pc() + 1024, relocInfo::none); | |
180 delayed()->nop(); | |
181 br( lessEqual, false, lbl1 ); | |
182 delayed()->nop(); | |
183 br( never, false, lbl1 ); | |
184 delayed()->nop(); | |
185 | |
186 bp( less, true, icc, pn, pc(), relocInfo::none); | |
187 delayed()->nop(); | |
188 bp( lessEqualUnsigned, false, xcc, pt, lbl2 ); | |
189 delayed()->nop(); | |
190 | |
191 call( pc(), relocInfo::none); | |
192 delayed()->nop(); | |
193 call( lbl3 ); | |
194 delayed()->nop(); | |
195 | |
196 | |
197 casa( L6, L7, O0 ); | |
198 casxa( O1, O2, O3, 0 ); | |
199 | |
200 udiv( O4, O5, O7 ); | |
201 udiv( G0, (1 << 12) - 1, G1 ); | |
202 sdiv( G1, G2, G3 ); | |
203 sdiv( G4, -((1 << 12) - 1), G5 ); | |
204 udivcc( G6, G7, I0 ); | |
205 udivcc( I1, -((1 << 12) - 2), I2 ); | |
206 sdivcc( I3, I4, I5 ); | |
207 sdivcc( I6, -((1 << 12) - 0), I7 ); | |
208 | |
209 done(); | |
210 retry(); | |
211 | |
212 fadd( FloatRegisterImpl::S, F0, F1, F2 ); | |
213 fsub( FloatRegisterImpl::D, F34, F0, F62 ); | |
214 | |
215 fcmp( FloatRegisterImpl::Q, fcc0, F0, F60); | |
216 fcmpe( FloatRegisterImpl::S, fcc1, F31, F30); | |
217 | |
218 ftox( FloatRegisterImpl::D, F2, F4 ); | |
219 ftoi( FloatRegisterImpl::Q, F4, F8 ); | |
220 | |
221 ftof( FloatRegisterImpl::S, FloatRegisterImpl::Q, F3, F12 ); | |
222 | |
223 fxtof( FloatRegisterImpl::S, F4, F5 ); | |
224 fitof( FloatRegisterImpl::D, F6, F8 ); | |
225 | |
226 fmov( FloatRegisterImpl::Q, F16, F20 ); | |
227 fneg( FloatRegisterImpl::S, F6, F7 ); | |
228 fabs( FloatRegisterImpl::D, F10, F12 ); | |
229 | |
230 fmul( FloatRegisterImpl::Q, F24, F28, F32 ); | |
231 fmul( FloatRegisterImpl::S, FloatRegisterImpl::D, F8, F9, F14 ); | |
232 fdiv( FloatRegisterImpl::S, F10, F11, F12 ); | |
233 | |
234 fsqrt( FloatRegisterImpl::S, F13, F14 ); | |
235 | |
236 flush( L0, L1 ); | |
237 flush( L2, -1 ); | |
238 | |
239 flushw(); | |
240 | |
241 illtrap( (1 << 22) - 2); | |
242 | |
243 impdep1( 17, (1 << 19) - 1 ); | |
244 impdep2( 3, 0 ); | |
245 | |
246 jmpl( L3, L4, L5 ); | |
247 delayed()->nop(); | |
248 jmpl( L6, -1, L7, Relocation::spec_simple(relocInfo::none)); | |
249 delayed()->nop(); | |
250 | |
251 | |
252 ldf( FloatRegisterImpl::S, O0, O1, F15 ); | |
253 ldf( FloatRegisterImpl::D, O2, -1, F14 ); | |
254 | |
255 | |
256 ldfsr( O3, O4 ); | |
257 ldfsr( O5, -1 ); | |
258 ldxfsr( O6, O7 ); | |
259 ldxfsr( I0, -1 ); | |
260 | |
261 ldfa( FloatRegisterImpl::D, I1, I2, 1, F16 ); | |
262 ldfa( FloatRegisterImpl::Q, I3, -1, F36 ); | |
263 | |
264 ldsb( I4, I5, I6 ); | |
265 ldsb( I7, -1, G0 ); | |
266 ldsh( G1, G3, G4 ); | |
267 ldsh( G5, -1, G6 ); | |
268 ldsw( G7, L0, L1 ); | |
269 ldsw( L2, -1, L3 ); | |
270 ldub( L4, L5, L6 ); | |
271 ldub( L7, -1, O0 ); | |
272 lduh( O1, O2, O3 ); | |
273 lduh( O4, -1, O5 ); | |
274 lduw( O6, O7, G0 ); | |
275 lduw( G1, -1, G2 ); | |
276 ldx( G3, G4, G5 ); | |
277 ldx( G6, -1, G7 ); | |
278 ldd( I0, I1, I2 ); | |
279 ldd( I3, -1, I4 ); | |
280 | |
281 ldsba( I5, I6, 2, I7 ); | |
282 ldsba( L0, -1, L1 ); | |
283 ldsha( L2, L3, 3, L4 ); | |
284 ldsha( L5, -1, L6 ); | |
285 ldswa( L7, O0, (1 << 8) - 1, O1 ); | |
286 ldswa( O2, -1, O3 ); | |
287 lduba( O4, O5, 0, O6 ); | |
288 lduba( O7, -1, I0 ); | |
289 lduha( I1, I2, 1, I3 ); | |
290 lduha( I4, -1, I5 ); | |
291 lduwa( I6, I7, 2, L0 ); | |
292 lduwa( L1, -1, L2 ); | |
293 ldxa( L3, L4, 3, L5 ); | |
294 ldxa( L6, -1, L7 ); | |
295 ldda( G0, G1, 4, G2 ); | |
296 ldda( G3, -1, G4 ); | |
297 | |
298 ldstub( G5, G6, G7 ); | |
299 ldstub( O0, -1, O1 ); | |
300 | |
301 ldstuba( O2, O3, 5, O4 ); | |
302 ldstuba( O5, -1, O6 ); | |
303 | |
304 and3( I0, L0, O0 ); | |
305 and3( G7, -1, O7 ); | |
306 andcc( L2, I2, G2 ); | |
307 andcc( L4, -1, G4 ); | |
308 andn( I5, I6, I7 ); | |
309 andn( I6, -1, I7 ); | |
310 andncc( I5, I6, I7 ); | |
311 andncc( I7, -1, I6 ); | |
312 or3( I5, I6, I7 ); | |
313 or3( I7, -1, I6 ); | |
314 orcc( I5, I6, I7 ); | |
315 orcc( I7, -1, I6 ); | |
316 orn( I5, I6, I7 ); | |
317 orn( I7, -1, I6 ); | |
318 orncc( I5, I6, I7 ); | |
319 orncc( I7, -1, I6 ); | |
320 xor3( I5, I6, I7 ); | |
321 xor3( I7, -1, I6 ); | |
322 xorcc( I5, I6, I7 ); | |
323 xorcc( I7, -1, I6 ); | |
324 xnor( I5, I6, I7 ); | |
325 xnor( I7, -1, I6 ); | |
326 xnorcc( I5, I6, I7 ); | |
327 xnorcc( I7, -1, I6 ); | |
328 | |
329 membar( Membar_mask_bits(StoreStore | LoadStore | StoreLoad | LoadLoad | Sync | MemIssue | Lookaside ) ); | |
330 membar( StoreStore ); | |
331 membar( LoadStore ); | |
332 membar( StoreLoad ); | |
333 membar( LoadLoad ); | |
334 membar( Sync ); | |
335 membar( MemIssue ); | |
336 membar( Lookaside ); | |
337 | |
338 fmov( FloatRegisterImpl::S, f_ordered, true, fcc2, F16, F17 ); | |
339 fmov( FloatRegisterImpl::D, rc_lz, L5, F18, F20 ); | |
340 | |
341 movcc( overflowClear, false, icc, I6, L4 ); | |
342 movcc( f_unorderedOrEqual, true, fcc2, (1 << 10) - 1, O0 ); | |
343 | |
344 movr( rc_nz, I5, I6, I7 ); | |
345 movr( rc_gz, L1, -1, L2 ); | |
346 | |
347 mulx( I5, I6, I7 ); | |
348 mulx( I7, -1, I6 ); | |
349 sdivx( I5, I6, I7 ); | |
350 sdivx( I7, -1, I6 ); | |
351 udivx( I5, I6, I7 ); | |
352 udivx( I7, -1, I6 ); | |
353 | |
354 umul( I5, I6, I7 ); | |
355 umul( I7, -1, I6 ); | |
356 smul( I5, I6, I7 ); | |
357 smul( I7, -1, I6 ); | |
358 umulcc( I5, I6, I7 ); | |
359 umulcc( I7, -1, I6 ); | |
360 smulcc( I5, I6, I7 ); | |
361 smulcc( I7, -1, I6 ); | |
362 | |
363 mulscc( I5, I6, I7 ); | |
364 mulscc( I7, -1, I6 ); | |
365 | |
366 nop(); | |
367 | |
368 | |
369 popc( G0, G1); | |
370 popc( -1, G2); | |
371 | |
372 prefetch( L1, L2, severalReads ); | |
373 prefetch( L3, -1, oneRead ); | |
374 prefetcha( O3, O2, 6, severalWritesAndPossiblyReads ); | |
375 prefetcha( G2, -1, oneWrite ); | |
376 | |
377 rett( I7, I7); | |
378 delayed()->nop(); | |
379 rett( G0, -1, relocInfo::none); | |
380 delayed()->nop(); | |
381 | |
382 save( I5, I6, I7 ); | |
383 save( I7, -1, I6 ); | |
384 restore( I5, I6, I7 ); | |
385 restore( I7, -1, I6 ); | |
386 | |
387 saved(); | |
388 restored(); | |
389 | |
390 sethi( 0xaaaaaaaa, I3, Relocation::spec_simple(relocInfo::none)); | |
391 | |
392 sll( I5, I6, I7 ); | |
393 sll( I7, 31, I6 ); | |
394 srl( I5, I6, I7 ); | |
395 srl( I7, 0, I6 ); | |
396 sra( I5, I6, I7 ); | |
397 sra( I7, 30, I6 ); | |
398 sllx( I5, I6, I7 ); | |
399 sllx( I7, 63, I6 ); | |
400 srlx( I5, I6, I7 ); | |
401 srlx( I7, 0, I6 ); | |
402 srax( I5, I6, I7 ); | |
403 srax( I7, 62, I6 ); | |
404 | |
405 sir( -1 ); | |
406 | |
407 stbar(); | |
408 | |
409 stf( FloatRegisterImpl::Q, F40, G0, I7 ); | |
410 stf( FloatRegisterImpl::S, F18, I3, -1 ); | |
411 | |
412 stfsr( L1, L2 ); | |
413 stfsr( I7, -1 ); | |
414 stxfsr( I6, I5 ); | |
415 stxfsr( L4, -1 ); | |
416 | |
417 stfa( FloatRegisterImpl::D, F22, I6, I7, 7 ); | |
418 stfa( FloatRegisterImpl::Q, F44, G0, -1 ); | |
419 | |
420 stb( L5, O2, I7 ); | |
421 stb( I7, I6, -1 ); | |
422 sth( L5, O2, I7 ); | |
423 sth( I7, I6, -1 ); | |
424 stw( L5, O2, I7 ); | |
425 stw( I7, I6, -1 ); | |
426 stx( L5, O2, I7 ); | |
427 stx( I7, I6, -1 ); | |
428 std( L5, O2, I7 ); | |
429 std( I7, I6, -1 ); | |
430 | |
431 stba( L5, O2, I7, 8 ); | |
432 stba( I7, I6, -1 ); | |
433 stha( L5, O2, I7, 9 ); | |
434 stha( I7, I6, -1 ); | |
435 stwa( L5, O2, I7, 0 ); | |
436 stwa( I7, I6, -1 ); | |
437 stxa( L5, O2, I7, 11 ); | |
438 stxa( I7, I6, -1 ); | |
439 stda( L5, O2, I7, 12 ); | |
440 stda( I7, I6, -1 ); | |
441 | |
442 sub( I5, I6, I7 ); | |
443 sub( I7, -1, I6 ); | |
444 subcc( I5, I6, I7 ); | |
445 subcc( I7, -1, I6 ); | |
446 subc( I5, I6, I7 ); | |
447 subc( I7, -1, I6 ); | |
448 subccc( I5, I6, I7 ); | |
449 subccc( I7, -1, I6 ); | |
450 | |
451 swap( I5, I6, I7 ); | |
452 swap( I7, -1, I6 ); | |
453 | |
454 swapa( G0, G1, 13, G2 ); | |
455 swapa( I7, -1, I6 ); | |
456 | |
457 taddcc( I5, I6, I7 ); | |
458 taddcc( I7, -1, I6 ); | |
459 taddcctv( I5, I6, I7 ); | |
460 taddcctv( I7, -1, I6 ); | |
461 | |
462 tsubcc( I5, I6, I7 ); | |
463 tsubcc( I7, -1, I6 ); | |
464 tsubcctv( I5, I6, I7 ); | |
465 tsubcctv( I7, -1, I6 ); | |
466 | |
467 trap( overflowClear, xcc, G0, G1 ); | |
468 trap( lessEqual, icc, I7, 17 ); | |
469 | |
470 bind(lbl2); | |
471 bind(lbl3); | |
472 | |
473 code()->decode(); | |
474 } | |
475 | |
476 // Generate a bunch 'o stuff unique to V8 | |
477 void Assembler::test_v8_onlys() { | |
478 Label lbl1; | |
479 | |
480 cb( cp_0or1or2, false, pc() - 4, relocInfo::none); | |
481 delayed()->nop(); | |
482 cb( cp_never, true, lbl1); | |
483 delayed()->nop(); | |
484 | |
485 cpop1(1, 2, 3, 4); | |
486 cpop2(5, 6, 7, 8); | |
487 | |
488 ldc( I0, I1, 31); | |
489 ldc( I2, -1, 0); | |
490 | |
491 lddc( I4, I4, 30); | |
492 lddc( I6, 0, 1 ); | |
493 | |
494 ldcsr( L0, L1, 0); | |
495 ldcsr( L1, (1 << 12) - 1, 17 ); | |
496 | |
497 stc( 31, L4, L5); | |
498 stc( 30, L6, -(1 << 12) ); | |
499 | |
500 stdc( 0, L7, G0); | |
501 stdc( 1, G1, 0 ); | |
502 | |
503 stcsr( 16, G2, G3); | |
504 stcsr( 17, G4, 1 ); | |
505 | |
506 stdcq( 4, G5, G6); | |
507 stdcq( 5, G7, -1 ); | |
508 | |
509 bind(lbl1); | |
510 | |
511 code()->decode(); | |
512 } | |
513 #endif | |
514 | |
515 // Implementation of MacroAssembler | |
516 | |
517 void MacroAssembler::null_check(Register reg, int offset) { | |
518 if (needs_explicit_null_check((intptr_t)offset)) { | |
519 // provoke OS NULL exception if reg = NULL by | |
520 // accessing M[reg] w/o changing any registers | |
521 ld_ptr(reg, 0, G0); | |
522 } | |
523 else { | |
524 // nothing to do, (later) access of M[reg + offset] | |
525 // will provoke OS NULL exception if reg = NULL | |
526 } | |
527 } | |
528 | |
529 // Ring buffer jumps | |
530 | |
531 #ifndef PRODUCT | |
532 void MacroAssembler::ret( bool trace ) { if (trace) { | |
533 mov(I7, O7); // traceable register | |
534 JMP(O7, 2 * BytesPerInstWord); | |
535 } else { | |
536 jmpl( I7, 2 * BytesPerInstWord, G0 ); | |
537 } | |
538 } | |
539 | |
540 void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord); | |
541 else jmpl( O7, 2 * BytesPerInstWord, G0 ); } | |
542 #endif /* PRODUCT */ | |
543 | |
544 | |
545 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) { | |
546 assert_not_delayed(); | |
547 // This can only be traceable if r1 & r2 are visible after a window save | |
548 if (TraceJumps) { | |
549 #ifndef PRODUCT | |
550 save_frame(0); | |
551 verify_thread(); | |
552 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); | |
553 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); | |
554 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); | |
555 add(O2, O1, O1); | |
556 | |
557 add(r1->after_save(), r2->after_save(), O2); | |
558 set((intptr_t)file, O3); | |
559 set(line, O4); | |
560 Label L; | |
561 // get nearby pc, store jmp target | |
562 call(L, relocInfo::none); // No relocation for call to pc+0x8 | |
563 delayed()->st(O2, O1, 0); | |
564 bind(L); | |
565 | |
566 // store nearby pc | |
567 st(O7, O1, sizeof(intptr_t)); | |
568 // store file | |
569 st(O3, O1, 2*sizeof(intptr_t)); | |
570 // store line | |
571 st(O4, O1, 3*sizeof(intptr_t)); | |
572 add(O0, 1, O0); | |
573 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); | |
574 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); | |
575 restore(); | |
576 #endif /* PRODUCT */ | |
577 } | |
578 jmpl(r1, r2, G0); | |
579 } | |
580 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) { | |
581 assert_not_delayed(); | |
582 // This can only be traceable if r1 is visible after a window save | |
583 if (TraceJumps) { | |
584 #ifndef PRODUCT | |
585 save_frame(0); | |
586 verify_thread(); | |
587 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); | |
588 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); | |
589 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); | |
590 add(O2, O1, O1); | |
591 | |
592 add(r1->after_save(), offset, O2); | |
593 set((intptr_t)file, O3); | |
594 set(line, O4); | |
595 Label L; | |
596 // get nearby pc, store jmp target | |
597 call(L, relocInfo::none); // No relocation for call to pc+0x8 | |
598 delayed()->st(O2, O1, 0); | |
599 bind(L); | |
600 | |
601 // store nearby pc | |
602 st(O7, O1, sizeof(intptr_t)); | |
603 // store file | |
604 st(O3, O1, 2*sizeof(intptr_t)); | |
605 // store line | |
606 st(O4, O1, 3*sizeof(intptr_t)); | |
607 add(O0, 1, O0); | |
608 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); | |
609 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); | |
610 restore(); | |
611 #endif /* PRODUCT */ | |
612 } | |
613 jmp(r1, offset); | |
614 } | |
615 | |
616 // This code sequence is relocatable to any address, even on LP64. | |
617 void MacroAssembler::jumpl( Address& a, Register d, int offset, const char* file, int line ) { | |
618 assert_not_delayed(); | |
619 // Force fixed length sethi because NativeJump and NativeFarCall don't handle | |
620 // variable length instruction streams. | |
621 sethi(a, /*ForceRelocatable=*/ true); | |
622 if (TraceJumps) { | |
623 #ifndef PRODUCT | |
624 // Must do the add here so relocation can find the remainder of the | |
625 // value to be relocated. | |
626 add(a.base(), a.disp() + offset, a.base(), a.rspec(offset)); | |
627 save_frame(0); | |
628 verify_thread(); | |
629 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); | |
630 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); | |
631 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); | |
632 add(O2, O1, O1); | |
633 | |
634 set((intptr_t)file, O3); | |
635 set(line, O4); | |
636 Label L; | |
637 | |
638 // get nearby pc, store jmp target | |
639 call(L, relocInfo::none); // No relocation for call to pc+0x8 | |
640 delayed()->st(a.base()->after_save(), O1, 0); | |
641 bind(L); | |
642 | |
643 // store nearby pc | |
644 st(O7, O1, sizeof(intptr_t)); | |
645 // store file | |
646 st(O3, O1, 2*sizeof(intptr_t)); | |
647 // store line | |
648 st(O4, O1, 3*sizeof(intptr_t)); | |
649 add(O0, 1, O0); | |
650 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); | |
651 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); | |
652 restore(); | |
653 jmpl(a.base(), G0, d); | |
654 #else | |
655 jmpl(a, d, offset); | |
656 #endif /* PRODUCT */ | |
657 } else { | |
658 jmpl(a, d, offset); | |
659 } | |
660 } | |
661 | |
662 void MacroAssembler::jump( Address& a, int offset, const char* file, int line ) { | |
663 jumpl( a, G0, offset, file, line ); | |
664 } | |
665 | |
666 | |
667 // Convert to C varargs format | |
668 void MacroAssembler::set_varargs( Argument inArg, Register d ) { | |
669 // spill register-resident args to their memory slots | |
670 // (SPARC calling convention requires callers to have already preallocated these) | |
671 // Note that the inArg might in fact be an outgoing argument, | |
672 // if a leaf routine or stub does some tricky argument shuffling. | |
673 // This routine must work even though one of the saved arguments | |
674 // is in the d register (e.g., set_varargs(Argument(0, false), O0)). | |
675 for (Argument savePtr = inArg; | |
676 savePtr.is_register(); | |
677 savePtr = savePtr.successor()) { | |
678 st_ptr(savePtr.as_register(), savePtr.address_in_frame()); | |
679 } | |
680 // return the address of the first memory slot | |
681 add(inArg.address_in_frame(), d); | |
682 } | |
683 | |
684 // Conditional breakpoint (for assertion checks in assembly code) | |
685 void MacroAssembler::breakpoint_trap(Condition c, CC cc) { | |
686 trap(c, cc, G0, ST_RESERVED_FOR_USER_0); | |
687 } | |
688 | |
689 // We want to use ST_BREAKPOINT here, but the debugger is confused by it. | |
690 void MacroAssembler::breakpoint_trap() { | |
691 trap(ST_RESERVED_FOR_USER_0); | |
692 } | |
693 | |
694 // flush windows (except current) using flushw instruction if avail. | |
695 void MacroAssembler::flush_windows() { | |
696 if (VM_Version::v9_instructions_work()) flushw(); | |
697 else flush_windows_trap(); | |
698 } | |
699 | |
700 // Write serialization page so VM thread can do a pseudo remote membar | |
701 // We use the current thread pointer to calculate a thread specific | |
702 // offset to write to within the page. This minimizes bus traffic | |
703 // due to cache line collision. | |
704 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) { | |
705 Address mem_serialize_page(tmp1, os::get_memory_serialize_page()); | |
706 srl(thread, os::get_serialize_page_shift_count(), tmp2); | |
707 if (Assembler::is_simm13(os::vm_page_size())) { | |
708 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2); | |
709 } | |
710 else { | |
711 set((os::vm_page_size() - sizeof(int)), tmp1); | |
712 and3(tmp2, tmp1, tmp2); | |
713 } | |
714 load_address(mem_serialize_page); | |
715 st(G0, tmp1, tmp2); | |
716 } | |
717 | |
718 | |
719 | |
720 void MacroAssembler::enter() { | |
721 Unimplemented(); | |
722 } | |
723 | |
724 void MacroAssembler::leave() { | |
725 Unimplemented(); | |
726 } | |
727 | |
728 void MacroAssembler::mult(Register s1, Register s2, Register d) { | |
729 if(VM_Version::v9_instructions_work()) { | |
730 mulx (s1, s2, d); | |
731 } else { | |
732 smul (s1, s2, d); | |
733 } | |
734 } | |
735 | |
736 void MacroAssembler::mult(Register s1, int simm13a, Register d) { | |
737 if(VM_Version::v9_instructions_work()) { | |
738 mulx (s1, simm13a, d); | |
739 } else { | |
740 smul (s1, simm13a, d); | |
741 } | |
742 } | |
743 | |
744 | |
745 #ifdef ASSERT | |
746 void MacroAssembler::read_ccr_v8_assert(Register ccr_save) { | |
747 const Register s1 = G3_scratch; | |
748 const Register s2 = G4_scratch; | |
749 Label get_psr_test; | |
750 // Get the condition codes the V8 way. | |
751 read_ccr_trap(s1); | |
752 mov(ccr_save, s2); | |
753 // This is a test of V8 which has icc but not xcc | |
754 // so mask off the xcc bits | |
755 and3(s2, 0xf, s2); | |
756 // Compare condition codes from the V8 and V9 ways. | |
757 subcc(s2, s1, G0); | |
758 br(Assembler::notEqual, true, Assembler::pt, get_psr_test); | |
759 delayed()->breakpoint_trap(); | |
760 bind(get_psr_test); | |
761 } | |
762 | |
763 void MacroAssembler::write_ccr_v8_assert(Register ccr_save) { | |
764 const Register s1 = G3_scratch; | |
765 const Register s2 = G4_scratch; | |
766 Label set_psr_test; | |
767 // Write out the saved condition codes the V8 way | |
768 write_ccr_trap(ccr_save, s1, s2); | |
769 // Read back the condition codes using the V9 instruction | |
770 rdccr(s1); | |
771 mov(ccr_save, s2); | |
772 // This is a test of V8 which has icc but not xcc | |
773 // so mask off the xcc bits | |
774 and3(s2, 0xf, s2); | |
775 and3(s1, 0xf, s1); | |
776 // Compare the V8 way with the V9 way. | |
777 subcc(s2, s1, G0); | |
778 br(Assembler::notEqual, true, Assembler::pt, set_psr_test); | |
779 delayed()->breakpoint_trap(); | |
780 bind(set_psr_test); | |
781 } | |
782 #else | |
783 #define read_ccr_v8_assert(x) | |
784 #define write_ccr_v8_assert(x) | |
785 #endif // ASSERT | |
786 | |
787 void MacroAssembler::read_ccr(Register ccr_save) { | |
788 if (VM_Version::v9_instructions_work()) { | |
789 rdccr(ccr_save); | |
790 // Test code sequence used on V8. Do not move above rdccr. | |
791 read_ccr_v8_assert(ccr_save); | |
792 } else { | |
793 read_ccr_trap(ccr_save); | |
794 } | |
795 } | |
796 | |
797 void MacroAssembler::write_ccr(Register ccr_save) { | |
798 if (VM_Version::v9_instructions_work()) { | |
799 // Test code sequence used on V8. Do not move below wrccr. | |
800 write_ccr_v8_assert(ccr_save); | |
801 wrccr(ccr_save); | |
802 } else { | |
803 const Register temp_reg1 = G3_scratch; | |
804 const Register temp_reg2 = G4_scratch; | |
805 write_ccr_trap(ccr_save, temp_reg1, temp_reg2); | |
806 } | |
807 } | |
808 | |
809 | |
810 // Calls to C land | |
811 | |
812 #ifdef ASSERT | |
813 // a hook for debugging | |
814 static Thread* reinitialize_thread() { | |
815 return ThreadLocalStorage::thread(); | |
816 } | |
817 #else | |
818 #define reinitialize_thread ThreadLocalStorage::thread | |
819 #endif | |
820 | |
821 #ifdef ASSERT | |
822 address last_get_thread = NULL; | |
823 #endif | |
824 | |
825 // call this when G2_thread is not known to be valid | |
826 void MacroAssembler::get_thread() { | |
827 save_frame(0); // to avoid clobbering O0 | |
828 mov(G1, L0); // avoid clobbering G1 | |
829 mov(G5_method, L1); // avoid clobbering G5 | |
830 mov(G3, L2); // avoid clobbering G3 also | |
831 mov(G4, L5); // avoid clobbering G4 | |
832 #ifdef ASSERT | |
833 Address last_get_thread_addr(L3, (address)&last_get_thread); | |
834 sethi(last_get_thread_addr); | |
835 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call | |
836 st_ptr(L4, last_get_thread_addr); | |
837 #endif | |
838 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type); | |
839 delayed()->nop(); | |
840 mov(L0, G1); | |
841 mov(L1, G5_method); | |
842 mov(L2, G3); | |
843 mov(L5, G4); | |
844 restore(O0, 0, G2_thread); | |
845 } | |
846 | |
847 static Thread* verify_thread_subroutine(Thread* gthread_value) { | |
848 Thread* correct_value = ThreadLocalStorage::thread(); | |
849 guarantee(gthread_value == correct_value, "G2_thread value must be the thread"); | |
850 return correct_value; | |
851 } | |
852 | |
853 void MacroAssembler::verify_thread() { | |
854 if (VerifyThread) { | |
855 // NOTE: this chops off the heads of the 64-bit O registers. | |
856 #ifdef CC_INTERP | |
857 save_frame(0); | |
858 #else | |
859 // make sure G2_thread contains the right value | |
860 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof) | |
861 mov(G1, L1); // avoid clobbering G1 | |
862 // G2 saved below | |
863 mov(G3, L3); // avoid clobbering G3 | |
864 mov(G4, L4); // avoid clobbering G4 | |
865 mov(G5_method, L5); // avoid clobbering G5_method | |
866 #endif /* CC_INTERP */ | |
867 #if defined(COMPILER2) && !defined(_LP64) | |
868 // Save & restore possible 64-bit Long arguments in G-regs | |
869 srlx(G1,32,L0); | |
870 srlx(G4,32,L6); | |
871 #endif | |
872 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type); | |
873 delayed()->mov(G2_thread, O0); | |
874 | |
875 mov(L1, G1); // Restore G1 | |
876 // G2 restored below | |
877 mov(L3, G3); // restore G3 | |
878 mov(L4, G4); // restore G4 | |
879 mov(L5, G5_method); // restore G5_method | |
880 #if defined(COMPILER2) && !defined(_LP64) | |
881 // Save & restore possible 64-bit Long arguments in G-regs | |
882 sllx(L0,32,G2); // Move old high G1 bits high in G2 | |
883 sllx(G1, 0,G1); // Clear current high G1 bits | |
884 or3 (G1,G2,G1); // Recover 64-bit G1 | |
885 sllx(L6,32,G2); // Move old high G4 bits high in G2 | |
886 sllx(G4, 0,G4); // Clear current high G4 bits | |
887 or3 (G4,G2,G4); // Recover 64-bit G4 | |
888 #endif | |
889 restore(O0, 0, G2_thread); | |
890 } | |
891 } | |
892 | |
893 | |
894 void MacroAssembler::save_thread(const Register thread_cache) { | |
895 verify_thread(); | |
896 if (thread_cache->is_valid()) { | |
897 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); | |
898 mov(G2_thread, thread_cache); | |
899 } | |
900 if (VerifyThread) { | |
901 // smash G2_thread, as if the VM were about to anyway | |
902 set(0x67676767, G2_thread); | |
903 } | |
904 } | |
905 | |
906 | |
907 void MacroAssembler::restore_thread(const Register thread_cache) { | |
908 if (thread_cache->is_valid()) { | |
909 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); | |
910 mov(thread_cache, G2_thread); | |
911 verify_thread(); | |
912 } else { | |
913 // do it the slow way | |
914 get_thread(); | |
915 } | |
916 } | |
917 | |
918 | |
919 // %%% maybe get rid of [re]set_last_Java_frame | |
920 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) { | |
921 assert_not_delayed(); | |
922 Address flags(G2_thread, | |
923 0, | |
924 in_bytes(JavaThread::frame_anchor_offset()) + | |
925 in_bytes(JavaFrameAnchor::flags_offset())); | |
926 Address pc_addr(G2_thread, | |
927 0, | |
928 in_bytes(JavaThread::last_Java_pc_offset())); | |
929 | |
930 // Always set last_Java_pc and flags first because once last_Java_sp is visible | |
931 // has_last_Java_frame is true and users will look at the rest of the fields. | |
932 // (Note: flags should always be zero before we get here so doesn't need to be set.) | |
933 | |
934 #ifdef ASSERT | |
935 // Verify that flags was zeroed on return to Java | |
936 Label PcOk; | |
937 save_frame(0); // to avoid clobbering O0 | |
938 ld_ptr(pc_addr, L0); | |
939 tst(L0); | |
940 #ifdef _LP64 | |
941 brx(Assembler::zero, false, Assembler::pt, PcOk); | |
942 #else | |
943 br(Assembler::zero, false, Assembler::pt, PcOk); | |
944 #endif // _LP64 | |
945 delayed() -> nop(); | |
946 stop("last_Java_pc not zeroed before leaving Java"); | |
947 bind(PcOk); | |
948 | |
949 // Verify that flags was zeroed on return to Java | |
950 Label FlagsOk; | |
951 ld(flags, L0); | |
952 tst(L0); | |
953 br(Assembler::zero, false, Assembler::pt, FlagsOk); | |
954 delayed() -> restore(); | |
955 stop("flags not zeroed before leaving Java"); | |
956 bind(FlagsOk); | |
957 #endif /* ASSERT */ | |
958 // | |
959 // When returning from calling out from Java mode the frame anchor's last_Java_pc | |
960 // will always be set to NULL. It is set here so that if we are doing a call to | |
961 // native (not VM) that we capture the known pc and don't have to rely on the | |
962 // native call having a standard frame linkage where we can find the pc. | |
963 | |
964 if (last_Java_pc->is_valid()) { | |
965 st_ptr(last_Java_pc, pc_addr); | |
966 } | |
967 | |
968 #ifdef _LP64 | |
969 #ifdef ASSERT | |
970 // Make sure that we have an odd stack | |
971 Label StackOk; | |
972 andcc(last_java_sp, 0x01, G0); | |
973 br(Assembler::notZero, false, Assembler::pt, StackOk); | |
974 delayed() -> nop(); | |
975 stop("Stack Not Biased in set_last_Java_frame"); | |
976 bind(StackOk); | |
977 #endif // ASSERT | |
978 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame"); | |
979 add( last_java_sp, STACK_BIAS, G4_scratch ); | |
980 st_ptr(G4_scratch, Address(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset()))); | |
981 #else | |
982 st_ptr(last_java_sp, Address(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset()))); | |
983 #endif // _LP64 | |
984 } | |
985 | |
986 void MacroAssembler::reset_last_Java_frame(void) { | |
987 assert_not_delayed(); | |
988 | |
989 Address sp_addr(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset())); | |
990 Address pc_addr(G2_thread, | |
991 0, | |
992 in_bytes(JavaThread::frame_anchor_offset()) + in_bytes(JavaFrameAnchor::last_Java_pc_offset())); | |
993 Address flags(G2_thread, | |
994 0, | |
995 in_bytes(JavaThread::frame_anchor_offset()) + in_bytes(JavaFrameAnchor::flags_offset())); | |
996 | |
997 #ifdef ASSERT | |
998 // check that it WAS previously set | |
999 #ifdef CC_INTERP | |
1000 save_frame(0); | |
1001 #else | |
1002 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof | |
1003 #endif /* CC_INTERP */ | |
1004 ld_ptr(sp_addr, L0); | |
1005 tst(L0); | |
1006 breakpoint_trap(Assembler::zero, Assembler::ptr_cc); | |
1007 restore(); | |
1008 #endif // ASSERT | |
1009 | |
1010 st_ptr(G0, sp_addr); | |
1011 // Always return last_Java_pc to zero | |
1012 st_ptr(G0, pc_addr); | |
1013 // Always null flags after return to Java | |
1014 st(G0, flags); | |
1015 } | |
1016 | |
1017 | |
1018 void MacroAssembler::call_VM_base( | |
1019 Register oop_result, | |
1020 Register thread_cache, | |
1021 Register last_java_sp, | |
1022 address entry_point, | |
1023 int number_of_arguments, | |
1024 bool check_exceptions) | |
1025 { | |
1026 assert_not_delayed(); | |
1027 | |
1028 // determine last_java_sp register | |
1029 if (!last_java_sp->is_valid()) { | |
1030 last_java_sp = SP; | |
1031 } | |
1032 // debugging support | |
1033 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); | |
1034 | |
1035 // 64-bit last_java_sp is biased! | |
1036 set_last_Java_frame(last_java_sp, noreg); | |
1037 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early | |
1038 save_thread(thread_cache); | |
1039 // do the call | |
1040 call(entry_point, relocInfo::runtime_call_type); | |
1041 if (!VerifyThread) | |
1042 delayed()->mov(G2_thread, O0); // pass thread as first argument | |
1043 else | |
1044 delayed()->nop(); // (thread already passed) | |
1045 restore_thread(thread_cache); | |
1046 reset_last_Java_frame(); | |
1047 | |
1048 // check for pending exceptions. use Gtemp as scratch register. | |
1049 if (check_exceptions) { | |
1050 check_and_forward_exception(Gtemp); | |
1051 } | |
1052 | |
1053 // get oop result if there is one and reset the value in the thread | |
1054 if (oop_result->is_valid()) { | |
1055 get_vm_result(oop_result); | |
1056 } | |
1057 } | |
1058 | |
1059 void MacroAssembler::check_and_forward_exception(Register scratch_reg) | |
1060 { | |
1061 Label L; | |
1062 | |
1063 check_and_handle_popframe(scratch_reg); | |
1064 check_and_handle_earlyret(scratch_reg); | |
1065 | |
1066 Address exception_addr(G2_thread, 0, in_bytes(Thread::pending_exception_offset())); | |
1067 ld_ptr(exception_addr, scratch_reg); | |
1068 br_null(scratch_reg,false,pt,L); | |
1069 delayed()->nop(); | |
1070 // we use O7 linkage so that forward_exception_entry has the issuing PC | |
1071 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); | |
1072 delayed()->nop(); | |
1073 bind(L); | |
1074 } | |
1075 | |
1076 | |
1077 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) { | |
1078 } | |
1079 | |
1080 | |
1081 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) { | |
1082 } | |
1083 | |
1084 | |
1085 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { | |
1086 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); | |
1087 } | |
1088 | |
1089 | |
1090 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) { | |
1091 // O0 is reserved for the thread | |
1092 mov(arg_1, O1); | |
1093 call_VM(oop_result, entry_point, 1, check_exceptions); | |
1094 } | |
1095 | |
1096 | |
1097 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { | |
1098 // O0 is reserved for the thread | |
1099 mov(arg_1, O1); | |
1100 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1101 call_VM(oop_result, entry_point, 2, check_exceptions); | |
1102 } | |
1103 | |
1104 | |
1105 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { | |
1106 // O0 is reserved for the thread | |
1107 mov(arg_1, O1); | |
1108 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1109 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); | |
1110 call_VM(oop_result, entry_point, 3, check_exceptions); | |
1111 } | |
1112 | |
1113 | |
1114 | |
1115 // Note: The following call_VM overloadings are useful when a "save" | |
1116 // has already been performed by a stub, and the last Java frame is | |
1117 // the previous one. In that case, last_java_sp must be passed as FP | |
1118 // instead of SP. | |
1119 | |
1120 | |
1121 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) { | |
1122 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions); | |
1123 } | |
1124 | |
1125 | |
1126 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) { | |
1127 // O0 is reserved for the thread | |
1128 mov(arg_1, O1); | |
1129 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); | |
1130 } | |
1131 | |
1132 | |
1133 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { | |
1134 // O0 is reserved for the thread | |
1135 mov(arg_1, O1); | |
1136 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1137 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); | |
1138 } | |
1139 | |
1140 | |
1141 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { | |
1142 // O0 is reserved for the thread | |
1143 mov(arg_1, O1); | |
1144 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); | |
1145 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); | |
1146 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); | |
1147 } | |
1148 | |
1149 | |
1150 | |
1151 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) { | |
1152 assert_not_delayed(); | |
1153 save_thread(thread_cache); | |
1154 // do the call | |
1155 call(entry_point, relocInfo::runtime_call_type); | |
1156 delayed()->nop(); | |
1157 restore_thread(thread_cache); | |
1158 } | |
1159 | |
1160 | |
1161 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) { | |
1162 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments); | |
1163 } | |
1164 | |
1165 | |
1166 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) { | |
1167 mov(arg_1, O0); | |
1168 call_VM_leaf(thread_cache, entry_point, 1); | |
1169 } | |
1170 | |
1171 | |
1172 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) { | |
1173 mov(arg_1, O0); | |
1174 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); | |
1175 call_VM_leaf(thread_cache, entry_point, 2); | |
1176 } | |
1177 | |
1178 | |
1179 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) { | |
1180 mov(arg_1, O0); | |
1181 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); | |
1182 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument"); | |
1183 call_VM_leaf(thread_cache, entry_point, 3); | |
1184 } | |
1185 | |
1186 | |
1187 void MacroAssembler::get_vm_result(Register oop_result) { | |
1188 verify_thread(); | |
1189 Address vm_result_addr(G2_thread, 0, in_bytes(JavaThread::vm_result_offset())); | |
1190 ld_ptr( vm_result_addr, oop_result); | |
1191 st_ptr(G0, vm_result_addr); | |
1192 verify_oop(oop_result); | |
1193 } | |
1194 | |
1195 | |
1196 void MacroAssembler::get_vm_result_2(Register oop_result) { | |
1197 verify_thread(); | |
1198 Address vm_result_addr_2(G2_thread, 0, in_bytes(JavaThread::vm_result_2_offset())); | |
1199 ld_ptr(vm_result_addr_2, oop_result); | |
1200 st_ptr(G0, vm_result_addr_2); | |
1201 verify_oop(oop_result); | |
1202 } | |
1203 | |
1204 | |
1205 // We require that C code which does not return a value in vm_result will | |
1206 // leave it undisturbed. | |
1207 void MacroAssembler::set_vm_result(Register oop_result) { | |
1208 verify_thread(); | |
1209 Address vm_result_addr(G2_thread, 0, in_bytes(JavaThread::vm_result_offset())); | |
1210 verify_oop(oop_result); | |
1211 | |
1212 # ifdef ASSERT | |
1213 // Check that we are not overwriting any other oop. | |
1214 #ifdef CC_INTERP | |
1215 save_frame(0); | |
1216 #else | |
1217 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof | |
1218 #endif /* CC_INTERP */ | |
1219 ld_ptr(vm_result_addr, L0); | |
1220 tst(L0); | |
1221 restore(); | |
1222 breakpoint_trap(notZero, Assembler::ptr_cc); | |
1223 // } | |
1224 # endif | |
1225 | |
1226 st_ptr(oop_result, vm_result_addr); | |
1227 } | |
1228 | |
1229 | |
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1230 void MacroAssembler::card_table_write(jbyte* byte_map_base, |
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1231 Register tmp, Register obj) { |
0 | 1232 #ifdef _LP64 |
1233 srlx(obj, CardTableModRefBS::card_shift, obj); | |
1234 #else | |
1235 srl(obj, CardTableModRefBS::card_shift, obj); | |
1236 #endif | |
1237 assert( tmp != obj, "need separate temp reg"); | |
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1238 Address rs(tmp, (address)byte_map_base); |
0 | 1239 load_address(rs); |
1240 stb(G0, rs.base(), obj); | |
1241 } | |
1242 | |
1243 // %%% Note: The following six instructions have been moved, | |
1244 // unchanged, from assembler_sparc.inline.hpp. | |
1245 // They will be refactored at a later date. | |
1246 | |
1247 void MacroAssembler::sethi(intptr_t imm22a, | |
1248 Register d, | |
1249 bool ForceRelocatable, | |
1250 RelocationHolder const& rspec) { | |
1251 Address adr( d, (address)imm22a, rspec ); | |
1252 MacroAssembler::sethi( adr, ForceRelocatable ); | |
1253 } | |
1254 | |
1255 | |
1256 void MacroAssembler::sethi(Address& a, bool ForceRelocatable) { | |
1257 address save_pc; | |
1258 int shiftcnt; | |
1259 // if addr of local, do not need to load it | |
1260 assert(a.base() != FP && a.base() != SP, "just use ld or st for locals"); | |
1261 #ifdef _LP64 | |
1262 # ifdef CHECK_DELAY | |
1263 assert_not_delayed( (char *)"cannot put two instructions in delay slot" ); | |
1264 # endif | |
1265 v9_dep(); | |
1266 // ForceRelocatable = 1; | |
1267 save_pc = pc(); | |
1268 if (a.hi32() == 0 && a.low32() >= 0) { | |
1269 Assembler::sethi(a.low32(), a.base(), a.rspec()); | |
1270 } | |
1271 else if (a.hi32() == -1) { | |
1272 Assembler::sethi(~a.low32(), a.base(), a.rspec()); | |
1273 xor3(a.base(), ~low10(~0), a.base()); | |
1274 } | |
1275 else { | |
1276 Assembler::sethi(a.hi32(), a.base(), a.rspec() ); // 22 | |
1277 if ( a.hi32() & 0x3ff ) // Any bits? | |
1278 or3( a.base(), a.hi32() & 0x3ff ,a.base() ); // High 32 bits are now in low 32 | |
1279 if ( a.low32() & 0xFFFFFC00 ) { // done? | |
1280 if( (a.low32() >> 20) & 0xfff ) { // Any bits set? | |
1281 sllx(a.base(), 12, a.base()); // Make room for next 12 bits | |
1282 or3( a.base(), (a.low32() >> 20) & 0xfff,a.base() ); // Or in next 12 | |
1283 shiftcnt = 0; // We already shifted | |
1284 } | |
1285 else | |
1286 shiftcnt = 12; | |
1287 if( (a.low32() >> 10) & 0x3ff ) { | |
1288 sllx(a.base(), shiftcnt+10, a.base());// Make room for last 10 bits | |
1289 or3( a.base(), (a.low32() >> 10) & 0x3ff,a.base() ); // Or in next 10 | |
1290 shiftcnt = 0; | |
1291 } | |
1292 else | |
1293 shiftcnt = 10; | |
1294 sllx(a.base(), shiftcnt+10 , a.base()); // Shift leaving disp field 0'd | |
1295 } | |
1296 else | |
1297 sllx( a.base(), 32, a.base() ); | |
1298 } | |
1299 // Pad out the instruction sequence so it can be | |
1300 // patched later. | |
1301 if ( ForceRelocatable || (a.rtype() != relocInfo::none && | |
1302 a.rtype() != relocInfo::runtime_call_type) ) { | |
1303 while ( pc() < (save_pc + (7 * BytesPerInstWord )) ) | |
1304 nop(); | |
1305 } | |
1306 #else | |
1307 Assembler::sethi(a.hi(), a.base(), a.rspec()); | |
1308 #endif | |
1309 | |
1310 } | |
1311 | |
1312 int MacroAssembler::size_of_sethi(address a, bool worst_case) { | |
1313 #ifdef _LP64 | |
1314 if (worst_case) return 7; | |
1315 intptr_t iaddr = (intptr_t)a; | |
1316 int hi32 = (int)(iaddr >> 32); | |
1317 int lo32 = (int)(iaddr); | |
1318 int inst_count; | |
1319 if (hi32 == 0 && lo32 >= 0) | |
1320 inst_count = 1; | |
1321 else if (hi32 == -1) | |
1322 inst_count = 2; | |
1323 else { | |
1324 inst_count = 2; | |
1325 if ( hi32 & 0x3ff ) | |
1326 inst_count++; | |
1327 if ( lo32 & 0xFFFFFC00 ) { | |
1328 if( (lo32 >> 20) & 0xfff ) inst_count += 2; | |
1329 if( (lo32 >> 10) & 0x3ff ) inst_count += 2; | |
1330 } | |
1331 } | |
1332 return BytesPerInstWord * inst_count; | |
1333 #else | |
1334 return BytesPerInstWord; | |
1335 #endif | |
1336 } | |
1337 | |
1338 int MacroAssembler::worst_case_size_of_set() { | |
1339 return size_of_sethi(NULL, true) + 1; | |
1340 } | |
1341 | |
1342 void MacroAssembler::set(intptr_t value, Register d, | |
1343 RelocationHolder const& rspec) { | |
1344 Address val( d, (address)value, rspec); | |
1345 | |
1346 if ( rspec.type() == relocInfo::none ) { | |
1347 // can optimize | |
1348 if (-4096 <= value && value <= 4095) { | |
1349 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended) | |
1350 return; | |
1351 } | |
1352 if (inv_hi22(hi22(value)) == value) { | |
1353 sethi(val); | |
1354 return; | |
1355 } | |
1356 } | |
1357 assert_not_delayed( (char *)"cannot put two instructions in delay slot" ); | |
1358 sethi( val ); | |
1359 if (rspec.type() != relocInfo::none || (value & 0x3ff) != 0) { | |
1360 add( d, value & 0x3ff, d, rspec); | |
1361 } | |
1362 } | |
1363 | |
1364 void MacroAssembler::setsw(int value, Register d, | |
1365 RelocationHolder const& rspec) { | |
1366 Address val( d, (address)value, rspec); | |
1367 if ( rspec.type() == relocInfo::none ) { | |
1368 // can optimize | |
1369 if (-4096 <= value && value <= 4095) { | |
1370 or3(G0, value, d); | |
1371 return; | |
1372 } | |
1373 if (inv_hi22(hi22(value)) == value) { | |
1374 sethi( val ); | |
1375 #ifndef _LP64 | |
1376 if ( value < 0 ) { | |
1377 assert_not_delayed(); | |
1378 sra (d, G0, d); | |
1379 } | |
1380 #endif | |
1381 return; | |
1382 } | |
1383 } | |
1384 assert_not_delayed(); | |
1385 sethi( val ); | |
1386 add( d, value & 0x3ff, d, rspec); | |
1387 | |
1388 // (A negative value could be loaded in 2 insns with sethi/xor, | |
1389 // but it would take a more complex relocation.) | |
1390 #ifndef _LP64 | |
1391 if ( value < 0) | |
1392 sra(d, G0, d); | |
1393 #endif | |
1394 } | |
1395 | |
1396 // %%% End of moved six set instructions. | |
1397 | |
1398 | |
1399 void MacroAssembler::set64(jlong value, Register d, Register tmp) { | |
1400 assert_not_delayed(); | |
1401 v9_dep(); | |
1402 | |
1403 int hi = (int)(value >> 32); | |
1404 int lo = (int)(value & ~0); | |
1405 // (Matcher::isSimpleConstant64 knows about the following optimizations.) | |
1406 if (Assembler::is_simm13(lo) && value == lo) { | |
1407 or3(G0, lo, d); | |
1408 } else if (hi == 0) { | |
1409 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32 | |
1410 if (low10(lo) != 0) | |
1411 or3(d, low10(lo), d); | |
1412 } | |
1413 else if (hi == -1) { | |
1414 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32 | |
1415 xor3(d, low10(lo) ^ ~low10(~0), d); | |
1416 } | |
1417 else if (lo == 0) { | |
1418 if (Assembler::is_simm13(hi)) { | |
1419 or3(G0, hi, d); | |
1420 } else { | |
1421 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32 | |
1422 if (low10(hi) != 0) | |
1423 or3(d, low10(hi), d); | |
1424 } | |
1425 sllx(d, 32, d); | |
1426 } | |
1427 else { | |
1428 Assembler::sethi(hi, tmp); | |
1429 Assembler::sethi(lo, d); // macro assembler version sign-extends | |
1430 if (low10(hi) != 0) | |
1431 or3 (tmp, low10(hi), tmp); | |
1432 if (low10(lo) != 0) | |
1433 or3 ( d, low10(lo), d); | |
1434 sllx(tmp, 32, tmp); | |
1435 or3 (d, tmp, d); | |
1436 } | |
1437 } | |
1438 | |
1439 // compute size in bytes of sparc frame, given | |
1440 // number of extraWords | |
1441 int MacroAssembler::total_frame_size_in_bytes(int extraWords) { | |
1442 | |
1443 int nWords = frame::memory_parameter_word_sp_offset; | |
1444 | |
1445 nWords += extraWords; | |
1446 | |
1447 if (nWords & 1) ++nWords; // round up to double-word | |
1448 | |
1449 return nWords * BytesPerWord; | |
1450 } | |
1451 | |
1452 | |
1453 // save_frame: given number of "extra" words in frame, | |
1454 // issue approp. save instruction (p 200, v8 manual) | |
1455 | |
1456 void MacroAssembler::save_frame(int extraWords = 0) { | |
1457 int delta = -total_frame_size_in_bytes(extraWords); | |
1458 if (is_simm13(delta)) { | |
1459 save(SP, delta, SP); | |
1460 } else { | |
1461 set(delta, G3_scratch); | |
1462 save(SP, G3_scratch, SP); | |
1463 } | |
1464 } | |
1465 | |
1466 | |
1467 void MacroAssembler::save_frame_c1(int size_in_bytes) { | |
1468 if (is_simm13(-size_in_bytes)) { | |
1469 save(SP, -size_in_bytes, SP); | |
1470 } else { | |
1471 set(-size_in_bytes, G3_scratch); | |
1472 save(SP, G3_scratch, SP); | |
1473 } | |
1474 } | |
1475 | |
1476 | |
1477 void MacroAssembler::save_frame_and_mov(int extraWords, | |
1478 Register s1, Register d1, | |
1479 Register s2, Register d2) { | |
1480 assert_not_delayed(); | |
1481 | |
1482 // The trick here is to use precisely the same memory word | |
1483 // that trap handlers also use to save the register. | |
1484 // This word cannot be used for any other purpose, but | |
1485 // it works fine to save the register's value, whether or not | |
1486 // an interrupt flushes register windows at any given moment! | |
1487 Address s1_addr; | |
1488 if (s1->is_valid() && (s1->is_in() || s1->is_local())) { | |
1489 s1_addr = s1->address_in_saved_window(); | |
1490 st_ptr(s1, s1_addr); | |
1491 } | |
1492 | |
1493 Address s2_addr; | |
1494 if (s2->is_valid() && (s2->is_in() || s2->is_local())) { | |
1495 s2_addr = s2->address_in_saved_window(); | |
1496 st_ptr(s2, s2_addr); | |
1497 } | |
1498 | |
1499 save_frame(extraWords); | |
1500 | |
1501 if (s1_addr.base() == SP) { | |
1502 ld_ptr(s1_addr.after_save(), d1); | |
1503 } else if (s1->is_valid()) { | |
1504 mov(s1->after_save(), d1); | |
1505 } | |
1506 | |
1507 if (s2_addr.base() == SP) { | |
1508 ld_ptr(s2_addr.after_save(), d2); | |
1509 } else if (s2->is_valid()) { | |
1510 mov(s2->after_save(), d2); | |
1511 } | |
1512 } | |
1513 | |
1514 | |
1515 Address MacroAssembler::allocate_oop_address(jobject obj, Register d) { | |
1516 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
1517 int oop_index = oop_recorder()->allocate_index(obj); | |
1518 return Address(d, address(obj), oop_Relocation::spec(oop_index)); | |
1519 } | |
1520 | |
1521 | |
1522 Address MacroAssembler::constant_oop_address(jobject obj, Register d) { | |
1523 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); | |
1524 int oop_index = oop_recorder()->find_index(obj); | |
1525 return Address(d, address(obj), oop_Relocation::spec(oop_index)); | |
1526 } | |
1527 | |
1528 | |
1529 void MacroAssembler::align(int modulus) { | |
1530 while (offset() % modulus != 0) nop(); | |
1531 } | |
1532 | |
1533 | |
1534 void MacroAssembler::safepoint() { | |
1535 relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint)); | |
1536 } | |
1537 | |
1538 | |
1539 void RegistersForDebugging::print(outputStream* s) { | |
1540 int j; | |
1541 for ( j = 0; j < 8; ++j ) | |
1542 if ( j != 6 ) s->print_cr("i%d = 0x%.16lx", j, i[j]); | |
1543 else s->print_cr( "fp = 0x%.16lx", i[j]); | |
1544 s->cr(); | |
1545 | |
1546 for ( j = 0; j < 8; ++j ) | |
1547 s->print_cr("l%d = 0x%.16lx", j, l[j]); | |
1548 s->cr(); | |
1549 | |
1550 for ( j = 0; j < 8; ++j ) | |
1551 if ( j != 6 ) s->print_cr("o%d = 0x%.16lx", j, o[j]); | |
1552 else s->print_cr( "sp = 0x%.16lx", o[j]); | |
1553 s->cr(); | |
1554 | |
1555 for ( j = 0; j < 8; ++j ) | |
1556 s->print_cr("g%d = 0x%.16lx", j, g[j]); | |
1557 s->cr(); | |
1558 | |
1559 // print out floats with compression | |
1560 for (j = 0; j < 32; ) { | |
1561 jfloat val = f[j]; | |
1562 int last = j; | |
1563 for ( ; last+1 < 32; ++last ) { | |
1564 char b1[1024], b2[1024]; | |
1565 sprintf(b1, "%f", val); | |
1566 sprintf(b2, "%f", f[last+1]); | |
1567 if (strcmp(b1, b2)) | |
1568 break; | |
1569 } | |
1570 s->print("f%d", j); | |
1571 if ( j != last ) s->print(" - f%d", last); | |
1572 s->print(" = %f", val); | |
1573 s->fill_to(25); | |
1574 s->print_cr(" (0x%x)", val); | |
1575 j = last + 1; | |
1576 } | |
1577 s->cr(); | |
1578 | |
1579 // and doubles (evens only) | |
1580 for (j = 0; j < 32; ) { | |
1581 jdouble val = d[j]; | |
1582 int last = j; | |
1583 for ( ; last+1 < 32; ++last ) { | |
1584 char b1[1024], b2[1024]; | |
1585 sprintf(b1, "%f", val); | |
1586 sprintf(b2, "%f", d[last+1]); | |
1587 if (strcmp(b1, b2)) | |
1588 break; | |
1589 } | |
1590 s->print("d%d", 2 * j); | |
1591 if ( j != last ) s->print(" - d%d", last); | |
1592 s->print(" = %f", val); | |
1593 s->fill_to(30); | |
1594 s->print("(0x%x)", *(int*)&val); | |
1595 s->fill_to(42); | |
1596 s->print_cr("(0x%x)", *(1 + (int*)&val)); | |
1597 j = last + 1; | |
1598 } | |
1599 s->cr(); | |
1600 } | |
1601 | |
1602 void RegistersForDebugging::save_registers(MacroAssembler* a) { | |
1603 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0); | |
1604 a->flush_windows(); | |
1605 int i; | |
1606 for (i = 0; i < 8; ++i) { | |
1607 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i)); | |
1608 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i)); | |
1609 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i)); | |
1610 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i)); | |
1611 } | |
1612 for (i = 0; i < 32; ++i) { | |
1613 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i)); | |
1614 } | |
1615 for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) { | |
1616 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i)); | |
1617 } | |
1618 } | |
1619 | |
1620 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) { | |
1621 for (int i = 1; i < 8; ++i) { | |
1622 a->ld_ptr(r, g_offset(i), as_gRegister(i)); | |
1623 } | |
1624 for (int j = 0; j < 32; ++j) { | |
1625 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j)); | |
1626 } | |
1627 for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) { | |
1628 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k)); | |
1629 } | |
1630 } | |
1631 | |
1632 | |
1633 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
1634 void MacroAssembler::push_fTOS() { | |
1635 // %%%%%% need to implement this | |
1636 } | |
1637 | |
1638 // pops double TOS element from CPU stack and pushes on FPU stack | |
1639 void MacroAssembler::pop_fTOS() { | |
1640 // %%%%%% need to implement this | |
1641 } | |
1642 | |
1643 void MacroAssembler::empty_FPU_stack() { | |
1644 // %%%%%% need to implement this | |
1645 } | |
1646 | |
1647 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) { | |
1648 // plausibility check for oops | |
1649 if (!VerifyOops) return; | |
1650 | |
1651 if (reg == G0) return; // always NULL, which is always an oop | |
1652 | |
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1653 char buffer[64]; |
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1654 #ifdef COMPILER1 |
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1655 if (CommentedAssembly) { |
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1656 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset()); |
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1657 block_comment(buffer); |
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1658 } |
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1659 #endif |
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1660 |
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1661 int len = strlen(file) + strlen(msg) + 1 + 4; |
0 | 1662 sprintf(buffer, "%d", line); |
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1663 len += strlen(buffer); |
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1664 sprintf(buffer, " at offset %d ", offset()); |
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1665 len += strlen(buffer); |
0 | 1666 char * real_msg = new char[len]; |
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1667 sprintf(real_msg, "%s%s(%s:%d)", msg, buffer, file, line); |
0 | 1668 |
1669 // Call indirectly to solve generation ordering problem | |
1670 Address a(O7, (address)StubRoutines::verify_oop_subroutine_entry_address()); | |
1671 | |
1672 // Make some space on stack above the current register window. | |
1673 // Enough to hold 8 64-bit registers. | |
1674 add(SP,-8*8,SP); | |
1675 | |
1676 // Save some 64-bit registers; a normal 'save' chops the heads off | |
1677 // of 64-bit longs in the 32-bit build. | |
1678 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); | |
1679 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); | |
1680 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed | |
1681 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); | |
1682 | |
1683 set((intptr_t)real_msg, O1); | |
1684 // Load address to call to into O7 | |
1685 load_ptr_contents(a, O7); | |
1686 // Register call to verify_oop_subroutine | |
1687 callr(O7, G0); | |
1688 delayed()->nop(); | |
1689 // recover frame size | |
1690 add(SP, 8*8,SP); | |
1691 } | |
1692 | |
1693 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) { | |
1694 // plausibility check for oops | |
1695 if (!VerifyOops) return; | |
1696 | |
1697 char buffer[64]; | |
1698 sprintf(buffer, "%d", line); | |
1699 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer); | |
1700 sprintf(buffer, " at SP+%d ", addr.disp()); | |
1701 len += strlen(buffer); | |
1702 char * real_msg = new char[len]; | |
1703 sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line); | |
1704 | |
1705 // Call indirectly to solve generation ordering problem | |
1706 Address a(O7, (address)StubRoutines::verify_oop_subroutine_entry_address()); | |
1707 | |
1708 // Make some space on stack above the current register window. | |
1709 // Enough to hold 8 64-bit registers. | |
1710 add(SP,-8*8,SP); | |
1711 | |
1712 // Save some 64-bit registers; a normal 'save' chops the heads off | |
1713 // of 64-bit longs in the 32-bit build. | |
1714 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); | |
1715 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); | |
1716 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed | |
1717 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); | |
1718 | |
1719 set((intptr_t)real_msg, O1); | |
1720 // Load address to call to into O7 | |
1721 load_ptr_contents(a, O7); | |
1722 // Register call to verify_oop_subroutine | |
1723 callr(O7, G0); | |
1724 delayed()->nop(); | |
1725 // recover frame size | |
1726 add(SP, 8*8,SP); | |
1727 } | |
1728 | |
1729 // side-door communication with signalHandler in os_solaris.cpp | |
1730 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL }; | |
1731 | |
1732 // This macro is expanded just once; it creates shared code. Contract: | |
1733 // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY | |
1734 // registers, including flags. May not use a register 'save', as this blows | |
1735 // the high bits of the O-regs if they contain Long values. Acts as a 'leaf' | |
1736 // call. | |
1737 void MacroAssembler::verify_oop_subroutine() { | |
1738 assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" ); | |
1739 | |
1740 // Leaf call; no frame. | |
1741 Label succeed, fail, null_or_fail; | |
1742 | |
1743 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home). | |
1744 // O0 is now the oop to be checked. O7 is the return address. | |
1745 Register O0_obj = O0; | |
1746 | |
1747 // Save some more registers for temps. | |
1748 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8); | |
1749 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8); | |
1750 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8); | |
1751 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8); | |
1752 | |
1753 // Save flags | |
1754 Register O5_save_flags = O5; | |
1755 rdccr( O5_save_flags ); | |
1756 | |
1757 { // count number of verifies | |
1758 Register O2_adr = O2; | |
1759 Register O3_accum = O3; | |
1760 Address count_addr( O2_adr, (address) StubRoutines::verify_oop_count_addr() ); | |
1761 sethi(count_addr); | |
1762 ld(count_addr, O3_accum); | |
1763 inc(O3_accum); | |
1764 st(O3_accum, count_addr); | |
1765 } | |
1766 | |
1767 Register O2_mask = O2; | |
1768 Register O3_bits = O3; | |
1769 Register O4_temp = O4; | |
1770 | |
1771 // mark lower end of faulting range | |
1772 assert(_verify_oop_implicit_branch[0] == NULL, "set once"); | |
1773 _verify_oop_implicit_branch[0] = pc(); | |
1774 | |
1775 // We can't check the mark oop because it could be in the process of | |
1776 // locking or unlocking while this is running. | |
1777 set(Universe::verify_oop_mask (), O2_mask); | |
1778 set(Universe::verify_oop_bits (), O3_bits); | |
1779 | |
1780 // assert((obj & oop_mask) == oop_bits); | |
1781 and3(O0_obj, O2_mask, O4_temp); | |
1782 cmp(O4_temp, O3_bits); | |
1783 brx(notEqual, false, pn, null_or_fail); | |
1784 delayed()->nop(); | |
1785 | |
1786 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) { | |
1787 // the null_or_fail case is useless; must test for null separately | |
1788 br_null(O0_obj, false, pn, succeed); | |
1789 delayed()->nop(); | |
1790 } | |
1791 | |
1792 // Check the klassOop of this object for being in the right area of memory. | |
1793 // Cannot do the load in the delay above slot in case O0 is null | |
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1794 load_klass(O0_obj, O0_obj); |
0 | 1795 // assert((klass & klass_mask) == klass_bits); |
1796 if( Universe::verify_klass_mask() != Universe::verify_oop_mask() ) | |
1797 set(Universe::verify_klass_mask(), O2_mask); | |
1798 if( Universe::verify_klass_bits() != Universe::verify_oop_bits() ) | |
1799 set(Universe::verify_klass_bits(), O3_bits); | |
1800 and3(O0_obj, O2_mask, O4_temp); | |
1801 cmp(O4_temp, O3_bits); | |
1802 brx(notEqual, false, pn, fail); | |
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1803 delayed()->nop(); |
0 | 1804 // Check the klass's klass |
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1805 load_klass(O0_obj, O0_obj); |
0 | 1806 and3(O0_obj, O2_mask, O4_temp); |
1807 cmp(O4_temp, O3_bits); | |
1808 brx(notEqual, false, pn, fail); | |
1809 delayed()->wrccr( O5_save_flags ); // Restore CCR's | |
1810 | |
1811 // mark upper end of faulting range | |
1812 _verify_oop_implicit_branch[1] = pc(); | |
1813 | |
1814 //----------------------- | |
1815 // all tests pass | |
1816 bind(succeed); | |
1817 | |
1818 // Restore prior 64-bit registers | |
1819 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0); | |
1820 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1); | |
1821 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2); | |
1822 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3); | |
1823 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4); | |
1824 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5); | |
1825 | |
1826 retl(); // Leaf return; restore prior O7 in delay slot | |
1827 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7); | |
1828 | |
1829 //----------------------- | |
1830 bind(null_or_fail); // nulls are less common but OK | |
1831 br_null(O0_obj, false, pt, succeed); | |
1832 delayed()->wrccr( O5_save_flags ); // Restore CCR's | |
1833 | |
1834 //----------------------- | |
1835 // report failure: | |
1836 bind(fail); | |
1837 _verify_oop_implicit_branch[2] = pc(); | |
1838 | |
1839 wrccr( O5_save_flags ); // Restore CCR's | |
1840 | |
1841 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); | |
1842 | |
1843 // stop_subroutine expects message pointer in I1. | |
1844 mov(I1, O1); | |
1845 | |
1846 // Restore prior 64-bit registers | |
1847 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0); | |
1848 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1); | |
1849 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2); | |
1850 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3); | |
1851 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4); | |
1852 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5); | |
1853 | |
1854 // factor long stop-sequence into subroutine to save space | |
1855 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); | |
1856 | |
1857 // call indirectly to solve generation ordering problem | |
1858 Address a(O5, (address)StubRoutines::Sparc::stop_subroutine_entry_address()); | |
1859 load_ptr_contents(a, O5); | |
1860 jmpl(O5, 0, O7); | |
1861 delayed()->nop(); | |
1862 } | |
1863 | |
1864 | |
1865 void MacroAssembler::stop(const char* msg) { | |
1866 // save frame first to get O7 for return address | |
1867 // add one word to size in case struct is odd number of words long | |
1868 // It must be doubleword-aligned for storing doubles into it. | |
1869 | |
1870 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); | |
1871 | |
1872 // stop_subroutine expects message pointer in I1. | |
1873 set((intptr_t)msg, O1); | |
1874 | |
1875 // factor long stop-sequence into subroutine to save space | |
1876 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); | |
1877 | |
1878 // call indirectly to solve generation ordering problem | |
1879 Address a(O5, (address)StubRoutines::Sparc::stop_subroutine_entry_address()); | |
1880 load_ptr_contents(a, O5); | |
1881 jmpl(O5, 0, O7); | |
1882 delayed()->nop(); | |
1883 | |
1884 breakpoint_trap(); // make stop actually stop rather than writing | |
1885 // unnoticeable results in the output files. | |
1886 | |
1887 // restore(); done in callee to save space! | |
1888 } | |
1889 | |
1890 | |
1891 void MacroAssembler::warn(const char* msg) { | |
1892 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); | |
1893 RegistersForDebugging::save_registers(this); | |
1894 mov(O0, L0); | |
1895 set((intptr_t)msg, O0); | |
1896 call( CAST_FROM_FN_PTR(address, warning) ); | |
1897 delayed()->nop(); | |
1898 // ret(); | |
1899 // delayed()->restore(); | |
1900 RegistersForDebugging::restore_registers(this, L0); | |
1901 restore(); | |
1902 } | |
1903 | |
1904 | |
1905 void MacroAssembler::untested(const char* what) { | |
1906 // We must be able to turn interactive prompting off | |
1907 // in order to run automated test scripts on the VM | |
1908 // Use the flag ShowMessageBoxOnError | |
1909 | |
1910 char* b = new char[1024]; | |
1911 sprintf(b, "untested: %s", what); | |
1912 | |
1913 if ( ShowMessageBoxOnError ) stop(b); | |
1914 else warn(b); | |
1915 } | |
1916 | |
1917 | |
1918 void MacroAssembler::stop_subroutine() { | |
1919 RegistersForDebugging::save_registers(this); | |
1920 | |
1921 // for the sake of the debugger, stick a PC on the current frame | |
1922 // (this assumes that the caller has performed an extra "save") | |
1923 mov(I7, L7); | |
1924 add(O7, -7 * BytesPerInt, I7); | |
1925 | |
1926 save_frame(); // one more save to free up another O7 register | |
1927 mov(I0, O1); // addr of reg save area | |
1928 | |
1929 // We expect pointer to message in I1. Caller must set it up in O1 | |
1930 mov(I1, O0); // get msg | |
1931 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); | |
1932 delayed()->nop(); | |
1933 | |
1934 restore(); | |
1935 | |
1936 RegistersForDebugging::restore_registers(this, O0); | |
1937 | |
1938 save_frame(0); | |
1939 call(CAST_FROM_FN_PTR(address,breakpoint)); | |
1940 delayed()->nop(); | |
1941 restore(); | |
1942 | |
1943 mov(L7, I7); | |
1944 retl(); | |
1945 delayed()->restore(); // see stop above | |
1946 } | |
1947 | |
1948 | |
1949 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) { | |
1950 if ( ShowMessageBoxOnError ) { | |
1951 JavaThreadState saved_state = JavaThread::current()->thread_state(); | |
1952 JavaThread::current()->set_thread_state(_thread_in_vm); | |
1953 { | |
1954 // In order to get locks work, we need to fake a in_VM state | |
1955 ttyLocker ttyl; | |
1956 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg); | |
1957 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { | |
1958 ::tty->print_cr("Interpreter::bytecode_counter = %d", BytecodeCounter::counter_value()); | |
1959 } | |
1960 if (os::message_box(msg, "Execution stopped, print registers?")) | |
1961 regs->print(::tty); | |
1962 } | |
1963 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state); | |
1964 } | |
1965 else | |
1966 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); | |
1967 assert(false, "error"); | |
1968 } | |
1969 | |
1970 | |
1971 #ifndef PRODUCT | |
1972 void MacroAssembler::test() { | |
1973 ResourceMark rm; | |
1974 | |
1975 CodeBuffer cb("test", 10000, 10000); | |
1976 MacroAssembler* a = new MacroAssembler(&cb); | |
1977 VM_Version::allow_all(); | |
1978 a->test_v9(); | |
1979 a->test_v8_onlys(); | |
1980 VM_Version::revert(); | |
1981 | |
1982 StubRoutines::Sparc::test_stop_entry()(); | |
1983 } | |
1984 #endif | |
1985 | |
1986 | |
1987 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) { | |
1988 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words? | |
1989 Label no_extras; | |
1990 br( negative, true, pt, no_extras ); // if neg, clear reg | |
1991 delayed()->set( 0, Rresult); // annuled, so only if taken | |
1992 bind( no_extras ); | |
1993 } | |
1994 | |
1995 | |
1996 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) { | |
1997 #ifdef _LP64 | |
1998 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult); | |
1999 #else | |
2000 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult); | |
2001 #endif | |
2002 bclr(1, Rresult); | |
2003 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes | |
2004 } | |
2005 | |
2006 | |
2007 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) { | |
2008 calc_frame_size(Rextra_words, Rresult); | |
2009 neg(Rresult); | |
2010 save(SP, Rresult, SP); | |
2011 } | |
2012 | |
2013 | |
2014 // --------------------------------------------------------- | |
2015 Assembler::RCondition cond2rcond(Assembler::Condition c) { | |
2016 switch (c) { | |
2017 /*case zero: */ | |
2018 case Assembler::equal: return Assembler::rc_z; | |
2019 case Assembler::lessEqual: return Assembler::rc_lez; | |
2020 case Assembler::less: return Assembler::rc_lz; | |
2021 /*case notZero:*/ | |
2022 case Assembler::notEqual: return Assembler::rc_nz; | |
2023 case Assembler::greater: return Assembler::rc_gz; | |
2024 case Assembler::greaterEqual: return Assembler::rc_gez; | |
2025 } | |
2026 ShouldNotReachHere(); | |
2027 return Assembler::rc_z; | |
2028 } | |
2029 | |
2030 // compares register with zero and branches. NOT FOR USE WITH 64-bit POINTERS | |
2031 void MacroAssembler::br_zero( Condition c, bool a, Predict p, Register s1, Label& L) { | |
2032 tst(s1); | |
2033 br (c, a, p, L); | |
2034 } | |
2035 | |
2036 | |
2037 // Compares a pointer register with zero and branches on null. | |
2038 // Does a test & branch on 32-bit systems and a register-branch on 64-bit. | |
2039 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) { | |
2040 assert_not_delayed(); | |
2041 #ifdef _LP64 | |
2042 bpr( rc_z, a, p, s1, L ); | |
2043 #else | |
2044 tst(s1); | |
2045 br ( zero, a, p, L ); | |
2046 #endif | |
2047 } | |
2048 | |
2049 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) { | |
2050 assert_not_delayed(); | |
2051 #ifdef _LP64 | |
2052 bpr( rc_nz, a, p, s1, L ); | |
2053 #else | |
2054 tst(s1); | |
2055 br ( notZero, a, p, L ); | |
2056 #endif | |
2057 } | |
2058 | |
342
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2059 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p, |
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2060 Register s1, address d, |
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2061 relocInfo::relocType rt ) { |
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2062 if (VM_Version::v9_instructions_work()) { |
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2063 bpr(rc, a, p, s1, d, rt); |
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2064 } else { |
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2065 tst(s1); |
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2066 br(reg_cond_to_cc_cond(rc), a, p, d, rt); |
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2067 } |
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2068 } |
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2069 |
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2070 void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p, |
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2071 Register s1, Label& L ) { |
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2072 if (VM_Version::v9_instructions_work()) { |
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2073 bpr(rc, a, p, s1, L); |
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2074 } else { |
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2075 tst(s1); |
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2076 br(reg_cond_to_cc_cond(rc), a, p, L); |
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2077 } |
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2078 } |
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2079 |
0 | 2080 |
2081 // instruction sequences factored across compiler & interpreter | |
2082 | |
2083 | |
2084 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low, | |
2085 Register Rb_hi, Register Rb_low, | |
2086 Register Rresult) { | |
2087 | |
2088 Label check_low_parts, done; | |
2089 | |
2090 cmp(Ra_hi, Rb_hi ); // compare hi parts | |
2091 br(equal, true, pt, check_low_parts); | |
2092 delayed()->cmp(Ra_low, Rb_low); // test low parts | |
2093 | |
2094 // And, with an unsigned comparison, it does not matter if the numbers | |
2095 // are negative or not. | |
2096 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff. | |
2097 // The second one is bigger (unsignedly). | |
2098 | |
2099 // Other notes: The first move in each triplet can be unconditional | |
2100 // (and therefore probably prefetchable). | |
2101 // And the equals case for the high part does not need testing, | |
2102 // since that triplet is reached only after finding the high halves differ. | |
2103 | |
2104 if (VM_Version::v9_instructions_work()) { | |
2105 | |
2106 mov ( -1, Rresult); | |
2107 ba( false, done ); delayed()-> movcc(greater, false, icc, 1, Rresult); | |
2108 } | |
2109 else { | |
2110 br(less, true, pt, done); delayed()-> set(-1, Rresult); | |
2111 br(greater, true, pt, done); delayed()-> set( 1, Rresult); | |
2112 } | |
2113 | |
2114 bind( check_low_parts ); | |
2115 | |
2116 if (VM_Version::v9_instructions_work()) { | |
2117 mov( -1, Rresult); | |
2118 movcc(equal, false, icc, 0, Rresult); | |
2119 movcc(greaterUnsigned, false, icc, 1, Rresult); | |
2120 } | |
2121 else { | |
2122 set(-1, Rresult); | |
2123 br(equal, true, pt, done); delayed()->set( 0, Rresult); | |
2124 br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult); | |
2125 } | |
2126 bind( done ); | |
2127 } | |
2128 | |
2129 void MacroAssembler::lneg( Register Rhi, Register Rlow ) { | |
2130 subcc( G0, Rlow, Rlow ); | |
2131 subc( G0, Rhi, Rhi ); | |
2132 } | |
2133 | |
2134 void MacroAssembler::lshl( Register Rin_high, Register Rin_low, | |
2135 Register Rcount, | |
2136 Register Rout_high, Register Rout_low, | |
2137 Register Rtemp ) { | |
2138 | |
2139 | |
2140 Register Ralt_count = Rtemp; | |
2141 Register Rxfer_bits = Rtemp; | |
2142 | |
2143 assert( Ralt_count != Rin_high | |
2144 && Ralt_count != Rin_low | |
2145 && Ralt_count != Rcount | |
2146 && Rxfer_bits != Rin_low | |
2147 && Rxfer_bits != Rin_high | |
2148 && Rxfer_bits != Rcount | |
2149 && Rxfer_bits != Rout_low | |
2150 && Rout_low != Rin_high, | |
2151 "register alias checks"); | |
2152 | |
2153 Label big_shift, done; | |
2154 | |
2155 // This code can be optimized to use the 64 bit shifts in V9. | |
2156 // Here we use the 32 bit shifts. | |
2157 | |
2158 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits | |
2159 subcc(Rcount, 31, Ralt_count); | |
2160 br(greater, true, pn, big_shift); | |
2161 delayed()-> | |
2162 dec(Ralt_count); | |
2163 | |
2164 // shift < 32 bits, Ralt_count = Rcount-31 | |
2165 | |
2166 // We get the transfer bits by shifting right by 32-count the low | |
2167 // register. This is done by shifting right by 31-count and then by one | |
2168 // more to take care of the special (rare) case where count is zero | |
2169 // (shifting by 32 would not work). | |
2170 | |
2171 neg( Ralt_count ); | |
2172 | |
2173 // The order of the next two instructions is critical in the case where | |
2174 // Rin and Rout are the same and should not be reversed. | |
2175 | |
2176 srl( Rin_low, Ralt_count, Rxfer_bits ); // shift right by 31-count | |
2177 if (Rcount != Rout_low) { | |
2178 sll( Rin_low, Rcount, Rout_low ); // low half | |
2179 } | |
2180 sll( Rin_high, Rcount, Rout_high ); | |
2181 if (Rcount == Rout_low) { | |
2182 sll( Rin_low, Rcount, Rout_low ); // low half | |
2183 } | |
2184 srl( Rxfer_bits, 1, Rxfer_bits ); // shift right by one more | |
2185 ba (false, done); | |
2186 delayed()-> | |
2187 or3( Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low | |
2188 | |
2189 // shift >= 32 bits, Ralt_count = Rcount-32 | |
2190 bind(big_shift); | |
2191 sll( Rin_low, Ralt_count, Rout_high ); | |
2192 clr( Rout_low ); | |
2193 | |
2194 bind(done); | |
2195 } | |
2196 | |
2197 | |
2198 void MacroAssembler::lshr( Register Rin_high, Register Rin_low, | |
2199 Register Rcount, | |
2200 Register Rout_high, Register Rout_low, | |
2201 Register Rtemp ) { | |
2202 | |
2203 Register Ralt_count = Rtemp; | |
2204 Register Rxfer_bits = Rtemp; | |
2205 | |
2206 assert( Ralt_count != Rin_high | |
2207 && Ralt_count != Rin_low | |
2208 && Ralt_count != Rcount | |
2209 && Rxfer_bits != Rin_low | |
2210 && Rxfer_bits != Rin_high | |
2211 && Rxfer_bits != Rcount | |
2212 && Rxfer_bits != Rout_high | |
2213 && Rout_high != Rin_low, | |
2214 "register alias checks"); | |
2215 | |
2216 Label big_shift, done; | |
2217 | |
2218 // This code can be optimized to use the 64 bit shifts in V9. | |
2219 // Here we use the 32 bit shifts. | |
2220 | |
2221 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits | |
2222 subcc(Rcount, 31, Ralt_count); | |
2223 br(greater, true, pn, big_shift); | |
2224 delayed()->dec(Ralt_count); | |
2225 | |
2226 // shift < 32 bits, Ralt_count = Rcount-31 | |
2227 | |
2228 // We get the transfer bits by shifting left by 32-count the high | |
2229 // register. This is done by shifting left by 31-count and then by one | |
2230 // more to take care of the special (rare) case where count is zero | |
2231 // (shifting by 32 would not work). | |
2232 | |
2233 neg( Ralt_count ); | |
2234 if (Rcount != Rout_low) { | |
2235 srl( Rin_low, Rcount, Rout_low ); | |
2236 } | |
2237 | |
2238 // The order of the next two instructions is critical in the case where | |
2239 // Rin and Rout are the same and should not be reversed. | |
2240 | |
2241 sll( Rin_high, Ralt_count, Rxfer_bits ); // shift left by 31-count | |
2242 sra( Rin_high, Rcount, Rout_high ); // high half | |
2243 sll( Rxfer_bits, 1, Rxfer_bits ); // shift left by one more | |
2244 if (Rcount == Rout_low) { | |
2245 srl( Rin_low, Rcount, Rout_low ); | |
2246 } | |
2247 ba (false, done); | |
2248 delayed()-> | |
2249 or3( Rout_low, Rxfer_bits, Rout_low ); // new low value: or shifted old low part and xfer from high | |
2250 | |
2251 // shift >= 32 bits, Ralt_count = Rcount-32 | |
2252 bind(big_shift); | |
2253 | |
2254 sra( Rin_high, Ralt_count, Rout_low ); | |
2255 sra( Rin_high, 31, Rout_high ); // sign into hi | |
2256 | |
2257 bind( done ); | |
2258 } | |
2259 | |
2260 | |
2261 | |
2262 void MacroAssembler::lushr( Register Rin_high, Register Rin_low, | |
2263 Register Rcount, | |
2264 Register Rout_high, Register Rout_low, | |
2265 Register Rtemp ) { | |
2266 | |
2267 Register Ralt_count = Rtemp; | |
2268 Register Rxfer_bits = Rtemp; | |
2269 | |
2270 assert( Ralt_count != Rin_high | |
2271 && Ralt_count != Rin_low | |
2272 && Ralt_count != Rcount | |
2273 && Rxfer_bits != Rin_low | |
2274 && Rxfer_bits != Rin_high | |
2275 && Rxfer_bits != Rcount | |
2276 && Rxfer_bits != Rout_high | |
2277 && Rout_high != Rin_low, | |
2278 "register alias checks"); | |
2279 | |
2280 Label big_shift, done; | |
2281 | |
2282 // This code can be optimized to use the 64 bit shifts in V9. | |
2283 // Here we use the 32 bit shifts. | |
2284 | |
2285 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits | |
2286 subcc(Rcount, 31, Ralt_count); | |
2287 br(greater, true, pn, big_shift); | |
2288 delayed()->dec(Ralt_count); | |
2289 | |
2290 // shift < 32 bits, Ralt_count = Rcount-31 | |
2291 | |
2292 // We get the transfer bits by shifting left by 32-count the high | |
2293 // register. This is done by shifting left by 31-count and then by one | |
2294 // more to take care of the special (rare) case where count is zero | |
2295 // (shifting by 32 would not work). | |
2296 | |
2297 neg( Ralt_count ); | |
2298 if (Rcount != Rout_low) { | |
2299 srl( Rin_low, Rcount, Rout_low ); | |
2300 } | |
2301 | |
2302 // The order of the next two instructions is critical in the case where | |
2303 // Rin and Rout are the same and should not be reversed. | |
2304 | |
2305 sll( Rin_high, Ralt_count, Rxfer_bits ); // shift left by 31-count | |
2306 srl( Rin_high, Rcount, Rout_high ); // high half | |
2307 sll( Rxfer_bits, 1, Rxfer_bits ); // shift left by one more | |
2308 if (Rcount == Rout_low) { | |
2309 srl( Rin_low, Rcount, Rout_low ); | |
2310 } | |
2311 ba (false, done); | |
2312 delayed()-> | |
2313 or3( Rout_low, Rxfer_bits, Rout_low ); // new low value: or shifted old low part and xfer from high | |
2314 | |
2315 // shift >= 32 bits, Ralt_count = Rcount-32 | |
2316 bind(big_shift); | |
2317 | |
2318 srl( Rin_high, Ralt_count, Rout_low ); | |
2319 clr( Rout_high ); | |
2320 | |
2321 bind( done ); | |
2322 } | |
2323 | |
2324 #ifdef _LP64 | |
2325 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) { | |
2326 cmp(Ra, Rb); | |
2327 mov( -1, Rresult); | |
2328 movcc(equal, false, xcc, 0, Rresult); | |
2329 movcc(greater, false, xcc, 1, Rresult); | |
2330 } | |
2331 #endif | |
2332 | |
2333 | |
2334 void MacroAssembler::float_cmp( bool is_float, int unordered_result, | |
2335 FloatRegister Fa, FloatRegister Fb, | |
2336 Register Rresult) { | |
2337 | |
2338 fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb); | |
2339 | |
2340 Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less; | |
2341 Condition eq = f_equal; | |
2342 Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater; | |
2343 | |
2344 if (VM_Version::v9_instructions_work()) { | |
2345 | |
2346 mov( -1, Rresult ); | |
2347 movcc( eq, true, fcc0, 0, Rresult ); | |
2348 movcc( gt, true, fcc0, 1, Rresult ); | |
2349 | |
2350 } else { | |
2351 Label done; | |
2352 | |
2353 set( -1, Rresult ); | |
2354 //fb(lt, true, pn, done); delayed()->set( -1, Rresult ); | |
2355 fb( eq, true, pn, done); delayed()->set( 0, Rresult ); | |
2356 fb( gt, true, pn, done); delayed()->set( 1, Rresult ); | |
2357 | |
2358 bind (done); | |
2359 } | |
2360 } | |
2361 | |
2362 | |
2363 void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) | |
2364 { | |
2365 if (VM_Version::v9_instructions_work()) { | |
2366 Assembler::fneg(w, s, d); | |
2367 } else { | |
2368 if (w == FloatRegisterImpl::S) { | |
2369 Assembler::fneg(w, s, d); | |
2370 } else if (w == FloatRegisterImpl::D) { | |
2371 // number() does a sanity check on the alignment. | |
2372 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && | |
2373 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); | |
2374 | |
2375 Assembler::fneg(FloatRegisterImpl::S, s, d); | |
2376 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2377 } else { | |
2378 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); | |
2379 | |
2380 // number() does a sanity check on the alignment. | |
2381 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && | |
2382 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); | |
2383 | |
2384 Assembler::fneg(FloatRegisterImpl::S, s, d); | |
2385 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2386 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); | |
2387 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); | |
2388 } | |
2389 } | |
2390 } | |
2391 | |
2392 void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) | |
2393 { | |
2394 if (VM_Version::v9_instructions_work()) { | |
2395 Assembler::fmov(w, s, d); | |
2396 } else { | |
2397 if (w == FloatRegisterImpl::S) { | |
2398 Assembler::fmov(w, s, d); | |
2399 } else if (w == FloatRegisterImpl::D) { | |
2400 // number() does a sanity check on the alignment. | |
2401 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && | |
2402 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); | |
2403 | |
2404 Assembler::fmov(FloatRegisterImpl::S, s, d); | |
2405 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2406 } else { | |
2407 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); | |
2408 | |
2409 // number() does a sanity check on the alignment. | |
2410 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && | |
2411 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); | |
2412 | |
2413 Assembler::fmov(FloatRegisterImpl::S, s, d); | |
2414 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2415 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); | |
2416 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); | |
2417 } | |
2418 } | |
2419 } | |
2420 | |
2421 void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) | |
2422 { | |
2423 if (VM_Version::v9_instructions_work()) { | |
2424 Assembler::fabs(w, s, d); | |
2425 } else { | |
2426 if (w == FloatRegisterImpl::S) { | |
2427 Assembler::fabs(w, s, d); | |
2428 } else if (w == FloatRegisterImpl::D) { | |
2429 // number() does a sanity check on the alignment. | |
2430 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && | |
2431 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); | |
2432 | |
2433 Assembler::fabs(FloatRegisterImpl::S, s, d); | |
2434 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2435 } else { | |
2436 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); | |
2437 | |
2438 // number() does a sanity check on the alignment. | |
2439 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && | |
2440 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); | |
2441 | |
2442 Assembler::fabs(FloatRegisterImpl::S, s, d); | |
2443 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); | |
2444 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); | |
2445 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); | |
2446 } | |
2447 } | |
2448 } | |
2449 | |
2450 void MacroAssembler::save_all_globals_into_locals() { | |
2451 mov(G1,L1); | |
2452 mov(G2,L2); | |
2453 mov(G3,L3); | |
2454 mov(G4,L4); | |
2455 mov(G5,L5); | |
2456 mov(G6,L6); | |
2457 mov(G7,L7); | |
2458 } | |
2459 | |
2460 void MacroAssembler::restore_globals_from_locals() { | |
2461 mov(L1,G1); | |
2462 mov(L2,G2); | |
2463 mov(L3,G3); | |
2464 mov(L4,G4); | |
2465 mov(L5,G5); | |
2466 mov(L6,G6); | |
2467 mov(L7,G7); | |
2468 } | |
2469 | |
2470 // Use for 64 bit operation. | |
2471 void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) | |
2472 { | |
2473 // store ptr_reg as the new top value | |
2474 #ifdef _LP64 | |
2475 casx(top_ptr_reg, top_reg, ptr_reg); | |
2476 #else | |
2477 cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm); | |
2478 #endif // _LP64 | |
2479 } | |
2480 | |
2481 // [RGV] This routine does not handle 64 bit operations. | |
2482 // use casx_under_lock() or casx directly!!! | |
2483 void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) | |
2484 { | |
2485 // store ptr_reg as the new top value | |
2486 if (VM_Version::v9_instructions_work()) { | |
2487 cas(top_ptr_reg, top_reg, ptr_reg); | |
2488 } else { | |
2489 | |
2490 // If the register is not an out nor global, it is not visible | |
2491 // after the save. Allocate a register for it, save its | |
2492 // value in the register save area (the save may not flush | |
2493 // registers to the save area). | |
2494 | |
2495 Register top_ptr_reg_after_save; | |
2496 Register top_reg_after_save; | |
2497 Register ptr_reg_after_save; | |
2498 | |
2499 if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) { | |
2500 top_ptr_reg_after_save = top_ptr_reg->after_save(); | |
2501 } else { | |
2502 Address reg_save_addr = top_ptr_reg->address_in_saved_window(); | |
2503 top_ptr_reg_after_save = L0; | |
2504 st(top_ptr_reg, reg_save_addr); | |
2505 } | |
2506 | |
2507 if (top_reg->is_out() || top_reg->is_global()) { | |
2508 top_reg_after_save = top_reg->after_save(); | |
2509 } else { | |
2510 Address reg_save_addr = top_reg->address_in_saved_window(); | |
2511 top_reg_after_save = L1; | |
2512 st(top_reg, reg_save_addr); | |
2513 } | |
2514 | |
2515 if (ptr_reg->is_out() || ptr_reg->is_global()) { | |
2516 ptr_reg_after_save = ptr_reg->after_save(); | |
2517 } else { | |
2518 Address reg_save_addr = ptr_reg->address_in_saved_window(); | |
2519 ptr_reg_after_save = L2; | |
2520 st(ptr_reg, reg_save_addr); | |
2521 } | |
2522 | |
2523 const Register& lock_reg = L3; | |
2524 const Register& lock_ptr_reg = L4; | |
2525 const Register& value_reg = L5; | |
2526 const Register& yield_reg = L6; | |
2527 const Register& yieldall_reg = L7; | |
2528 | |
2529 save_frame(); | |
2530 | |
2531 if (top_ptr_reg_after_save == L0) { | |
2532 ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save); | |
2533 } | |
2534 | |
2535 if (top_reg_after_save == L1) { | |
2536 ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save); | |
2537 } | |
2538 | |
2539 if (ptr_reg_after_save == L2) { | |
2540 ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save); | |
2541 } | |
2542 | |
2543 Label(retry_get_lock); | |
2544 Label(not_same); | |
2545 Label(dont_yield); | |
2546 | |
2547 assert(lock_addr, "lock_address should be non null for v8"); | |
2548 set((intptr_t)lock_addr, lock_ptr_reg); | |
2549 // Initialize yield counter | |
2550 mov(G0,yield_reg); | |
2551 mov(G0, yieldall_reg); | |
2552 set(StubRoutines::Sparc::locked, lock_reg); | |
2553 | |
2554 bind(retry_get_lock); | |
2555 cmp(yield_reg, V8AtomicOperationUnderLockSpinCount); | |
2556 br(Assembler::less, false, Assembler::pt, dont_yield); | |
2557 delayed()->nop(); | |
2558 | |
2559 if(use_call_vm) { | |
2560 Untested("Need to verify global reg consistancy"); | |
2561 call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg); | |
2562 } else { | |
2563 // Save the regs and make space for a C call | |
2564 save(SP, -96, SP); | |
2565 save_all_globals_into_locals(); | |
2566 call(CAST_FROM_FN_PTR(address,os::yield_all)); | |
2567 delayed()->mov(yieldall_reg, O0); | |
2568 restore_globals_from_locals(); | |
2569 restore(); | |
2570 } | |
2571 | |
2572 // reset the counter | |
2573 mov(G0,yield_reg); | |
2574 add(yieldall_reg, 1, yieldall_reg); | |
2575 | |
2576 bind(dont_yield); | |
2577 // try to get lock | |
2578 swap(lock_ptr_reg, 0, lock_reg); | |
2579 | |
2580 // did we get the lock? | |
2581 cmp(lock_reg, StubRoutines::Sparc::unlocked); | |
2582 br(Assembler::notEqual, true, Assembler::pn, retry_get_lock); | |
2583 delayed()->add(yield_reg,1,yield_reg); | |
2584 | |
2585 // yes, got lock. do we have the same top? | |
2586 ld(top_ptr_reg_after_save, 0, value_reg); | |
2587 cmp(value_reg, top_reg_after_save); | |
2588 br(Assembler::notEqual, false, Assembler::pn, not_same); | |
2589 delayed()->nop(); | |
2590 | |
2591 // yes, same top. | |
2592 st(ptr_reg_after_save, top_ptr_reg_after_save, 0); | |
2593 membar(Assembler::StoreStore); | |
2594 | |
2595 bind(not_same); | |
2596 mov(value_reg, ptr_reg_after_save); | |
2597 st(lock_reg, lock_ptr_reg, 0); // unlock | |
2598 | |
2599 restore(); | |
2600 } | |
2601 } | |
2602 | |
2603 void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg, | |
2604 Label& done, Label* slow_case, | |
2605 BiasedLockingCounters* counters) { | |
2606 assert(UseBiasedLocking, "why call this otherwise?"); | |
2607 | |
2608 if (PrintBiasedLockingStatistics) { | |
2609 assert_different_registers(obj_reg, mark_reg, temp_reg, O7); | |
2610 if (counters == NULL) | |
2611 counters = BiasedLocking::counters(); | |
2612 } | |
2613 | |
2614 Label cas_label; | |
2615 | |
2616 // Biased locking | |
2617 // See whether the lock is currently biased toward our thread and | |
2618 // whether the epoch is still valid | |
2619 // Note that the runtime guarantees sufficient alignment of JavaThread | |
2620 // pointers to allow age to be placed into low bits | |
2621 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); | |
2622 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); | |
2623 cmp(temp_reg, markOopDesc::biased_lock_pattern); | |
2624 brx(Assembler::notEqual, false, Assembler::pn, cas_label); | |
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2625 delayed()->nop(); |
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2626 |
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2627 load_klass(obj_reg, temp_reg); |
0 | 2628 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); |
2629 or3(G2_thread, temp_reg, temp_reg); | |
2630 xor3(mark_reg, temp_reg, temp_reg); | |
2631 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg); | |
2632 if (counters != NULL) { | |
2633 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg); | |
2634 // Reload mark_reg as we may need it later | |
2635 ld_ptr(Address(obj_reg, 0, oopDesc::mark_offset_in_bytes()), mark_reg); | |
2636 } | |
2637 brx(Assembler::equal, true, Assembler::pt, done); | |
2638 delayed()->nop(); | |
2639 | |
2640 Label try_revoke_bias; | |
2641 Label try_rebias; | |
2642 Address mark_addr = Address(obj_reg, 0, oopDesc::mark_offset_in_bytes()); | |
2643 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
2644 | |
2645 // At this point we know that the header has the bias pattern and | |
2646 // that we are not the bias owner in the current epoch. We need to | |
2647 // figure out more details about the state of the header in order to | |
2648 // know what operations can be legally performed on the object's | |
2649 // header. | |
2650 | |
2651 // If the low three bits in the xor result aren't clear, that means | |
2652 // the prototype header is no longer biased and we have to revoke | |
2653 // the bias on this object. | |
2654 btst(markOopDesc::biased_lock_mask_in_place, temp_reg); | |
2655 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias); | |
2656 | |
2657 // Biasing is still enabled for this data type. See whether the | |
2658 // epoch of the current bias is still valid, meaning that the epoch | |
2659 // bits of the mark word are equal to the epoch bits of the | |
2660 // prototype header. (Note that the prototype header's epoch bits | |
2661 // only change at a safepoint.) If not, attempt to rebias the object | |
2662 // toward the current thread. Note that we must be absolutely sure | |
2663 // that the current epoch is invalid in order to do this because | |
2664 // otherwise the manipulations it performs on the mark word are | |
2665 // illegal. | |
2666 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg); | |
2667 brx(Assembler::notZero, false, Assembler::pn, try_rebias); | |
2668 | |
2669 // The epoch of the current bias is still valid but we know nothing | |
2670 // about the owner; it might be set or it might be clear. Try to | |
2671 // acquire the bias of the object using an atomic operation. If this | |
2672 // fails we will go in to the runtime to revoke the object's bias. | |
2673 // Note that we first construct the presumed unbiased header so we | |
2674 // don't accidentally blow away another thread's valid bias. | |
2675 delayed()->and3(mark_reg, | |
2676 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place, | |
2677 mark_reg); | |
2678 or3(G2_thread, mark_reg, temp_reg); | |
2679 casx_under_lock(mark_addr.base(), mark_reg, temp_reg, | |
2680 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
2681 // If the biasing toward our thread failed, this means that | |
2682 // another thread succeeded in biasing it toward itself and we | |
2683 // need to revoke that bias. The revocation will occur in the | |
2684 // interpreter runtime in the slow case. | |
2685 cmp(mark_reg, temp_reg); | |
2686 if (counters != NULL) { | |
2687 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg); | |
2688 } | |
2689 if (slow_case != NULL) { | |
2690 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); | |
2691 delayed()->nop(); | |
2692 } | |
2693 br(Assembler::always, false, Assembler::pt, done); | |
2694 delayed()->nop(); | |
2695 | |
2696 bind(try_rebias); | |
2697 // At this point we know the epoch has expired, meaning that the | |
2698 // current "bias owner", if any, is actually invalid. Under these | |
2699 // circumstances _only_, we are allowed to use the current header's | |
2700 // value as the comparison value when doing the cas to acquire the | |
2701 // bias in the current epoch. In other words, we allow transfer of | |
2702 // the bias from one thread to another directly in this situation. | |
2703 // | |
2704 // FIXME: due to a lack of registers we currently blow away the age | |
2705 // bits in this situation. Should attempt to preserve them. | |
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2706 load_klass(obj_reg, temp_reg); |
0 | 2707 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); |
2708 or3(G2_thread, temp_reg, temp_reg); | |
2709 casx_under_lock(mark_addr.base(), mark_reg, temp_reg, | |
2710 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
2711 // If the biasing toward our thread failed, this means that | |
2712 // another thread succeeded in biasing it toward itself and we | |
2713 // need to revoke that bias. The revocation will occur in the | |
2714 // interpreter runtime in the slow case. | |
2715 cmp(mark_reg, temp_reg); | |
2716 if (counters != NULL) { | |
2717 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg); | |
2718 } | |
2719 if (slow_case != NULL) { | |
2720 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); | |
2721 delayed()->nop(); | |
2722 } | |
2723 br(Assembler::always, false, Assembler::pt, done); | |
2724 delayed()->nop(); | |
2725 | |
2726 bind(try_revoke_bias); | |
2727 // The prototype mark in the klass doesn't have the bias bit set any | |
2728 // more, indicating that objects of this data type are not supposed | |
2729 // to be biased any more. We are going to try to reset the mark of | |
2730 // this object to the prototype value and fall through to the | |
2731 // CAS-based locking scheme. Note that if our CAS fails, it means | |
2732 // that another thread raced us for the privilege of revoking the | |
2733 // bias of this particular object, so it's okay to continue in the | |
2734 // normal locking code. | |
2735 // | |
2736 // FIXME: due to a lack of registers we currently blow away the age | |
2737 // bits in this situation. Should attempt to preserve them. | |
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2738 load_klass(obj_reg, temp_reg); |
0 | 2739 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); |
2740 casx_under_lock(mark_addr.base(), mark_reg, temp_reg, | |
2741 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
2742 // Fall through to the normal CAS-based lock, because no matter what | |
2743 // the result of the above CAS, some thread must have succeeded in | |
2744 // removing the bias bit from the object's header. | |
2745 if (counters != NULL) { | |
2746 cmp(mark_reg, temp_reg); | |
2747 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg); | |
2748 } | |
2749 | |
2750 bind(cas_label); | |
2751 } | |
2752 | |
2753 void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done, | |
2754 bool allow_delay_slot_filling) { | |
2755 // Check for biased locking unlock case, which is a no-op | |
2756 // Note: we do not have to check the thread ID for two reasons. | |
2757 // First, the interpreter checks for IllegalMonitorStateException at | |
2758 // a higher level. Second, if the bias was revoked while we held the | |
2759 // lock, the object could not be rebiased toward another thread, so | |
2760 // the bias bit would be clear. | |
2761 ld_ptr(mark_addr, temp_reg); | |
2762 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); | |
2763 cmp(temp_reg, markOopDesc::biased_lock_pattern); | |
2764 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done); | |
2765 delayed(); | |
2766 if (!allow_delay_slot_filling) { | |
2767 nop(); | |
2768 } | |
2769 } | |
2770 | |
2771 | |
2772 // CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by | |
2773 // Solaris/SPARC's "as". Another apt name would be cas_ptr() | |
2774 | |
2775 void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) { | |
2776 casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()) ; | |
2777 } | |
2778 | |
2779 | |
2780 | |
2781 // compiler_lock_object() and compiler_unlock_object() are direct transliterations | |
2782 // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments. | |
2783 // The code could be tightened up considerably. | |
2784 // | |
2785 // box->dhw disposition - post-conditions at DONE_LABEL. | |
2786 // - Successful inflated lock: box->dhw != 0. | |
2787 // Any non-zero value suffices. | |
2788 // Consider G2_thread, rsp, boxReg, or unused_mark() | |
2789 // - Successful Stack-lock: box->dhw == mark. | |
2790 // box->dhw must contain the displaced mark word value | |
2791 // - Failure -- icc.ZFlag == 0 and box->dhw is undefined. | |
2792 // The slow-path fast_enter() and slow_enter() operators | |
2793 // are responsible for setting box->dhw = NonZero (typically ::unused_mark). | |
2794 // - Biased: box->dhw is undefined | |
2795 // | |
2796 // SPARC refworkload performance - specifically jetstream and scimark - are | |
2797 // extremely sensitive to the size of the code emitted by compiler_lock_object | |
2798 // and compiler_unlock_object. Critically, the key factor is code size, not path | |
2799 // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the | |
2800 // effect). | |
2801 | |
2802 | |
2803 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark, Register Rbox, Register Rscratch, | |
2804 BiasedLockingCounters* counters) { | |
2805 Address mark_addr(Roop, 0, oopDesc::mark_offset_in_bytes()); | |
2806 | |
2807 verify_oop(Roop); | |
2808 Label done ; | |
2809 | |
2810 if (counters != NULL) { | |
2811 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch); | |
2812 } | |
2813 | |
2814 if (EmitSync & 1) { | |
2815 mov (3, Rscratch) ; | |
2816 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
2817 cmp (SP, G0) ; | |
2818 return ; | |
2819 } | |
2820 | |
2821 if (EmitSync & 2) { | |
2822 | |
2823 // Fetch object's markword | |
2824 ld_ptr(mark_addr, Rmark); | |
2825 | |
2826 if (UseBiasedLocking) { | |
2827 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); | |
2828 } | |
2829 | |
2830 // Save Rbox in Rscratch to be used for the cas operation | |
2831 mov(Rbox, Rscratch); | |
2832 | |
2833 // set Rmark to markOop | markOopDesc::unlocked_value | |
2834 or3(Rmark, markOopDesc::unlocked_value, Rmark); | |
2835 | |
2836 // Initialize the box. (Must happen before we update the object mark!) | |
2837 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
2838 | |
2839 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop | |
2840 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
2841 casx_under_lock(mark_addr.base(), Rmark, Rscratch, | |
2842 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
2843 | |
2844 // if compare/exchange succeeded we found an unlocked object and we now have locked it | |
2845 // hence we are done | |
2846 cmp(Rmark, Rscratch); | |
2847 #ifdef _LP64 | |
2848 sub(Rscratch, STACK_BIAS, Rscratch); | |
2849 #endif | |
2850 brx(Assembler::equal, false, Assembler::pt, done); | |
2851 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot | |
2852 | |
2853 // we did not find an unlocked object so see if this is a recursive case | |
2854 // sub(Rscratch, SP, Rscratch); | |
2855 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); | |
2856 andcc(Rscratch, 0xfffff003, Rscratch); | |
2857 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
2858 bind (done) ; | |
2859 return ; | |
2860 } | |
2861 | |
2862 Label Egress ; | |
2863 | |
2864 if (EmitSync & 256) { | |
2865 Label IsInflated ; | |
2866 | |
2867 ld_ptr (mark_addr, Rmark); // fetch obj->mark | |
2868 // Triage: biased, stack-locked, neutral, inflated | |
2869 if (UseBiasedLocking) { | |
2870 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); | |
2871 // Invariant: if control reaches this point in the emitted stream | |
2872 // then Rmark has not been modified. | |
2873 } | |
2874 | |
2875 // Store mark into displaced mark field in the on-stack basic-lock "box" | |
2876 // Critically, this must happen before the CAS | |
2877 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty. | |
2878 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
2879 andcc (Rmark, 2, G0) ; | |
2880 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ; | |
2881 delayed() -> | |
2882 | |
2883 // Try stack-lock acquisition. | |
2884 // Beware: the 1st instruction is in a delay slot | |
2885 mov (Rbox, Rscratch); | |
2886 or3 (Rmark, markOopDesc::unlocked_value, Rmark); | |
2887 assert (mark_addr.disp() == 0, "cas must take a zero displacement"); | |
2888 casn (mark_addr.base(), Rmark, Rscratch) ; | |
2889 cmp (Rmark, Rscratch); | |
2890 brx (Assembler::equal, false, Assembler::pt, done); | |
2891 delayed()->sub(Rscratch, SP, Rscratch); | |
2892 | |
2893 // Stack-lock attempt failed - check for recursive stack-lock. | |
2894 // See the comments below about how we might remove this case. | |
2895 #ifdef _LP64 | |
2896 sub (Rscratch, STACK_BIAS, Rscratch); | |
2897 #endif | |
2898 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); | |
2899 andcc (Rscratch, 0xfffff003, Rscratch); | |
2900 br (Assembler::always, false, Assembler::pt, done) ; | |
2901 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
2902 | |
2903 bind (IsInflated) ; | |
2904 if (EmitSync & 64) { | |
2905 // If m->owner != null goto IsLocked | |
2906 // Pessimistic form: Test-and-CAS vs CAS | |
2907 // The optimistic form avoids RTS->RTO cache line upgrades. | |
2908 ld_ptr (Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; | |
2909 andcc (Rscratch, Rscratch, G0) ; | |
2910 brx (Assembler::notZero, false, Assembler::pn, done) ; | |
2911 delayed()->nop() ; | |
2912 // m->owner == null : it's unlocked. | |
2913 } | |
2914 | |
2915 // Try to CAS m->owner from null to Self | |
2916 // Invariant: if we acquire the lock then _recursions should be 0. | |
2917 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; | |
2918 mov (G2_thread, Rscratch) ; | |
2919 casn (Rmark, G0, Rscratch) ; | |
2920 cmp (Rscratch, G0) ; | |
2921 // Intentional fall-through into done | |
2922 } else { | |
2923 // Aggressively avoid the Store-before-CAS penalty | |
2924 // Defer the store into box->dhw until after the CAS | |
2925 Label IsInflated, Recursive ; | |
2926 | |
2927 // Anticipate CAS -- Avoid RTS->RTO upgrade | |
2928 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ; | |
2929 | |
2930 ld_ptr (mark_addr, Rmark); // fetch obj->mark | |
2931 // Triage: biased, stack-locked, neutral, inflated | |
2932 | |
2933 if (UseBiasedLocking) { | |
2934 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); | |
2935 // Invariant: if control reaches this point in the emitted stream | |
2936 // then Rmark has not been modified. | |
2937 } | |
2938 andcc (Rmark, 2, G0) ; | |
2939 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ; | |
2940 delayed()-> // Beware - dangling delay-slot | |
2941 | |
2942 // Try stack-lock acquisition. | |
2943 // Transiently install BUSY (0) encoding in the mark word. | |
2944 // if the CAS of 0 into the mark was successful then we execute: | |
2945 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box | |
2946 // ST obj->mark = box -- overwrite transient 0 value | |
2947 // This presumes TSO, of course. | |
2948 | |
2949 mov (0, Rscratch) ; | |
2950 or3 (Rmark, markOopDesc::unlocked_value, Rmark); | |
2951 assert (mark_addr.disp() == 0, "cas must take a zero displacement"); | |
2952 casn (mark_addr.base(), Rmark, Rscratch) ; | |
2953 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ; | |
2954 cmp (Rscratch, Rmark) ; | |
2955 brx (Assembler::notZero, false, Assembler::pn, Recursive) ; | |
2956 delayed() -> | |
2957 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
2958 if (counters != NULL) { | |
2959 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); | |
2960 } | |
2961 br (Assembler::always, false, Assembler::pt, done); | |
2962 delayed() -> | |
2963 st_ptr (Rbox, mark_addr) ; | |
2964 | |
2965 bind (Recursive) ; | |
2966 // Stack-lock attempt failed - check for recursive stack-lock. | |
2967 // Tests show that we can remove the recursive case with no impact | |
2968 // on refworkload 0.83. If we need to reduce the size of the code | |
2969 // emitted by compiler_lock_object() the recursive case is perfect | |
2970 // candidate. | |
2971 // | |
2972 // A more extreme idea is to always inflate on stack-lock recursion. | |
2973 // This lets us eliminate the recursive checks in compiler_lock_object | |
2974 // and compiler_unlock_object and the (box->dhw == 0) encoding. | |
2975 // A brief experiment - requiring changes to synchronizer.cpp, interpreter, | |
2976 // and showed a performance *increase*. In the same experiment I eliminated | |
2977 // the fast-path stack-lock code from the interpreter and always passed | |
2978 // control to the "slow" operators in synchronizer.cpp. | |
2979 | |
2980 // RScratch contains the fetched obj->mark value from the failed CASN. | |
2981 #ifdef _LP64 | |
2982 sub (Rscratch, STACK_BIAS, Rscratch); | |
2983 #endif | |
2984 sub(Rscratch, SP, Rscratch); | |
2985 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); | |
2986 andcc (Rscratch, 0xfffff003, Rscratch); | |
2987 if (counters != NULL) { | |
2988 // Accounting needs the Rscratch register | |
2989 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
2990 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); | |
2991 br (Assembler::always, false, Assembler::pt, done) ; | |
2992 delayed()->nop() ; | |
2993 } else { | |
2994 br (Assembler::always, false, Assembler::pt, done) ; | |
2995 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
2996 } | |
2997 | |
2998 bind (IsInflated) ; | |
2999 if (EmitSync & 64) { | |
3000 // If m->owner != null goto IsLocked | |
3001 // Test-and-CAS vs CAS | |
3002 // Pessimistic form avoids futile (doomed) CAS attempts | |
3003 // The optimistic form avoids RTS->RTO cache line upgrades. | |
3004 ld_ptr (Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; | |
3005 andcc (Rscratch, Rscratch, G0) ; | |
3006 brx (Assembler::notZero, false, Assembler::pn, done) ; | |
3007 delayed()->nop() ; | |
3008 // m->owner == null : it's unlocked. | |
3009 } | |
3010 | |
3011 // Try to CAS m->owner from null to Self | |
3012 // Invariant: if we acquire the lock then _recursions should be 0. | |
3013 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; | |
3014 mov (G2_thread, Rscratch) ; | |
3015 casn (Rmark, G0, Rscratch) ; | |
3016 cmp (Rscratch, G0) ; | |
3017 // ST box->displaced_header = NonZero. | |
3018 // Any non-zero value suffices: | |
3019 // unused_mark(), G2_thread, RBox, RScratch, rsp, etc. | |
3020 st_ptr (Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes()); | |
3021 // Intentional fall-through into done | |
3022 } | |
3023 | |
3024 bind (done) ; | |
3025 } | |
3026 | |
3027 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark, Register Rbox, Register Rscratch) { | |
3028 Address mark_addr(Roop, 0, oopDesc::mark_offset_in_bytes()); | |
3029 | |
3030 Label done ; | |
3031 | |
3032 if (EmitSync & 4) { | |
3033 cmp (SP, G0) ; | |
3034 return ; | |
3035 } | |
3036 | |
3037 if (EmitSync & 8) { | |
3038 if (UseBiasedLocking) { | |
3039 biased_locking_exit(mark_addr, Rscratch, done); | |
3040 } | |
3041 | |
3042 // Test first if it is a fast recursive unlock | |
3043 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark); | |
3044 cmp(Rmark, G0); | |
3045 brx(Assembler::equal, false, Assembler::pt, done); | |
3046 delayed()->nop(); | |
3047 | |
3048 // Check if it is still a light weight lock, this is is true if we see | |
3049 // the stack address of the basicLock in the markOop of the object | |
3050 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); | |
3051 casx_under_lock(mark_addr.base(), Rbox, Rmark, | |
3052 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); | |
3053 br (Assembler::always, false, Assembler::pt, done); | |
3054 delayed()->cmp(Rbox, Rmark); | |
3055 bind (done) ; | |
3056 return ; | |
3057 } | |
3058 | |
3059 // Beware ... If the aggregate size of the code emitted by CLO and CUO is | |
3060 // is too large performance rolls abruptly off a cliff. | |
3061 // This could be related to inlining policies, code cache management, or | |
3062 // I$ effects. | |
3063 Label LStacked ; | |
3064 | |
3065 if (UseBiasedLocking) { | |
3066 // TODO: eliminate redundant LDs of obj->mark | |
3067 biased_locking_exit(mark_addr, Rscratch, done); | |
3068 } | |
3069 | |
3070 ld_ptr (Roop, oopDesc::mark_offset_in_bytes(), Rmark) ; | |
3071 ld_ptr (Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch); | |
3072 andcc (Rscratch, Rscratch, G0); | |
3073 brx (Assembler::zero, false, Assembler::pn, done); | |
3074 delayed()-> nop() ; // consider: relocate fetch of mark, above, into this DS | |
3075 andcc (Rmark, 2, G0) ; | |
3076 brx (Assembler::zero, false, Assembler::pt, LStacked) ; | |
3077 delayed()-> nop() ; | |
3078 | |
3079 // It's inflated | |
3080 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before | |
3081 // the ST of 0 into _owner which releases the lock. This prevents loads | |
3082 // and stores within the critical section from reordering (floating) | |
3083 // past the store that releases the lock. But TSO is a strong memory model | |
3084 // and that particular flavor of barrier is a noop, so we can safely elide it. | |
3085 // Note that we use 1-0 locking by default for the inflated case. We | |
3086 // close the resultant (and rare) race by having contented threads in | |
3087 // monitorenter periodically poll _owner. | |
3088 ld_ptr (Address(Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; | |
3089 ld_ptr (Address(Rmark, 0, ObjectMonitor::recursions_offset_in_bytes()-2), Rbox) ; | |
3090 xor3 (Rscratch, G2_thread, Rscratch) ; | |
3091 orcc (Rbox, Rscratch, Rbox) ; | |
3092 brx (Assembler::notZero, false, Assembler::pn, done) ; | |
3093 delayed()-> | |
3094 ld_ptr (Address (Rmark, 0, ObjectMonitor::EntryList_offset_in_bytes()-2), Rscratch) ; | |
3095 ld_ptr (Address (Rmark, 0, ObjectMonitor::cxq_offset_in_bytes()-2), Rbox) ; | |
3096 orcc (Rbox, Rscratch, G0) ; | |
3097 if (EmitSync & 65536) { | |
3098 Label LSucc ; | |
3099 brx (Assembler::notZero, false, Assembler::pn, LSucc) ; | |
3100 delayed()->nop() ; | |
3101 br (Assembler::always, false, Assembler::pt, done) ; | |
3102 delayed()-> | |
3103 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
3104 | |
3105 bind (LSucc) ; | |
3106 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
3107 if (os::is_MP()) { membar (StoreLoad) ; } | |
3108 ld_ptr (Address (Rmark, 0, ObjectMonitor::succ_offset_in_bytes()-2), Rscratch) ; | |
3109 andcc (Rscratch, Rscratch, G0) ; | |
3110 brx (Assembler::notZero, false, Assembler::pt, done) ; | |
3111 delayed()-> andcc (G0, G0, G0) ; | |
3112 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; | |
3113 mov (G2_thread, Rscratch) ; | |
3114 casn (Rmark, G0, Rscratch) ; | |
3115 cmp (Rscratch, G0) ; | |
3116 // invert icc.zf and goto done | |
3117 brx (Assembler::notZero, false, Assembler::pt, done) ; | |
3118 delayed() -> cmp (G0, G0) ; | |
3119 br (Assembler::always, false, Assembler::pt, done); | |
3120 delayed() -> cmp (G0, 1) ; | |
3121 } else { | |
3122 brx (Assembler::notZero, false, Assembler::pn, done) ; | |
3123 delayed()->nop() ; | |
3124 br (Assembler::always, false, Assembler::pt, done) ; | |
3125 delayed()-> | |
3126 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
3127 } | |
3128 | |
3129 bind (LStacked) ; | |
3130 // Consider: we could replace the expensive CAS in the exit | |
3131 // path with a simple ST of the displaced mark value fetched from | |
3132 // the on-stack basiclock box. That admits a race where a thread T2 | |
3133 // in the slow lock path -- inflating with monitor M -- could race a | |
3134 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2. | |
3135 // More precisely T1 in the stack-lock unlock path could "stomp" the | |
3136 // inflated mark value M installed by T2, resulting in an orphan | |
3137 // object monitor M and T2 becoming stranded. We can remedy that situation | |
3138 // by having T2 periodically poll the object's mark word using timed wait | |
3139 // operations. If T2 discovers that a stomp has occurred it vacates | |
3140 // the monitor M and wakes any other threads stranded on the now-orphan M. | |
3141 // In addition the monitor scavenger, which performs deflation, | |
3142 // would also need to check for orpan monitors and stranded threads. | |
3143 // | |
3144 // Finally, inflation is also used when T2 needs to assign a hashCode | |
3145 // to O and O is stack-locked by T1. The "stomp" race could cause | |
3146 // an assigned hashCode value to be lost. We can avoid that condition | |
3147 // and provide the necessary hashCode stability invariants by ensuring | |
3148 // that hashCode generation is idempotent between copying GCs. | |
3149 // For example we could compute the hashCode of an object O as | |
3150 // O's heap address XOR some high quality RNG value that is refreshed | |
3151 // at GC-time. The monitor scavenger would install the hashCode | |
3152 // found in any orphan monitors. Again, the mechanism admits a | |
3153 // lost-update "stomp" WAW race but detects and recovers as needed. | |
3154 // | |
3155 // A prototype implementation showed excellent results, although | |
3156 // the scavenger and timeout code was rather involved. | |
3157 | |
3158 casn (mark_addr.base(), Rbox, Rscratch) ; | |
3159 cmp (Rbox, Rscratch); | |
3160 // Intentional fall through into done ... | |
3161 | |
3162 bind (done) ; | |
3163 } | |
3164 | |
3165 | |
3166 | |
3167 void MacroAssembler::print_CPU_state() { | |
3168 // %%%%% need to implement this | |
3169 } | |
3170 | |
3171 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { | |
3172 // %%%%% need to implement this | |
3173 } | |
3174 | |
3175 void MacroAssembler::push_IU_state() { | |
3176 // %%%%% need to implement this | |
3177 } | |
3178 | |
3179 | |
3180 void MacroAssembler::pop_IU_state() { | |
3181 // %%%%% need to implement this | |
3182 } | |
3183 | |
3184 | |
3185 void MacroAssembler::push_FPU_state() { | |
3186 // %%%%% need to implement this | |
3187 } | |
3188 | |
3189 | |
3190 void MacroAssembler::pop_FPU_state() { | |
3191 // %%%%% need to implement this | |
3192 } | |
3193 | |
3194 | |
3195 void MacroAssembler::push_CPU_state() { | |
3196 // %%%%% need to implement this | |
3197 } | |
3198 | |
3199 | |
3200 void MacroAssembler::pop_CPU_state() { | |
3201 // %%%%% need to implement this | |
3202 } | |
3203 | |
3204 | |
3205 | |
3206 void MacroAssembler::verify_tlab() { | |
3207 #ifdef ASSERT | |
3208 if (UseTLAB && VerifyOops) { | |
3209 Label next, next2, ok; | |
3210 Register t1 = L0; | |
3211 Register t2 = L1; | |
3212 Register t3 = L2; | |
3213 | |
3214 save_frame(0); | |
3215 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); | |
3216 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2); | |
3217 or3(t1, t2, t3); | |
3218 cmp(t1, t2); | |
3219 br(Assembler::greaterEqual, false, Assembler::pn, next); | |
3220 delayed()->nop(); | |
3221 stop("assert(top >= start)"); | |
3222 should_not_reach_here(); | |
3223 | |
3224 bind(next); | |
3225 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); | |
3226 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2); | |
3227 or3(t3, t2, t3); | |
3228 cmp(t1, t2); | |
3229 br(Assembler::lessEqual, false, Assembler::pn, next2); | |
3230 delayed()->nop(); | |
3231 stop("assert(top <= end)"); | |
3232 should_not_reach_here(); | |
3233 | |
3234 bind(next2); | |
3235 and3(t3, MinObjAlignmentInBytesMask, t3); | |
3236 cmp(t3, 0); | |
3237 br(Assembler::lessEqual, false, Assembler::pn, ok); | |
3238 delayed()->nop(); | |
3239 stop("assert(aligned)"); | |
3240 should_not_reach_here(); | |
3241 | |
3242 bind(ok); | |
3243 restore(); | |
3244 } | |
3245 #endif | |
3246 } | |
3247 | |
3248 | |
3249 void MacroAssembler::eden_allocate( | |
3250 Register obj, // result: pointer to object after successful allocation | |
3251 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
3252 int con_size_in_bytes, // object size in bytes if known at compile time | |
3253 Register t1, // temp register | |
3254 Register t2, // temp register | |
3255 Label& slow_case // continuation point if fast allocation fails | |
3256 ){ | |
3257 // make sure arguments make sense | |
3258 assert_different_registers(obj, var_size_in_bytes, t1, t2); | |
3259 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size"); | |
3260 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); | |
3261 | |
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3262 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { |
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3263 // No allocation in the shared eden. |
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3264 br(Assembler::always, false, Assembler::pt, slow_case); |
0 | 3265 delayed()->nop(); |
342
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3266 } else { |
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3267 // get eden boundaries |
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3268 // note: we need both top & top_addr! |
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3269 const Register top_addr = t1; |
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3270 const Register end = t2; |
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3271 |
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3272 CollectedHeap* ch = Universe::heap(); |
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3273 set((intx)ch->top_addr(), top_addr); |
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3274 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr(); |
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3275 ld_ptr(top_addr, delta, end); |
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3276 ld_ptr(top_addr, 0, obj); |
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3277 |
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3278 // try to allocate |
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3279 Label retry; |
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3280 bind(retry); |
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3281 #ifdef ASSERT |
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3282 // make sure eden top is properly aligned |
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3283 { |
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3284 Label L; |
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3285 btst(MinObjAlignmentInBytesMask, obj); |
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3286 br(Assembler::zero, false, Assembler::pt, L); |
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3287 delayed()->nop(); |
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3288 stop("eden top is not properly aligned"); |
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3289 bind(L); |
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3290 } |
0 | 3291 #endif // ASSERT |
342
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3292 const Register free = end; |
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3293 sub(end, obj, free); // compute amount of free space |
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3294 if (var_size_in_bytes->is_valid()) { |
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3295 // size is unknown at compile time |
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3296 cmp(free, var_size_in_bytes); |
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3297 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case |
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3298 delayed()->add(obj, var_size_in_bytes, end); |
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3299 } else { |
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3300 // size is known at compile time |
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3301 cmp(free, con_size_in_bytes); |
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3302 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case |
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3303 delayed()->add(obj, con_size_in_bytes, end); |
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3304 } |
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3305 // Compare obj with the value at top_addr; if still equal, swap the value of |
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3306 // end with the value at top_addr. If not equal, read the value at top_addr |
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3307 // into end. |
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3308 casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); |
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3309 // if someone beat us on the allocation, try again, otherwise continue |
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3310 cmp(obj, end); |
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3311 brx(Assembler::notEqual, false, Assembler::pn, retry); |
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3312 delayed()->mov(end, obj); // nop if successfull since obj == end |
0 | 3313 |
3314 #ifdef ASSERT | |
342
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3315 // make sure eden top is properly aligned |
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3316 { |
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3317 Label L; |
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3318 const Register top_addr = t1; |
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3319 |
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3320 set((intx)ch->top_addr(), top_addr); |
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3321 ld_ptr(top_addr, 0, top_addr); |
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3322 btst(MinObjAlignmentInBytesMask, top_addr); |
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3323 br(Assembler::zero, false, Assembler::pt, L); |
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3324 delayed()->nop(); |
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3325 stop("eden top is not properly aligned"); |
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3326 bind(L); |
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3327 } |
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3328 #endif // ASSERT |
0 | 3329 } |
3330 } | |
3331 | |
3332 | |
3333 void MacroAssembler::tlab_allocate( | |
3334 Register obj, // result: pointer to object after successful allocation | |
3335 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
3336 int con_size_in_bytes, // object size in bytes if known at compile time | |
3337 Register t1, // temp register | |
3338 Label& slow_case // continuation point if fast allocation fails | |
3339 ){ | |
3340 // make sure arguments make sense | |
3341 assert_different_registers(obj, var_size_in_bytes, t1); | |
3342 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size"); | |
3343 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); | |
3344 | |
3345 const Register free = t1; | |
3346 | |
3347 verify_tlab(); | |
3348 | |
3349 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj); | |
3350 | |
3351 // calculate amount of free space | |
3352 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free); | |
3353 sub(free, obj, free); | |
3354 | |
3355 Label done; | |
3356 if (var_size_in_bytes == noreg) { | |
3357 cmp(free, con_size_in_bytes); | |
3358 } else { | |
3359 cmp(free, var_size_in_bytes); | |
3360 } | |
3361 br(Assembler::less, false, Assembler::pn, slow_case); | |
3362 // calculate the new top pointer | |
3363 if (var_size_in_bytes == noreg) { | |
3364 delayed()->add(obj, con_size_in_bytes, free); | |
3365 } else { | |
3366 delayed()->add(obj, var_size_in_bytes, free); | |
3367 } | |
3368 | |
3369 bind(done); | |
3370 | |
3371 #ifdef ASSERT | |
3372 // make sure new free pointer is properly aligned | |
3373 { | |
3374 Label L; | |
3375 btst(MinObjAlignmentInBytesMask, free); | |
3376 br(Assembler::zero, false, Assembler::pt, L); | |
3377 delayed()->nop(); | |
3378 stop("updated TLAB free is not properly aligned"); | |
3379 bind(L); | |
3380 } | |
3381 #endif // ASSERT | |
3382 | |
3383 // update the tlab top pointer | |
3384 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset())); | |
3385 verify_tlab(); | |
3386 } | |
3387 | |
3388 | |
3389 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) { | |
3390 Register top = O0; | |
3391 Register t1 = G1; | |
3392 Register t2 = G3; | |
3393 Register t3 = O1; | |
3394 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */); | |
3395 Label do_refill, discard_tlab; | |
3396 | |
3397 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { | |
3398 // No allocation in the shared eden. | |
3399 br(Assembler::always, false, Assembler::pt, slow_case); | |
3400 delayed()->nop(); | |
3401 } | |
3402 | |
3403 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top); | |
3404 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1); | |
3405 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2); | |
3406 | |
3407 // calculate amount of free space | |
3408 sub(t1, top, t1); | |
3409 srl_ptr(t1, LogHeapWordSize, t1); | |
3410 | |
3411 // Retain tlab and allocate object in shared space if | |
3412 // the amount free in the tlab is too large to discard. | |
3413 cmp(t1, t2); | |
3414 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab); | |
3415 | |
3416 // increment waste limit to prevent getting stuck on this slow path | |
3417 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2); | |
3418 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())); | |
3419 if (TLABStats) { | |
3420 // increment number of slow_allocations | |
3421 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2); | |
3422 add(t2, 1, t2); | |
3423 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset())); | |
3424 } | |
3425 br(Assembler::always, false, Assembler::pt, try_eden); | |
3426 delayed()->nop(); | |
3427 | |
3428 bind(discard_tlab); | |
3429 if (TLABStats) { | |
3430 // increment number of refills | |
3431 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2); | |
3432 add(t2, 1, t2); | |
3433 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset())); | |
3434 // accumulate wastage | |
3435 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2); | |
3436 add(t2, t1, t2); | |
3437 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())); | |
3438 } | |
3439 | |
3440 // if tlab is currently allocated (top or end != null) then | |
3441 // fill [top, end + alignment_reserve) with array object | |
3442 br_null(top, false, Assembler::pn, do_refill); | |
3443 delayed()->nop(); | |
3444 | |
3445 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2); | |
3446 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word | |
3447 // set klass to intArrayKlass | |
3448 set((intptr_t)Universe::intArrayKlassObj_addr(), t2); | |
3449 ld_ptr(t2, 0, t2); | |
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3450 store_klass(t2, top); |
0 | 3451 sub(t1, typeArrayOopDesc::header_size(T_INT), t1); |
3452 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1); | |
3453 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1); | |
3454 st(t1, top, arrayOopDesc::length_offset_in_bytes()); | |
3455 verify_oop(top); | |
3456 | |
3457 // refill the tlab with an eden allocation | |
3458 bind(do_refill); | |
3459 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1); | |
3460 sll_ptr(t1, LogHeapWordSize, t1); | |
3461 // add object_size ?? | |
3462 eden_allocate(top, t1, 0, t2, t3, slow_case); | |
3463 | |
3464 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset())); | |
3465 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset())); | |
3466 #ifdef ASSERT | |
3467 // check that tlab_size (t1) is still valid | |
3468 { | |
3469 Label ok; | |
3470 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2); | |
3471 sll_ptr(t2, LogHeapWordSize, t2); | |
3472 cmp(t1, t2); | |
3473 br(Assembler::equal, false, Assembler::pt, ok); | |
3474 delayed()->nop(); | |
3475 stop("assert(t1 == tlab_size)"); | |
3476 should_not_reach_here(); | |
3477 | |
3478 bind(ok); | |
3479 } | |
3480 #endif // ASSERT | |
3481 add(top, t1, top); // t1 is tlab_size | |
3482 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top); | |
3483 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset())); | |
3484 verify_tlab(); | |
3485 br(Assembler::always, false, Assembler::pt, retry); | |
3486 delayed()->nop(); | |
3487 } | |
3488 | |
3489 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { | |
3490 switch (cond) { | |
3491 // Note some conditions are synonyms for others | |
3492 case Assembler::never: return Assembler::always; | |
3493 case Assembler::zero: return Assembler::notZero; | |
3494 case Assembler::lessEqual: return Assembler::greater; | |
3495 case Assembler::less: return Assembler::greaterEqual; | |
3496 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned; | |
3497 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned; | |
3498 case Assembler::negative: return Assembler::positive; | |
3499 case Assembler::overflowSet: return Assembler::overflowClear; | |
3500 case Assembler::always: return Assembler::never; | |
3501 case Assembler::notZero: return Assembler::zero; | |
3502 case Assembler::greater: return Assembler::lessEqual; | |
3503 case Assembler::greaterEqual: return Assembler::less; | |
3504 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned; | |
3505 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned; | |
3506 case Assembler::positive: return Assembler::negative; | |
3507 case Assembler::overflowClear: return Assembler::overflowSet; | |
3508 } | |
3509 | |
3510 ShouldNotReachHere(); return Assembler::overflowClear; | |
3511 } | |
3512 | |
3513 void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr, | |
3514 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) { | |
3515 Condition negated_cond = negate_condition(cond); | |
3516 Label L; | |
3517 brx(negated_cond, false, Assembler::pt, L); | |
3518 delayed()->nop(); | |
3519 inc_counter(counter_ptr, Rtmp1, Rtmp2); | |
3520 bind(L); | |
3521 } | |
3522 | |
3523 void MacroAssembler::inc_counter(address counter_ptr, Register Rtmp1, Register Rtmp2) { | |
3524 Address counter_addr(Rtmp1, counter_ptr); | |
3525 load_contents(counter_addr, Rtmp2); | |
3526 inc(Rtmp2); | |
3527 store_contents(Rtmp2, counter_addr); | |
3528 } | |
3529 | |
3530 SkipIfEqual::SkipIfEqual( | |
3531 MacroAssembler* masm, Register temp, const bool* flag_addr, | |
3532 Assembler::Condition condition) { | |
3533 _masm = masm; | |
3534 Address flag(temp, (address)flag_addr, relocInfo::none); | |
3535 _masm->sethi(flag); | |
3536 _masm->ldub(flag, temp); | |
3537 _masm->tst(temp); | |
3538 _masm->br(condition, false, Assembler::pt, _label); | |
3539 _masm->delayed()->nop(); | |
3540 } | |
3541 | |
3542 SkipIfEqual::~SkipIfEqual() { | |
3543 _masm->bind(_label); | |
3544 } | |
3545 | |
3546 | |
3547 // Writes to stack successive pages until offset reached to check for | |
3548 // stack overflow + shadow pages. This clobbers tsp and scratch. | |
3549 void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp, | |
3550 Register Rscratch) { | |
3551 // Use stack pointer in temp stack pointer | |
3552 mov(SP, Rtsp); | |
3553 | |
3554 // Bang stack for total size given plus stack shadow page size. | |
3555 // Bang one page at a time because a large size can overflow yellow and | |
3556 // red zones (the bang will fail but stack overflow handling can't tell that | |
3557 // it was a stack overflow bang vs a regular segv). | |
3558 int offset = os::vm_page_size(); | |
3559 Register Roffset = Rscratch; | |
3560 | |
3561 Label loop; | |
3562 bind(loop); | |
3563 set((-offset)+STACK_BIAS, Rscratch); | |
3564 st(G0, Rtsp, Rscratch); | |
3565 set(offset, Roffset); | |
3566 sub(Rsize, Roffset, Rsize); | |
3567 cmp(Rsize, G0); | |
3568 br(Assembler::greater, false, Assembler::pn, loop); | |
3569 delayed()->sub(Rtsp, Roffset, Rtsp); | |
3570 | |
3571 // Bang down shadow pages too. | |
3572 // The -1 because we already subtracted 1 page. | |
3573 for (int i = 0; i< StackShadowPages-1; i++) { | |
3574 set((-i*offset)+STACK_BIAS, Rscratch); | |
3575 st(G0, Rtsp, Rscratch); | |
3576 } | |
3577 } | |
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3578 |
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3579 /////////////////////////////////////////////////////////////////////////////////// |
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3580 #ifndef SERIALGC |
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3581 |
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3582 static uint num_stores = 0; |
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3583 static uint num_null_pre_stores = 0; |
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3584 |
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3585 static void count_null_pre_vals(void* pre_val) { |
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3586 num_stores++; |
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3587 if (pre_val == NULL) num_null_pre_stores++; |
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3588 if ((num_stores % 1000000) == 0) { |
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3589 tty->print_cr(UINT32_FORMAT " stores, " UINT32_FORMAT " (%5.2f%%) with null pre-vals.", |
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3590 num_stores, num_null_pre_stores, |
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3591 100.0*(float)num_null_pre_stores/(float)num_stores); |
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3592 } |
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3593 } |
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3594 |
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3595 static address satb_log_enqueue_with_frame = 0; |
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3596 static u_char* satb_log_enqueue_with_frame_end = 0; |
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3597 |
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3598 static address satb_log_enqueue_frameless = 0; |
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3599 static u_char* satb_log_enqueue_frameless_end = 0; |
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3600 |
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3601 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions? |
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3602 |
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3603 // The calls to this don't work. We'd need to do a fair amount of work to |
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3604 // make it work. |
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3605 static void check_index(int ind) { |
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3606 assert(0 <= ind && ind <= 64*K && ((ind % oopSize) == 0), |
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3607 "Invariants.") |
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3608 } |
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3609 |
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3610 static void generate_satb_log_enqueue(bool with_frame) { |
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3611 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize); |
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3612 CodeBuffer buf(bb->instructions_begin(), bb->instructions_size()); |
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3613 MacroAssembler masm(&buf); |
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3614 address start = masm.pc(); |
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3615 Register pre_val; |
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3616 |
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3617 Label refill, restart; |
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|
3618 if (with_frame) { |
37f87013dfd8
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diff
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|
3619 masm.save_frame(0); |
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diff
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|
3620 pre_val = I0; // Was O0 before the save. |
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|
3621 } else { |
37f87013dfd8
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diff
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|
3622 pre_val = O0; |
37f87013dfd8
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diff
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|
3623 } |
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124
diff
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|
3624 int satb_q_index_byte_offset = |
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|
3625 in_bytes(JavaThread::satb_mark_queue_offset() + |
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diff
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|
3626 PtrQueue::byte_offset_of_index()); |
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124
diff
changeset
|
3627 int satb_q_buf_byte_offset = |
37f87013dfd8
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124
diff
changeset
|
3628 in_bytes(JavaThread::satb_mark_queue_offset() + |
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diff
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|
3629 PtrQueue::byte_offset_of_buf()); |
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|
3630 assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) && |
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|
3631 in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t), |
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|
3632 "check sizes in assembly below"); |
37f87013dfd8
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diff
changeset
|
3633 |
37f87013dfd8
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|
3634 masm.bind(restart); |
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|
3635 masm.ld_ptr(G2_thread, satb_q_index_byte_offset, L0); |
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|
3636 |
37f87013dfd8
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|
3637 masm.br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn, L0, refill); |
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3638 // If the branch is taken, no harm in executing this in the delay slot. |
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|
3639 masm.delayed()->ld_ptr(G2_thread, satb_q_buf_byte_offset, L1); |
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|
3640 masm.sub(L0, oopSize, L0); |
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|
3641 |
37f87013dfd8
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|
3642 masm.st_ptr(pre_val, L1, L0); // [_buf + index] := I0 |
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diff
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|
3643 if (!with_frame) { |
37f87013dfd8
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diff
changeset
|
3644 // Use return-from-leaf |
37f87013dfd8
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diff
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|
3645 masm.retl(); |
37f87013dfd8
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|
3646 masm.delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset); |
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|
3647 } else { |
37f87013dfd8
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diff
changeset
|
3648 // Not delayed. |
37f87013dfd8
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|
3649 masm.st_ptr(L0, G2_thread, satb_q_index_byte_offset); |
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diff
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|
3650 } |
37f87013dfd8
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124
diff
changeset
|
3651 if (with_frame) { |
37f87013dfd8
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diff
changeset
|
3652 masm.ret(); |
37f87013dfd8
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diff
changeset
|
3653 masm.delayed()->restore(); |
37f87013dfd8
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124
diff
changeset
|
3654 } |
37f87013dfd8
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124
diff
changeset
|
3655 masm.bind(refill); |
37f87013dfd8
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124
diff
changeset
|
3656 |
37f87013dfd8
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124
diff
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|
3657 address handle_zero = |
37f87013dfd8
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124
diff
changeset
|
3658 CAST_FROM_FN_PTR(address, |
37f87013dfd8
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124
diff
changeset
|
3659 &SATBMarkQueueSet::handle_zero_index_for_thread); |
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diff
changeset
|
3660 // This should be rare enough that we can afford to save all the |
37f87013dfd8
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124
diff
changeset
|
3661 // scratch registers that the calling context might be using. |
37f87013dfd8
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124
diff
changeset
|
3662 masm.mov(G1_scratch, L0); |
37f87013dfd8
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124
diff
changeset
|
3663 masm.mov(G3_scratch, L1); |
37f87013dfd8
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124
diff
changeset
|
3664 masm.mov(G4, L2); |
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124
diff
changeset
|
3665 // We need the value of O0 above (for the write into the buffer), so we |
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diff
changeset
|
3666 // save and restore it. |
37f87013dfd8
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124
diff
changeset
|
3667 masm.mov(O0, L3); |
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124
diff
changeset
|
3668 // Since the call will overwrite O7, we save and restore that, as well. |
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diff
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|
3669 masm.mov(O7, L4); |
37f87013dfd8
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diff
changeset
|
3670 masm.call_VM_leaf(L5, handle_zero, G2_thread); |
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diff
changeset
|
3671 masm.mov(L0, G1_scratch); |
37f87013dfd8
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124
diff
changeset
|
3672 masm.mov(L1, G3_scratch); |
37f87013dfd8
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124
diff
changeset
|
3673 masm.mov(L2, G4); |
37f87013dfd8
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parents:
124
diff
changeset
|
3674 masm.mov(L3, O0); |
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diff
changeset
|
3675 masm.br(Assembler::always, /*annul*/false, Assembler::pt, restart); |
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diff
changeset
|
3676 masm.delayed()->mov(L4, O7); |
37f87013dfd8
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124
diff
changeset
|
3677 |
37f87013dfd8
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124
diff
changeset
|
3678 if (with_frame) { |
37f87013dfd8
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124
diff
changeset
|
3679 satb_log_enqueue_with_frame = start; |
37f87013dfd8
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124
diff
changeset
|
3680 satb_log_enqueue_with_frame_end = masm.pc(); |
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124
diff
changeset
|
3681 } else { |
37f87013dfd8
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124
diff
changeset
|
3682 satb_log_enqueue_frameless = start; |
37f87013dfd8
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diff
changeset
|
3683 satb_log_enqueue_frameless_end = masm.pc(); |
37f87013dfd8
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124
diff
changeset
|
3684 } |
37f87013dfd8
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parents:
124
diff
changeset
|
3685 } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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parents:
124
diff
changeset
|
3686 |
37f87013dfd8
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|
3687 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) { |
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124
diff
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|
3688 if (with_frame) { |
37f87013dfd8
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124
diff
changeset
|
3689 if (satb_log_enqueue_with_frame == 0) { |
37f87013dfd8
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124
diff
changeset
|
3690 generate_satb_log_enqueue(with_frame); |
37f87013dfd8
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124
diff
changeset
|
3691 assert(satb_log_enqueue_with_frame != 0, "postcondition."); |
37f87013dfd8
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124
diff
changeset
|
3692 if (G1SATBPrintStubs) { |
37f87013dfd8
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124
diff
changeset
|
3693 tty->print_cr("Generated with-frame satb enqueue:"); |
37f87013dfd8
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|
3694 Disassembler::decode((u_char*)satb_log_enqueue_with_frame, |
37f87013dfd8
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124
diff
changeset
|
3695 satb_log_enqueue_with_frame_end, |
37f87013dfd8
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parents:
124
diff
changeset
|
3696 tty); |
37f87013dfd8
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parents:
124
diff
changeset
|
3697 } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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parents:
124
diff
changeset
|
3698 } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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parents:
124
diff
changeset
|
3699 } else { |
37f87013dfd8
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124
diff
changeset
|
3700 if (satb_log_enqueue_frameless == 0) { |
37f87013dfd8
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124
diff
changeset
|
3701 generate_satb_log_enqueue(with_frame); |
37f87013dfd8
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124
diff
changeset
|
3702 assert(satb_log_enqueue_frameless != 0, "postcondition."); |
37f87013dfd8
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124
diff
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|
3703 if (G1SATBPrintStubs) { |
37f87013dfd8
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124
diff
changeset
|
3704 tty->print_cr("Generated frameless satb enqueue:"); |
37f87013dfd8
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|
3705 Disassembler::decode((u_char*)satb_log_enqueue_frameless, |
37f87013dfd8
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diff
changeset
|
3706 satb_log_enqueue_frameless_end, |
37f87013dfd8
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124
diff
changeset
|
3707 tty); |
37f87013dfd8
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124
diff
changeset
|
3708 } |
37f87013dfd8
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124
diff
changeset
|
3709 } |
37f87013dfd8
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parents:
124
diff
changeset
|
3710 } |
37f87013dfd8
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124
diff
changeset
|
3711 } |
37f87013dfd8
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124
diff
changeset
|
3712 |
37f87013dfd8
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|
3713 void MacroAssembler::g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs) { |
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|
3714 assert(offset == 0 || index == noreg, "choose one"); |
37f87013dfd8
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diff
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|
3715 |
37f87013dfd8
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diff
changeset
|
3716 if (G1DisablePreBarrier) return; |
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|
3717 // satb_log_barrier(tmp, obj, offset, preserve_o_regs); |
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|
3718 Label filtered; |
37f87013dfd8
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|
3719 // satb_log_barrier_work0(tmp, filtered); |
37f87013dfd8
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|
3720 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { |
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|
3721 ld(G2, |
37f87013dfd8
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diff
changeset
|
3722 in_bytes(JavaThread::satb_mark_queue_offset() + |
37f87013dfd8
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|
3723 PtrQueue::byte_offset_of_active()), |
37f87013dfd8
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diff
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|
3724 tmp); |
37f87013dfd8
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diff
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|
3725 } else { |
37f87013dfd8
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|
3726 guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1, |
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|
3727 "Assumption"); |
37f87013dfd8
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diff
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|
3728 ldsb(G2, |
37f87013dfd8
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124
diff
changeset
|
3729 in_bytes(JavaThread::satb_mark_queue_offset() + |
37f87013dfd8
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diff
changeset
|
3730 PtrQueue::byte_offset_of_active()), |
37f87013dfd8
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diff
changeset
|
3731 tmp); |
37f87013dfd8
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124
diff
changeset
|
3732 } |
37f87013dfd8
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diff
changeset
|
3733 // Check on whether to annul. |
37f87013dfd8
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|
3734 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered); |
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changeset
|
3735 delayed() -> nop(); |
37f87013dfd8
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changeset
|
3736 |
37f87013dfd8
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|
3737 // satb_log_barrier_work1(tmp, offset); |
37f87013dfd8
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|
3738 if (index == noreg) { |
37f87013dfd8
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changeset
|
3739 if (Assembler::is_simm13(offset)) { |
37f87013dfd8
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changeset
|
3740 ld_ptr(obj, offset, tmp); |
37f87013dfd8
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diff
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|
3741 } else { |
37f87013dfd8
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diff
changeset
|
3742 set(offset, tmp); |
37f87013dfd8
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diff
changeset
|
3743 ld_ptr(obj, tmp, tmp); |
37f87013dfd8
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124
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|
3744 } |
37f87013dfd8
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diff
changeset
|
3745 } else { |
37f87013dfd8
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changeset
|
3746 ld_ptr(obj, index, tmp); |
37f87013dfd8
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|
3747 } |
37f87013dfd8
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|
3748 |
37f87013dfd8
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|
3749 // satb_log_barrier_work2(obj, tmp, offset); |
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|
3750 |
37f87013dfd8
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|
3751 // satb_log_barrier_work3(tmp, filtered, preserve_o_regs); |
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3752 |
37f87013dfd8
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|
3753 const Register pre_val = tmp; |
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|
3754 |
37f87013dfd8
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|
3755 if (G1SATBBarrierPrintNullPreVals) { |
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|
3756 save_frame(0); |
37f87013dfd8
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|
3757 mov(pre_val, O0); |
37f87013dfd8
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|
3758 // Save G-regs that target may use. |
37f87013dfd8
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|
3759 mov(G1, L1); |
37f87013dfd8
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diff
changeset
|
3760 mov(G2, L2); |
37f87013dfd8
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diff
changeset
|
3761 mov(G3, L3); |
37f87013dfd8
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diff
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|
3762 mov(G4, L4); |
37f87013dfd8
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|
3763 mov(G5, L5); |
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|
3764 call(CAST_FROM_FN_PTR(address, &count_null_pre_vals)); |
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|
3765 delayed()->nop(); |
37f87013dfd8
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diff
changeset
|
3766 // Restore G-regs that target may have used. |
37f87013dfd8
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diff
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|
3767 mov(L1, G1); |
37f87013dfd8
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diff
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|
3768 mov(L2, G2); |
37f87013dfd8
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diff
changeset
|
3769 mov(L3, G3); |
37f87013dfd8
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diff
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|
3770 mov(L4, G4); |
37f87013dfd8
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diff
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|
3771 mov(L5, G5); |
37f87013dfd8
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diff
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|
3772 restore(G0, G0, G0); |
37f87013dfd8
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|
3773 } |
37f87013dfd8
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|
3774 |
37f87013dfd8
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|
3775 // Check on whether to annul. |
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|
3776 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, pre_val, filtered); |
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|
3777 delayed() -> nop(); |
37f87013dfd8
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|
3778 |
37f87013dfd8
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|
3779 // OK, it's not filtered, so we'll need to call enqueue. In the normal |
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3780 // case, pre_val will be a scratch G-reg, but there's some cases in which |
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|
3781 // it's an O-reg. In the first case, do a normal call. In the latter, |
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|
3782 // do a save here and call the frameless version. |
37f87013dfd8
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|
3783 |
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|
3784 guarantee(pre_val->is_global() || pre_val->is_out(), |
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|
3785 "Or we need to think harder."); |
37f87013dfd8
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|
3786 if (pre_val->is_global() && !preserve_o_regs) { |
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|
3787 generate_satb_log_enqueue_if_necessary(true); // with frame. |
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|
3788 call(satb_log_enqueue_with_frame); |
37f87013dfd8
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124
diff
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|
3789 delayed()->mov(pre_val, O0); |
37f87013dfd8
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124
diff
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|
3790 } else { |
37f87013dfd8
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|
3791 generate_satb_log_enqueue_if_necessary(false); // with frameless. |
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|
3792 save_frame(0); |
37f87013dfd8
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124
diff
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|
3793 call(satb_log_enqueue_frameless); |
37f87013dfd8
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|
3794 delayed()->mov(pre_val->after_save(), O0); |
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|
3795 restore(); |
37f87013dfd8
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124
diff
changeset
|
3796 } |
37f87013dfd8
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124
diff
changeset
|
3797 |
37f87013dfd8
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124
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|
3798 bind(filtered); |
37f87013dfd8
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124
diff
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|
3799 } |
37f87013dfd8
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124
diff
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|
3800 |
37f87013dfd8
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|
3801 static jint num_ct_writes = 0; |
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|
3802 static jint num_ct_writes_filtered_in_hr = 0; |
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|
3803 static jint num_ct_writes_filtered_null = 0; |
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|
3804 static jint num_ct_writes_filtered_pop = 0; |
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|
3805 static G1CollectedHeap* g1 = NULL; |
37f87013dfd8
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|
3806 |
37f87013dfd8
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|
3807 static Thread* count_ct_writes(void* filter_val, void* new_val) { |
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|
3808 Atomic::inc(&num_ct_writes); |
37f87013dfd8
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124
diff
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|
3809 if (filter_val == NULL) { |
37f87013dfd8
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|
3810 Atomic::inc(&num_ct_writes_filtered_in_hr); |
37f87013dfd8
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|
3811 } else if (new_val == NULL) { |
37f87013dfd8
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|
3812 Atomic::inc(&num_ct_writes_filtered_null); |
37f87013dfd8
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|
3813 } else { |
37f87013dfd8
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|
3814 if (g1 == NULL) { |
37f87013dfd8
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|
3815 g1 = G1CollectedHeap::heap(); |
37f87013dfd8
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|
3816 } |
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|
3817 if ((HeapWord*)new_val < g1->popular_object_boundary()) { |
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|
3818 Atomic::inc(&num_ct_writes_filtered_pop); |
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|
3819 } |
37f87013dfd8
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|
3820 } |
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|
3821 if ((num_ct_writes % 1000000) == 0) { |
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|
3822 jint num_ct_writes_filtered = |
37f87013dfd8
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|
3823 num_ct_writes_filtered_in_hr + |
37f87013dfd8
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124
diff
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|
3824 num_ct_writes_filtered_null + |
37f87013dfd8
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124
diff
changeset
|
3825 num_ct_writes_filtered_pop; |
37f87013dfd8
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|
3826 |
37f87013dfd8
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|
3827 tty->print_cr("%d potential CT writes: %5.2f%% filtered\n" |
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|
3828 " (%5.2f%% intra-HR, %5.2f%% null, %5.2f%% popular).", |
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|
3829 num_ct_writes, |
37f87013dfd8
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|
3830 100.0*(float)num_ct_writes_filtered/(float)num_ct_writes, |
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|
3831 100.0*(float)num_ct_writes_filtered_in_hr/ |
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|
3832 (float)num_ct_writes, |
37f87013dfd8
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|
3833 100.0*(float)num_ct_writes_filtered_null/ |
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|
3834 (float)num_ct_writes, |
37f87013dfd8
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124
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|
3835 100.0*(float)num_ct_writes_filtered_pop/ |
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|
3836 (float)num_ct_writes); |
37f87013dfd8
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diff
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|
3837 } |
37f87013dfd8
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|
3838 return Thread::current(); |
37f87013dfd8
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|
3839 } |
37f87013dfd8
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|
3840 |
37f87013dfd8
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|
3841 static address dirty_card_log_enqueue = 0; |
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|
3842 static u_char* dirty_card_log_enqueue_end = 0; |
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|
3843 |
37f87013dfd8
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|
3844 // This gets to assume that o0 contains the object address. |
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|
3845 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) { |
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|
3846 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2); |
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|
3847 CodeBuffer buf(bb->instructions_begin(), bb->instructions_size()); |
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|
3848 MacroAssembler masm(&buf); |
37f87013dfd8
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|
3849 address start = masm.pc(); |
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|
3850 |
37f87013dfd8
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|
3851 Label not_already_dirty, restart, refill; |
37f87013dfd8
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|
3852 |
37f87013dfd8
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|
3853 #ifdef _LP64 |
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|
3854 masm.srlx(O0, CardTableModRefBS::card_shift, O0); |
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|
3855 #else |
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|
3856 masm.srl(O0, CardTableModRefBS::card_shift, O0); |
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|
3857 #endif |
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|
3858 Address rs(O1, (address)byte_map_base); |
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|
3859 masm.load_address(rs); // O1 := <card table base> |
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|
3860 masm.ldub(O0, O1, O2); // O2 := [O0 + O1] |
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|
3861 |
37f87013dfd8
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|
3862 masm.br_on_reg_cond(Assembler::rc_nz, /*annul*/false, Assembler::pt, |
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|
3863 O2, not_already_dirty); |
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|
3864 // Get O1 + O2 into a reg by itself -- useful in the take-the-branch |
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|
3865 // case, harmless if not. |
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|
3866 masm.delayed()->add(O0, O1, O3); |
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|
3867 |
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|
3868 // We didn't take the branch, so we're already dirty: return. |
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|
3869 // Use return-from-leaf |
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|
3870 masm.retl(); |
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|
3871 masm.delayed()->nop(); |
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|
3872 |
37f87013dfd8
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diff
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|
3873 // Not dirty. |
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diff
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|
3874 masm.bind(not_already_dirty); |
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|
3875 // First, dirty it. |
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|
3876 masm.stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty). |
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|
3877 int dirty_card_q_index_byte_offset = |
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|
3878 in_bytes(JavaThread::dirty_card_queue_offset() + |
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|
3879 PtrQueue::byte_offset_of_index()); |
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|
3880 int dirty_card_q_buf_byte_offset = |
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|
3881 in_bytes(JavaThread::dirty_card_queue_offset() + |
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|
3882 PtrQueue::byte_offset_of_buf()); |
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|
3883 masm.bind(restart); |
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|
3884 masm.ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0); |
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|
3885 |
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3886 masm.br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn, |
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|
3887 L0, refill); |
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diff
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|
3888 // If the branch is taken, no harm in executing this in the delay slot. |
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|
3889 masm.delayed()->ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1); |
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|
3890 masm.sub(L0, oopSize, L0); |
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diff
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|
3891 |
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|
3892 masm.st_ptr(O3, L1, L0); // [_buf + index] := I0 |
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diff
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|
3893 // Use return-from-leaf |
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diff
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|
3894 masm.retl(); |
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|
3895 masm.delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset); |
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diff
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|
3896 |
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diff
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|
3897 masm.bind(refill); |
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diff
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|
3898 address handle_zero = |
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diff
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|
3899 CAST_FROM_FN_PTR(address, |
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|
3900 &DirtyCardQueueSet::handle_zero_index_for_thread); |
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diff
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|
3901 // This should be rare enough that we can afford to save all the |
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diff
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|
3902 // scratch registers that the calling context might be using. |
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diff
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|
3903 masm.mov(G1_scratch, L3); |
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diff
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|
3904 masm.mov(G3_scratch, L5); |
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diff
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|
3905 // We need the value of O3 above (for the write into the buffer), so we |
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diff
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|
3906 // save and restore it. |
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diff
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|
3907 masm.mov(O3, L6); |
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|
3908 // Since the call will overwrite O7, we save and restore that, as well. |
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|
3909 masm.mov(O7, L4); |
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diff
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|
3910 |
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|
3911 masm.call_VM_leaf(L7_thread_cache, handle_zero, G2_thread); |
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|
3912 masm.mov(L3, G1_scratch); |
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diff
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|
3913 masm.mov(L5, G3_scratch); |
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diff
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|
3914 masm.mov(L6, O3); |
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|
3915 masm.br(Assembler::always, /*annul*/false, Assembler::pt, restart); |
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diff
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|
3916 masm.delayed()->mov(L4, O7); |
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diff
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|
3917 |
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|
3918 dirty_card_log_enqueue = start; |
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|
3919 dirty_card_log_enqueue_end = masm.pc(); |
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diff
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|
3920 // XXX Should have a guarantee here about not going off the end! |
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diff
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|
3921 // Does it already do so? Do an experiment... |
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diff
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|
3922 } |
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diff
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|
3923 |
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|
3924 static inline void |
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|
3925 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) { |
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|
3926 if (dirty_card_log_enqueue == 0) { |
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|
3927 generate_dirty_card_log_enqueue(byte_map_base); |
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|
3928 assert(dirty_card_log_enqueue != 0, "postcondition."); |
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diff
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|
3929 if (G1SATBPrintStubs) { |
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diff
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|
3930 tty->print_cr("Generated dirty_card enqueue:"); |
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|
3931 Disassembler::decode((u_char*)dirty_card_log_enqueue, |
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|
3932 dirty_card_log_enqueue_end, |
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diff
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|
3933 tty); |
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diff
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|
3934 } |
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diff
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|
3935 } |
37f87013dfd8
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diff
changeset
|
3936 } |
37f87013dfd8
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124
diff
changeset
|
3937 |
37f87013dfd8
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diff
changeset
|
3938 |
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|
3939 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) { |
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|
3940 |
37f87013dfd8
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diff
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|
3941 Label filtered; |
37f87013dfd8
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diff
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|
3942 MacroAssembler* post_filter_masm = this; |
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|
3943 |
37f87013dfd8
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|
3944 if (new_val == G0) return; |
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diff
changeset
|
3945 if (G1DisablePostBarrier) return; |
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diff
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|
3946 |
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|
3947 G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set(); |
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|
3948 assert(bs->kind() == BarrierSet::G1SATBCT || |
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|
3949 bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier"); |
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|
3950 if (G1RSBarrierRegionFilter) { |
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diff
changeset
|
3951 xor3(store_addr, new_val, tmp); |
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diff
changeset
|
3952 #ifdef _LP64 |
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|
3953 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp); |
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diff
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|
3954 #else |
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diff
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|
3955 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp); |
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diff
changeset
|
3956 #endif |
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diff
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|
3957 if (G1PrintCTFilterStats) { |
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diff
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|
3958 guarantee(tmp->is_global(), "Or stats won't work..."); |
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|
3959 // This is a sleazy hack: I'm temporarily hijacking G2, which I |
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diff
changeset
|
3960 // promise to restore. |
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diff
changeset
|
3961 mov(new_val, G2); |
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124
diff
changeset
|
3962 save_frame(0); |
37f87013dfd8
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124
diff
changeset
|
3963 mov(tmp, O0); |
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124
diff
changeset
|
3964 mov(G2, O1); |
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124
diff
changeset
|
3965 // Save G-regs that target may use. |
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diff
changeset
|
3966 mov(G1, L1); |
37f87013dfd8
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124
diff
changeset
|
3967 mov(G2, L2); |
37f87013dfd8
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124
diff
changeset
|
3968 mov(G3, L3); |
37f87013dfd8
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124
diff
changeset
|
3969 mov(G4, L4); |
37f87013dfd8
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124
diff
changeset
|
3970 mov(G5, L5); |
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diff
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|
3971 call(CAST_FROM_FN_PTR(address, &count_ct_writes)); |
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diff
changeset
|
3972 delayed()->nop(); |
37f87013dfd8
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diff
changeset
|
3973 mov(O0, G2); |
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124
diff
changeset
|
3974 // Restore G-regs that target may have used. |
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124
diff
changeset
|
3975 mov(L1, G1); |
37f87013dfd8
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124
diff
changeset
|
3976 mov(L3, G3); |
37f87013dfd8
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124
diff
changeset
|
3977 mov(L4, G4); |
37f87013dfd8
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parents:
124
diff
changeset
|
3978 mov(L5, G5); |
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diff
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|
3979 restore(G0, G0, G0); |
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diff
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|
3980 } |
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|
3981 // XXX Should I predict this taken or not? Does it mattern? |
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|
3982 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered); |
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|
3983 delayed()->nop(); |
37f87013dfd8
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diff
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|
3984 } |
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|
3985 |
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|
3986 // Now we decide how to generate the card table write. If we're |
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|
3987 // enqueueing, we call out to a generated function. Otherwise, we do it |
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diff
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|
3988 // inline here. |
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diff
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|
3989 |
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|
3990 if (G1RSBarrierUseQueue) { |
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|
3991 // If the "store_addr" register is an "in" or "local" register, move it to |
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|
3992 // a scratch reg so we can pass it as an argument. |
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|
3993 bool use_scr = !(store_addr->is_global() || store_addr->is_out()); |
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|
3994 // Pick a scratch register different from "tmp". |
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|
3995 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch); |
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|
3996 // Make sure we use up the delay slot! |
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|
3997 if (use_scr) { |
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|
3998 post_filter_masm->mov(store_addr, scr); |
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|
3999 } else { |
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|
4000 post_filter_masm->nop(); |
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|
4001 } |
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|
4002 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base); |
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|
4003 save_frame(0); |
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|
4004 call(dirty_card_log_enqueue); |
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|
4005 if (use_scr) { |
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|
4006 delayed()->mov(scr, O0); |
37f87013dfd8
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|
4007 } else { |
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|
4008 delayed()->mov(store_addr->after_save(), O0); |
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|
4009 } |
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|
4010 restore(); |
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|
4011 |
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|
4012 } else { |
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|
4013 |
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|
4014 #ifdef _LP64 |
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|
4015 post_filter_masm->srlx(store_addr, CardTableModRefBS::card_shift, store_addr); |
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|
4016 #else |
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|
4017 post_filter_masm->srl(store_addr, CardTableModRefBS::card_shift, store_addr); |
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|
4018 #endif |
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|
4019 assert( tmp != store_addr, "need separate temp reg"); |
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diff
changeset
|
4020 Address rs(tmp, (address)bs->byte_map_base); |
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6711316: Open source the Garbage-First garbage collector
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parents:
124
diff
changeset
|
4021 load_address(rs); |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
124
diff
changeset
|
4022 stb(G0, rs.base(), store_addr); |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
124
diff
changeset
|
4023 } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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parents:
124
diff
changeset
|
4024 |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
124
diff
changeset
|
4025 bind(filtered); |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
124
diff
changeset
|
4026 |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
124
diff
changeset
|
4027 } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
124
diff
changeset
|
4028 |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
124
diff
changeset
|
4029 #endif // SERIALGC |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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parents:
124
diff
changeset
|
4030 /////////////////////////////////////////////////////////////////////////////////// |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
124
diff
changeset
|
4031 |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
ysr
parents:
124
diff
changeset
|
4032 void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) { |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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parents:
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diff
changeset
|
4033 // If we're writing constant NULL, we can skip the write barrier. |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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parents:
124
diff
changeset
|
4034 if (new_val == G0) return; |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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parents:
124
diff
changeset
|
4035 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set(); |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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parents:
124
diff
changeset
|
4036 assert(bs->kind() == BarrierSet::CardTableModRef || |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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parents:
124
diff
changeset
|
4037 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier"); |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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parents:
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diff
changeset
|
4038 card_table_write(bs->byte_map_base, tmp, store_addr); |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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parents:
124
diff
changeset
|
4039 } |
37f87013dfd8
6711316: Open source the Garbage-First garbage collector
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diff
changeset
|
4040 |
113
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diff
changeset
|
4041 void MacroAssembler::load_klass(Register s, Register d) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4042 // The number of bytes in this code is used by |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
changeset
|
4043 // MachCallDynamicJavaNode::ret_addr_offset() |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
changeset
|
4044 // if this changes, change that. |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4045 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4046 lduw(s, oopDesc::klass_offset_in_bytes(), d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4047 decode_heap_oop_not_null(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
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|
4048 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
changeset
|
4049 ld_ptr(s, oopDesc::klass_offset_in_bytes(), d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
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|
4050 } |
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
changeset
|
4051 } |
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
changeset
|
4052 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4053 // ??? figure out src vs. dst! |
ba764ed4b6f2
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parents:
0
diff
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|
4054 void MacroAssembler::store_klass(Register d, Register s1) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4055 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4056 assert(s1 != d, "not enough registers"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
changeset
|
4057 encode_heap_oop_not_null(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
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|
4058 // Zero out entire klass field first. |
ba764ed4b6f2
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parents:
0
diff
changeset
|
4059 st_ptr(G0, s1, oopDesc::klass_offset_in_bytes()); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
changeset
|
4060 st(d, s1, oopDesc::klass_offset_in_bytes()); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
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|
4061 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
changeset
|
4062 st_ptr(d, s1, oopDesc::klass_offset_in_bytes()); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
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|
4063 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
changeset
|
4064 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4065 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4066 void MacroAssembler::load_heap_oop(const Address& s, Register d, int offset) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4067 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4068 lduw(s, d, offset); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4069 decode_heap_oop(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
changeset
|
4070 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4071 ld_ptr(s, d, offset); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4072 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
changeset
|
4073 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4074 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4075 void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4076 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4077 lduw(s1, s2, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4078 decode_heap_oop(d, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4079 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4080 ld_ptr(s1, s2, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
changeset
|
4081 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4082 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4083 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4084 void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4085 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4086 lduw(s1, simm13a, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4087 decode_heap_oop(d, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4088 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4089 ld_ptr(s1, simm13a, d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4090 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4091 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4092 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4093 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4094 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4095 assert(s1 != d && s2 != d, "not enough registers"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4096 encode_heap_oop(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4097 st(d, s1, s2); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4098 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4099 st_ptr(d, s1, s2); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4100 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4101 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4102 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4103 void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4104 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4105 assert(s1 != d, "not enough registers"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4106 encode_heap_oop(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4107 st(d, s1, simm13a); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
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|
4108 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4109 st_ptr(d, s1, simm13a); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4110 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4111 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4112 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4113 void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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0
diff
changeset
|
4114 if (UseCompressedOops) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4115 assert(a.base() != d, "not enough registers"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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parents:
0
diff
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|
4116 encode_heap_oop(d); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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0
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changeset
|
4117 st(d, a, offset); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
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0
diff
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|
4118 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4119 st_ptr(d, a, offset); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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0
diff
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|
4120 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4121 } |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4122 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4123 |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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0
diff
changeset
|
4124 void MacroAssembler::encode_heap_oop(Register src, Register dst) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4125 assert (UseCompressedOops, "must be compressed"); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4126 Label done; |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4127 if (src == dst) { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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0
diff
changeset
|
4128 // optimize for frequent case src == dst |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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0
diff
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|
4129 bpr(rc_nz, true, Assembler::pt, src, done); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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0
diff
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|
4130 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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0
diff
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|
4131 bind(done); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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0
diff
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|
4132 srlx(src, LogMinObjAlignmentInBytes, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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0
diff
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|
4133 } else { |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4134 bpr(rc_z, false, Assembler::pn, src, done); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4135 delayed() -> mov(G0, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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0
diff
changeset
|
4136 // could be moved before branch, and annulate delay, |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4137 // but may add some unneeded work decoding null |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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0
diff
changeset
|
4138 sub(src, G6_heapbase, dst); |
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
0
diff
changeset
|
4139 srlx(dst, LogMinObjAlignmentInBytes, dst); |
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4140 bind(done); |
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4141 } |
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4142 } |
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4143 |
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4144 |
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4145 void MacroAssembler::encode_heap_oop_not_null(Register r) { |
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4146 assert (UseCompressedOops, "must be compressed"); |
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4147 sub(r, G6_heapbase, r); |
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4148 srlx(r, LogMinObjAlignmentInBytes, r); |
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4149 } |
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4150 |
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4151 void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) { |
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4152 assert (UseCompressedOops, "must be compressed"); |
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4153 sub(src, G6_heapbase, dst); |
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4154 srlx(dst, LogMinObjAlignmentInBytes, dst); |
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4155 } |
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4156 |
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4157 // Same algorithm as oops.inline.hpp decode_heap_oop. |
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4158 void MacroAssembler::decode_heap_oop(Register src, Register dst) { |
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4159 assert (UseCompressedOops, "must be compressed"); |
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4160 Label done; |
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4161 sllx(src, LogMinObjAlignmentInBytes, dst); |
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4162 bpr(rc_nz, true, Assembler::pt, dst, done); |
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4163 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken |
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4164 bind(done); |
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4165 } |
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4166 |
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4167 void MacroAssembler::decode_heap_oop_not_null(Register r) { |
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4168 // Do not add assert code to this unless you change vtableStubs_sparc.cpp |
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4169 // pd_code_size_limit. |
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4170 assert (UseCompressedOops, "must be compressed"); |
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4171 sllx(r, LogMinObjAlignmentInBytes, r); |
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4172 add(r, G6_heapbase, r); |
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4173 } |
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4174 |
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4175 void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) { |
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4176 // Do not add assert code to this unless you change vtableStubs_sparc.cpp |
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4177 // pd_code_size_limit. |
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4178 assert (UseCompressedOops, "must be compressed"); |
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4179 sllx(src, LogMinObjAlignmentInBytes, dst); |
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4180 add(dst, G6_heapbase, dst); |
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4181 } |
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4182 |
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4183 void MacroAssembler::reinit_heapbase() { |
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4184 if (UseCompressedOops) { |
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4185 // call indirectly to solve generation ordering problem |
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4186 Address base(G6_heapbase, (address)Universe::heap_base_addr()); |
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4187 load_ptr_contents(base, G6_heapbase); |
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4188 } |
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4189 } |