Mercurial > hg > graal-compiler
annotate graal/GraalCompiler/src/com/sun/c1x/alloc/LinearScanWalker.java @ 2776:398b8fa5dc81
Removed stateAfter from BlockEnd class. Clean up.
author | Thomas Wuerthinger <thomas@wuerthinger.net> |
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date | Tue, 24 May 2011 13:55:56 +0200 |
parents | a2f62de90c76 |
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rev | line source |
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1 /* |
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2 * Copyright (c) 2009, 2011, Oracle and/or its affiliates. All rights reserved. |
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
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4 * |
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5 * This code is free software; you can redistribute it and/or modify it |
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6 * under the terms of the GNU General Public License version 2 only, as |
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7 * published by the Free Software Foundation. |
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8 * |
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9 * This code is distributed in the hope that it will be useful, but WITHOUT |
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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12 * version 2 for more details (a copy is included in the LICENSE file that |
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13 * accompanied this code). |
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14 * |
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15 * You should have received a copy of the GNU General Public License version |
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16 * 2 along with this work; if not, write to the Free Software Foundation, |
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
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18 * |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
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22 */ |
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23 package com.sun.c1x.alloc; |
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24 |
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25 import static com.sun.cri.ci.CiUtil.*; |
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26 |
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27 import java.util.*; |
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28 |
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29 import com.sun.c1x.*; |
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30 import com.sun.c1x.alloc.Interval.*; |
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31 import com.sun.c1x.debug.*; |
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32 import com.sun.c1x.lir.*; |
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33 import com.sun.c1x.util.*; |
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34 import com.sun.cri.ci.*; |
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35 import com.sun.cri.ci.CiRegister.*; |
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36 |
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37 /** |
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38 * |
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39 * @author Thomas Wuerthinger |
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40 */ |
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41 final class LinearScanWalker extends IntervalWalker { |
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42 |
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43 private CiRegister[] availableRegs; |
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44 |
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45 private final int[] usePos; |
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46 private final int[] blockPos; |
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47 |
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48 private List<Interval>[] spillIntervals; |
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49 |
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50 private MoveResolver moveResolver; // for ordering spill moves |
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51 |
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52 // accessors mapped to same functions in class LinearScan |
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53 int blockCount() { |
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54 return allocator.blockCount(); |
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55 } |
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56 |
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57 LIRBlock blockAt(int idx) { |
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58 return allocator.blockAt(idx); |
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59 } |
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60 |
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61 LIRBlock blockOfOpWithId(int opId) { |
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62 return allocator.blockForId(opId); |
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63 } |
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64 |
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65 LinearScanWalker(LinearScan allocator, Interval unhandledFixedFirst, Interval unhandledAnyFirst) { |
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66 super(allocator, unhandledFixedFirst, unhandledAnyFirst); |
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67 moveResolver = new MoveResolver(allocator); |
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68 spillIntervals = Util.uncheckedCast(new List[allocator.registers.length]); |
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69 for (int i = 0; i < allocator.registers.length; i++) { |
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70 spillIntervals[i] = new ArrayList<Interval>(2); |
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71 } |
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72 usePos = new int[allocator.registers.length]; |
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73 blockPos = new int[allocator.registers.length]; |
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74 } |
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75 |
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76 void initUseLists(boolean onlyProcessUsePos) { |
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77 for (CiRegister register : availableRegs) { |
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78 int i = register.number; |
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79 usePos[i] = Integer.MAX_VALUE; |
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80 |
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81 if (!onlyProcessUsePos) { |
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82 blockPos[i] = Integer.MAX_VALUE; |
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83 spillIntervals[i].clear(); |
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84 } |
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85 } |
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86 } |
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87 |
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88 void excludeFromUse(Interval i) { |
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89 CiValue location = i.location(); |
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90 int i1 = location.asRegister().number; |
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91 if (i1 >= availableRegs[0].number && i1 <= availableRegs[availableRegs.length - 1].number) { |
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92 usePos[i1] = 0; |
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93 } |
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94 } |
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95 |
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96 void setUsePos(Interval interval, int usePos, boolean onlyProcessUsePos) { |
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97 if (usePos != -1) { |
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98 assert usePos != 0 : "must use excludeFromUse to set usePos to 0"; |
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99 int i = interval.location().asRegister().number; |
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100 if (i >= availableRegs[0].number && i <= availableRegs[availableRegs.length - 1].number) { |
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101 if (this.usePos[i] > usePos) { |
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102 this.usePos[i] = usePos; |
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103 } |
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104 if (!onlyProcessUsePos) { |
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105 spillIntervals[i].add(interval); |
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106 } |
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107 } |
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108 } |
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109 } |
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110 |
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111 void setBlockPos(Interval i, int blockPos) { |
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112 if (blockPos != -1) { |
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113 int reg = i.location().asRegister().number; |
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114 if (reg >= availableRegs[0].number && reg <= availableRegs[availableRegs.length - 1].number) { |
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115 if (this.blockPos[reg] > blockPos) { |
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116 this.blockPos[reg] = blockPos; |
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117 } |
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118 if (usePos[reg] > blockPos) { |
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119 usePos[reg] = blockPos; |
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120 } |
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121 } |
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122 } |
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123 } |
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124 |
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125 void freeExcludeActiveFixed() { |
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126 Interval interval = activeLists.get(RegisterBinding.Fixed); |
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127 while (interval != Interval.EndMarker) { |
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128 assert interval.location().isRegister() : "active interval must have a register assigned"; |
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129 excludeFromUse(interval); |
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130 interval = interval.next; |
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131 } |
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132 } |
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133 |
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134 void freeExcludeActiveAny() { |
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135 Interval interval = activeLists.get(RegisterBinding.Any); |
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136 while (interval != Interval.EndMarker) { |
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137 assert interval.location().isRegister() : "active interval must have a register assigned"; |
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138 excludeFromUse(interval); |
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139 interval = interval.next; |
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140 } |
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141 } |
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142 |
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143 void freeCollectInactiveFixed(Interval current) { |
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144 Interval interval = inactiveLists.get(RegisterBinding.Fixed); |
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145 while (interval != Interval.EndMarker) { |
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146 if (current.to() <= interval.currentFrom()) { |
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147 assert interval.currentIntersectsAt(current) == -1 : "must not intersect"; |
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148 setUsePos(interval, interval.currentFrom(), true); |
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149 } else { |
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150 setUsePos(interval, interval.currentIntersectsAt(current), true); |
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151 } |
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152 interval = interval.next; |
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153 } |
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154 } |
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155 |
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156 void freeCollectInactiveAny(Interval current) { |
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157 Interval interval = inactiveLists.get(RegisterBinding.Any); |
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158 while (interval != Interval.EndMarker) { |
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159 setUsePos(interval, interval.currentIntersectsAt(current), true); |
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160 interval = interval.next; |
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161 } |
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162 } |
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163 |
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164 void freeCollectUnhandled(RegisterBinding kind, Interval current) { |
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165 Interval interval = unhandledLists.get(kind); |
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166 while (interval != Interval.EndMarker) { |
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167 setUsePos(interval, interval.intersectsAt(current), true); |
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168 if (kind == RegisterBinding.Fixed && current.to() <= interval.from()) { |
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169 setUsePos(interval, interval.from(), true); |
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170 } |
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171 interval = interval.next; |
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172 } |
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173 } |
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174 |
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175 void spillExcludeActiveFixed() { |
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176 Interval interval = activeLists.get(RegisterBinding.Fixed); |
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177 while (interval != Interval.EndMarker) { |
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178 excludeFromUse(interval); |
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179 interval = interval.next; |
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180 } |
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181 } |
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182 |
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183 void spillBlockUnhandledFixed(Interval current) { |
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184 Interval interval = unhandledLists.get(RegisterBinding.Fixed); |
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185 while (interval != Interval.EndMarker) { |
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186 setBlockPos(interval, interval.intersectsAt(current)); |
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187 interval = interval.next; |
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188 } |
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189 } |
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190 |
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191 void spillBlockInactiveFixed(Interval current) { |
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192 Interval interval = inactiveLists.get(RegisterBinding.Fixed); |
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193 while (interval != Interval.EndMarker) { |
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194 if (current.to() > interval.currentFrom()) { |
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195 setBlockPos(interval, interval.currentIntersectsAt(current)); |
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196 } else { |
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197 assert interval.currentIntersectsAt(current) == -1 : "invalid optimization: intervals intersect"; |
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198 } |
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199 |
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200 interval = interval.next; |
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201 } |
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202 } |
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203 |
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204 void spillCollectActiveAny() { |
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205 Interval interval = activeLists.get(RegisterBinding.Any); |
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206 while (interval != Interval.EndMarker) { |
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207 setUsePos(interval, Math.min(interval.nextUsage(RegisterPriority.LiveAtLoopEnd, currentPosition), interval.to()), false); |
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208 interval = interval.next; |
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209 } |
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210 } |
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211 |
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212 void spillCollectInactiveAny(Interval current) { |
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213 Interval interval = inactiveLists.get(RegisterBinding.Any); |
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214 while (interval != Interval.EndMarker) { |
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215 if (interval.currentIntersects(current)) { |
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216 setUsePos(interval, Math.min(interval.nextUsage(RegisterPriority.LiveAtLoopEnd, currentPosition), interval.to()), false); |
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217 } |
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218 interval = interval.next; |
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219 } |
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220 } |
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221 |
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222 void insertMove(int opId, Interval srcIt, Interval dstIt) { |
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223 // output all moves here. When source and target are equal, the move is |
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224 // optimized away later in assignRegNums |
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225 |
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226 opId = (opId + 1) & ~1; |
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227 LIRBlock opBlock = allocator.blockForId(opId); |
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228 assert opId > 0 && allocator.blockForId(opId - 2) == opBlock : "cannot insert move at block boundary"; |
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229 |
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230 // calculate index of instruction inside instruction list of current block |
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231 // the minimal index (for a block with no spill moves) can be calculated because the |
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232 // numbering of instructions is known. |
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233 // When the block already contains spill moves, the index must be increased until the |
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234 // correct index is reached. |
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235 List<LIRInstruction> list = opBlock.lir().instructionsList(); |
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236 int index = (opId - list.get(0).id) >> 1; |
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237 assert list.get(index).id <= opId : "error in calculation"; |
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238 |
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239 while (list.get(index).id != opId) { |
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240 index++; |
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241 assert 0 <= index && index < list.size() : "index out of bounds"; |
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242 } |
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243 assert 1 <= index && index < list.size() : "index out of bounds"; |
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244 assert list.get(index).id == opId : "error in calculation"; |
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245 |
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246 // insert new instruction before instruction at position index |
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247 moveResolver.moveInsertPosition(opBlock.lir(), index - 1); |
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248 moveResolver.addMapping(srcIt, dstIt); |
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249 } |
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250 |
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251 int findOptimalSplitPos(LIRBlock minBlock, LIRBlock maxBlock, int maxSplitPos) { |
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252 int fromBlockNr = minBlock.linearScanNumber(); |
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253 int toBlockNr = maxBlock.linearScanNumber(); |
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254 |
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255 assert 0 <= fromBlockNr && fromBlockNr < blockCount() : "out of range"; |
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256 assert 0 <= toBlockNr && toBlockNr < blockCount() : "out of range"; |
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257 assert fromBlockNr < toBlockNr : "must cross block boundary"; |
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258 |
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259 // Try to split at end of maxBlock. If this would be after |
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260 // maxSplitPos, then use the begin of maxBlock |
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261 int optimalSplitPos = maxBlock.lastLirInstructionId() + 2; |
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262 if (optimalSplitPos > maxSplitPos) { |
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263 optimalSplitPos = maxBlock.firstLirInstructionId(); |
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264 } |
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265 |
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266 int minLoopDepth = maxBlock.loopDepth(); |
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267 for (int i = toBlockNr - 1; i >= fromBlockNr; i--) { |
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268 LIRBlock cur = blockAt(i); |
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269 |
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270 if (cur.loopDepth() < minLoopDepth) { |
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271 // block with lower loop-depth found . split at the end of this block |
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272 minLoopDepth = cur.loopDepth(); |
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273 optimalSplitPos = cur.lastLirInstructionId() + 2; |
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274 } |
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275 } |
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276 assert optimalSplitPos > allocator.maxOpId() || allocator.isBlockBegin(optimalSplitPos) : "algorithm must move split pos to block boundary"; |
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277 |
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278 return optimalSplitPos; |
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279 } |
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280 |
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281 int findOptimalSplitPos(Interval interval, int minSplitPos, int maxSplitPos, boolean doLoopOptimization) { |
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282 int optimalSplitPos = -1; |
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283 if (minSplitPos == maxSplitPos) { |
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284 // trivial case, no optimization of split position possible |
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285 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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286 TTY.println(" min-pos and max-pos are equal, no optimization possible"); |
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287 } |
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288 optimalSplitPos = minSplitPos; |
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289 |
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290 } else { |
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291 assert minSplitPos < maxSplitPos : "must be true then"; |
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292 assert minSplitPos > 0 : "cannot access minSplitPos - 1 otherwise"; |
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293 |
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294 // reason for using minSplitPos - 1: when the minimal split pos is exactly at the |
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295 // beginning of a block, then minSplitPos is also a possible split position. |
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296 // Use the block before as minBlock, because then minBlock.lastLirInstructionId() + 2 == minSplitPos |
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297 LIRBlock minBlock = allocator.blockForId(minSplitPos - 1); |
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298 |
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299 // reason for using maxSplitPos - 1: otherwise there would be an assert on failure |
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300 // when an interval ends at the end of the last block of the method |
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301 // (in this case, maxSplitPos == allocator().maxLirOpId() + 2, and there is no |
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302 // block at this opId) |
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303 LIRBlock maxBlock = allocator.blockForId(maxSplitPos - 1); |
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304 |
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305 assert minBlock.linearScanNumber() <= maxBlock.linearScanNumber() : "invalid order"; |
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306 if (minBlock == maxBlock) { |
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307 // split position cannot be moved to block boundary : so split as late as possible |
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308 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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309 TTY.println(" cannot move split pos to block boundary because minPos and maxPos are in same block"); |
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310 } |
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311 optimalSplitPos = maxSplitPos; |
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312 |
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313 } else { |
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314 if (interval.hasHoleBetween(maxSplitPos - 1, maxSplitPos) && !allocator.isBlockBegin(maxSplitPos)) { |
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315 // Do not move split position if the interval has a hole before maxSplitPos. |
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316 // Intervals resulting from Phi-Functions have more than one definition (marked |
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317 // as mustHaveRegister) with a hole before each definition. When the register is needed |
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318 // for the second definition : an earlier reloading is unnecessary. |
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319 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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320 TTY.println(" interval has hole just before maxSplitPos, so splitting at maxSplitPos"); |
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321 } |
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322 optimalSplitPos = maxSplitPos; |
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323 |
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324 } else { |
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325 // seach optimal block boundary between minSplitPos and maxSplitPos |
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326 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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327 TTY.println(" moving split pos to optimal block boundary between block B%d and B%d", minBlock.blockID(), maxBlock.blockID()); |
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328 } |
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329 |
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330 if (doLoopOptimization) { |
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331 // Loop optimization: if a loop-end marker is found between min- and max-position : |
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332 // then split before this loop |
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333 int loopEndPos = interval.nextUsageExact(RegisterPriority.LiveAtLoopEnd, minBlock.lastLirInstructionId() + 2); |
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334 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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335 TTY.println(" loop optimization: loop end found at pos %d", loopEndPos); |
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336 } |
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337 |
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338 assert loopEndPos > minSplitPos : "invalid order"; |
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339 if (loopEndPos < maxSplitPos) { |
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340 // loop-end marker found between min- and max-position |
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341 // if it is not the end marker for the same loop as the min-position : then move |
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342 // the max-position to this loop block. |
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343 // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading |
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344 // of the interval (normally, only mustHaveRegister causes a reloading) |
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345 LIRBlock loopBlock = allocator.blockForId(loopEndPos); |
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346 |
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347 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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348 TTY.println(" interval is used in loop that ends in block B%d, so trying to move maxBlock back from B%d to B%d", loopBlock.blockID(), maxBlock.blockID(), loopBlock.blockID()); |
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349 } |
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350 assert loopBlock != minBlock : "loopBlock and minBlock must be different because block boundary is needed between"; |
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351 |
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352 optimalSplitPos = findOptimalSplitPos(minBlock, loopBlock, loopBlock.lastLirInstructionId() + 2); |
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353 if (optimalSplitPos == loopBlock.lastLirInstructionId() + 2) { |
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354 optimalSplitPos = -1; |
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355 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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356 TTY.println(" loop optimization not necessary"); |
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357 } |
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358 } else { |
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359 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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360 TTY.println(" loop optimization successful"); |
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361 } |
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362 } |
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363 } |
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364 } |
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365 |
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366 if (optimalSplitPos == -1) { |
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367 // not calculated by loop optimization |
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368 optimalSplitPos = findOptimalSplitPos(minBlock, maxBlock, maxSplitPos); |
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369 } |
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370 } |
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371 } |
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372 } |
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373 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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374 TTY.println(" optimal split position: %d", optimalSplitPos); |
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375 } |
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376 |
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377 return optimalSplitPos; |
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378 } |
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379 |
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380 // split an interval at the optimal position between minSplitPos and |
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381 // maxSplitPos in two parts: |
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382 // 1) the left part has already a location assigned |
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383 // 2) the right part is sorted into to the unhandled-list |
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384 void splitBeforeUsage(Interval interval, int minSplitPos, int maxSplitPos) { |
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385 if (C1XOptions.TraceLinearScanLevel >= 2) { |
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386 TTY.println("----- splitting interval: "); |
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387 } |
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388 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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389 TTY.println(interval.logString(allocator)); |
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390 } |
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391 if (C1XOptions.TraceLinearScanLevel >= 2) { |
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392 TTY.println(" between %d and %d", minSplitPos, maxSplitPos); |
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393 } |
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394 |
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395 assert interval.from() < minSplitPos : "cannot split at start of interval"; |
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396 assert currentPosition < minSplitPos : "cannot split before current position"; |
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397 assert minSplitPos <= maxSplitPos : "invalid order"; |
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398 assert maxSplitPos <= interval.to() : "cannot split after end of interval"; |
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399 |
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400 int optimalSplitPos = findOptimalSplitPos(interval, minSplitPos, maxSplitPos, true); |
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401 |
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402 assert minSplitPos <= optimalSplitPos && optimalSplitPos <= maxSplitPos : "out of range"; |
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403 assert optimalSplitPos <= interval.to() : "cannot split after end of interval"; |
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404 assert optimalSplitPos > interval.from() : "cannot split at start of interval"; |
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405 |
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406 if (optimalSplitPos == interval.to() && interval.nextUsage(RegisterPriority.MustHaveRegister, minSplitPos) == Integer.MAX_VALUE) { |
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407 // the split position would be just before the end of the interval |
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408 // . no split at all necessary |
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409 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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410 TTY.println(" no split necessary because optimal split position is at end of interval"); |
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411 } |
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412 return; |
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413 } |
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414 |
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415 // must calculate this before the actual split is performed and before split position is moved to odd opId |
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416 boolean moveNecessary = !allocator.isBlockBegin(optimalSplitPos) && !interval.hasHoleBetween(optimalSplitPos - 1, optimalSplitPos); |
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417 |
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418 if (!allocator.isBlockBegin(optimalSplitPos)) { |
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419 // move position before actual instruction (odd opId) |
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420 optimalSplitPos = (optimalSplitPos - 1) | 1; |
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421 } |
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422 |
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423 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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424 TTY.println(" splitting at position %d", optimalSplitPos); |
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425 } |
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426 assert allocator.isBlockBegin(optimalSplitPos) || (optimalSplitPos % 2 == 1) : "split pos must be odd when not on block boundary"; |
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427 assert !allocator.isBlockBegin(optimalSplitPos) || (optimalSplitPos % 2 == 0) : "split pos must be even on block boundary"; |
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428 |
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429 Interval splitPart = interval.split(optimalSplitPos, allocator); |
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430 |
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431 allocator.copyRegisterFlags(interval, splitPart); |
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432 splitPart.setInsertMoveWhenActivated(moveNecessary); |
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433 |
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434 assert splitPart.from() >= current.currentFrom() : "cannot append new interval before current walk position"; |
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435 unhandledLists.addToListSortedByStartAndUsePositions(RegisterBinding.Any, splitPart); |
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436 |
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437 if (C1XOptions.TraceLinearScanLevel >= 2) { |
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438 TTY.println(" split interval in two parts (insertMoveWhenActivated: %b)", moveNecessary); |
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439 } |
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440 if (C1XOptions.TraceLinearScanLevel >= 2) { |
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441 TTY.print(" "); |
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442 TTY.println(interval.logString(allocator)); |
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443 TTY.print(" "); |
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444 TTY.println(splitPart.logString(allocator)); |
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445 } |
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446 } |
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447 |
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448 // split an interval at the optimal position between minSplitPos and |
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449 // maxSplitPos in two parts: |
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450 // 1) the left part has already a location assigned |
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451 // 2) the right part is always on the stack and therefore ignored in further processing |
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452 |
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453 void splitForSpilling(Interval interval) { |
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454 // calculate allowed range of splitting position |
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455 int maxSplitPos = currentPosition; |
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456 int minSplitPos = Math.max(interval.previousUsage(RegisterPriority.ShouldHaveRegister, maxSplitPos) + 1, interval.from()); |
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457 |
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458 if (C1XOptions.TraceLinearScanLevel >= 2) { |
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459 TTY.print("----- splitting and spilling interval: "); |
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460 TTY.println(interval.logString(allocator)); |
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461 TTY.println(" between %d and %d", minSplitPos, maxSplitPos); |
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462 } |
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463 |
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464 assert interval.state == State.Active : "why spill interval that is not active?"; |
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465 assert interval.from() <= minSplitPos : "cannot split before start of interval"; |
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466 assert minSplitPos <= maxSplitPos : "invalid order"; |
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467 assert maxSplitPos < interval.to() : "cannot split at end end of interval"; |
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468 assert currentPosition < interval.to() : "interval must not end before current position"; |
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469 |
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470 if (minSplitPos == interval.from()) { |
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471 // the whole interval is never used, so spill it entirely to memory |
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472 if (C1XOptions.TraceLinearScanLevel >= 2) { |
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473 TTY.println(" spilling entire interval because split pos is at beginning of interval"); |
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474 TTY.println(" use positions: " + interval.usePosList().size()); |
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475 } |
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476 assert interval.firstUsage(RegisterPriority.ShouldHaveRegister) > currentPosition : "interval must not have use position before currentPosition"; |
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477 |
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478 allocator.assignSpillSlot(interval); |
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479 allocator.changeSpillState(interval, minSplitPos); |
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480 |
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481 // Also kick parent intervals out of register to memory when they have no use |
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482 // position. This avoids short interval in register surrounded by intervals in |
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483 // memory . avoid useless moves from memory to register and back |
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484 Interval parent = interval; |
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485 while (parent != null && parent.isSplitChild()) { |
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486 parent = parent.getSplitChildBeforeOpId(parent.from()); |
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487 |
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488 if (parent.location().isRegister()) { |
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489 if (parent.firstUsage(RegisterPriority.ShouldHaveRegister) == Integer.MAX_VALUE) { |
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490 // parent is never used, so kick it out of its assigned register |
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491 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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492 TTY.println(" kicking out interval %d out of its register because it is never used", parent.operandNumber); |
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493 } |
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494 allocator.assignSpillSlot(parent); |
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495 } else { |
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496 // do not go further back because the register is actually used by the interval |
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497 parent = null; |
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498 } |
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499 } |
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500 } |
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501 |
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502 } else { |
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503 // search optimal split pos, split interval and spill only the right hand part |
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504 int optimalSplitPos = findOptimalSplitPos(interval, minSplitPos, maxSplitPos, false); |
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505 |
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506 assert minSplitPos <= optimalSplitPos && optimalSplitPos <= maxSplitPos : "out of range"; |
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507 assert optimalSplitPos < interval.to() : "cannot split at end of interval"; |
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508 assert optimalSplitPos >= interval.from() : "cannot split before start of interval"; |
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509 |
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510 if (!allocator.isBlockBegin(optimalSplitPos)) { |
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511 // move position before actual instruction (odd opId) |
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512 optimalSplitPos = (optimalSplitPos - 1) | 1; |
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513 } |
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514 |
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515 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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516 TTY.println(" splitting at position %d", optimalSplitPos); |
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517 } |
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518 assert allocator.isBlockBegin(optimalSplitPos) || (optimalSplitPos % 2 == 1) : "split pos must be odd when not on block boundary"; |
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519 assert !allocator.isBlockBegin(optimalSplitPos) || (optimalSplitPos % 2 == 0) : "split pos must be even on block boundary"; |
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520 |
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521 Interval spilledPart = interval.split(optimalSplitPos, allocator); |
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522 allocator.assignSpillSlot(spilledPart); |
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523 allocator.changeSpillState(spilledPart, optimalSplitPos); |
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524 |
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525 if (!allocator.isBlockBegin(optimalSplitPos)) { |
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526 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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527 TTY.println(" inserting move from interval %d to %d", interval.operandNumber, spilledPart.operandNumber); |
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528 } |
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529 insertMove(optimalSplitPos, interval, spilledPart); |
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530 } |
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531 |
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532 // the currentSplitChild is needed later when moves are inserted for reloading |
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533 assert spilledPart.currentSplitChild() == interval : "overwriting wrong currentSplitChild"; |
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534 spilledPart.makeCurrentSplitChild(); |
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535 |
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536 if (C1XOptions.TraceLinearScanLevel >= 2) { |
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537 TTY.println(" split interval in two parts"); |
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538 TTY.print(" "); |
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539 TTY.println(interval.logString(allocator)); |
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540 TTY.print(" "); |
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541 TTY.println(spilledPart.logString(allocator)); |
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542 } |
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543 } |
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544 } |
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545 |
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546 void splitStackInterval(Interval interval) { |
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547 int minSplitPos = currentPosition + 1; |
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548 int maxSplitPos = Math.min(interval.firstUsage(RegisterPriority.ShouldHaveRegister), interval.to()); |
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549 |
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550 splitBeforeUsage(interval, minSplitPos, maxSplitPos); |
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551 } |
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552 |
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553 void splitWhenPartialRegisterAvailable(Interval interval, int registerAvailableUntil) { |
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554 int minSplitPos = Math.max(interval.previousUsage(RegisterPriority.ShouldHaveRegister, registerAvailableUntil), interval.from() + 1); |
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555 splitBeforeUsage(interval, minSplitPos, registerAvailableUntil); |
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556 } |
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557 |
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558 void splitAndSpillInterval(Interval interval) { |
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559 assert interval.state == State.Active || interval.state == State.Inactive : "other states not allowed"; |
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560 |
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561 int currentPos = currentPosition; |
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562 if (interval.state == State.Inactive) { |
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563 // the interval is currently inactive, so no spill slot is needed for now. |
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564 // when the split part is activated, the interval has a new chance to get a register, |
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565 // so in the best case no stack slot is necessary |
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566 assert interval.hasHoleBetween(currentPos - 1, currentPos + 1) : "interval can not be inactive otherwise"; |
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567 splitBeforeUsage(interval, currentPos + 1, currentPos + 1); |
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568 |
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569 } else { |
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Thomas Wuerthinger <thomas@wuerthinger.net>
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570 // search the position where the interval must have a register and split |
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571 // at the optimal position before. |
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572 // The new created part is added to the unhandled list and will get a register |
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573 // when it is activated |
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574 int minSplitPos = currentPos + 1; |
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575 int maxSplitPos = Math.min(interval.nextUsage(RegisterPriority.MustHaveRegister, minSplitPos), interval.to()); |
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576 |
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577 splitBeforeUsage(interval, minSplitPos, maxSplitPos); |
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578 |
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579 assert interval.nextUsage(RegisterPriority.MustHaveRegister, currentPos) == Integer.MAX_VALUE : "the remaining part is spilled to stack and therefore has no register"; |
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580 splitForSpilling(interval); |
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581 } |
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582 } |
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583 |
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584 boolean allocFreeRegister(Interval interval) { |
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585 if (C1XOptions.TraceLinearScanLevel >= 2) { |
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586 TTY.println("trying to find free register for " + interval.logString(allocator)); |
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587 } |
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588 |
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589 initUseLists(true); |
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590 freeExcludeActiveFixed(); |
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591 freeExcludeActiveAny(); |
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592 freeCollectInactiveFixed(interval); |
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593 freeCollectInactiveAny(interval); |
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594 // freeCollectUnhandled(fixedKind, cur); |
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595 assert unhandledLists.get(RegisterBinding.Fixed) == Interval.EndMarker : "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"; |
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596 |
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597 // usePos contains the start of the next interval that has this register assigned |
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598 // (either as a fixed register or a normal allocated register in the past) |
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599 // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely |
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changeset
|
600 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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601 TTY.println(" state of registers:"); |
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602 for (CiRegister register : availableRegs) { |
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|
603 int i = register.number; |
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|
604 TTY.println(" reg %d: usePos: %d", register.number, usePos[i]); |
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605 } |
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|
606 } |
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diff
changeset
|
607 |
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|
608 CiRegister hint = null; |
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diff
changeset
|
609 Interval locationHint = interval.locationHint(true, allocator); |
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610 if (locationHint != null && locationHint.location() != null && locationHint.location().isRegister()) { |
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611 hint = locationHint.location().asRegister(); |
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612 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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613 TTY.println(" hint register %d from interval %s", hint.number, locationHint.logString(allocator)); |
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614 } |
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615 } |
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616 assert interval.location() == null : "register already assigned to interval"; |
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617 |
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618 // the register must be free at least until this position |
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619 int regNeededUntil = interval.from() + 1; |
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620 int intervalTo = interval.to(); |
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621 |
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622 boolean needSplit = false; |
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623 int splitPos = -1; |
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624 |
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625 CiRegister reg = null; |
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626 CiRegister minFullReg = null; |
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627 CiRegister maxPartialReg = null; |
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628 |
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629 for (int i = 0; i < availableRegs.length; ++i) { |
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630 CiRegister availableReg = availableRegs[i]; |
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631 int number = availableReg.number; |
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632 if (usePos[number] >= intervalTo) { |
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633 // this register is free for the full interval |
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634 if (minFullReg == null || availableReg == hint || (usePos[number] < usePos[minFullReg.number] && minFullReg != hint)) { |
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635 minFullReg = availableReg; |
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636 } |
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637 } else if (usePos[number] > regNeededUntil) { |
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638 // this register is at least free until regNeededUntil |
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639 if (maxPartialReg == null || availableReg == hint || (usePos[number] > usePos[maxPartialReg.number] && maxPartialReg != hint)) { |
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640 maxPartialReg = availableReg; |
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641 } |
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642 } |
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643 } |
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|
644 |
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645 if (minFullReg != null) { |
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646 reg = minFullReg; |
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647 } else if (maxPartialReg != null) { |
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648 needSplit = true; |
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649 reg = maxPartialReg; |
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650 } else { |
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651 return false; |
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652 } |
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653 |
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654 splitPos = usePos[reg.number]; |
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655 interval.assignLocation(reg.asValue(interval.kind())); |
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656 if (C1XOptions.TraceLinearScanLevel >= 2) { |
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657 TTY.println("selected register %d", reg.number); |
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658 } |
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659 |
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660 assert splitPos > 0 : "invalid splitPos"; |
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661 if (needSplit) { |
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662 // register not available for full interval, so split it |
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663 splitWhenPartialRegisterAvailable(interval, splitPos); |
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664 } |
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665 |
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666 // only return true if interval is completely assigned |
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667 return true; |
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668 } |
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669 |
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670 CiRegister findLockedRegister(int regNeededUntil, int intervalTo, CiValue ignoreReg, boolean[] needSplit) { |
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671 int maxReg = -1; |
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672 CiRegister ignore = ignoreReg.isRegister() ? ignoreReg.asRegister() : null; |
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673 |
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674 for (CiRegister reg : availableRegs) { |
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675 int i = reg.number; |
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676 if (reg == ignore) { |
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677 // this register must be ignored |
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678 |
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679 } else if (usePos[i] > regNeededUntil) { |
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680 if (maxReg == -1 || (usePos[i] > usePos[maxReg])) { |
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681 maxReg = i; |
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682 } |
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683 } |
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684 } |
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685 |
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686 if (maxReg != -1) { |
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687 if (blockPos[maxReg] <= intervalTo) { |
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688 needSplit[0] = true; |
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689 } |
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690 return availableRegs[maxReg]; |
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691 } |
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|
692 |
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693 return null; |
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|
694 } |
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|
695 |
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696 void splitAndSpillIntersectingIntervals(CiRegister reg) { |
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697 assert reg != null : "no register assigned"; |
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|
698 |
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699 for (int i = 0; i < spillIntervals[reg.number].size(); i++) { |
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700 Interval interval = spillIntervals[reg.number].get(i); |
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701 removeFromList(interval); |
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|
702 splitAndSpillInterval(interval); |
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703 } |
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|
704 } |
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|
705 |
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|
706 // Split an Interval and spill it to memory so that cur can be placed in a register |
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707 void allocLockedRegister(Interval interval) { |
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708 if (C1XOptions.TraceLinearScanLevel >= 2) { |
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709 TTY.println("need to split and spill to get register for " + interval.logString(allocator)); |
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|
710 } |
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|
711 |
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|
712 // collect current usage of registers |
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|
713 initUseLists(false); |
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|
714 spillExcludeActiveFixed(); |
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|
715 // spillBlockUnhandledFixed(cur); |
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716 assert unhandledLists.get(RegisterBinding.Fixed) == Interval.EndMarker : "must not have unhandled fixed intervals because all fixed intervals have a use at position 0"; |
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|
717 spillBlockInactiveFixed(interval); |
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718 spillCollectActiveAny(); |
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diff
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|
719 spillCollectInactiveAny(interval); |
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|
720 |
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|
721 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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|
722 TTY.println(" state of registers:"); |
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|
723 for (CiRegister reg : availableRegs) { |
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parents:
diff
changeset
|
724 int i = reg.number; |
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diff
changeset
|
725 TTY.print(" reg %d: usePos: %d, blockPos: %d, intervals: ", i, usePos[i], blockPos[i]); |
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726 for (int j = 0; j < spillIntervals[i].size(); j++) { |
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|
727 TTY.print("%d ", spillIntervals[i].get(j).operandNumber); |
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parents:
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changeset
|
728 } |
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parents:
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changeset
|
729 TTY.println(); |
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|
730 } |
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|
731 } |
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changeset
|
732 |
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|
733 // the register must be free at least until this position |
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|
734 int firstUsage = interval.firstUsage(RegisterPriority.MustHaveRegister); |
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735 int regNeededUntil = Math.min(firstUsage, interval.from() + 1); |
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|
736 int intervalTo = interval.to(); |
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|
737 assert regNeededUntil > 0 && regNeededUntil < Integer.MAX_VALUE : "interval has no use"; |
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|
738 |
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changeset
|
739 CiRegister reg = null; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
740 CiRegister ignore = interval.location() != null && interval.location().isRegister() ? interval.location().asRegister() : null; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
741 for (CiRegister availableReg : availableRegs) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
742 int number = availableReg.number; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
743 if (availableReg == ignore) { |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
744 // this register must be ignored |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
745 } else if (usePos[number] > regNeededUntil) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
746 if (reg == null || (usePos[number] > usePos[reg.number])) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
747 reg = availableReg; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
748 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
749 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
750 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
751 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
752 if (reg == null || usePos[reg.number] <= firstUsage) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
753 // the first use of cur is later than the spilling position -> spill cur |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
754 if (C1XOptions.TraceLinearScanLevel >= 4) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
755 TTY.println("able to spill current interval. firstUsage(register): %d, usePos: %d", firstUsage, reg == null ? 0 : usePos[reg.number]); |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
756 } |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
757 |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
758 if (firstUsage <= interval.from() + 1) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
759 assert false : "cannot spill interval that is used in first instruction (possible reason: no register found) firstUsage=" + firstUsage + ", interval.from()=" + interval.from(); |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
760 // assign a reasonable register and do a bailout in product mode to avoid errors |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
761 allocator.assignSpillSlot(interval); |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
762 throw new CiBailout("LinearScan: no register found"); |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
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|
763 } |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
764 |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
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|
765 splitAndSpillInterval(interval); |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
766 return; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
767 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
768 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
769 boolean needSplit = blockPos[reg.number] <= intervalTo; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
770 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
771 int splitPos = blockPos[reg.number]; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
772 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
773 if (C1XOptions.TraceLinearScanLevel >= 4) { |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
774 TTY.println("decided to use register %d", reg.number); |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
775 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
776 assert splitPos > 0 : "invalid splitPos"; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
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777 assert needSplit || splitPos > interval.from() : "splitting interval at from"; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
778 |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
779 interval.assignLocation(reg.asValue(interval.kind())); |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
780 if (needSplit) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
781 // register not available for full interval : so split it |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
782 splitWhenPartialRegisterAvailable(interval, splitPos); |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
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|
783 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
784 |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
785 // perform splitting and spilling for all affected intervals |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
786 splitAndSpillIntersectingIntervals(reg); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
787 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
788 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
789 boolean noAllocationPossible(Interval interval) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
790 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
791 if (compilation.target.arch.isX86()) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
792 // fast calculation of intervals that can never get a register because the |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
793 // the next instruction is a call that blocks all registers |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
794 // Note: this does not work if callee-saved registers are available (e.g. on Sparc) |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
795 |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
796 // check if this interval is the result of a split operation |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
797 // (an interval got a register until this position) |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
798 int pos = interval.from(); |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
799 if (isOdd(pos)) { |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
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diff
changeset
|
800 // the current instruction is a call that blocks all registers |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
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changeset
|
801 if (pos < allocator.maxOpId() && allocator.hasCall(pos + 1) && interval.to() > pos + 1) { |
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Pull over of compiler from maxine repository.
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parents:
diff
changeset
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802 if (C1XOptions.TraceLinearScanLevel >= 4) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
803 TTY.println(" free register cannot be available because all registers blocked by following call"); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
804 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
805 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
806 // safety check that there is really no register available |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
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changeset
|
807 assert !allocFreeRegister(interval) : "found a register for this interval"; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
808 return true; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
809 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
810 |
9ec15d6914ca
Pull over of compiler from maxine repository.
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parents:
diff
changeset
|
811 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
812 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
813 return false; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
814 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
815 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
816 void initVarsForAlloc(Interval interval) { |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
817 EnumMap<RegisterFlag, CiRegister[]> categorizedRegs = allocator.compilation.registerConfig.getCategorizedAllocatableRegisters(); |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
818 if (allocator.operands.mustBeByteRegister(interval.operand)) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
819 assert interval.kind() != CiKind.Float && interval.kind() != CiKind.Double : "cpu regs only"; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
820 availableRegs = categorizedRegs.get(RegisterFlag.Byte); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
821 } else if (interval.kind() == CiKind.Float || interval.kind() == CiKind.Double) { |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
822 availableRegs = categorizedRegs.get(RegisterFlag.FPU); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
823 } else { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
824 availableRegs = categorizedRegs.get(RegisterFlag.CPU); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
825 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
826 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
827 |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
828 boolean isMove(LIRInstruction op, Interval from, Interval to) { |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
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829 if (op.code != LIROpcode.Move) { |
9ec15d6914ca
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
830 return false; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
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|
831 } |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
832 assert op instanceof LIROp1 : "move must be LIROp1"; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
833 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
834 CiValue input = ((LIROp1) op).operand(); |
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Pull over of compiler from maxine repository.
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diff
changeset
|
835 CiValue result = ((LIROp1) op).result(); |
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
836 return input.isVariable() && result.isVariable() && input == from.operand && result == to.operand; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
837 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
838 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
839 // optimization (especially for phi functions of nested loops): |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
840 // assign same spill slot to non-intersecting intervals |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
841 void combineSpilledIntervals(Interval interval) { |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
842 if (interval.isSplitChild()) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
843 // optimization is only suitable for split parents |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
844 return; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
845 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
846 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
847 Interval registerHint = interval.locationHint(false, allocator); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
848 if (registerHint == null) { |
9ec15d6914ca
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Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
849 // cur is not the target of a move : otherwise registerHint would be set |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
850 return; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
851 } |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
852 assert registerHint.isSplitParent() : "register hint must be split parent"; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
853 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
854 if (interval.spillState() != SpillState.NoOptimization || registerHint.spillState() != SpillState.NoOptimization) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
855 // combining the stack slots for intervals where spill move optimization is applied |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
856 // is not benefitial and would cause problems |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
857 return; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
858 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
859 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
860 int beginPos = interval.from(); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
861 int endPos = interval.to(); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
862 if (endPos > allocator.maxOpId() || isOdd(beginPos) || isOdd(endPos)) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
863 // safety check that lirOpWithId is allowed |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
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|
864 return; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
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|
865 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
866 |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
867 if (!isMove(allocator.instructionForId(beginPos), registerHint, interval) || !isMove(allocator.instructionForId(endPos), interval, registerHint)) { |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
868 // cur and registerHint are not connected with two moves |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
869 return; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
870 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
871 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
872 Interval beginHint = registerHint.getSplitChildAtOpId(beginPos, LIRInstruction.OperandMode.Input, allocator); |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
873 Interval endHint = registerHint.getSplitChildAtOpId(endPos, LIRInstruction.OperandMode.Output, allocator); |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
874 if (beginHint == endHint || beginHint.to() != beginPos || endHint.from() != endPos) { |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
875 // registerHint must be split : otherwise the re-writing of use positions does not work |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
876 return; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
877 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
878 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
879 assert beginHint.location() != null : "must have register assigned"; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
880 assert endHint.location() == null : "must not have register assigned"; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
881 assert interval.firstUsage(RegisterPriority.MustHaveRegister) == beginPos : "must have use position at begin of interval because of move"; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
882 assert endHint.firstUsage(RegisterPriority.MustHaveRegister) == endPos : "must have use position at begin of interval because of move"; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
883 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
884 if (beginHint.location().isRegister()) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
885 // registerHint is not spilled at beginPos : so it would not be benefitial to immediately spill cur |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
886 return; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
887 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
888 assert registerHint.spillSlot() != null : "must be set when part of interval was spilled"; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
889 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
890 // modify intervals such that cur gets the same stack slot as registerHint |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
891 // delete use positions to prevent the intervals to get a register at beginning |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
892 interval.setSpillSlot(registerHint.spillSlot()); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
893 interval.removeFirstUsePos(); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
894 endHint.removeFirstUsePos(); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
895 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
896 |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
897 // allocate a physical register or memory location to an interval |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
898 @Override |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
899 boolean activateCurrent() { |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
900 Interval interval = current; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
901 boolean result = true; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
902 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
903 if (C1XOptions.TraceLinearScanLevel >= 2) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
904 TTY.println("+++++ activating interval " + interval.logString(allocator)); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
905 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
906 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
907 if (C1XOptions.TraceLinearScanLevel >= 4) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
908 TTY.println(" splitParent: %s, insertMoveWhenActivated: %b", interval.splitParent().operandNumber, interval.insertMoveWhenActivated()); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
909 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
910 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
911 final CiValue operand = interval.operand; |
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Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
912 if (interval.location() != null && interval.location().isStackSlot()) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
913 // activating an interval that has a stack slot assigned . split it at first use position |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
914 // used for method parameters |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
915 if (C1XOptions.TraceLinearScanLevel >= 4) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
916 TTY.println(" interval has spill slot assigned (method parameter) . split it before first use"); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
917 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
918 splitStackInterval(interval); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
919 result = false; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
920 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
921 } else { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
922 if (operand.isVariable() && allocator.operands.mustStartInMemory((CiVariable) operand)) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
923 assert interval.location() == null : "register already assigned"; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
924 allocator.assignSpillSlot(interval); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
925 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
926 if (!allocator.operands.mustStayInMemory((CiVariable) operand)) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
927 // activating an interval that must start in a stack slot but may get a register later |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
928 // used for lirRoundfp: rounding is done by store to stack and reload later |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
929 if (C1XOptions.TraceLinearScanLevel >= 4) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
930 TTY.println(" interval must start in stack slot . split it before first use"); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
931 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
932 splitStackInterval(interval); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
933 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
934 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
935 result = false; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
936 } else if (interval.location() == null) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
937 // interval has not assigned register . normal allocation |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
938 // (this is the normal case for most intervals) |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
939 if (C1XOptions.TraceLinearScanLevel >= 4) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
940 TTY.println(" normal allocation of register"); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
941 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
942 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
943 // assign same spill slot to non-intersecting intervals |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
944 combineSpilledIntervals(interval); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
945 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
946 initVarsForAlloc(interval); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
947 if (noAllocationPossible(interval) || !allocFreeRegister(interval)) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
948 // no empty register available. |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
949 // split and spill another interval so that this interval gets a register |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
950 allocLockedRegister(interval); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
951 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
952 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
953 // spilled intervals need not be move to active-list |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
954 if (!interval.location().isRegister()) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
955 result = false; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
956 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
957 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
958 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
959 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
960 // load spilled values that become active from stack slot to register |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
961 if (interval.insertMoveWhenActivated()) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
962 assert interval.isSplitChild(); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
963 assert interval.currentSplitChild() != null; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
964 assert interval.currentSplitChild().operand != operand : "cannot insert move between same interval"; |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
965 if (C1XOptions.TraceLinearScanLevel >= 4) { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
966 TTY.println("Inserting move from interval %d to %d because insertMoveWhenActivated is set", interval.currentSplitChild().operandNumber, interval.operandNumber); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
967 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
968 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
969 insertMove(interval.from(), interval.currentSplitChild(), interval); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
970 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
971 interval.makeCurrentSplitChild(); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
972 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
973 return result; // true = interval is moved to active list |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
974 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
975 |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
976 public void finishAllocation() { |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
977 // must be called when all intervals are allocated |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
978 moveResolver.resolveAndAppendMoves(); |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
979 } |
9ec15d6914ca
Pull over of compiler from maxine repository.
Thomas Wuerthinger <thomas@wuerthinger.net>
parents:
diff
changeset
|
980 } |