Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/vm_version_x86.cpp @ 3860:3be7439273c5
7044486: open jdk repos have files with incorrect copyright headers, which can end up in src bundles
Reviewed-by: ohair, trims
author | katleman |
---|---|
date | Wed, 25 May 2011 13:31:51 -0700 |
parents | 6ae7a1561b53 |
children | 9f12ede5571a |
rev | line source |
---|---|
585 | 1 /* |
3860
3be7439273c5
7044486: open jdk repos have files with incorrect copyright headers, which can end up in src bundles
katleman
parents:
3787
diff
changeset
|
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. |
585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1060
diff
changeset
|
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1060
diff
changeset
|
20 * or visit www.oracle.com if you need additional information or have any |
c18cbe5936b8
6941466: Oracle rebranding changes for Hotspot repositories
trims
parents:
1060
diff
changeset
|
21 * questions. |
585 | 22 * |
23 */ | |
24 | |
1972 | 25 #include "precompiled.hpp" |
26 #include "assembler_x86.inline.hpp" | |
27 #include "memory/resourceArea.hpp" | |
28 #include "runtime/java.hpp" | |
29 #include "runtime/stubCodeGenerator.hpp" | |
30 #include "vm_version_x86.hpp" | |
31 #ifdef TARGET_OS_FAMILY_linux | |
32 # include "os_linux.inline.hpp" | |
33 #endif | |
34 #ifdef TARGET_OS_FAMILY_solaris | |
35 # include "os_solaris.inline.hpp" | |
36 #endif | |
37 #ifdef TARGET_OS_FAMILY_windows | |
38 # include "os_windows.inline.hpp" | |
39 #endif | |
585 | 40 |
41 | |
42 int VM_Version::_cpu; | |
43 int VM_Version::_model; | |
44 int VM_Version::_stepping; | |
45 int VM_Version::_cpuFeatures; | |
46 const char* VM_Version::_features_str = ""; | |
47 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; | |
48 | |
49 static BufferBlob* stub_blob; | |
1622 | 50 static const int stub_size = 400; |
585 | 51 |
52 extern "C" { | |
53 typedef void (*getPsrInfo_stub_t)(void*); | |
54 } | |
55 static getPsrInfo_stub_t getPsrInfo_stub = NULL; | |
56 | |
57 | |
58 class VM_Version_StubGenerator: public StubCodeGenerator { | |
59 public: | |
60 | |
61 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} | |
62 | |
63 address generate_getPsrInfo() { | |
64 // Flags to test CPU type. | |
65 const uint32_t EFL_AC = 0x40000; | |
66 const uint32_t EFL_ID = 0x200000; | |
67 // Values for when we don't have a CPUID instruction. | |
68 const int CPU_FAMILY_SHIFT = 8; | |
69 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); | |
70 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); | |
71 | |
1622 | 72 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; |
585 | 73 Label ext_cpuid1, ext_cpuid5, done; |
74 | |
75 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); | |
76 # define __ _masm-> | |
77 | |
78 address start = __ pc(); | |
79 | |
80 // | |
81 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info); | |
82 // | |
83 // LP64: rcx and rdx are first and second argument registers on windows | |
84 | |
85 __ push(rbp); | |
86 #ifdef _LP64 | |
87 __ mov(rbp, c_rarg0); // cpuid_info address | |
88 #else | |
89 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address | |
90 #endif | |
91 __ push(rbx); | |
92 __ push(rsi); | |
93 __ pushf(); // preserve rbx, and flags | |
94 __ pop(rax); | |
95 __ push(rax); | |
96 __ mov(rcx, rax); | |
97 // | |
98 // if we are unable to change the AC flag, we have a 386 | |
99 // | |
100 __ xorl(rax, EFL_AC); | |
101 __ push(rax); | |
102 __ popf(); | |
103 __ pushf(); | |
104 __ pop(rax); | |
105 __ cmpptr(rax, rcx); | |
106 __ jccb(Assembler::notEqual, detect_486); | |
107 | |
108 __ movl(rax, CPU_FAMILY_386); | |
109 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
110 __ jmp(done); | |
111 | |
112 // | |
113 // If we are unable to change the ID flag, we have a 486 which does | |
114 // not support the "cpuid" instruction. | |
115 // | |
116 __ bind(detect_486); | |
117 __ mov(rax, rcx); | |
118 __ xorl(rax, EFL_ID); | |
119 __ push(rax); | |
120 __ popf(); | |
121 __ pushf(); | |
122 __ pop(rax); | |
123 __ cmpptr(rcx, rax); | |
124 __ jccb(Assembler::notEqual, detect_586); | |
125 | |
126 __ bind(cpu486); | |
127 __ movl(rax, CPU_FAMILY_486); | |
128 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); | |
129 __ jmp(done); | |
130 | |
131 // | |
132 // At this point, we have a chip which supports the "cpuid" instruction | |
133 // | |
134 __ bind(detect_586); | |
135 __ xorl(rax, rax); | |
136 __ cpuid(); | |
137 __ orl(rax, rax); | |
138 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input | |
139 // value of at least 1, we give up and | |
140 // assume a 486 | |
141 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); | |
142 __ movl(Address(rsi, 0), rax); | |
143 __ movl(Address(rsi, 4), rbx); | |
144 __ movl(Address(rsi, 8), rcx); | |
145 __ movl(Address(rsi,12), rdx); | |
146 | |
1622 | 147 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? |
148 __ jccb(Assembler::belowEqual, std_cpuid4); | |
149 | |
150 // | |
151 // cpuid(0xB) Processor Topology | |
152 // | |
153 __ movl(rax, 0xb); | |
154 __ xorl(rcx, rcx); // Threads level | |
155 __ cpuid(); | |
156 | |
157 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); | |
158 __ movl(Address(rsi, 0), rax); | |
159 __ movl(Address(rsi, 4), rbx); | |
160 __ movl(Address(rsi, 8), rcx); | |
161 __ movl(Address(rsi,12), rdx); | |
162 | |
163 __ movl(rax, 0xb); | |
164 __ movl(rcx, 1); // Cores level | |
165 __ cpuid(); | |
166 __ push(rax); | |
167 __ andl(rax, 0x1f); // Determine if valid topology level | |
168 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level | |
169 __ andl(rax, 0xffff); | |
170 __ pop(rax); | |
171 __ jccb(Assembler::equal, std_cpuid4); | |
172 | |
173 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); | |
174 __ movl(Address(rsi, 0), rax); | |
175 __ movl(Address(rsi, 4), rbx); | |
176 __ movl(Address(rsi, 8), rcx); | |
177 __ movl(Address(rsi,12), rdx); | |
178 | |
179 __ movl(rax, 0xb); | |
180 __ movl(rcx, 2); // Packages level | |
181 __ cpuid(); | |
182 __ push(rax); | |
183 __ andl(rax, 0x1f); // Determine if valid topology level | |
184 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level | |
185 __ andl(rax, 0xffff); | |
186 __ pop(rax); | |
187 __ jccb(Assembler::equal, std_cpuid4); | |
188 | |
189 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); | |
190 __ movl(Address(rsi, 0), rax); | |
191 __ movl(Address(rsi, 4), rbx); | |
192 __ movl(Address(rsi, 8), rcx); | |
193 __ movl(Address(rsi,12), rdx); | |
585 | 194 |
195 // | |
196 // cpuid(0x4) Deterministic cache params | |
197 // | |
1622 | 198 __ bind(std_cpuid4); |
585 | 199 __ movl(rax, 4); |
1622 | 200 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? |
201 __ jccb(Assembler::greater, std_cpuid1); | |
202 | |
585 | 203 __ xorl(rcx, rcx); // L1 cache |
204 __ cpuid(); | |
205 __ push(rax); | |
206 __ andl(rax, 0x1f); // Determine if valid cache parameters used | |
207 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache | |
208 __ pop(rax); | |
209 __ jccb(Assembler::equal, std_cpuid1); | |
210 | |
211 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); | |
212 __ movl(Address(rsi, 0), rax); | |
213 __ movl(Address(rsi, 4), rbx); | |
214 __ movl(Address(rsi, 8), rcx); | |
215 __ movl(Address(rsi,12), rdx); | |
216 | |
217 // | |
218 // Standard cpuid(0x1) | |
219 // | |
220 __ bind(std_cpuid1); | |
221 __ movl(rax, 1); | |
222 __ cpuid(); | |
223 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); | |
224 __ movl(Address(rsi, 0), rax); | |
225 __ movl(Address(rsi, 4), rbx); | |
226 __ movl(Address(rsi, 8), rcx); | |
227 __ movl(Address(rsi,12), rdx); | |
228 | |
229 __ movl(rax, 0x80000000); | |
230 __ cpuid(); | |
231 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? | |
232 __ jcc(Assembler::belowEqual, done); | |
233 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? | |
234 __ jccb(Assembler::belowEqual, ext_cpuid1); | |
235 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? | |
236 __ jccb(Assembler::belowEqual, ext_cpuid5); | |
237 // | |
238 // Extended cpuid(0x80000008) | |
239 // | |
240 __ movl(rax, 0x80000008); | |
241 __ cpuid(); | |
242 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); | |
243 __ movl(Address(rsi, 0), rax); | |
244 __ movl(Address(rsi, 4), rbx); | |
245 __ movl(Address(rsi, 8), rcx); | |
246 __ movl(Address(rsi,12), rdx); | |
247 | |
248 // | |
249 // Extended cpuid(0x80000005) | |
250 // | |
251 __ bind(ext_cpuid5); | |
252 __ movl(rax, 0x80000005); | |
253 __ cpuid(); | |
254 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); | |
255 __ movl(Address(rsi, 0), rax); | |
256 __ movl(Address(rsi, 4), rbx); | |
257 __ movl(Address(rsi, 8), rcx); | |
258 __ movl(Address(rsi,12), rdx); | |
259 | |
260 // | |
261 // Extended cpuid(0x80000001) | |
262 // | |
263 __ bind(ext_cpuid1); | |
264 __ movl(rax, 0x80000001); | |
265 __ cpuid(); | |
266 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); | |
267 __ movl(Address(rsi, 0), rax); | |
268 __ movl(Address(rsi, 4), rbx); | |
269 __ movl(Address(rsi, 8), rcx); | |
270 __ movl(Address(rsi,12), rdx); | |
271 | |
272 // | |
273 // return | |
274 // | |
275 __ bind(done); | |
276 __ popf(); | |
277 __ pop(rsi); | |
278 __ pop(rbx); | |
279 __ pop(rbp); | |
280 __ ret(0); | |
281 | |
282 # undef __ | |
283 | |
284 return start; | |
285 }; | |
286 }; | |
287 | |
288 | |
289 void VM_Version::get_processor_features() { | |
290 | |
291 _cpu = 4; // 486 by default | |
292 _model = 0; | |
293 _stepping = 0; | |
294 _cpuFeatures = 0; | |
295 _logical_processors_per_package = 1; | |
296 | |
297 if (!Use486InstrsOnly) { | |
298 // Get raw processor info | |
299 getPsrInfo_stub(&_cpuid_info); | |
300 assert_is_initialized(); | |
301 _cpu = extended_cpu_family(); | |
302 _model = extended_cpu_model(); | |
303 _stepping = cpu_stepping(); | |
304 | |
305 if (cpu_family() > 4) { // it supports CPUID | |
306 _cpuFeatures = feature_flags(); | |
307 // Logical processors are only available on P4s and above, | |
308 // and only if hyperthreading is available. | |
309 _logical_processors_per_package = logical_processor_count(); | |
310 } | |
311 } | |
312 | |
313 _supports_cx8 = supports_cmpxchg8(); | |
314 | |
315 #ifdef _LP64 | |
316 // OS should support SSE for x64 and hardware should support at least SSE2. | |
317 if (!VM_Version::supports_sse2()) { | |
318 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); | |
319 } | |
1060 | 320 // in 64 bit the use of SSE2 is the minimum |
321 if (UseSSE < 2) UseSSE = 2; | |
585 | 322 #endif |
323 | |
3787
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
324 #ifdef AMD64 |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
325 // flush_icache_stub have to be generated first. |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
326 // That is why Icache line size is hard coded in ICache class, |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
327 // see icache_x86.hpp. It is also the reason why we can't use |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
328 // clflush instruction in 32-bit VM since it could be running |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
329 // on CPU which does not support it. |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
330 // |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
331 // The only thing we can do is to verify that flushed |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
332 // ICache::line_size has correct value. |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
333 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
334 // clflush_size is size in quadwords (8 bytes). |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
335 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
336 #endif |
6ae7a1561b53
6990015: Incorrect Icache line size is used for 64 bit x86
kvn
parents:
3276
diff
changeset
|
337 |
585 | 338 // If the OS doesn't support SSE, we can't use this feature even if the HW does |
339 if (!os::supports_sse()) | |
340 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); | |
341 | |
342 if (UseSSE < 4) { | |
343 _cpuFeatures &= ~CPU_SSE4_1; | |
344 _cpuFeatures &= ~CPU_SSE4_2; | |
345 } | |
346 | |
347 if (UseSSE < 3) { | |
348 _cpuFeatures &= ~CPU_SSE3; | |
349 _cpuFeatures &= ~CPU_SSSE3; | |
350 _cpuFeatures &= ~CPU_SSE4A; | |
351 } | |
352 | |
353 if (UseSSE < 2) | |
354 _cpuFeatures &= ~CPU_SSE2; | |
355 | |
356 if (UseSSE < 1) | |
357 _cpuFeatures &= ~CPU_SSE; | |
358 | |
359 if (logical_processors_per_package() == 1) { | |
360 // HT processor could be installed on a system which doesn't support HT. | |
361 _cpuFeatures &= ~CPU_HT; | |
362 } | |
363 | |
364 char buf[256]; | |
2479 | 365 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", |
585 | 366 cores_per_cpu(), threads_per_core(), |
367 cpu_family(), _model, _stepping, | |
368 (supports_cmov() ? ", cmov" : ""), | |
369 (supports_cmpxchg8() ? ", cx8" : ""), | |
370 (supports_fxsr() ? ", fxsr" : ""), | |
371 (supports_mmx() ? ", mmx" : ""), | |
372 (supports_sse() ? ", sse" : ""), | |
373 (supports_sse2() ? ", sse2" : ""), | |
374 (supports_sse3() ? ", sse3" : ""), | |
375 (supports_ssse3()? ", ssse3": ""), | |
376 (supports_sse4_1() ? ", sse4.1" : ""), | |
377 (supports_sse4_2() ? ", sse4.2" : ""), | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
378 (supports_popcnt() ? ", popcnt" : ""), |
585 | 379 (supports_mmx_ext() ? ", mmxext" : ""), |
2479 | 380 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
381 (supports_lzcnt() ? ", lzcnt": ""), |
585 | 382 (supports_sse4a() ? ", sse4a": ""), |
383 (supports_ht() ? ", ht": "")); | |
384 _features_str = strdup(buf); | |
385 | |
386 // UseSSE is set to the smaller of what hardware supports and what | |
387 // the command line requires. I.e., you cannot set UseSSE to 2 on | |
388 // older Pentiums which do not support it. | |
389 if( UseSSE > 4 ) UseSSE=4; | |
390 if( UseSSE < 0 ) UseSSE=0; | |
391 if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support | |
392 UseSSE = MIN2((intx)3,UseSSE); | |
393 if( !supports_sse3() ) // Drop to 2 if no SSE3 support | |
394 UseSSE = MIN2((intx)2,UseSSE); | |
395 if( !supports_sse2() ) // Drop to 1 if no SSE2 support | |
396 UseSSE = MIN2((intx)1,UseSSE); | |
397 if( !supports_sse () ) // Drop to 0 if no SSE support | |
398 UseSSE = 0; | |
399 | |
400 // On new cpus instructions which update whole XMM register should be used | |
401 // to prevent partial register stall due to dependencies on high half. | |
402 // | |
403 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) | |
404 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) | |
405 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). | |
406 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). | |
407 | |
408 if( is_amd() ) { // AMD cpus specific settings | |
409 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { | |
410 // Use it on new AMD cpus starting from Opteron. | |
411 UseAddressNop = true; | |
412 } | |
413 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { | |
414 // Use it on new AMD cpus starting from Opteron. | |
415 UseNewLongLShift = true; | |
416 } | |
417 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
418 if( supports_sse4a() ) { | |
419 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron | |
420 } else { | |
421 UseXmmLoadAndClearUpper = false; | |
422 } | |
423 } | |
424 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
425 if( supports_sse4a() ) { | |
426 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' | |
427 } else { | |
428 UseXmmRegToRegMoveAll = false; | |
429 } | |
430 } | |
431 if( FLAG_IS_DEFAULT(UseXmmI2F) ) { | |
432 if( supports_sse4a() ) { | |
433 UseXmmI2F = true; | |
434 } else { | |
435 UseXmmI2F = false; | |
436 } | |
437 } | |
438 if( FLAG_IS_DEFAULT(UseXmmI2D) ) { | |
439 if( supports_sse4a() ) { | |
440 UseXmmI2D = true; | |
441 } else { | |
442 UseXmmI2D = false; | |
443 } | |
444 } | |
2406 | 445 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) { |
446 if( supports_sse4_2() && UseSSE >= 4 ) { | |
447 UseSSE42Intrinsics = true; | |
448 } | |
449 } | |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
450 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
451 // Use count leading zeros count instruction if available. |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
452 if (supports_lzcnt()) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
453 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
454 UseCountLeadingZerosInstruction = true; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
455 } |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
456 } |
2358 | 457 |
3276
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
458 // some defaults for AMD family 15h |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
459 if ( cpu_family() == 0x15 ) { |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
460 // On family 15h processors default is no sw prefetch |
2358 | 461 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { |
462 AllocatePrefetchStyle = 0; | |
463 } | |
3276
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
464 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
465 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
466 AllocatePrefetchInstr = 3; |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
467 } |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
468 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
469 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
470 UseXMMForArrayCopy = true; |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
471 } |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
472 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
473 UseUnalignedLoadStores = true; |
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
474 } |
2358 | 475 } |
3276
2a34a4fbc52c
7037812: few more defaults changes for new AMD processors
kvn
parents:
2479
diff
changeset
|
476 |
585 | 477 } |
478 | |
479 if( is_intel() ) { // Intel cpus specific settings | |
480 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { | |
481 UseStoreImmI16 = false; // don't use it on Intel cpus | |
482 } | |
483 if( cpu_family() == 6 || cpu_family() == 15 ) { | |
484 if( FLAG_IS_DEFAULT(UseAddressNop) ) { | |
485 // Use it on all Intel cpus starting from PentiumPro | |
486 UseAddressNop = true; | |
487 } | |
488 } | |
489 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { | |
490 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus | |
491 } | |
492 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { | |
493 if( supports_sse3() ) { | |
494 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus | |
495 } else { | |
496 UseXmmRegToRegMoveAll = false; | |
497 } | |
498 } | |
499 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus | |
500 #ifdef COMPILER2 | |
501 if( FLAG_IS_DEFAULT(MaxLoopPad) ) { | |
502 // For new Intel cpus do the next optimization: | |
503 // don't align the beginning of a loop if there are enough instructions | |
504 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) | |
505 // in current fetch line (OptoLoopAlignment) or the padding | |
506 // is big (> MaxLoopPad). | |
507 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of | |
508 // generated NOP instructions. 11 is the largest size of one | |
509 // address NOP instruction '0F 1F' (see Assembler::nop(i)). | |
510 MaxLoopPad = 11; | |
511 } | |
512 #endif // COMPILER2 | |
513 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) { | |
514 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus | |
515 } | |
516 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus | |
517 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) { | |
518 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus | |
519 } | |
520 } | |
681 | 521 if( supports_sse4_2() && UseSSE >= 4 ) { |
522 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { | |
523 UseSSE42Intrinsics = true; | |
524 } | |
525 } | |
585 | 526 } |
527 } | |
528 | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
529 // Use population count instruction if available. |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
530 if (supports_popcnt()) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
531 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
532 UsePopCountInstruction = true; |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
533 } |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
534 } |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
585
diff
changeset
|
535 |
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
536 #ifdef COMPILER2 |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
537 if (UseFPUForSpilling) { |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
538 if (UseSSE < 2) { |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
539 // Only supported with SSE2+ |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
540 FLAG_SET_DEFAULT(UseFPUForSpilling, false); |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
541 } |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
542 } |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
543 #endif |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
544 |
585 | 545 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value"); |
546 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value"); | |
547 | |
548 // set valid Prefetch instruction | |
549 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0; | |
550 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3; | |
2479 | 551 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0; |
552 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3; | |
585 | 553 |
554 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; | |
555 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3; | |
2479 | 556 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; |
557 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; | |
585 | 558 |
559 // Allocation prefetch settings | |
560 intx cache_line_size = L1_data_cache_line_size(); | |
561 if( cache_line_size > AllocatePrefetchStepSize ) | |
562 AllocatePrefetchStepSize = cache_line_size; | |
563 if( FLAG_IS_DEFAULT(AllocatePrefetchLines) ) | |
564 AllocatePrefetchLines = 3; // Optimistic value | |
565 assert(AllocatePrefetchLines > 0, "invalid value"); | |
566 if( AllocatePrefetchLines < 1 ) // set valid value in product VM | |
567 AllocatePrefetchLines = 1; // Conservative value | |
568 | |
569 AllocatePrefetchDistance = allocate_prefetch_distance(); | |
570 AllocatePrefetchStyle = allocate_prefetch_style(); | |
571 | |
1622 | 572 if( is_intel() && cpu_family() == 6 && supports_sse3() ) { |
573 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core | |
585 | 574 #ifdef _LP64 |
1622 | 575 AllocatePrefetchDistance = 384; |
585 | 576 #else |
1622 | 577 AllocatePrefetchDistance = 320; |
585 | 578 #endif |
1622 | 579 } |
580 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus | |
581 AllocatePrefetchDistance = 192; | |
582 AllocatePrefetchLines = 4; | |
1730
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
583 #ifdef COMPILER2 |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
584 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) { |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
585 FLAG_SET_DEFAULT(UseFPUForSpilling, true); |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
586 } |
f55c4f82ab9d
6978249: spill between cpu and fpu registers when those moves are fast
never
parents:
1622
diff
changeset
|
587 #endif |
1622 | 588 } |
585 | 589 } |
590 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value"); | |
591 | |
592 #ifdef _LP64 | |
593 // Prefetch settings | |
594 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); | |
595 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); | |
596 PrefetchFieldsAhead = prefetch_fields_ahead(); | |
597 #endif | |
598 | |
599 #ifndef PRODUCT | |
600 if (PrintMiscellaneous && Verbose) { | |
601 tty->print_cr("Logical CPUs per core: %u", | |
602 logical_processors_per_package()); | |
603 tty->print_cr("UseSSE=%d",UseSSE); | |
604 tty->print("Allocation: "); | |
2479 | 605 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { |
585 | 606 tty->print_cr("no prefetching"); |
607 } else { | |
2479 | 608 if (UseSSE == 0 && supports_3dnow_prefetch()) { |
585 | 609 tty->print("PREFETCHW"); |
610 } else if (UseSSE >= 1) { | |
611 if (AllocatePrefetchInstr == 0) { | |
612 tty->print("PREFETCHNTA"); | |
613 } else if (AllocatePrefetchInstr == 1) { | |
614 tty->print("PREFETCHT0"); | |
615 } else if (AllocatePrefetchInstr == 2) { | |
616 tty->print("PREFETCHT2"); | |
617 } else if (AllocatePrefetchInstr == 3) { | |
618 tty->print("PREFETCHW"); | |
619 } | |
620 } | |
621 if (AllocatePrefetchLines > 1) { | |
622 tty->print_cr(" %d, %d lines with step %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize); | |
623 } else { | |
624 tty->print_cr(" %d, one line", AllocatePrefetchDistance); | |
625 } | |
626 } | |
627 | |
628 if (PrefetchCopyIntervalInBytes > 0) { | |
629 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes); | |
630 } | |
631 if (PrefetchScanIntervalInBytes > 0) { | |
632 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes); | |
633 } | |
634 if (PrefetchFieldsAhead > 0) { | |
635 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead); | |
636 } | |
637 } | |
638 #endif // !PRODUCT | |
639 } | |
640 | |
641 void VM_Version::initialize() { | |
642 ResourceMark rm; | |
643 // Making this stub must be FIRST use of assembler | |
644 | |
645 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size); | |
646 if (stub_blob == NULL) { | |
647 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub"); | |
648 } | |
1748 | 649 CodeBuffer c(stub_blob); |
585 | 650 VM_Version_StubGenerator g(&c); |
651 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t, | |
652 g.generate_getPsrInfo()); | |
653 | |
654 get_processor_features(); | |
655 } |