Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/sparc.ad @ 1333:3f12a94552cc
Added tag jdk7-b88 for changeset 4b60f23c4223
author | mikejwre |
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date | Thu, 08 Apr 2010 17:02:41 -0700 |
parents | 2883969d09e7 |
children | 9e321dcfa5b7 |
rev | line source |
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0 | 1 // |
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2 // Copyright 1998-2010 Sun Microsystems, Inc. All Rights Reserved. |
0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 // | |
5 // This code is free software; you can redistribute it and/or modify it | |
6 // under the terms of the GNU General Public License version 2 only, as | |
7 // published by the Free Software Foundation. | |
8 // | |
9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 // version 2 for more details (a copy is included in the LICENSE file that | |
13 // accompanied this code). | |
14 // | |
15 // You should have received a copy of the GNU General Public License version | |
16 // 2 along with this work; if not, write to the Free Software Foundation, | |
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 // | |
19 // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 // CA 95054 USA or visit www.sun.com if you need additional information or | |
21 // have any questions. | |
22 // | |
23 // | |
24 | |
25 // SPARC Architecture Description File | |
26 | |
27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
28 // This information is used by the matcher and the register allocator to | |
29 // describe individual registers and classes of registers within the target | |
30 // archtecture. | |
31 register %{ | |
32 //----------Architecture Description Register Definitions---------------------- | |
33 // General Registers | |
34 // "reg_def" name ( register save type, C convention save type, | |
35 // ideal register type, encoding, vm name ); | |
36 // Register Save Types: | |
37 // | |
38 // NS = No-Save: The register allocator assumes that these registers | |
39 // can be used without saving upon entry to the method, & | |
40 // that they do not need to be saved at call sites. | |
41 // | |
42 // SOC = Save-On-Call: The register allocator assumes that these registers | |
43 // can be used without saving upon entry to the method, | |
44 // but that they must be saved at call sites. | |
45 // | |
46 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
47 // must be saved before using them upon entry to the | |
48 // method, but they do not need to be saved at call | |
49 // sites. | |
50 // | |
51 // AS = Always-Save: The register allocator assumes that these registers | |
52 // must be saved before using them upon entry to the | |
53 // method, & that they must be saved at call sites. | |
54 // | |
55 // Ideal Register Type is used to determine how to save & restore a | |
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
58 // | |
59 // The encoding number is the actual bit-pattern placed into the opcodes. | |
60 | |
61 | |
62 // ---------------------------- | |
63 // Integer/Long Registers | |
64 // ---------------------------- | |
65 | |
66 // Need to expose the hi/lo aspect of 64-bit registers | |
67 // This register set is used for both the 64-bit build and | |
68 // the 32-bit build with 1-register longs. | |
69 | |
70 // Global Registers 0-7 | |
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); | |
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); | |
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); | |
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); | |
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); | |
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); | |
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); | |
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); | |
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); | |
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); | |
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); | |
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); | |
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); | |
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); | |
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); | |
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); | |
87 | |
88 // Output Registers 0-7 | |
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); | |
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); | |
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); | |
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); | |
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); | |
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); | |
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); | |
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); | |
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); | |
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); | |
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); | |
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); | |
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); | |
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); | |
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); | |
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); | |
105 | |
106 // Local Registers 0-7 | |
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); | |
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); | |
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); | |
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); | |
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); | |
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); | |
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); | |
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); | |
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); | |
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); | |
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); | |
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); | |
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); | |
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); | |
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); | |
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); | |
123 | |
124 // Input Registers 0-7 | |
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); | |
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); | |
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); | |
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); | |
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); | |
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); | |
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); | |
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); | |
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); | |
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); | |
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); | |
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); | |
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); | |
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); | |
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); | |
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); | |
141 | |
142 // ---------------------------- | |
143 // Float/Double Registers | |
144 // ---------------------------- | |
145 | |
146 // Float Registers | |
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); | |
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); | |
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); | |
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); | |
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); | |
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); | |
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); | |
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); | |
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); | |
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); | |
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); | |
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); | |
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); | |
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); | |
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); | |
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); | |
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); | |
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); | |
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); | |
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); | |
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); | |
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); | |
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); | |
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); | |
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); | |
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); | |
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); | |
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); | |
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); | |
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); | |
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); | |
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); | |
179 | |
180 // Double Registers | |
181 // The rules of ADL require that double registers be defined in pairs. | |
182 // Each pair must be two 32-bit values, but not necessarily a pair of | |
183 // single float registers. In each pair, ADLC-assigned register numbers | |
184 // must be adjacent, with the lower number even. Finally, when the | |
185 // CPU stores such a register pair to memory, the word associated with | |
186 // the lower ADLC-assigned number must be stored to the lower address. | |
187 | |
188 // These definitions specify the actual bit encodings of the sparc | |
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp | |
190 // wants 0-63, so we have to convert every time we want to use fp regs | |
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object(). | |
605 | 192 // 255 is a flag meaning "don't go here". |
0 | 193 // I believe we can't handle callee-save doubles D32 and up until |
194 // the place in the sparc stack crawler that asserts on the 255 is | |
195 // fixed up. | |
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196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); |
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197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); |
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198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); |
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199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); |
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200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); |
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201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); |
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202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); |
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203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); |
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204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); |
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205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); |
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206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); |
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207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); |
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208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); |
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209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); |
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210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); |
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211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); |
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212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); |
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213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); |
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214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); |
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215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); |
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216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); |
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217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); |
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218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); |
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219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); |
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220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); |
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221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); |
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222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); |
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223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); |
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224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); |
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225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); |
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226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); |
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227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); |
0 | 228 |
229 | |
230 // ---------------------------- | |
231 // Special Registers | |
232 // Condition Codes Flag Registers | |
233 // I tried to break out ICC and XCC but it's not very pretty. | |
234 // Every Sparc instruction which defs/kills one also kills the other. | |
235 // Hence every compare instruction which defs one kind of flags ends | |
236 // up needing a kill of the other. | |
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
238 | |
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); | |
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); | |
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); | |
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); | |
243 | |
244 // ---------------------------- | |
245 // Specify the enum values for the registers. These enums are only used by the | |
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed | |
247 // for visibility to the rest of the vm. The order of this enum influences the | |
248 // register allocator so having the freedom to set this order and not be stuck | |
249 // with the order that is natural for the rest of the vm is worth it. | |
250 alloc_class chunk0( | |
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, | |
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, | |
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, | |
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); | |
255 | |
256 // Note that a register is not allocatable unless it is also mentioned | |
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. | |
258 | |
259 alloc_class chunk1( | |
260 // The first registers listed here are those most likely to be used | |
261 // as temporaries. We move F0..F7 away from the front of the list, | |
262 // to reduce the likelihood of interferences with parameters and | |
263 // return values. Likewise, we avoid using F0/F1 for parameters, | |
264 // since they are used for return values. | |
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. | |
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, | |
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, | |
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values | |
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, | |
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, | |
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); | |
274 | |
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); | |
276 | |
277 //----------Architecture Description Register Classes-------------------------- | |
278 // Several register classes are automatically defined based upon information in | |
279 // this architecture description. | |
280 // 1) reg_class inline_cache_reg ( as defined in frame section ) | |
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) | |
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
283 // | |
284 | |
285 // G0 is not included in integer class since it has special meaning. | |
286 reg_class g0_reg(R_G0); | |
287 | |
288 // ---------------------------- | |
289 // Integer Register Classes | |
290 // ---------------------------- | |
291 // Exclusions from i_reg: | |
292 // R_G0: hardwired zero | |
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java) | |
294 // R_G6: reserved by Solaris ABI to tools | |
295 // R_G7: reserved by Solaris ABI to libthread | |
296 // R_O7: Used as a temp in many encodings | |
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
298 | |
299 // Class for all integer registers, except the G registers. This is used for | |
300 // encodings which use G registers as temps. The regular inputs to such | |
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator | |
302 // will not put an input into a temp register. | |
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
304 | |
305 reg_class g1_regI(R_G1); | |
306 reg_class g3_regI(R_G3); | |
307 reg_class g4_regI(R_G4); | |
308 reg_class o0_regI(R_O0); | |
309 reg_class o7_regI(R_O7); | |
310 | |
311 // ---------------------------- | |
312 // Pointer Register Classes | |
313 // ---------------------------- | |
314 #ifdef _LP64 | |
315 // 64-bit build means 64-bit pointers means hi/lo pairs | |
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
320 // Lock encodings use G3 and G4 internally | |
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, | |
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, | |
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); | |
325 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
326 // It is also used for memory addressing, allowing direct TLS addressing. | |
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, | |
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, | |
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, | |
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); | |
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
332 // We use it to save R_G2 across calls out of Java. | |
333 reg_class l7_regP(R_L7H,R_L7); | |
334 | |
335 // Other special pointer regs | |
336 reg_class g1_regP(R_G1H,R_G1); | |
337 reg_class g2_regP(R_G2H,R_G2); | |
338 reg_class g3_regP(R_G3H,R_G3); | |
339 reg_class g4_regP(R_G4H,R_G4); | |
340 reg_class g5_regP(R_G5H,R_G5); | |
341 reg_class i0_regP(R_I0H,R_I0); | |
342 reg_class o0_regP(R_O0H,R_O0); | |
343 reg_class o1_regP(R_O1H,R_O1); | |
344 reg_class o2_regP(R_O2H,R_O2); | |
345 reg_class o7_regP(R_O7H,R_O7); | |
346 | |
347 #else // _LP64 | |
348 // 32-bit build means 32-bit pointers means 1 register. | |
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, | |
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
353 // Lock encodings use G3 and G4 internally | |
354 reg_class lock_ptr_reg(R_G1, R_G5, | |
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, | |
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); | |
358 // Special class for storeP instructions, which can store SP or RPC to TLS. | |
359 // It is also used for memory addressing, allowing direct TLS addressing. | |
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, | |
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, | |
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, | |
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); | |
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register | |
365 // We use it to save R_G2 across calls out of Java. | |
366 reg_class l7_regP(R_L7); | |
367 | |
368 // Other special pointer regs | |
369 reg_class g1_regP(R_G1); | |
370 reg_class g2_regP(R_G2); | |
371 reg_class g3_regP(R_G3); | |
372 reg_class g4_regP(R_G4); | |
373 reg_class g5_regP(R_G5); | |
374 reg_class i0_regP(R_I0); | |
375 reg_class o0_regP(R_O0); | |
376 reg_class o1_regP(R_O1); | |
377 reg_class o2_regP(R_O2); | |
378 reg_class o7_regP(R_O7); | |
379 #endif // _LP64 | |
380 | |
381 | |
382 // ---------------------------- | |
383 // Long Register Classes | |
384 // ---------------------------- | |
385 // Longs in 1 register. Aligned adjacent hi/lo pairs. | |
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp. | |
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 | |
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 | |
389 #ifdef _LP64 | |
390 // 64-bit, longs in 1 register: use all 64-bit integer registers | |
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. | |
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 | |
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 | |
394 #endif // _LP64 | |
395 ); | |
396 | |
397 reg_class g1_regL(R_G1H,R_G1); | |
420
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398 reg_class g3_regL(R_G3H,R_G3); |
0 | 399 reg_class o2_regL(R_O2H,R_O2); |
400 reg_class o7_regL(R_O7H,R_O7); | |
401 | |
402 // ---------------------------- | |
403 // Special Class for Condition Code Flags Register | |
404 reg_class int_flags(CCR); | |
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3); | |
406 reg_class float_flag0(FCC0); | |
407 | |
408 | |
409 // ---------------------------- | |
410 // Float Point Register Classes | |
411 // ---------------------------- | |
412 // Skip F30/F31, they are reserved for mem-mem copies | |
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); | |
414 | |
415 // Paired floating point registers--they show up in the same order as the floats, | |
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, | |
419 /* Use extra V9 double registers; this AD file does not support V8 */ | |
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, | |
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x | |
422 ); | |
423 | |
424 // Paired floating point registers--they show up in the same order as the floats, | |
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs. | |
426 // This class is usable for mis-aligned loads as happen in I2C adapters. | |
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, | |
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); | |
429 %} | |
430 | |
431 //----------DEFINITION BLOCK--------------------------------------------------- | |
432 // Define name --> value mappings to inform the ADLC of an integer valued name | |
433 // Current support includes integer values in the range [0, 0x7FFFFFFF] | |
434 // Format: | |
435 // int_def <name> ( <int_value>, <expression>); | |
436 // Generated Code in ad_<arch>.hpp | |
437 // #define <name> (<expression>) | |
438 // // value == <int_value> | |
439 // Generated code in ad_<arch>.cpp adlc_verification() | |
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); | |
441 // | |
442 definitions %{ | |
443 // The default cost (of an ALU instruction). | |
444 int_def DEFAULT_COST ( 100, 100); | |
445 int_def HUGE_COST (1000000, 1000000); | |
446 | |
447 // Memory refs are twice as expensive as run-of-the-mill. | |
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); | |
449 | |
450 // Branches are even more expensive. | |
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); | |
452 int_def CALL_COST ( 300, DEFAULT_COST * 3); | |
453 %} | |
454 | |
455 | |
456 //----------SOURCE BLOCK------------------------------------------------------- | |
457 // This is a block of C++ code which provides values, functions, and | |
458 // definitions necessary in the rest of the architecture description | |
459 source_hpp %{ | |
460 // Must be visible to the DFA in dfa_sparc.cpp | |
461 extern bool can_branch_register( Node *bol, Node *cmp ); | |
462 | |
463 // Macros to extract hi & lo halves from a long pair. | |
464 // G0 is not part of any long pair, so assert on that. | |
605 | 465 // Prevents accidentally using G1 instead of G0. |
0 | 466 #define LONG_HI_REG(x) (x) |
467 #define LONG_LO_REG(x) (x) | |
468 | |
469 %} | |
470 | |
471 source %{ | |
472 #define __ _masm. | |
473 | |
474 // tertiary op of a LoadP or StoreP encoding | |
475 #define REGP_OP true | |
476 | |
477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); | |
478 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); | |
479 static Register reg_to_register_object(int register_encoding); | |
480 | |
481 // Used by the DFA in dfa_sparc.cpp. | |
482 // Check for being able to use a V9 branch-on-register. Requires a | |
483 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign- | |
484 // extended. Doesn't work following an integer ADD, for example, because of | |
485 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On | |
486 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and | |
487 // replace them with zero, which could become sign-extension in a different OS | |
488 // release. There's no obvious reason why an interrupt will ever fill these | |
489 // bits with non-zero junk (the registers are reloaded with standard LD | |
490 // instructions which either zero-fill or sign-fill). | |
491 bool can_branch_register( Node *bol, Node *cmp ) { | |
492 if( !BranchOnRegister ) return false; | |
493 #ifdef _LP64 | |
494 if( cmp->Opcode() == Op_CmpP ) | |
495 return true; // No problems with pointer compares | |
496 #endif | |
497 if( cmp->Opcode() == Op_CmpL ) | |
498 return true; // No problems with long compares | |
499 | |
500 if( !SparcV9RegsHiBitsZero ) return false; | |
501 if( bol->as_Bool()->_test._test != BoolTest::ne && | |
502 bol->as_Bool()->_test._test != BoolTest::eq ) | |
503 return false; | |
504 | |
505 // Check for comparing against a 'safe' value. Any operation which | |
506 // clears out the high word is safe. Thus, loads and certain shifts | |
507 // are safe, as are non-negative constants. Any operation which | |
508 // preserves zero bits in the high word is safe as long as each of its | |
509 // inputs are safe. Thus, phis and bitwise booleans are safe if their | |
510 // inputs are safe. At present, the only important case to recognize | |
511 // seems to be loads. Constants should fold away, and shifts & | |
512 // logicals can use the 'cc' forms. | |
513 Node *x = cmp->in(1); | |
514 if( x->is_Load() ) return true; | |
515 if( x->is_Phi() ) { | |
516 for( uint i = 1; i < x->req(); i++ ) | |
517 if( !x->in(i)->is_Load() ) | |
518 return false; | |
519 return true; | |
520 } | |
521 return false; | |
522 } | |
523 | |
524 // **************************************************************************** | |
525 | |
526 // REQUIRED FUNCTIONALITY | |
527 | |
528 // !!!!! Special hack to get all type of calls to specify the byte offset | |
529 // from the start of the call to the point where the return address | |
530 // will point. | |
531 // The "return address" is the address of the call instruction, plus 8. | |
532 | |
533 int MachCallStaticJavaNode::ret_addr_offset() { | |
534 return NativeCall::instruction_size; // call; delay slot | |
535 } | |
536 | |
537 int MachCallDynamicJavaNode::ret_addr_offset() { | |
538 int vtable_index = this->_vtable_index; | |
539 if (vtable_index < 0) { | |
540 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
541 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
542 return (NativeMovConstReg::instruction_size + | |
543 NativeCall::instruction_size); // sethi; setlo; call; delay slot | |
544 } else { | |
545 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
546 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); | |
547 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
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548 int klass_load_size; |
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549 if (UseCompressedOops) { |
642
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550 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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551 if (Universe::narrow_oop_base() == NULL) |
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552 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() |
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553 else |
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554 klass_load_size = 3*BytesPerInstWord; |
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555 } else { |
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556 klass_load_size = 1*BytesPerInstWord; |
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557 } |
0 | 558 if( Assembler::is_simm13(v_off) ) { |
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559 return klass_load_size + |
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560 (2*BytesPerInstWord + // ld_ptr, ld_ptr |
0 | 561 NativeCall::instruction_size); // call; delay slot |
562 } else { | |
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563 return klass_load_size + |
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564 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr |
0 | 565 NativeCall::instruction_size); // call; delay slot |
566 } | |
567 } | |
568 } | |
569 | |
570 int MachCallRuntimeNode::ret_addr_offset() { | |
571 #ifdef _LP64 | |
572 return NativeFarCall::instruction_size; // farcall; delay slot | |
573 #else | |
574 return NativeCall::instruction_size; // call; delay slot | |
575 #endif | |
576 } | |
577 | |
578 // Indicate if the safepoint node needs the polling page as an input. | |
579 // Since Sparc does not have absolute addressing, it does. | |
580 bool SafePointNode::needs_polling_address_input() { | |
581 return true; | |
582 } | |
583 | |
584 // emit an interrupt that is caught by the debugger (for debugging compiler) | |
585 void emit_break(CodeBuffer &cbuf) { | |
586 MacroAssembler _masm(&cbuf); | |
587 __ breakpoint_trap(); | |
588 } | |
589 | |
590 #ifndef PRODUCT | |
591 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
592 st->print("TA"); | |
593 } | |
594 #endif | |
595 | |
596 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
597 emit_break(cbuf); | |
598 } | |
599 | |
600 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { | |
601 return MachNode::size(ra_); | |
602 } | |
603 | |
604 // Traceable jump | |
605 void emit_jmpl(CodeBuffer &cbuf, int jump_target) { | |
606 MacroAssembler _masm(&cbuf); | |
607 Register rdest = reg_to_register_object(jump_target); | |
608 __ JMP(rdest, 0); | |
609 __ delayed()->nop(); | |
610 } | |
611 | |
612 // Traceable jump and set exception pc | |
613 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { | |
614 MacroAssembler _masm(&cbuf); | |
615 Register rdest = reg_to_register_object(jump_target); | |
616 __ JMP(rdest, 0); | |
617 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); | |
618 } | |
619 | |
620 void emit_nop(CodeBuffer &cbuf) { | |
621 MacroAssembler _masm(&cbuf); | |
622 __ nop(); | |
623 } | |
624 | |
625 void emit_illtrap(CodeBuffer &cbuf) { | |
626 MacroAssembler _masm(&cbuf); | |
627 __ illtrap(0); | |
628 } | |
629 | |
630 | |
631 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { | |
632 assert(n->rule() != loadUB_rule, ""); | |
633 | |
634 intptr_t offset = 0; | |
635 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP | |
636 const Node* addr = n->get_base_and_disp(offset, adr_type); | |
637 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); | |
638 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); | |
639 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
640 atype = atype->add_offset(offset); | |
641 assert(disp32 == offset, "wrong disp32"); | |
642 return atype->_offset; | |
643 } | |
644 | |
645 | |
646 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { | |
647 assert(n->rule() != loadUB_rule, ""); | |
648 | |
649 intptr_t offset = 0; | |
650 Node* addr = n->in(2); | |
651 assert(addr->bottom_type()->isa_oopptr() == atype, ""); | |
652 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { | |
653 Node* a = addr->in(2/*AddPNode::Address*/); | |
654 Node* o = addr->in(3/*AddPNode::Offset*/); | |
655 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; | |
656 atype = a->bottom_type()->is_ptr()->add_offset(offset); | |
657 assert(atype->isa_oop_ptr(), "still an oop"); | |
658 } | |
659 offset = atype->is_ptr()->_offset; | |
660 if (offset != Type::OffsetBot) offset += disp32; | |
661 return offset; | |
662 } | |
663 | |
664 // Standard Sparc opcode form2 field breakdown | |
665 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { | |
666 f0 &= (1<<19)-1; // Mask displacement to 19 bits | |
667 int op = (f30 << 30) | | |
668 (f29 << 29) | | |
669 (f25 << 25) | | |
670 (f22 << 22) | | |
671 (f20 << 20) | | |
672 (f19 << 19) | | |
673 (f0 << 0); | |
674 *((int*)(cbuf.code_end())) = op; | |
675 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
676 } | |
677 | |
678 // Standard Sparc opcode form2 field breakdown | |
679 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { | |
680 f0 >>= 10; // Drop 10 bits | |
681 f0 &= (1<<22)-1; // Mask displacement to 22 bits | |
682 int op = (f30 << 30) | | |
683 (f25 << 25) | | |
684 (f22 << 22) | | |
685 (f0 << 0); | |
686 *((int*)(cbuf.code_end())) = op; | |
687 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
688 } | |
689 | |
690 // Standard Sparc opcode form3 field breakdown | |
691 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { | |
692 int op = (f30 << 30) | | |
693 (f25 << 25) | | |
694 (f19 << 19) | | |
695 (f14 << 14) | | |
696 (f5 << 5) | | |
697 (f0 << 0); | |
698 *((int*)(cbuf.code_end())) = op; | |
699 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
700 } | |
701 | |
702 // Standard Sparc opcode form3 field breakdown | |
703 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { | |
704 simm13 &= (1<<13)-1; // Mask to 13 bits | |
705 int op = (f30 << 30) | | |
706 (f25 << 25) | | |
707 (f19 << 19) | | |
708 (f14 << 14) | | |
709 (1 << 13) | // bit to indicate immediate-mode | |
710 (simm13<<0); | |
711 *((int*)(cbuf.code_end())) = op; | |
712 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
713 } | |
714 | |
715 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { | |
716 simm10 &= (1<<10)-1; // Mask to 10 bits | |
717 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); | |
718 } | |
719 | |
720 #ifdef ASSERT | |
721 // Helper function for VerifyOops in emit_form3_mem_reg | |
722 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { | |
723 warning("VerifyOops encountered unexpected instruction:"); | |
724 n->dump(2); | |
725 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); | |
726 } | |
727 #endif | |
728 | |
729 | |
730 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
731 int src1_enc, int disp32, int src2_enc, int dst_enc) { | |
732 | |
733 #ifdef ASSERT | |
734 // The following code implements the +VerifyOops feature. | |
735 // It verifies oop values which are loaded into or stored out of | |
736 // the current method activation. +VerifyOops complements techniques | |
737 // like ScavengeALot, because it eagerly inspects oops in transit, | |
738 // as they enter or leave the stack, as opposed to ScavengeALot, | |
739 // which inspects oops "at rest", in the stack or heap, at safepoints. | |
740 // For this reason, +VerifyOops can sometimes detect bugs very close | |
741 // to their point of creation. It can also serve as a cross-check | |
742 // on the validity of oop maps, when used toegether with ScavengeALot. | |
743 | |
744 // It would be good to verify oops at other points, especially | |
745 // when an oop is used as a base pointer for a load or store. | |
746 // This is presently difficult, because it is hard to know when | |
747 // a base address is biased or not. (If we had such information, | |
748 // it would be easy and useful to make a two-argument version of | |
749 // verify_oop which unbiases the base, and performs verification.) | |
750 | |
751 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); | |
752 bool is_verified_oop_base = false; | |
753 bool is_verified_oop_load = false; | |
754 bool is_verified_oop_store = false; | |
755 int tmp_enc = -1; | |
756 if (VerifyOops && src1_enc != R_SP_enc) { | |
757 // classify the op, mainly for an assert check | |
758 int st_op = 0, ld_op = 0; | |
759 switch (primary) { | |
760 case Assembler::stb_op3: st_op = Op_StoreB; break; | |
761 case Assembler::sth_op3: st_op = Op_StoreC; break; | |
762 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 | |
763 case Assembler::stw_op3: st_op = Op_StoreI; break; | |
764 case Assembler::std_op3: st_op = Op_StoreL; break; | |
765 case Assembler::stf_op3: st_op = Op_StoreF; break; | |
766 case Assembler::stdf_op3: st_op = Op_StoreD; break; | |
767 | |
768 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; | |
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769 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; |
0 | 770 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; |
771 case Assembler::ldx_op3: // may become LoadP or stay LoadI | |
772 case Assembler::ldsw_op3: // may become LoadP or stay LoadI | |
773 case Assembler::lduw_op3: ld_op = Op_LoadI; break; | |
774 case Assembler::ldd_op3: ld_op = Op_LoadL; break; | |
775 case Assembler::ldf_op3: ld_op = Op_LoadF; break; | |
776 case Assembler::lddf_op3: ld_op = Op_LoadD; break; | |
777 case Assembler::ldub_op3: ld_op = Op_LoadB; break; | |
778 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; | |
779 | |
780 default: ShouldNotReachHere(); | |
781 } | |
782 if (tertiary == REGP_OP) { | |
783 if (st_op == Op_StoreI) st_op = Op_StoreP; | |
784 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; | |
785 else ShouldNotReachHere(); | |
786 if (st_op) { | |
787 // a store | |
788 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
789 Node* n2 = n->in(3); | |
790 if (n2 != NULL) { | |
791 const Type* t = n2->bottom_type(); | |
792 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
793 } | |
794 } else { | |
795 // a load | |
796 const Type* t = n->bottom_type(); | |
797 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; | |
798 } | |
799 } | |
800 | |
801 if (ld_op) { | |
802 // a Load | |
803 // inputs are (0:control, 1:memory, 2:address) | |
804 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases | |
805 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && | |
806 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && | |
807 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && | |
808 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && | |
809 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && | |
810 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && | |
811 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && | |
812 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && | |
813 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && | |
814 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && | |
815 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && | |
816 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && | |
817 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && | |
818 !(n->rule() == loadUB_rule)) { | |
819 verify_oops_warning(n, n->ideal_Opcode(), ld_op); | |
820 } | |
821 } else if (st_op) { | |
822 // a Store | |
823 // inputs are (0:control, 1:memory, 2:address, 3:value) | |
824 if (!(n->ideal_Opcode()==st_op) && // Following are special cases | |
825 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && | |
826 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && | |
827 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && | |
828 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && | |
829 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { | |
830 verify_oops_warning(n, n->ideal_Opcode(), st_op); | |
831 } | |
832 } | |
833 | |
834 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { | |
835 Node* addr = n->in(2); | |
836 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { | |
837 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? | |
838 if (atype != NULL) { | |
839 intptr_t offset = get_offset_from_base(n, atype, disp32); | |
840 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); | |
841 if (offset != offset_2) { | |
842 get_offset_from_base(n, atype, disp32); | |
843 get_offset_from_base_2(n, atype, disp32); | |
844 } | |
845 assert(offset == offset_2, "different offsets"); | |
846 if (offset == disp32) { | |
847 // we now know that src1 is a true oop pointer | |
848 is_verified_oop_base = true; | |
849 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { | |
850 if( primary == Assembler::ldd_op3 ) { | |
851 is_verified_oop_base = false; // Cannot 'ldd' into O7 | |
852 } else { | |
853 tmp_enc = dst_enc; | |
854 dst_enc = R_O7_enc; // Load into O7; preserve source oop | |
855 assert(src1_enc != dst_enc, ""); | |
856 } | |
857 } | |
858 } | |
859 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) | |
860 || offset == oopDesc::mark_offset_in_bytes())) { | |
861 // loading the mark should not be allowed either, but | |
862 // we don't check this since it conflicts with InlineObjectHash | |
863 // usage of LoadINode to get the mark. We could keep the | |
864 // check if we create a new LoadMarkNode | |
865 // but do not verify the object before its header is initialized | |
866 ShouldNotReachHere(); | |
867 } | |
868 } | |
869 } | |
870 } | |
871 } | |
872 #endif | |
873 | |
874 uint instr; | |
875 instr = (Assembler::ldst_op << 30) | |
876 | (dst_enc << 25) | |
877 | (primary << 19) | |
878 | (src1_enc << 14); | |
879 | |
880 uint index = src2_enc; | |
881 int disp = disp32; | |
882 | |
883 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
884 disp += STACK_BIAS; | |
885 | |
886 // We should have a compiler bailout here rather than a guarantee. | |
887 // Better yet would be some mechanism to handle variable-size matches correctly. | |
888 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
889 | |
890 if( disp == 0 ) { | |
891 // use reg-reg form | |
892 // bit 13 is already zero | |
893 instr |= index; | |
894 } else { | |
895 // use reg-imm form | |
896 instr |= 0x00002000; // set bit 13 to one | |
897 instr |= disp & 0x1FFF; | |
898 } | |
899 | |
900 uint *code = (uint*)cbuf.code_end(); | |
901 *code = instr; | |
902 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
903 | |
904 #ifdef ASSERT | |
905 { | |
906 MacroAssembler _masm(&cbuf); | |
907 if (is_verified_oop_base) { | |
908 __ verify_oop(reg_to_register_object(src1_enc)); | |
909 } | |
910 if (is_verified_oop_store) { | |
911 __ verify_oop(reg_to_register_object(dst_enc)); | |
912 } | |
913 if (tmp_enc != -1) { | |
914 __ mov(O7, reg_to_register_object(tmp_enc)); | |
915 } | |
916 if (is_verified_oop_load) { | |
917 __ verify_oop(reg_to_register_object(dst_enc)); | |
918 } | |
919 } | |
920 #endif | |
921 } | |
922 | |
923 void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, | |
924 int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) { | |
925 | |
926 uint instr; | |
927 instr = (Assembler::ldst_op << 30) | |
928 | (dst_enc << 25) | |
929 | (primary << 19) | |
930 | (src1_enc << 14); | |
931 | |
932 int disp = disp32; | |
933 int index = src2_enc; | |
934 | |
935 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) | |
936 disp += STACK_BIAS; | |
937 | |
938 // We should have a compiler bailout here rather than a guarantee. | |
939 // Better yet would be some mechanism to handle variable-size matches correctly. | |
940 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); | |
941 | |
942 if( disp != 0 ) { | |
943 // use reg-reg form | |
944 // set src2=R_O7 contains offset | |
945 index = R_O7_enc; | |
946 emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp); | |
947 } | |
948 instr |= (asi << 5); | |
949 instr |= index; | |
950 uint *code = (uint*)cbuf.code_end(); | |
951 *code = instr; | |
952 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
953 } | |
954 | |
955 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { | |
956 // The method which records debug information at every safepoint | |
957 // expects the call to be the first instruction in the snippet as | |
958 // it creates a PcDesc structure which tracks the offset of a call | |
959 // from the start of the codeBlob. This offset is computed as | |
960 // code_end() - code_begin() of the code which has been emitted | |
961 // so far. | |
962 // In this particular case we have skirted around the problem by | |
963 // putting the "mov" instruction in the delay slot but the problem | |
964 // may bite us again at some other point and a cleaner/generic | |
965 // solution using relocations would be needed. | |
966 MacroAssembler _masm(&cbuf); | |
967 __ set_inst_mark(); | |
968 | |
969 // We flush the current window just so that there is a valid stack copy | |
970 // the fact that the current window becomes active again instantly is | |
971 // not a problem there is nothing live in it. | |
972 | |
973 #ifdef ASSERT | |
974 int startpos = __ offset(); | |
975 #endif /* ASSERT */ | |
976 | |
977 #ifdef _LP64 | |
978 // Calls to the runtime or native may not be reachable from compiled code, | |
979 // so we generate the far call sequence on 64 bit sparc. | |
980 // This code sequence is relocatable to any address, even on LP64. | |
981 if ( force_far_call ) { | |
982 __ relocate(rtype); | |
727 | 983 AddressLiteral dest(entry_point); |
984 __ jumpl_to(dest, O7, O7); | |
0 | 985 } |
986 else | |
987 #endif | |
988 { | |
989 __ call((address)entry_point, rtype); | |
990 } | |
991 | |
992 if (preserve_g2) __ delayed()->mov(G2, L7); | |
993 else __ delayed()->nop(); | |
994 | |
995 if (preserve_g2) __ mov(L7, G2); | |
996 | |
997 #ifdef ASSERT | |
998 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { | |
999 #ifdef _LP64 | |
1000 // Trash argument dump slots. | |
1001 __ set(0xb0b8ac0db0b8ac0d, G1); | |
1002 __ mov(G1, G5); | |
1003 __ stx(G1, SP, STACK_BIAS + 0x80); | |
1004 __ stx(G1, SP, STACK_BIAS + 0x88); | |
1005 __ stx(G1, SP, STACK_BIAS + 0x90); | |
1006 __ stx(G1, SP, STACK_BIAS + 0x98); | |
1007 __ stx(G1, SP, STACK_BIAS + 0xA0); | |
1008 __ stx(G1, SP, STACK_BIAS + 0xA8); | |
1009 #else // _LP64 | |
1010 // this is also a native call, so smash the first 7 stack locations, | |
1011 // and the various registers | |
1012 | |
1013 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], | |
1014 // while [SP+0x44..0x58] are the argument dump slots. | |
1015 __ set((intptr_t)0xbaadf00d, G1); | |
1016 __ mov(G1, G5); | |
1017 __ sllx(G1, 32, G1); | |
1018 __ or3(G1, G5, G1); | |
1019 __ mov(G1, G5); | |
1020 __ stx(G1, SP, 0x40); | |
1021 __ stx(G1, SP, 0x48); | |
1022 __ stx(G1, SP, 0x50); | |
1023 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot | |
1024 #endif // _LP64 | |
1025 } | |
1026 #endif /*ASSERT*/ | |
1027 } | |
1028 | |
1029 //============================================================================= | |
1030 // REQUIRED FUNCTIONALITY for encoding | |
1031 void emit_lo(CodeBuffer &cbuf, int val) { } | |
1032 void emit_hi(CodeBuffer &cbuf, int val) { } | |
1033 | |
1034 | |
1035 //============================================================================= | |
1036 | |
1037 #ifndef PRODUCT | |
1038 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1039 Compile* C = ra_->C; | |
1040 | |
1041 for (int i = 0; i < OptoPrologueNops; i++) { | |
1042 st->print_cr("NOP"); st->print("\t"); | |
1043 } | |
1044 | |
1045 if( VerifyThread ) { | |
1046 st->print_cr("Verify_Thread"); st->print("\t"); | |
1047 } | |
1048 | |
1049 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1050 | |
1051 // Calls to C2R adapters often do not accept exceptional returns. | |
1052 // We require that their callers must bang for them. But be careful, because | |
1053 // some VM calls (such as call site linkage) can use several kilobytes of | |
1054 // stack. But the stack safety zone should account for that. | |
1055 // See bugs 4446381, 4468289, 4497237. | |
1056 if (C->need_stack_bang(framesize)) { | |
1057 st->print_cr("! stack bang"); st->print("\t"); | |
1058 } | |
1059 | |
1060 if (Assembler::is_simm13(-framesize)) { | |
1061 st->print ("SAVE R_SP,-%d,R_SP",framesize); | |
1062 } else { | |
1063 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); | |
1064 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); | |
1065 st->print ("SAVE R_SP,R_G3,R_SP"); | |
1066 } | |
1067 | |
1068 } | |
1069 #endif | |
1070 | |
1071 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1072 Compile* C = ra_->C; | |
1073 MacroAssembler _masm(&cbuf); | |
1074 | |
1075 for (int i = 0; i < OptoPrologueNops; i++) { | |
1076 __ nop(); | |
1077 } | |
1078 | |
1079 __ verify_thread(); | |
1080 | |
1081 size_t framesize = C->frame_slots() << LogBytesPerInt; | |
1082 assert(framesize >= 16*wordSize, "must have room for reg. save area"); | |
1083 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); | |
1084 | |
1085 // Calls to C2R adapters often do not accept exceptional returns. | |
1086 // We require that their callers must bang for them. But be careful, because | |
1087 // some VM calls (such as call site linkage) can use several kilobytes of | |
1088 // stack. But the stack safety zone should account for that. | |
1089 // See bugs 4446381, 4468289, 4497237. | |
1090 if (C->need_stack_bang(framesize)) { | |
1091 __ generate_stack_overflow_check(framesize); | |
1092 } | |
1093 | |
1094 if (Assembler::is_simm13(-framesize)) { | |
1095 __ save(SP, -framesize, SP); | |
1096 } else { | |
1097 __ sethi(-framesize & ~0x3ff, G3); | |
1098 __ add(G3, -framesize & 0x3ff, G3); | |
1099 __ save(SP, G3, SP); | |
1100 } | |
1101 C->set_frame_complete( __ offset() ); | |
1102 } | |
1103 | |
1104 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { | |
1105 return MachNode::size(ra_); | |
1106 } | |
1107 | |
1108 int MachPrologNode::reloc() const { | |
1109 return 10; // a large enough number | |
1110 } | |
1111 | |
1112 //============================================================================= | |
1113 #ifndef PRODUCT | |
1114 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1115 Compile* C = ra_->C; | |
1116 | |
1117 if( do_polling() && ra_->C->is_method_compilation() ) { | |
1118 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); | |
1119 #ifdef _LP64 | |
1120 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); | |
1121 #else | |
1122 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); | |
1123 #endif | |
1124 } | |
1125 | |
1126 if( do_polling() ) | |
1127 st->print("RET\n\t"); | |
1128 | |
1129 st->print("RESTORE"); | |
1130 } | |
1131 #endif | |
1132 | |
1133 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1134 MacroAssembler _masm(&cbuf); | |
1135 Compile* C = ra_->C; | |
1136 | |
1137 __ verify_thread(); | |
1138 | |
1139 // If this does safepoint polling, then do it here | |
1140 if( do_polling() && ra_->C->is_method_compilation() ) { | |
727 | 1141 AddressLiteral polling_page(os::get_polling_page()); |
1142 __ sethi(polling_page, L0); | |
0 | 1143 __ relocate(relocInfo::poll_return_type); |
1144 __ ld_ptr( L0, 0, G0 ); | |
1145 } | |
1146 | |
1147 // If this is a return, then stuff the restore in the delay slot | |
1148 if( do_polling() ) { | |
1149 __ ret(); | |
1150 __ delayed()->restore(); | |
1151 } else { | |
1152 __ restore(); | |
1153 } | |
1154 } | |
1155 | |
1156 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { | |
1157 return MachNode::size(ra_); | |
1158 } | |
1159 | |
1160 int MachEpilogNode::reloc() const { | |
1161 return 16; // a large enough number | |
1162 } | |
1163 | |
1164 const Pipeline * MachEpilogNode::pipeline() const { | |
1165 return MachNode::pipeline_class(); | |
1166 } | |
1167 | |
1168 int MachEpilogNode::safepoint_offset() const { | |
1169 assert( do_polling(), "no return for this epilog node"); | |
1170 return MacroAssembler::size_of_sethi(os::get_polling_page()); | |
1171 } | |
1172 | |
1173 //============================================================================= | |
1174 | |
1175 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack | |
1176 enum RC { rc_bad, rc_int, rc_float, rc_stack }; | |
1177 static enum RC rc_class( OptoReg::Name reg ) { | |
1178 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
1179 if (OptoReg::is_stack(reg)) return rc_stack; | |
1180 VMReg r = OptoReg::as_VMReg(reg); | |
1181 if (r->is_Register()) return rc_int; | |
1182 assert(r->is_FloatRegister(), "must be"); | |
1183 return rc_float; | |
1184 } | |
1185 | |
1186 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { | |
1187 if( cbuf ) { | |
1188 // Better yet would be some mechanism to handle variable-size matches correctly | |
1189 if (!Assembler::is_simm13(offset + STACK_BIAS)) { | |
1190 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); | |
1191 } else { | |
1192 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); | |
1193 } | |
1194 } | |
1195 #ifndef PRODUCT | |
1196 else if( !do_size ) { | |
1197 if( size != 0 ) st->print("\n\t"); | |
1198 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); | |
1199 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); | |
1200 } | |
1201 #endif | |
1202 return size+4; | |
1203 } | |
1204 | |
1205 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { | |
1206 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); | |
1207 #ifndef PRODUCT | |
1208 else if( !do_size ) { | |
1209 if( size != 0 ) st->print("\n\t"); | |
1210 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); | |
1211 } | |
1212 #endif | |
1213 return size+4; | |
1214 } | |
1215 | |
1216 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, | |
1217 PhaseRegAlloc *ra_, | |
1218 bool do_size, | |
1219 outputStream* st ) const { | |
1220 // Get registers to move | |
1221 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
1222 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
1223 OptoReg::Name dst_second = ra_->get_reg_second(this ); | |
1224 OptoReg::Name dst_first = ra_->get_reg_first(this ); | |
1225 | |
1226 enum RC src_second_rc = rc_class(src_second); | |
1227 enum RC src_first_rc = rc_class(src_first); | |
1228 enum RC dst_second_rc = rc_class(dst_second); | |
1229 enum RC dst_first_rc = rc_class(dst_first); | |
1230 | |
1231 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); | |
1232 | |
1233 // Generate spill code! | |
1234 int size = 0; | |
1235 | |
1236 if( src_first == dst_first && src_second == dst_second ) | |
1237 return size; // Self copy, no move | |
1238 | |
1239 // -------------------------------------- | |
1240 // Check for mem-mem move. Load into unused float registers and fall into | |
1241 // the float-store case. | |
1242 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { | |
1243 int offset = ra_->reg2offset(src_first); | |
1244 // Further check for aligned-adjacent pair, so we can use a double load | |
1245 if( (src_first&1)==0 && src_first+1 == src_second ) { | |
1246 src_second = OptoReg::Name(R_F31_num); | |
1247 src_second_rc = rc_float; | |
1248 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); | |
1249 } else { | |
1250 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); | |
1251 } | |
1252 src_first = OptoReg::Name(R_F30_num); | |
1253 src_first_rc = rc_float; | |
1254 } | |
1255 | |
1256 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { | |
1257 int offset = ra_->reg2offset(src_second); | |
1258 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); | |
1259 src_second = OptoReg::Name(R_F31_num); | |
1260 src_second_rc = rc_float; | |
1261 } | |
1262 | |
1263 // -------------------------------------- | |
1264 // Check for float->int copy; requires a trip through memory | |
1265 if( src_first_rc == rc_float && dst_first_rc == rc_int ) { | |
1266 int offset = frame::register_save_words*wordSize; | |
1267 if( cbuf ) { | |
1268 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); | |
1269 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1270 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1271 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); | |
1272 } | |
1273 #ifndef PRODUCT | |
1274 else if( !do_size ) { | |
1275 if( size != 0 ) st->print("\n\t"); | |
1276 st->print( "SUB R_SP,16,R_SP\n"); | |
1277 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1278 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1279 st->print("\tADD R_SP,16,R_SP\n"); | |
1280 } | |
1281 #endif | |
1282 size += 16; | |
1283 } | |
1284 | |
1285 // -------------------------------------- | |
1286 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. | |
1287 // In such cases, I have to do the big-endian swap. For aligned targets, the | |
1288 // hardware does the flop for me. Doubles are always aligned, so no problem | |
1289 // there. Misaligned sources only come from native-long-returns (handled | |
1290 // special below). | |
1291 #ifndef _LP64 | |
1292 if( src_first_rc == rc_int && // source is already big-endian | |
1293 src_second_rc != rc_bad && // 64-bit move | |
1294 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst | |
1295 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); | |
1296 // Do the big-endian flop. | |
1297 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; | |
1298 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; | |
1299 } | |
1300 #endif | |
1301 | |
1302 // -------------------------------------- | |
1303 // Check for integer reg-reg copy | |
1304 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { | |
1305 #ifndef _LP64 | |
1306 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case | |
1307 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1308 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1309 // operand contains the least significant word of the 64-bit value and vice versa. | |
1310 OptoReg::Name tmp = OptoReg::Name(R_O7_num); | |
1311 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); | |
1312 // Shift O0 left in-place, zero-extend O1, then OR them into the dst | |
1313 if( cbuf ) { | |
1314 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); | |
1315 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); | |
1316 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); | |
1317 #ifndef PRODUCT | |
1318 } else if( !do_size ) { | |
1319 if( size != 0 ) st->print("\n\t"); | |
1320 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); | |
1321 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); | |
1322 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); | |
1323 #endif | |
1324 } | |
1325 return size+12; | |
1326 } | |
1327 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { | |
1328 // returning a long value in I0/I1 | |
1329 // a SpillCopy must be able to target a return instruction's reg_class | |
1330 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value | |
1331 // as stored in memory. On a big-endian machine like SPARC, this means that the _second | |
1332 // operand contains the least significant word of the 64-bit value and vice versa. | |
1333 OptoReg::Name tdest = dst_first; | |
1334 | |
1335 if (src_first == dst_first) { | |
1336 tdest = OptoReg::Name(R_O7_num); | |
1337 size += 4; | |
1338 } | |
1339 | |
1340 if( cbuf ) { | |
1341 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); | |
1342 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 | |
1343 // ShrL_reg_imm6 | |
1344 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); | |
1345 // ShrR_reg_imm6 src, 0, dst | |
1346 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); | |
1347 if (tdest != dst_first) { | |
1348 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); | |
1349 } | |
1350 } | |
1351 #ifndef PRODUCT | |
1352 else if( !do_size ) { | |
1353 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! | |
1354 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); | |
1355 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); | |
1356 if (tdest != dst_first) { | |
1357 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); | |
1358 } | |
1359 } | |
1360 #endif // PRODUCT | |
1361 return size+8; | |
1362 } | |
1363 #endif // !_LP64 | |
1364 // Else normal reg-reg copy | |
1365 assert( src_second != dst_first, "smashed second before evacuating it" ); | |
1366 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); | |
1367 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); | |
1368 // This moves an aligned adjacent pair. | |
1369 // See if we are done. | |
1370 if( src_first+1 == src_second && dst_first+1 == dst_second ) | |
1371 return size; | |
1372 } | |
1373 | |
1374 // Check for integer store | |
1375 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { | |
1376 int offset = ra_->reg2offset(dst_first); | |
1377 // Further check for aligned-adjacent pair, so we can use a double store | |
1378 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1379 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); | |
1380 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); | |
1381 } | |
1382 | |
1383 // Check for integer load | |
1384 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { | |
1385 int offset = ra_->reg2offset(src_first); | |
1386 // Further check for aligned-adjacent pair, so we can use a double load | |
1387 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1388 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); | |
1389 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); | |
1390 } | |
1391 | |
1392 // Check for float reg-reg copy | |
1393 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { | |
1394 // Further check for aligned-adjacent pair, so we can use a double move | |
1395 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1396 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); | |
1397 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); | |
1398 } | |
1399 | |
1400 // Check for float store | |
1401 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { | |
1402 int offset = ra_->reg2offset(dst_first); | |
1403 // Further check for aligned-adjacent pair, so we can use a double store | |
1404 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1405 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); | |
1406 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); | |
1407 } | |
1408 | |
1409 // Check for float load | |
1410 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { | |
1411 int offset = ra_->reg2offset(src_first); | |
1412 // Further check for aligned-adjacent pair, so we can use a double load | |
1413 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) | |
1414 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); | |
1415 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); | |
1416 } | |
1417 | |
1418 // -------------------------------------------------------------------- | |
1419 // Check for hi bits still needing moving. Only happens for misaligned | |
1420 // arguments to native calls. | |
1421 if( src_second == dst_second ) | |
1422 return size; // Self copy; no move | |
1423 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); | |
1424 | |
1425 #ifndef _LP64 | |
1426 // In the LP64 build, all registers can be moved as aligned/adjacent | |
605 | 1427 // pairs, so there's never any need to move the high bits separately. |
0 | 1428 // The 32-bit builds have to deal with the 32-bit ABI which can force |
1429 // all sorts of silly alignment problems. | |
1430 | |
1431 // Check for integer reg-reg copy. Hi bits are stuck up in the top | |
1432 // 32-bits of a 64-bit register, but are needed in low bits of another | |
1433 // register (else it's a hi-bits-to-hi-bits copy which should have | |
1434 // happened already as part of a 64-bit move) | |
1435 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { | |
1436 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); | |
1437 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); | |
1438 // Shift src_second down to dst_second's low bits. | |
1439 if( cbuf ) { | |
1440 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1441 #ifndef PRODUCT | |
1442 } else if( !do_size ) { | |
1443 if( size != 0 ) st->print("\n\t"); | |
1444 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); | |
1445 #endif | |
1446 } | |
1447 return size+4; | |
1448 } | |
1449 | |
1450 // Check for high word integer store. Must down-shift the hi bits | |
1451 // into a temp register, then fall into the case of storing int bits. | |
1452 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { | |
1453 // Shift src_second down to dst_second's low bits. | |
1454 if( cbuf ) { | |
1455 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); | |
1456 #ifndef PRODUCT | |
1457 } else if( !do_size ) { | |
1458 if( size != 0 ) st->print("\n\t"); | |
1459 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); | |
1460 #endif | |
1461 } | |
1462 size+=4; | |
1463 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! | |
1464 } | |
1465 | |
1466 // Check for high word integer load | |
1467 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) | |
1468 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); | |
1469 | |
1470 // Check for high word integer store | |
1471 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) | |
1472 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); | |
1473 | |
1474 // Check for high word float store | |
1475 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) | |
1476 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); | |
1477 | |
1478 #endif // !_LP64 | |
1479 | |
1480 Unimplemented(); | |
1481 } | |
1482 | |
1483 #ifndef PRODUCT | |
1484 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1485 implementation( NULL, ra_, false, st ); | |
1486 } | |
1487 #endif | |
1488 | |
1489 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1490 implementation( &cbuf, ra_, false, NULL ); | |
1491 } | |
1492 | |
1493 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { | |
1494 return implementation( NULL, ra_, true, NULL ); | |
1495 } | |
1496 | |
1497 //============================================================================= | |
1498 #ifndef PRODUCT | |
1499 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { | |
1500 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); | |
1501 } | |
1502 #endif | |
1503 | |
1504 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { | |
1505 MacroAssembler _masm(&cbuf); | |
1506 for(int i = 0; i < _count; i += 1) { | |
1507 __ nop(); | |
1508 } | |
1509 } | |
1510 | |
1511 uint MachNopNode::size(PhaseRegAlloc *ra_) const { | |
1512 return 4 * _count; | |
1513 } | |
1514 | |
1515 | |
1516 //============================================================================= | |
1517 #ifndef PRODUCT | |
1518 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
1520 int reg = ra_->get_reg_first(this); | |
1521 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); | |
1522 } | |
1523 #endif | |
1524 | |
1525 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1526 MacroAssembler _masm(&cbuf); | |
1527 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; | |
1528 int reg = ra_->get_encode(this); | |
1529 | |
1530 if (Assembler::is_simm13(offset)) { | |
1531 __ add(SP, offset, reg_to_register_object(reg)); | |
1532 } else { | |
1533 __ set(offset, O7); | |
1534 __ add(SP, O7, reg_to_register_object(reg)); | |
1535 } | |
1536 } | |
1537 | |
1538 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { | |
1539 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) | |
1540 assert(ra_ == ra_->C->regalloc(), "sanity"); | |
1541 return ra_->C->scratch_emit_size(this); | |
1542 } | |
1543 | |
1544 //============================================================================= | |
1545 | |
1546 // emit call stub, compiled java to interpretor | |
1547 void emit_java_to_interp(CodeBuffer &cbuf ) { | |
1548 | |
1549 // Stub is fixed up when the corresponding call is converted from calling | |
1550 // compiled code to calling interpreted code. | |
1551 // set (empty), G5 | |
1552 // jmp -1 | |
1553 | |
1554 address mark = cbuf.inst_mark(); // get mark within main instrs section | |
1555 | |
1556 MacroAssembler _masm(&cbuf); | |
1557 | |
1558 address base = | |
1559 __ start_a_stub(Compile::MAX_stubs_size); | |
1560 if (base == NULL) return; // CodeBuffer::expand failed | |
1561 | |
1562 // static stub relocation stores the instruction address of the call | |
1563 __ relocate(static_stub_Relocation::spec(mark)); | |
1564 | |
1565 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); | |
1566 | |
1567 __ set_inst_mark(); | |
727 | 1568 AddressLiteral addrlit(-1); |
1569 __ JUMP(addrlit, G3, 0); | |
0 | 1570 |
1571 __ delayed()->nop(); | |
1572 | |
1573 // Update current stubs pointer and restore code_end. | |
1574 __ end_a_stub(); | |
1575 } | |
1576 | |
1577 // size of call stub, compiled java to interpretor | |
1578 uint size_java_to_interp() { | |
1579 // This doesn't need to be accurate but it must be larger or equal to | |
1580 // the real size of the stub. | |
1581 return (NativeMovConstReg::instruction_size + // sethi/setlo; | |
1582 NativeJump::instruction_size + // sethi; jmp; nop | |
1583 (TraceJumps ? 20 * BytesPerInstWord : 0) ); | |
1584 } | |
1585 // relocation entries for call stub, compiled java to interpretor | |
1586 uint reloc_java_to_interp() { | |
1587 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call | |
1588 } | |
1589 | |
1590 | |
1591 //============================================================================= | |
1592 #ifndef PRODUCT | |
1593 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { | |
1594 st->print_cr("\nUEP:"); | |
1595 #ifdef _LP64 | |
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1596 if (UseCompressedOops) { |
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1597 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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1598 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); |
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1599 st->print_cr("\tSLL R_G5,3,R_G5"); |
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1600 if (Universe::narrow_oop_base() != NULL) |
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1601 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); |
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1602 } else { |
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1603 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); |
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1604 } |
0 | 1605 st->print_cr("\tCMP R_G5,R_G3" ); |
1606 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1607 #else // _LP64 | |
1608 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); | |
1609 st->print_cr("\tCMP R_G5,R_G3" ); | |
1610 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); | |
1611 #endif // _LP64 | |
1612 } | |
1613 #endif | |
1614 | |
1615 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { | |
1616 MacroAssembler _masm(&cbuf); | |
1617 Label L; | |
1618 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
1619 Register temp_reg = G3; | |
1620 assert( G5_ic_reg != temp_reg, "conflicting registers" ); | |
1621 | |
605 | 1622 // Load klass from receiver |
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1623 __ load_klass(O0, temp_reg); |
0 | 1624 // Compare against expected klass |
1625 __ cmp(temp_reg, G5_ic_reg); | |
1626 // Branch to miss code, checks xcc or icc depending | |
1627 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); | |
1628 } | |
1629 | |
1630 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { | |
1631 return MachNode::size(ra_); | |
1632 } | |
1633 | |
1634 | |
1635 //============================================================================= | |
1636 | |
1637 uint size_exception_handler() { | |
1638 if (TraceJumps) { | |
1639 return (400); // just a guess | |
1640 } | |
1641 return ( NativeJump::instruction_size ); // sethi;jmp;nop | |
1642 } | |
1643 | |
1644 uint size_deopt_handler() { | |
1645 if (TraceJumps) { | |
1646 return (400); // just a guess | |
1647 } | |
1648 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore | |
1649 } | |
1650 | |
1651 // Emit exception handler code. | |
1652 int emit_exception_handler(CodeBuffer& cbuf) { | |
1653 Register temp_reg = G3; | |
727 | 1654 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin()); |
0 | 1655 MacroAssembler _masm(&cbuf); |
1656 | |
1657 address base = | |
1658 __ start_a_stub(size_exception_handler()); | |
1659 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1660 | |
1661 int offset = __ offset(); | |
1662 | |
727 | 1663 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp |
0 | 1664 __ delayed()->nop(); |
1665 | |
1666 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); | |
1667 | |
1668 __ end_a_stub(); | |
1669 | |
1670 return offset; | |
1671 } | |
1672 | |
1673 int emit_deopt_handler(CodeBuffer& cbuf) { | |
1674 // Can't use any of the current frame's registers as we may have deopted | |
1675 // at a poll and everything (including G3) can be live. | |
1676 Register temp_reg = L0; | |
727 | 1677 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); |
0 | 1678 MacroAssembler _masm(&cbuf); |
1679 | |
1680 address base = | |
1681 __ start_a_stub(size_deopt_handler()); | |
1682 if (base == NULL) return 0; // CodeBuffer::expand failed | |
1683 | |
1684 int offset = __ offset(); | |
1685 __ save_frame(0); | |
727 | 1686 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp |
0 | 1687 __ delayed()->restore(); |
1688 | |
1689 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
1690 | |
1691 __ end_a_stub(); | |
1692 return offset; | |
1693 | |
1694 } | |
1695 | |
1696 // Given a register encoding, produce a Integer Register object | |
1697 static Register reg_to_register_object(int register_encoding) { | |
1698 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); | |
1699 return as_Register(register_encoding); | |
1700 } | |
1701 | |
1702 // Given a register encoding, produce a single-precision Float Register object | |
1703 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { | |
1704 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); | |
1705 return as_SingleFloatRegister(register_encoding); | |
1706 } | |
1707 | |
1708 // Given a register encoding, produce a double-precision Float Register object | |
1709 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { | |
1710 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); | |
1711 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); | |
1712 return as_DoubleFloatRegister(register_encoding); | |
1713 } | |
1714 | |
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1715 const bool Matcher::match_rule_supported(int opcode) { |
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1716 if (!has_match_rule(opcode)) |
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1717 return false; |
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1718 |
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1719 switch (opcode) { |
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1720 case Op_CountLeadingZerosI: |
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1721 case Op_CountLeadingZerosL: |
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1722 case Op_CountTrailingZerosI: |
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1723 case Op_CountTrailingZerosL: |
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1724 if (!UsePopCountInstruction) |
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1725 return false; |
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1726 break; |
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1727 } |
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1728 |
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1729 return true; // Per default match rules are supported. |
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1730 } |
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1731 |
0 | 1732 int Matcher::regnum_to_fpu_offset(int regnum) { |
1733 return regnum - 32; // The FP registers are in the second chunk | |
1734 } | |
1735 | |
1736 #ifdef ASSERT | |
1737 address last_rethrow = NULL; // debugging aid for Rethrow encoding | |
1738 #endif | |
1739 | |
1740 // Vector width in bytes | |
1741 const uint Matcher::vector_width_in_bytes(void) { | |
1742 return 8; | |
1743 } | |
1744 | |
1745 // Vector ideal reg | |
1746 const uint Matcher::vector_ideal_reg(void) { | |
1747 return Op_RegD; | |
1748 } | |
1749 | |
1750 // USII supports fxtof through the whole range of number, USIII doesn't | |
1751 const bool Matcher::convL2FSupported(void) { | |
1752 return VM_Version::has_fast_fxtof(); | |
1753 } | |
1754 | |
1755 // Is this branch offset short enough that a short branch can be used? | |
1756 // | |
1757 // NOTE: If the platform does not provide any short branch variants, then | |
1758 // this method should return false for offset 0. | |
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1759 bool Matcher::is_short_branch_offset(int rule, int offset) { |
0 | 1760 return false; |
1761 } | |
1762 | |
1763 const bool Matcher::isSimpleConstant64(jlong value) { | |
1764 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
1765 // Depends on optimizations in MacroAssembler::setx. | |
1766 int hi = (int)(value >> 32); | |
1767 int lo = (int)(value & ~0); | |
1768 return (hi == 0) || (hi == -1) || (lo == 0); | |
1769 } | |
1770 | |
1771 // No scaling for the parameter the ClearArray node. | |
1772 const bool Matcher::init_array_count_is_in_bytes = true; | |
1773 | |
1774 // Threshold size for cleararray. | |
1775 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
1776 | |
1777 // Should the Matcher clone shifts on addressing modes, expecting them to | |
1778 // be subsumed into complex addressing expressions or compute them into | |
1779 // registers? True for Intel but false for most RISCs | |
1780 const bool Matcher::clone_shift_expressions = false; | |
1781 | |
1782 // Is it better to copy float constants, or load them directly from memory? | |
1783 // Intel can load a float constant from a direct address, requiring no | |
1784 // extra registers. Most RISCs will have to materialize an address into a | |
1785 // register first, so they would do better to copy the constant from stack. | |
1786 const bool Matcher::rematerialize_float_constants = false; | |
1787 | |
1788 // If CPU can load and store mis-aligned doubles directly then no fixup is | |
1789 // needed. Else we split the double into 2 integer pieces and move it | |
1790 // piece-by-piece. Only happens when passing doubles into C code as the | |
1791 // Java calling convention forces doubles to be aligned. | |
1792 #ifdef _LP64 | |
1793 const bool Matcher::misaligned_doubles_ok = true; | |
1794 #else | |
1795 const bool Matcher::misaligned_doubles_ok = false; | |
1796 #endif | |
1797 | |
1798 // No-op on SPARC. | |
1799 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { | |
1800 } | |
1801 | |
1802 // Advertise here if the CPU requires explicit rounding operations | |
1803 // to implement the UseStrictFP mode. | |
1804 const bool Matcher::strict_fp_requires_explicit_rounding = false; | |
1805 | |
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1806 // Are floats conerted to double when stored to stack during deoptimization? |
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1807 // Sparc does not handle callee-save floats. |
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1808 bool Matcher::float_in_double() { return false; } |
0 | 1809 |
1810 // Do ints take an entire long register or just half? | |
1811 // Note that we if-def off of _LP64. | |
1812 // The relevant question is how the int is callee-saved. In _LP64 | |
1813 // the whole long is written but de-opt'ing will have to extract | |
1814 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written. | |
1815 #ifdef _LP64 | |
1816 const bool Matcher::int_in_long = true; | |
1817 #else | |
1818 const bool Matcher::int_in_long = false; | |
1819 #endif | |
1820 | |
1821 // Return whether or not this register is ever used as an argument. This | |
1822 // function is used on startup to build the trampoline stubs in generateOptoStub. | |
1823 // Registers not mentioned will be killed by the VM call in the trampoline, and | |
1824 // arguments in those registers not be available to the callee. | |
1825 bool Matcher::can_be_java_arg( int reg ) { | |
1826 // Standard sparc 6 args in registers | |
1827 if( reg == R_I0_num || | |
1828 reg == R_I1_num || | |
1829 reg == R_I2_num || | |
1830 reg == R_I3_num || | |
1831 reg == R_I4_num || | |
1832 reg == R_I5_num ) return true; | |
1833 #ifdef _LP64 | |
1834 // 64-bit builds can pass 64-bit pointers and longs in | |
1835 // the high I registers | |
1836 if( reg == R_I0H_num || | |
1837 reg == R_I1H_num || | |
1838 reg == R_I2H_num || | |
1839 reg == R_I3H_num || | |
1840 reg == R_I4H_num || | |
1841 reg == R_I5H_num ) return true; | |
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1842 |
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1843 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { |
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1844 return true; |
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1845 } |
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1846 |
0 | 1847 #else |
1848 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. | |
1849 // Longs cannot be passed in O regs, because O regs become I regs | |
1850 // after a 'save' and I regs get their high bits chopped off on | |
1851 // interrupt. | |
1852 if( reg == R_G1H_num || reg == R_G1_num ) return true; | |
1853 if( reg == R_G4H_num || reg == R_G4_num ) return true; | |
1854 #endif | |
1855 // A few float args in registers | |
1856 if( reg >= R_F0_num && reg <= R_F7_num ) return true; | |
1857 | |
1858 return false; | |
1859 } | |
1860 | |
1861 bool Matcher::is_spillable_arg( int reg ) { | |
1862 return can_be_java_arg(reg); | |
1863 } | |
1864 | |
1865 // Register for DIVI projection of divmodI | |
1866 RegMask Matcher::divI_proj_mask() { | |
1867 ShouldNotReachHere(); | |
1868 return RegMask(); | |
1869 } | |
1870 | |
1871 // Register for MODI projection of divmodI | |
1872 RegMask Matcher::modI_proj_mask() { | |
1873 ShouldNotReachHere(); | |
1874 return RegMask(); | |
1875 } | |
1876 | |
1877 // Register for DIVL projection of divmodL | |
1878 RegMask Matcher::divL_proj_mask() { | |
1879 ShouldNotReachHere(); | |
1880 return RegMask(); | |
1881 } | |
1882 | |
1883 // Register for MODL projection of divmodL | |
1884 RegMask Matcher::modL_proj_mask() { | |
1885 ShouldNotReachHere(); | |
1886 return RegMask(); | |
1887 } | |
1888 | |
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1889 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
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1890 return RegMask(); |
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1891 } |
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1892 |
0 | 1893 %} |
1894 | |
1895 | |
1896 // The intptr_t operand types, defined by textual substitution. | |
1897 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) | |
1898 #ifdef _LP64 | |
824 | 1899 #define immX immL |
1900 #define immX13 immL13 | |
1901 #define immX13m7 immL13m7 | |
1902 #define iRegX iRegL | |
1903 #define g1RegX g1RegL | |
0 | 1904 #else |
824 | 1905 #define immX immI |
1906 #define immX13 immI13 | |
1907 #define immX13m7 immI13m7 | |
1908 #define iRegX iRegI | |
1909 #define g1RegX g1RegI | |
0 | 1910 #endif |
1911 | |
1912 //----------ENCODING BLOCK----------------------------------------------------- | |
1913 // This block specifies the encoding classes used by the compiler to output | |
1914 // byte streams. Encoding classes are parameterized macros used by | |
1915 // Machine Instruction Nodes in order to generate the bit encoding of the | |
1916 // instruction. Operands specify their base encoding interface with the | |
1917 // interface keyword. There are currently supported four interfaces, | |
1918 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an | |
1919 // operand to generate a function which returns its register number when | |
1920 // queried. CONST_INTER causes an operand to generate a function which | |
1921 // returns the value of the constant when queried. MEMORY_INTER causes an | |
1922 // operand to generate four functions which return the Base Register, the | |
1923 // Index Register, the Scale Value, and the Offset Value of the operand when | |
1924 // queried. COND_INTER causes an operand to generate six functions which | |
1925 // return the encoding code (ie - encoding bits for the instruction) | |
1926 // associated with each basic boolean condition for a conditional instruction. | |
1927 // | |
1928 // Instructions specify two basic values for encoding. Again, a function | |
1929 // is available to check if the constant displacement is an oop. They use the | |
1930 // ins_encode keyword to specify their encoding classes (which must be | |
1931 // a sequence of enc_class names, and their parameters, specified in | |
1932 // the encoding block), and they use the | |
1933 // opcode keyword to specify, in order, their primary, secondary, and | |
1934 // tertiary opcode. Only the opcode sections which a particular instruction | |
1935 // needs for encoding need to be specified. | |
1936 encode %{ | |
1937 enc_class enc_untested %{ | |
1938 #ifdef ASSERT | |
1939 MacroAssembler _masm(&cbuf); | |
1940 __ untested("encoding"); | |
1941 #endif | |
1942 %} | |
1943 | |
1944 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ | |
1945 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, | |
1946 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); | |
1947 %} | |
1948 | |
415
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1949 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ |
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1950 emit_form3_mem_reg(cbuf, this, $primary, -1, |
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1951 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); |
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1952 %} |
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1953 |
0 | 1954 enc_class form3_mem_reg_little( memory mem, iRegI dst) %{ |
415
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1955 emit_form3_mem_reg_asi(cbuf, this, $primary, -1, |
0 | 1956 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE); |
1957 %} | |
1958 | |
1959 enc_class form3_mem_prefetch_read( memory mem ) %{ | |
415
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1960 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 1961 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); |
1962 %} | |
1963 | |
1964 enc_class form3_mem_prefetch_write( memory mem ) %{ | |
415
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1965 emit_form3_mem_reg(cbuf, this, $primary, -1, |
0 | 1966 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); |
1967 %} | |
1968 | |
1969 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ | |
1970 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
1971 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
1972 guarantee($mem$$index == R_G0_enc, "double index?"); | |
415
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1973 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); |
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1974 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); |
0 | 1975 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); |
1976 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); | |
1977 %} | |
1978 | |
1979 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ | |
1980 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); | |
1981 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); | |
1982 guarantee($mem$$index == R_G0_enc, "double index?"); | |
1983 // Load long with 2 instructions | |
415
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1984 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); |
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1985 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); |
0 | 1986 %} |
1987 | |
1988 //%%% form3_mem_plus_4_reg is a hack--get rid of it | |
1989 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ | |
1990 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); | |
415
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1991 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); |
0 | 1992 %} |
1993 | |
1994 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ | |
1995 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
1996 if( $rs2$$reg != $rd$$reg ) | |
1997 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); | |
1998 %} | |
1999 | |
2000 // Target lo half of long | |
2001 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ | |
2002 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2003 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) | |
2004 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); | |
2005 %} | |
2006 | |
2007 // Source lo half of long | |
2008 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ | |
2009 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2010 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) | |
2011 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); | |
2012 %} | |
2013 | |
2014 // Target hi half of long | |
2015 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ | |
2016 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); | |
2017 %} | |
2018 | |
2019 // Source lo half of long, and leave it sign extended. | |
2020 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ | |
2021 // Sign extend low half | |
2022 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); | |
2023 %} | |
2024 | |
2025 // Source hi half of long, and leave it sign extended. | |
2026 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ | |
2027 // Shift high half to low half | |
2028 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); | |
2029 %} | |
2030 | |
2031 // Source hi half of long | |
2032 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ | |
2033 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
2034 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) | |
2035 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); | |
2036 %} | |
2037 | |
2038 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ | |
2039 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); | |
2040 %} | |
2041 | |
2042 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ | |
2043 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); | |
2044 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); | |
2045 %} | |
2046 | |
2047 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ | |
2048 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); | |
2049 // clear if nothing else is happening | |
2050 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); | |
2051 // blt,a,pn done | |
2052 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); | |
2053 // mov dst,-1 in delay slot | |
2054 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2055 %} | |
2056 | |
2057 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ | |
2058 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); | |
2059 %} | |
2060 | |
2061 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ | |
2062 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); | |
2063 %} | |
2064 | |
2065 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ | |
2066 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); | |
2067 %} | |
2068 | |
2069 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ | |
2070 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); | |
2071 %} | |
2072 | |
2073 enc_class move_return_pc_to_o1() %{ | |
2074 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); | |
2075 %} | |
2076 | |
2077 #ifdef _LP64 | |
2078 /* %%% merge with enc_to_bool */ | |
2079 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ | |
2080 MacroAssembler _masm(&cbuf); | |
2081 | |
2082 Register src_reg = reg_to_register_object($src$$reg); | |
2083 Register dst_reg = reg_to_register_object($dst$$reg); | |
2084 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); | |
2085 %} | |
2086 #endif | |
2087 | |
2088 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ | |
2089 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) | |
2090 MacroAssembler _masm(&cbuf); | |
2091 | |
2092 Register p_reg = reg_to_register_object($p$$reg); | |
2093 Register q_reg = reg_to_register_object($q$$reg); | |
2094 Register y_reg = reg_to_register_object($y$$reg); | |
2095 Register tmp_reg = reg_to_register_object($tmp$$reg); | |
2096 | |
2097 __ subcc( p_reg, q_reg, p_reg ); | |
2098 __ add ( p_reg, y_reg, tmp_reg ); | |
2099 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); | |
2100 %} | |
2101 | |
2102 enc_class form_d2i_helper(regD src, regF dst) %{ | |
2103 // fcmp %fcc0,$src,$src | |
2104 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2105 // branch %fcc0 not-nan, predict taken | |
2106 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2107 // fdtoi $src,$dst | |
2108 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); | |
2109 // fitos $dst,$dst (if nan) | |
2110 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2111 // clear $dst (if nan) | |
2112 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2113 // carry on here... | |
2114 %} | |
2115 | |
2116 enc_class form_d2l_helper(regD src, regD dst) %{ | |
2117 // fcmp %fcc0,$src,$src check for NAN | |
2118 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); | |
2119 // branch %fcc0 not-nan, predict taken | |
2120 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2121 // fdtox $src,$dst convert in delay slot | |
2122 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); | |
2123 // fxtod $dst,$dst (if nan) | |
2124 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2125 // clear $dst (if nan) | |
2126 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2127 // carry on here... | |
2128 %} | |
2129 | |
2130 enc_class form_f2i_helper(regF src, regF dst) %{ | |
2131 // fcmps %fcc0,$src,$src | |
2132 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2133 // branch %fcc0 not-nan, predict taken | |
2134 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2135 // fstoi $src,$dst | |
2136 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); | |
2137 // fitos $dst,$dst (if nan) | |
2138 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); | |
2139 // clear $dst (if nan) | |
2140 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); | |
2141 // carry on here... | |
2142 %} | |
2143 | |
2144 enc_class form_f2l_helper(regF src, regD dst) %{ | |
2145 // fcmps %fcc0,$src,$src | |
2146 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); | |
2147 // branch %fcc0 not-nan, predict taken | |
2148 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); | |
2149 // fstox $src,$dst | |
2150 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); | |
2151 // fxtod $dst,$dst (if nan) | |
2152 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); | |
2153 // clear $dst (if nan) | |
2154 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); | |
2155 // carry on here... | |
2156 %} | |
2157 | |
2158 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2159 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2160 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2161 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2162 | |
2163 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2164 | |
2165 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} | |
2166 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} | |
2167 | |
2168 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ | |
2169 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2170 %} | |
2171 | |
2172 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ | |
2173 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2174 %} | |
2175 | |
2176 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ | |
2177 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2178 %} | |
2179 | |
2180 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ | |
2181 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); | |
2182 %} | |
2183 | |
2184 enc_class form3_convI2F(regF rs2, regF rd) %{ | |
2185 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); | |
2186 %} | |
2187 | |
2188 // Encloding class for traceable jumps | |
2189 enc_class form_jmpl(g3RegP dest) %{ | |
2190 emit_jmpl(cbuf, $dest$$reg); | |
2191 %} | |
2192 | |
2193 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ | |
2194 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); | |
2195 %} | |
2196 | |
2197 enc_class form2_nop() %{ | |
2198 emit_nop(cbuf); | |
2199 %} | |
2200 | |
2201 enc_class form2_illtrap() %{ | |
2202 emit_illtrap(cbuf); | |
2203 %} | |
2204 | |
2205 | |
2206 // Compare longs and convert into -1, 0, 1. | |
2207 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ | |
2208 // CMP $src1,$src2 | |
2209 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); | |
2210 // blt,a,pn done | |
2211 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); | |
2212 // mov dst,-1 in delay slot | |
2213 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); | |
2214 // bgt,a,pn done | |
2215 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); | |
2216 // mov dst,1 in delay slot | |
2217 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); | |
2218 // CLR $dst | |
2219 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); | |
2220 %} | |
2221 | |
2222 enc_class enc_PartialSubtypeCheck() %{ | |
2223 MacroAssembler _masm(&cbuf); | |
2224 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); | |
2225 __ delayed()->nop(); | |
2226 %} | |
2227 | |
2228 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ | |
2229 MacroAssembler _masm(&cbuf); | |
2230 Label &L = *($labl$$label); | |
2231 Assembler::Predict predict_taken = | |
2232 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2233 | |
2234 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); | |
2235 __ delayed()->nop(); | |
2236 %} | |
2237 | |
2238 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ | |
2239 MacroAssembler _masm(&cbuf); | |
2240 Label &L = *($labl$$label); | |
2241 Assembler::Predict predict_taken = | |
2242 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2243 | |
2244 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); | |
2245 __ delayed()->nop(); | |
2246 %} | |
2247 | |
2248 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ | |
2249 MacroAssembler _masm(&cbuf); | |
2250 Label &L = *($labl$$label); | |
2251 Assembler::Predict predict_taken = | |
2252 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2253 | |
2254 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); | |
2255 __ delayed()->nop(); | |
2256 %} | |
2257 | |
2258 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ | |
2259 MacroAssembler _masm(&cbuf); | |
2260 Label &L = *($labl$$label); | |
2261 Assembler::Predict predict_taken = | |
2262 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2263 | |
2264 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); | |
2265 __ delayed()->nop(); | |
2266 %} | |
2267 | |
2268 enc_class jump_enc( iRegX switch_val, o7RegI table) %{ | |
2269 MacroAssembler _masm(&cbuf); | |
2270 | |
2271 Register switch_reg = as_Register($switch_val$$reg); | |
2272 Register table_reg = O7; | |
2273 | |
2274 address table_base = __ address_table_constant(_index2label); | |
2275 RelocationHolder rspec = internal_word_Relocation::spec(table_base); | |
2276 | |
727 | 2277 // Move table address into a register. |
2278 __ set(table_base, table_reg, rspec); | |
0 | 2279 |
2280 // Jump to base address + switch value | |
2281 __ ld_ptr(table_reg, switch_reg, table_reg); | |
2282 __ jmp(table_reg, G0); | |
2283 __ delayed()->nop(); | |
2284 | |
2285 %} | |
2286 | |
2287 enc_class enc_ba( Label labl ) %{ | |
2288 MacroAssembler _masm(&cbuf); | |
2289 Label &L = *($labl$$label); | |
2290 __ ba(false, L); | |
2291 __ delayed()->nop(); | |
2292 %} | |
2293 | |
2294 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ | |
2295 MacroAssembler _masm(&cbuf); | |
2296 Label &L = *$labl$$label; | |
2297 Assembler::Predict predict_taken = | |
2298 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; | |
2299 | |
2300 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); | |
2301 __ delayed()->nop(); | |
2302 %} | |
2303 | |
2304 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ | |
2305 int op = (Assembler::arith_op << 30) | | |
2306 ($dst$$reg << 25) | | |
2307 (Assembler::movcc_op3 << 19) | | |
2308 (1 << 18) | // cc2 bit for 'icc' | |
2309 ($cmp$$cmpcode << 14) | | |
2310 (0 << 13) | // select register move | |
2311 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' | |
2312 ($src$$reg << 0); | |
2313 *((int*)(cbuf.code_end())) = op; | |
2314 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2315 %} | |
2316 | |
2317 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ | |
2318 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2319 int op = (Assembler::arith_op << 30) | | |
2320 ($dst$$reg << 25) | | |
2321 (Assembler::movcc_op3 << 19) | | |
2322 (1 << 18) | // cc2 bit for 'icc' | |
2323 ($cmp$$cmpcode << 14) | | |
2324 (1 << 13) | // select immediate move | |
2325 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' | |
2326 (simm11 << 0); | |
2327 *((int*)(cbuf.code_end())) = op; | |
2328 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2329 %} | |
2330 | |
2331 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ | |
2332 int op = (Assembler::arith_op << 30) | | |
2333 ($dst$$reg << 25) | | |
2334 (Assembler::movcc_op3 << 19) | | |
2335 (0 << 18) | // cc2 bit for 'fccX' | |
2336 ($cmp$$cmpcode << 14) | | |
2337 (0 << 13) | // select register move | |
2338 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2339 ($src$$reg << 0); | |
2340 *((int*)(cbuf.code_end())) = op; | |
2341 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2342 %} | |
2343 | |
2344 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ | |
2345 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits | |
2346 int op = (Assembler::arith_op << 30) | | |
2347 ($dst$$reg << 25) | | |
2348 (Assembler::movcc_op3 << 19) | | |
2349 (0 << 18) | // cc2 bit for 'fccX' | |
2350 ($cmp$$cmpcode << 14) | | |
2351 (1 << 13) | // select immediate move | |
2352 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 | |
2353 (simm11 << 0); | |
2354 *((int*)(cbuf.code_end())) = op; | |
2355 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2356 %} | |
2357 | |
2358 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ | |
2359 int op = (Assembler::arith_op << 30) | | |
2360 ($dst$$reg << 25) | | |
2361 (Assembler::fpop2_op3 << 19) | | |
2362 (0 << 18) | | |
2363 ($cmp$$cmpcode << 14) | | |
2364 (1 << 13) | // select register move | |
2365 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' | |
2366 ($primary << 5) | // select single, double or quad | |
2367 ($src$$reg << 0); | |
2368 *((int*)(cbuf.code_end())) = op; | |
2369 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2370 %} | |
2371 | |
2372 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ | |
2373 int op = (Assembler::arith_op << 30) | | |
2374 ($dst$$reg << 25) | | |
2375 (Assembler::fpop2_op3 << 19) | | |
2376 (0 << 18) | | |
2377 ($cmp$$cmpcode << 14) | | |
2378 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' | |
2379 ($primary << 5) | // select single, double or quad | |
2380 ($src$$reg << 0); | |
2381 *((int*)(cbuf.code_end())) = op; | |
2382 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2383 %} | |
2384 | |
2385 // Used by the MIN/MAX encodings. Same as a CMOV, but | |
2386 // the condition comes from opcode-field instead of an argument. | |
2387 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ | |
2388 int op = (Assembler::arith_op << 30) | | |
2389 ($dst$$reg << 25) | | |
2390 (Assembler::movcc_op3 << 19) | | |
2391 (1 << 18) | // cc2 bit for 'icc' | |
2392 ($primary << 14) | | |
2393 (0 << 13) | // select register move | |
2394 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2395 ($src$$reg << 0); | |
2396 *((int*)(cbuf.code_end())) = op; | |
2397 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2398 %} | |
2399 | |
2400 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ | |
2401 int op = (Assembler::arith_op << 30) | | |
2402 ($dst$$reg << 25) | | |
2403 (Assembler::movcc_op3 << 19) | | |
2404 (6 << 16) | // cc2 bit for 'xcc' | |
2405 ($primary << 14) | | |
2406 (0 << 13) | // select register move | |
2407 (0 << 11) | // cc1, cc0 bits for 'icc' | |
2408 ($src$$reg << 0); | |
2409 *((int*)(cbuf.code_end())) = op; | |
2410 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
2411 %} | |
2412 | |
2413 // Utility encoding for loading a 64 bit Pointer into a register | |
2414 // The 64 bit pointer is stored in the generated code stream | |
2415 enc_class SetPtr( immP src, iRegP rd ) %{ | |
2416 Register dest = reg_to_register_object($rd$$reg); | |
727 | 2417 MacroAssembler _masm(&cbuf); |
0 | 2418 // [RGV] This next line should be generated from ADLC |
2419 if ( _opnds[1]->constant_is_oop() ) { | |
2420 intptr_t val = $src$$constant; | |
2421 __ set_oop_constant((jobject)val, dest); | |
2422 } else { // non-oop pointers, e.g. card mark base, heap top | |
727 | 2423 __ set($src$$constant, dest); |
0 | 2424 } |
2425 %} | |
2426 | |
2427 enc_class Set13( immI13 src, iRegI rd ) %{ | |
2428 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); | |
2429 %} | |
2430 | |
2431 enc_class SetHi22( immI src, iRegI rd ) %{ | |
2432 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); | |
2433 %} | |
2434 | |
2435 enc_class Set32( immI src, iRegI rd ) %{ | |
2436 MacroAssembler _masm(&cbuf); | |
2437 __ set($src$$constant, reg_to_register_object($rd$$reg)); | |
2438 %} | |
2439 | |
2440 enc_class SetNull( iRegI rd ) %{ | |
2441 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 ); | |
2442 %} | |
2443 | |
2444 enc_class call_epilog %{ | |
2445 if( VerifyStackAtCalls ) { | |
2446 MacroAssembler _masm(&cbuf); | |
2447 int framesize = ra_->C->frame_slots() << LogBytesPerInt; | |
2448 Register temp_reg = G3; | |
2449 __ add(SP, framesize, temp_reg); | |
2450 __ cmp(temp_reg, FP); | |
2451 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); | |
2452 } | |
2453 %} | |
2454 | |
2455 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value | |
2456 // to G1 so the register allocator will not have to deal with the misaligned register | |
2457 // pair. | |
2458 enc_class adjust_long_from_native_call %{ | |
2459 #ifndef _LP64 | |
2460 if (returns_long()) { | |
2461 // sllx O0,32,O0 | |
2462 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); | |
2463 // srl O1,0,O1 | |
2464 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); | |
2465 // or O0,O1,G1 | |
2466 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); | |
2467 } | |
2468 #endif | |
2469 %} | |
2470 | |
2471 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime | |
2472 // CALL directly to the runtime | |
2473 // The user of this is responsible for ensuring that R_L7 is empty (killed). | |
2474 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, | |
2475 /*preserve_g2=*/true, /*force far call*/true); | |
2476 %} | |
2477 | |
2478 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL | |
2479 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2480 // who we intended to call. | |
2481 if ( !_method ) { | |
2482 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); | |
2483 } else if (_optimized_virtual) { | |
2484 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); | |
2485 } else { | |
2486 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); | |
2487 } | |
2488 if( _method ) { // Emit stub for static call | |
2489 emit_java_to_interp(cbuf); | |
2490 } | |
2491 %} | |
2492 | |
2493 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL | |
2494 MacroAssembler _masm(&cbuf); | |
2495 __ set_inst_mark(); | |
2496 int vtable_index = this->_vtable_index; | |
2497 // MachCallDynamicJavaNode::ret_addr_offset uses this same test | |
2498 if (vtable_index < 0) { | |
2499 // must be invalid_vtable_index, not nonvirtual_vtable_index | |
2500 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); | |
2501 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2502 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); | |
2503 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); | |
2504 // !!!!! | |
2505 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info | |
2506 // emit_call_dynamic_prologue( cbuf ); | |
2507 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); | |
2508 | |
2509 address virtual_call_oop_addr = __ inst_mark(); | |
2510 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine | |
2511 // who we intended to call. | |
2512 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); | |
2513 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); | |
2514 } else { | |
2515 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); | |
2516 // Just go thru the vtable | |
2517 // get receiver klass (receiver already checked for non-null) | |
2518 // If we end up going thru a c2i adapter interpreter expects method in G5 | |
2519 int off = __ offset(); | |
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2520 __ load_klass(O0, G3_scratch); |
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2521 int klass_load_size; |
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2522 if (UseCompressedOops) { |
642
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2523 assert(Universe::heap() != NULL, "java heap should be initialized"); |
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2524 if (Universe::narrow_oop_base() == NULL) |
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2525 klass_load_size = 2*BytesPerInstWord; |
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2526 else |
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2527 klass_load_size = 3*BytesPerInstWord; |
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2528 } else { |
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2529 klass_load_size = 1*BytesPerInstWord; |
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2530 } |
0 | 2531 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); |
2532 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); | |
2533 if( __ is_simm13(v_off) ) { | |
2534 __ ld_ptr(G3, v_off, G5_method); | |
2535 } else { | |
2536 // Generate 2 instructions | |
2537 __ Assembler::sethi(v_off & ~0x3ff, G5_method); | |
2538 __ or3(G5_method, v_off & 0x3ff, G5_method); | |
2539 // ld_ptr, set_hi, set | |
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2540 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, |
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2541 "Unexpected instruction size(s)"); |
0 | 2542 __ ld_ptr(G3, G5_method, G5_method); |
2543 } | |
2544 // NOTE: for vtable dispatches, the vtable entry will never be null. | |
2545 // However it may very well end up in handle_wrong_method if the | |
2546 // method is abstract for the particular class. | |
2547 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); | |
2548 // jump to target (either compiled code or c2iadapter) | |
2549 __ jmpl(G3_scratch, G0, O7); | |
2550 __ delayed()->nop(); | |
2551 } | |
2552 %} | |
2553 | |
2554 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL | |
2555 MacroAssembler _masm(&cbuf); | |
2556 | |
2557 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); | |
2558 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because | |
2559 // we might be calling a C2I adapter which needs it. | |
2560 | |
2561 assert(temp_reg != G5_ic_reg, "conflicting registers"); | |
2562 // Load nmethod | |
2563 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); | |
2564 | |
2565 // CALL to compiled java, indirect the contents of G3 | |
2566 __ set_inst_mark(); | |
2567 __ callr(temp_reg, G0); | |
2568 __ delayed()->nop(); | |
2569 %} | |
2570 | |
2571 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ | |
2572 MacroAssembler _masm(&cbuf); | |
2573 Register Rdividend = reg_to_register_object($src1$$reg); | |
2574 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2575 Register Rresult = reg_to_register_object($dst$$reg); | |
2576 | |
2577 __ sra(Rdivisor, 0, Rdivisor); | |
2578 __ sra(Rdividend, 0, Rdividend); | |
2579 __ sdivx(Rdividend, Rdivisor, Rresult); | |
2580 %} | |
2581 | |
2582 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ | |
2583 MacroAssembler _masm(&cbuf); | |
2584 | |
2585 Register Rdividend = reg_to_register_object($src1$$reg); | |
2586 int divisor = $imm$$constant; | |
2587 Register Rresult = reg_to_register_object($dst$$reg); | |
2588 | |
2589 __ sra(Rdividend, 0, Rdividend); | |
2590 __ sdivx(Rdividend, divisor, Rresult); | |
2591 %} | |
2592 | |
2593 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ | |
2594 MacroAssembler _masm(&cbuf); | |
2595 Register Rsrc1 = reg_to_register_object($src1$$reg); | |
2596 Register Rsrc2 = reg_to_register_object($src2$$reg); | |
2597 Register Rdst = reg_to_register_object($dst$$reg); | |
2598 | |
2599 __ sra( Rsrc1, 0, Rsrc1 ); | |
2600 __ sra( Rsrc2, 0, Rsrc2 ); | |
2601 __ mulx( Rsrc1, Rsrc2, Rdst ); | |
2602 __ srlx( Rdst, 32, Rdst ); | |
2603 %} | |
2604 | |
2605 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ | |
2606 MacroAssembler _masm(&cbuf); | |
2607 Register Rdividend = reg_to_register_object($src1$$reg); | |
2608 Register Rdivisor = reg_to_register_object($src2$$reg); | |
2609 Register Rresult = reg_to_register_object($dst$$reg); | |
2610 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2611 | |
2612 assert(Rdividend != Rscratch, ""); | |
2613 assert(Rdivisor != Rscratch, ""); | |
2614 | |
2615 __ sra(Rdividend, 0, Rdividend); | |
2616 __ sra(Rdivisor, 0, Rdivisor); | |
2617 __ sdivx(Rdividend, Rdivisor, Rscratch); | |
2618 __ mulx(Rscratch, Rdivisor, Rscratch); | |
2619 __ sub(Rdividend, Rscratch, Rresult); | |
2620 %} | |
2621 | |
2622 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ | |
2623 MacroAssembler _masm(&cbuf); | |
2624 | |
2625 Register Rdividend = reg_to_register_object($src1$$reg); | |
2626 int divisor = $imm$$constant; | |
2627 Register Rresult = reg_to_register_object($dst$$reg); | |
2628 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2629 | |
2630 assert(Rdividend != Rscratch, ""); | |
2631 | |
2632 __ sra(Rdividend, 0, Rdividend); | |
2633 __ sdivx(Rdividend, divisor, Rscratch); | |
2634 __ mulx(Rscratch, divisor, Rscratch); | |
2635 __ sub(Rdividend, Rscratch, Rresult); | |
2636 %} | |
2637 | |
2638 enc_class fabss (sflt_reg dst, sflt_reg src) %{ | |
2639 MacroAssembler _masm(&cbuf); | |
2640 | |
2641 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2642 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2643 | |
2644 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); | |
2645 %} | |
2646 | |
2647 enc_class fabsd (dflt_reg dst, dflt_reg src) %{ | |
2648 MacroAssembler _masm(&cbuf); | |
2649 | |
2650 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2651 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2652 | |
2653 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); | |
2654 %} | |
2655 | |
2656 enc_class fnegd (dflt_reg dst, dflt_reg src) %{ | |
2657 MacroAssembler _masm(&cbuf); | |
2658 | |
2659 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2660 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2661 | |
2662 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); | |
2663 %} | |
2664 | |
2665 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ | |
2666 MacroAssembler _masm(&cbuf); | |
2667 | |
2668 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2669 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2670 | |
2671 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); | |
2672 %} | |
2673 | |
2674 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ | |
2675 MacroAssembler _masm(&cbuf); | |
2676 | |
2677 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2678 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2679 | |
2680 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); | |
2681 %} | |
2682 | |
2683 enc_class fmovs (dflt_reg dst, dflt_reg src) %{ | |
2684 MacroAssembler _masm(&cbuf); | |
2685 | |
2686 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); | |
2687 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); | |
2688 | |
2689 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); | |
2690 %} | |
2691 | |
2692 enc_class fmovd (dflt_reg dst, dflt_reg src) %{ | |
2693 MacroAssembler _masm(&cbuf); | |
2694 | |
2695 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); | |
2696 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); | |
2697 | |
2698 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); | |
2699 %} | |
2700 | |
2701 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2702 MacroAssembler _masm(&cbuf); | |
2703 | |
2704 Register Roop = reg_to_register_object($oop$$reg); | |
2705 Register Rbox = reg_to_register_object($box$$reg); | |
2706 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2707 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2708 | |
2709 assert(Roop != Rscratch, ""); | |
2710 assert(Roop != Rmark, ""); | |
2711 assert(Rbox != Rscratch, ""); | |
2712 assert(Rbox != Rmark, ""); | |
2713 | |
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2714 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2715 %} |
2716 | |
2717 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ | |
2718 MacroAssembler _masm(&cbuf); | |
2719 | |
2720 Register Roop = reg_to_register_object($oop$$reg); | |
2721 Register Rbox = reg_to_register_object($box$$reg); | |
2722 Register Rscratch = reg_to_register_object($scratch$$reg); | |
2723 Register Rmark = reg_to_register_object($scratch2$$reg); | |
2724 | |
2725 assert(Roop != Rscratch, ""); | |
2726 assert(Roop != Rmark, ""); | |
2727 assert(Rbox != Rscratch, ""); | |
2728 assert(Rbox != Rmark, ""); | |
2729 | |
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|
2730 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); |
0 | 2731 %} |
2732 | |
2733 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ | |
2734 MacroAssembler _masm(&cbuf); | |
2735 Register Rmem = reg_to_register_object($mem$$reg); | |
2736 Register Rold = reg_to_register_object($old$$reg); | |
2737 Register Rnew = reg_to_register_object($new$$reg); | |
2738 | |
2739 // casx_under_lock picks 1 of 3 encodings: | |
2740 // For 32-bit pointers you get a 32-bit CAS | |
2741 // For 64-bit pointers you get a 64-bit CASX | |
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2742 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold |
0 | 2743 __ cmp( Rold, Rnew ); |
2744 %} | |
2745 | |
2746 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ | |
2747 Register Rmem = reg_to_register_object($mem$$reg); | |
2748 Register Rold = reg_to_register_object($old$$reg); | |
2749 Register Rnew = reg_to_register_object($new$$reg); | |
2750 | |
2751 MacroAssembler _masm(&cbuf); | |
2752 __ mov(Rnew, O7); | |
2753 __ casx(Rmem, Rold, O7); | |
2754 __ cmp( Rold, O7 ); | |
2755 %} | |
2756 | |
2757 // raw int cas, used for compareAndSwap | |
2758 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ | |
2759 Register Rmem = reg_to_register_object($mem$$reg); | |
2760 Register Rold = reg_to_register_object($old$$reg); | |
2761 Register Rnew = reg_to_register_object($new$$reg); | |
2762 | |
2763 MacroAssembler _masm(&cbuf); | |
2764 __ mov(Rnew, O7); | |
2765 __ cas(Rmem, Rold, O7); | |
2766 __ cmp( Rold, O7 ); | |
2767 %} | |
2768 | |
2769 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ | |
2770 Register Rres = reg_to_register_object($res$$reg); | |
2771 | |
2772 MacroAssembler _masm(&cbuf); | |
2773 __ mov(1, Rres); | |
2774 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); | |
2775 %} | |
2776 | |
2777 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ | |
2778 Register Rres = reg_to_register_object($res$$reg); | |
2779 | |
2780 MacroAssembler _masm(&cbuf); | |
2781 __ mov(1, Rres); | |
2782 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); | |
2783 %} | |
2784 | |
2785 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ | |
2786 MacroAssembler _masm(&cbuf); | |
2787 Register Rdst = reg_to_register_object($dst$$reg); | |
2788 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) | |
2789 : reg_to_DoubleFloatRegister_object($src1$$reg); | |
2790 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) | |
2791 : reg_to_DoubleFloatRegister_object($src2$$reg); | |
2792 | |
2793 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) | |
2794 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); | |
2795 %} | |
2796 | |
2797 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate | |
2798 MacroAssembler _masm(&cbuf); | |
2799 Register dest = reg_to_register_object($dst$$reg); | |
2800 Register temp = reg_to_register_object($tmp$$reg); | |
2801 __ set64( $src$$constant, dest, temp ); | |
2802 %} | |
2803 | |
2804 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ | |
2805 // Load a constant replicated "count" times with width "width" | |
2806 int bit_width = $width$$constant * 8; | |
2807 jlong elt_val = $src$$constant; | |
2808 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits | |
2809 jlong val = elt_val; | |
2810 for (int i = 0; i < $count$$constant - 1; i++) { | |
2811 val <<= bit_width; | |
2812 val |= elt_val; | |
2813 } | |
2814 jdouble dval = *(jdouble*)&val; // coerce to double type | |
727 | 2815 MacroAssembler _masm(&cbuf); |
2816 address double_address = __ double_constant(dval); | |
0 | 2817 RelocationHolder rspec = internal_word_Relocation::spec(double_address); |
727 | 2818 AddressLiteral addrlit(double_address, rspec); |
2819 | |
2820 __ sethi(addrlit, $tmp$$Register); | |
732
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2821 // XXX This is a quick fix for 6833573. |
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|
2822 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); |
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2823 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); |
0 | 2824 %} |
2825 | |
2826 // Compiler ensures base is doubleword aligned and cnt is count of doublewords | |
2827 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ | |
2828 MacroAssembler _masm(&cbuf); | |
2829 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); | |
2830 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); | |
2831 Register base_pointer_arg = reg_to_register_object($base$$reg); | |
2832 | |
2833 Label loop; | |
2834 __ mov(nof_bytes_arg, nof_bytes_tmp); | |
2835 | |
2836 // Loop and clear, walking backwards through the array. | |
2837 // nof_bytes_tmp (if >0) is always the number of bytes to zero | |
2838 __ bind(loop); | |
2839 __ deccc(nof_bytes_tmp, 8); | |
2840 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); | |
2841 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); | |
2842 // %%%% this mini-loop must not cross a cache boundary! | |
2843 %} | |
2844 | |
2845 | |
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|
2846 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ |
0 | 2847 Label Ldone, Lloop; |
2848 MacroAssembler _masm(&cbuf); | |
2849 | |
2850 Register str1_reg = reg_to_register_object($str1$$reg); | |
2851 Register str2_reg = reg_to_register_object($str2$$reg); | |
986
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2852 Register cnt1_reg = reg_to_register_object($cnt1$$reg); |
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2853 Register cnt2_reg = reg_to_register_object($cnt2$$reg); |
0 | 2854 Register result_reg = reg_to_register_object($result$$reg); |
2855 | |
986
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|
2856 assert(result_reg != str1_reg && |
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|
2857 result_reg != str2_reg && |
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2858 result_reg != cnt1_reg && |
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|
2859 result_reg != cnt2_reg , |
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2860 "need different registers"); |
0 | 2861 |
2862 // Compute the minimum of the string lengths(str1_reg) and the | |
2863 // difference of the string lengths (stack) | |
2864 | |
2865 // See if the lengths are different, and calculate min in str1_reg. | |
2866 // Stash diff in O7 in case we need it for a tie-breaker. | |
2867 Label Lskip; | |
986
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2868 __ subcc(cnt1_reg, cnt2_reg, O7); |
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2869 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2870 __ br(Assembler::greater, true, Assembler::pt, Lskip); |
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2871 // cnt2 is shorter, so use its count: |
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2872 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit |
0 | 2873 __ bind(Lskip); |
2874 | |
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2875 // reallocate cnt1_reg, cnt2_reg, result_reg |
0 | 2876 // Note: limit_reg holds the string length pre-scaled by 2 |
986
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2877 Register limit_reg = cnt1_reg; |
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2878 Register chr2_reg = cnt2_reg; |
0 | 2879 Register chr1_reg = result_reg; |
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2880 // str{12} are the base pointers |
0 | 2881 |
2882 // Is the minimum length zero? | |
2883 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity | |
2884 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2885 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2886 | |
2887 // Load first characters | |
986
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2888 __ lduh(str1_reg, 0, chr1_reg); |
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2889 __ lduh(str2_reg, 0, chr2_reg); |
0 | 2890 |
2891 // Compare first characters | |
2892 __ subcc(chr1_reg, chr2_reg, chr1_reg); | |
2893 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2894 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2895 __ delayed()->nop(); | |
2896 | |
2897 { | |
2898 // Check after comparing first character to see if strings are equivalent | |
2899 Label LSkip2; | |
2900 // Check if the strings start at same location | |
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2901 __ cmp(str1_reg, str2_reg); |
0 | 2902 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); |
2903 __ delayed()->nop(); | |
2904 | |
2905 // Check if the length difference is zero (in O7) | |
2906 __ cmp(G0, O7); | |
2907 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2908 __ delayed()->mov(G0, result_reg); // result is zero | |
2909 | |
2910 // Strings might not be equal | |
2911 __ bind(LSkip2); | |
2912 } | |
2913 | |
2914 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); | |
2915 __ br(Assembler::equal, true, Assembler::pn, Ldone); | |
2916 __ delayed()->mov(O7, result_reg); // result is difference in lengths | |
2917 | |
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2918 // Shift str1_reg and str2_reg to the end of the arrays, negate limit |
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2919 __ add(str1_reg, limit_reg, str1_reg); |
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2920 __ add(str2_reg, limit_reg, str2_reg); |
0 | 2921 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) |
2922 | |
2923 // Compare the rest of the characters | |
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|
2924 __ lduh(str1_reg, limit_reg, chr1_reg); |
0 | 2925 __ bind(Lloop); |
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|
2926 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
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2927 __ lduh(str2_reg, limit_reg, chr2_reg); |
0 | 2928 __ subcc(chr1_reg, chr2_reg, chr1_reg); |
2929 __ br(Assembler::notZero, false, Assembler::pt, Ldone); | |
2930 assert(chr1_reg == result_reg, "result must be pre-placed"); | |
2931 __ delayed()->inccc(limit_reg, sizeof(jchar)); | |
2932 // annul LDUH if branch is not taken to prevent access past end of string | |
2933 __ br(Assembler::notZero, true, Assembler::pt, Lloop); | |
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|
2934 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
0 | 2935 |
2936 // If strings are equal up to min length, return the length difference. | |
2937 __ mov(O7, result_reg); | |
2938 | |
2939 // Otherwise, return the difference between the first mismatched chars. | |
2940 __ bind(Ldone); | |
2941 %} | |
2942 | |
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2943 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ |
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2944 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; |
681 | 2945 MacroAssembler _masm(&cbuf); |
2946 | |
2947 Register str1_reg = reg_to_register_object($str1$$reg); | |
2948 Register str2_reg = reg_to_register_object($str2$$reg); | |
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2949 Register cnt_reg = reg_to_register_object($cnt$$reg); |
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2950 Register tmp1_reg = O7; |
681 | 2951 Register result_reg = reg_to_register_object($result$$reg); |
2952 | |
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2953 assert(result_reg != str1_reg && |
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2954 result_reg != str2_reg && |
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2955 result_reg != cnt_reg && |
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2956 result_reg != tmp1_reg , |
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2957 "need different registers"); |
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2958 |
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2959 __ cmp(str1_reg, str2_reg); //same char[] ? |
681 | 2960 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
2961 __ delayed()->add(G0, 1, result_reg); | |
2962 | |
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2963 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); |
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2964 __ delayed()->add(G0, 1, result_reg); // count == 0 |
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2965 |
681 | 2966 //rename registers |
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2967 Register limit_reg = cnt_reg; |
681 | 2968 Register chr1_reg = result_reg; |
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2969 Register chr2_reg = tmp1_reg; |
681 | 2970 |
2971 //check for alignment and position the pointers to the ends | |
986
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2972 __ or3(str1_reg, str2_reg, chr1_reg); |
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2973 __ andcc(chr1_reg, 0x3, chr1_reg); |
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2974 // notZero means at least one not 4-byte aligned. |
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2975 // We could optimize the case when both arrays are not aligned |
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2976 // but it is not frequent case and it requires additional checks. |
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2977 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare |
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2978 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count |
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2979 |
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2980 // Compare char[] arrays aligned to 4 bytes. |
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2981 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, |
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2982 chr1_reg, chr2_reg, Ldone); |
681 | 2983 __ ba(false,Ldone); |
2984 __ delayed()->add(G0, 1, result_reg); | |
2985 | |
986
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2986 // char by char compare |
681 | 2987 __ bind(Lchar); |
986
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2988 __ add(str1_reg, limit_reg, str1_reg); |
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2989 __ add(str2_reg, limit_reg, str2_reg); |
681 | 2990 __ neg(limit_reg); //negate count |
2991 | |
986
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2992 __ lduh(str1_reg, limit_reg, chr1_reg); |
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2993 // Lchar_loop |
681 | 2994 __ bind(Lchar_loop); |
986
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2995 __ lduh(str2_reg, limit_reg, chr2_reg); |
681 | 2996 __ cmp(chr1_reg, chr2_reg); |
2997 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); | |
2998 __ delayed()->mov(G0, result_reg); //not equal | |
2999 __ inccc(limit_reg, sizeof(jchar)); | |
3000 // annul LDUH if branch is not taken to prevent access past end of string | |
986
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3001 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); |
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3002 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted |
681 | 3003 |
3004 __ add(G0, 1, result_reg); //equal | |
3005 | |
3006 __ bind(Ldone); | |
3007 %} | |
3008 | |
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3009 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ |
681 | 3010 Label Lvector, Ldone, Lloop; |
3011 MacroAssembler _masm(&cbuf); | |
3012 | |
3013 Register ary1_reg = reg_to_register_object($ary1$$reg); | |
3014 Register ary2_reg = reg_to_register_object($ary2$$reg); | |
3015 Register tmp1_reg = reg_to_register_object($tmp1$$reg); | |
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3016 Register tmp2_reg = O7; |
681 | 3017 Register result_reg = reg_to_register_object($result$$reg); |
3018 | |
3019 int length_offset = arrayOopDesc::length_offset_in_bytes(); | |
3020 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); | |
3021 | |
3022 // return true if the same array | |
3023 __ cmp(ary1_reg, ary2_reg); | |
1016 | 3024 __ brx(Assembler::equal, true, Assembler::pn, Ldone); |
681 | 3025 __ delayed()->add(G0, 1, result_reg); // equal |
3026 | |
3027 __ br_null(ary1_reg, true, Assembler::pn, Ldone); | |
3028 __ delayed()->mov(G0, result_reg); // not equal | |
3029 | |
3030 __ br_null(ary2_reg, true, Assembler::pn, Ldone); | |
3031 __ delayed()->mov(G0, result_reg); // not equal | |
3032 | |
3033 //load the lengths of arrays | |
727 | 3034 __ ld(Address(ary1_reg, length_offset), tmp1_reg); |
3035 __ ld(Address(ary2_reg, length_offset), tmp2_reg); | |
681 | 3036 |
3037 // return false if the two arrays are not equal length | |
3038 __ cmp(tmp1_reg, tmp2_reg); | |
3039 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); | |
3040 __ delayed()->mov(G0, result_reg); // not equal | |
3041 | |
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3042 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); |
681 | 3043 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal |
3044 | |
3045 // load array addresses | |
3046 __ add(ary1_reg, base_offset, ary1_reg); | |
3047 __ add(ary2_reg, base_offset, ary2_reg); | |
3048 | |
3049 // renaming registers | |
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3050 Register chr1_reg = result_reg; // for characters in ary1 |
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3051 Register chr2_reg = tmp2_reg; // for characters in ary2 |
681 | 3052 Register limit_reg = tmp1_reg; // length |
3053 | |
3054 // set byte count | |
3055 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); | |
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3056 |
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3057 // Compare char[] arrays aligned to 4 bytes. |
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3058 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, |
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3059 chr1_reg, chr2_reg, Ldone); |
681 | 3060 __ add(G0, 1, result_reg); // equals |
3061 | |
3062 __ bind(Ldone); | |
3063 %} | |
3064 | |
0 | 3065 enc_class enc_rethrow() %{ |
3066 cbuf.set_inst_mark(); | |
3067 Register temp_reg = G3; | |
727 | 3068 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); |
0 | 3069 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); |
3070 MacroAssembler _masm(&cbuf); | |
3071 #ifdef ASSERT | |
3072 __ save_frame(0); | |
727 | 3073 AddressLiteral last_rethrow_addrlit(&last_rethrow); |
3074 __ sethi(last_rethrow_addrlit, L1); | |
3075 Address addr(L1, last_rethrow_addrlit.low10()); | |
0 | 3076 __ get_pc(L2); |
3077 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to | |
727 | 3078 __ st_ptr(L2, addr); |
0 | 3079 __ restore(); |
3080 #endif | |
727 | 3081 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp |
0 | 3082 __ delayed()->nop(); |
3083 %} | |
3084 | |
3085 enc_class emit_mem_nop() %{ | |
3086 // Generates the instruction LDUXA [o6,g0],#0x82,g0 | |
3087 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
3088 *code = (unsigned int)0xc0839040; | |
3089 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
3090 %} | |
3091 | |
3092 enc_class emit_fadd_nop() %{ | |
3093 // Generates the instruction FMOVS f31,f31 | |
3094 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
3095 *code = (unsigned int)0xbfa0003f; | |
3096 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
3097 %} | |
3098 | |
3099 enc_class emit_br_nop() %{ | |
3100 // Generates the instruction BPN,PN . | |
3101 unsigned int *code = (unsigned int*)cbuf.code_end(); | |
3102 *code = (unsigned int)0x00400000; | |
3103 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord); | |
3104 %} | |
3105 | |
3106 enc_class enc_membar_acquire %{ | |
3107 MacroAssembler _masm(&cbuf); | |
3108 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); | |
3109 %} | |
3110 | |
3111 enc_class enc_membar_release %{ | |
3112 MacroAssembler _masm(&cbuf); | |
3113 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); | |
3114 %} | |
3115 | |
3116 enc_class enc_membar_volatile %{ | |
3117 MacroAssembler _masm(&cbuf); | |
3118 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); | |
3119 %} | |
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3120 |
0 | 3121 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ |
3122 MacroAssembler _masm(&cbuf); | |
3123 Register src_reg = reg_to_register_object($src$$reg); | |
3124 Register dst_reg = reg_to_register_object($dst$$reg); | |
3125 __ sllx(src_reg, 56, dst_reg); | |
3126 __ srlx(dst_reg, 8, O7); | |
3127 __ or3 (dst_reg, O7, dst_reg); | |
3128 __ srlx(dst_reg, 16, O7); | |
3129 __ or3 (dst_reg, O7, dst_reg); | |
3130 __ srlx(dst_reg, 32, O7); | |
3131 __ or3 (dst_reg, O7, dst_reg); | |
3132 %} | |
3133 | |
3134 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ | |
3135 MacroAssembler _masm(&cbuf); | |
3136 Register src_reg = reg_to_register_object($src$$reg); | |
3137 Register dst_reg = reg_to_register_object($dst$$reg); | |
3138 __ sll(src_reg, 24, dst_reg); | |
3139 __ srl(dst_reg, 8, O7); | |
3140 __ or3(dst_reg, O7, dst_reg); | |
3141 __ srl(dst_reg, 16, O7); | |
3142 __ or3(dst_reg, O7, dst_reg); | |
3143 %} | |
3144 | |
3145 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ | |
3146 MacroAssembler _masm(&cbuf); | |
3147 Register src_reg = reg_to_register_object($src$$reg); | |
3148 Register dst_reg = reg_to_register_object($dst$$reg); | |
3149 __ sllx(src_reg, 48, dst_reg); | |
3150 __ srlx(dst_reg, 16, O7); | |
3151 __ or3 (dst_reg, O7, dst_reg); | |
3152 __ srlx(dst_reg, 32, O7); | |
3153 __ or3 (dst_reg, O7, dst_reg); | |
3154 %} | |
3155 | |
3156 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ | |
3157 MacroAssembler _masm(&cbuf); | |
3158 Register src_reg = reg_to_register_object($src$$reg); | |
3159 Register dst_reg = reg_to_register_object($dst$$reg); | |
3160 __ sllx(src_reg, 32, dst_reg); | |
3161 __ srlx(dst_reg, 32, O7); | |
3162 __ or3 (dst_reg, O7, dst_reg); | |
3163 %} | |
3164 | |
3165 %} | |
3166 | |
3167 //----------FRAME-------------------------------------------------------------- | |
3168 // Definition of frame structure and management information. | |
3169 // | |
3170 // S T A C K L A Y O U T Allocators stack-slot number | |
3171 // | (to get allocators register number | |
3172 // G Owned by | | v add VMRegImpl::stack0) | |
3173 // r CALLER | | | |
3174 // o | +--------+ pad to even-align allocators stack-slot | |
3175 // w V | pad0 | numbers; owned by CALLER | |
3176 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
3177 // h ^ | in | 5 | |
3178 // | | args | 4 Holes in incoming args owned by SELF | |
3179 // | | | | 3 | |
3180 // | | +--------+ | |
3181 // V | | old out| Empty on Intel, window on Sparc | |
3182 // | old |preserve| Must be even aligned. | |
3183 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned | |
3184 // | | in | 3 area for Intel ret address | |
3185 // Owned by |preserve| Empty on Sparc. | |
3186 // SELF +--------+ | |
3187 // | | pad2 | 2 pad to align old SP | |
3188 // | +--------+ 1 | |
3189 // | | locks | 0 | |
3190 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned | |
3191 // | | pad1 | 11 pad to align new SP | |
3192 // | +--------+ | |
3193 // | | | 10 | |
3194 // | | spills | 9 spills | |
3195 // V | | 8 (pad0 slot for callee) | |
3196 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
3197 // ^ | out | 7 | |
3198 // | | args | 6 Holes in outgoing args owned by CALLEE | |
3199 // Owned by +--------+ | |
3200 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
3201 // | new |preserve| Must be even-aligned. | |
3202 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
3203 // | | | | |
3204 // | |
3205 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
3206 // known from SELF's arguments and the Java calling convention. | |
3207 // Region 6-7 is determined per call site. | |
3208 // Note 2: If the calling convention leaves holes in the incoming argument | |
3209 // area, those holes are owned by SELF. Holes in the outgoing area | |
3210 // are owned by the CALLEE. Holes should not be nessecary in the | |
3211 // incoming area, as the Java calling convention is completely under | |
3212 // the control of the AD file. Doubles can be sorted and packed to | |
3213 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
3214 // varargs C calling conventions. | |
3215 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
3216 // even aligned with pad0 as needed. | |
3217 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
3218 // region 6-11 is even aligned; it may be padded out more so that | |
3219 // the region from SP to FP meets the minimum stack alignment. | |
3220 | |
3221 frame %{ | |
3222 // What direction does stack grow in (assumed to be same for native & Java) | |
3223 stack_direction(TOWARDS_LOW); | |
3224 | |
3225 // These two registers define part of the calling convention | |
3226 // between compiled code and the interpreter. | |
3227 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C | |
3228 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter | |
3229 | |
3230 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] | |
3231 cisc_spilling_operand_name(indOffset); | |
3232 | |
3233 // Number of stack slots consumed by a Monitor enter | |
3234 #ifdef _LP64 | |
3235 sync_stack_slots(2); | |
3236 #else | |
3237 sync_stack_slots(1); | |
3238 #endif | |
3239 | |
3240 // Compiled code's Frame Pointer | |
3241 frame_pointer(R_SP); | |
3242 | |
3243 // Stack alignment requirement | |
3244 stack_alignment(StackAlignmentInBytes); | |
3245 // LP64: Alignment size in bytes (128-bit -> 16 bytes) | |
3246 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) | |
3247 | |
3248 // Number of stack slots between incoming argument block and the start of | |
3249 // a new frame. The PROLOG must add this many slots to the stack. The | |
3250 // EPILOG must remove this many slots. | |
3251 in_preserve_stack_slots(0); | |
3252 | |
3253 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
3254 // for calls to C. Supports the var-args backing area for register parms. | |
3255 // ADLC doesn't support parsing expressions, so I folded the math by hand. | |
3256 #ifdef _LP64 | |
3257 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word | |
3258 varargs_C_out_slots_killed(12); | |
3259 #else | |
3260 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word | |
3261 varargs_C_out_slots_killed( 7); | |
3262 #endif | |
3263 | |
3264 // The after-PROLOG location of the return address. Location of | |
3265 // return address specifies a type (REG or STACK) and a number | |
3266 // representing the register number (i.e. - use a register name) or | |
3267 // stack slot. | |
3268 return_addr(REG R_I7); // Ret Addr is in register I7 | |
3269 | |
3270 // Body of function which returns an OptoRegs array locating | |
3271 // arguments either in registers or in stack slots for calling | |
3272 // java | |
3273 calling_convention %{ | |
3274 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); | |
3275 | |
3276 %} | |
3277 | |
3278 // Body of function which returns an OptoRegs array locating | |
3279 // arguments either in registers or in stack slots for callin | |
3280 // C. | |
3281 c_calling_convention %{ | |
3282 // This is obviously always outgoing | |
3283 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
3284 %} | |
3285 | |
3286 // Location of native (C/C++) and interpreter return values. This is specified to | |
3287 // be the same as Java. In the 32-bit VM, long values are actually returned from | |
3288 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying | |
3289 // to and from the register pairs is done by the appropriate call and epilog | |
3290 // opcodes. This simplifies the register allocator. | |
3291 c_return_value %{ | |
3292 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3293 #ifdef _LP64 | |
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3294 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3295 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3296 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3297 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3298 #else // !_LP64 |
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3299 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3300 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
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3301 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3302 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; |
0 | 3303 #endif |
3304 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3305 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3306 %} | |
3307 | |
3308 // Location of compiled Java return values. Same as C | |
3309 return_value %{ | |
3310 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); | |
3311 #ifdef _LP64 | |
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3312 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; |
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3313 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; |
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3314 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; |
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3315 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; |
0 | 3316 #else // !_LP64 |
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3317 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3318 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
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3319 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; |
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3320 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; |
0 | 3321 #endif |
3322 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], | |
3323 (is_outgoing?lo_out:lo_in)[ideal_reg] ); | |
3324 %} | |
3325 | |
3326 %} | |
3327 | |
3328 | |
3329 //----------ATTRIBUTES--------------------------------------------------------- | |
3330 //----------Operand Attributes------------------------------------------------- | |
3331 op_attrib op_cost(1); // Required cost attribute | |
3332 | |
3333 //----------Instruction Attributes--------------------------------------------- | |
3334 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute | |
3335 ins_attrib ins_size(32); // Required size attribute (in bits) | |
3336 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
3337 ins_attrib ins_short_branch(0); // Required flag: is this instruction a | |
3338 // non-matching short branch variant of some | |
3339 // long branch? | |
3340 | |
3341 //----------OPERANDS----------------------------------------------------------- | |
3342 // Operand definitions must precede instruction definitions for correct parsing | |
3343 // in the ADLC because operands constitute user defined types which are used in | |
3344 // instruction definitions. | |
3345 | |
3346 //----------Simple Operands---------------------------------------------------- | |
3347 // Immediate Operands | |
3348 // Integer Immediate: 32-bit | |
3349 operand immI() %{ | |
3350 match(ConI); | |
3351 | |
3352 op_cost(0); | |
3353 // formats are generated automatically for constants and base registers | |
3354 format %{ %} | |
3355 interface(CONST_INTER); | |
3356 %} | |
3357 | |
824 | 3358 // Integer Immediate: 8-bit |
3359 operand immI8() %{ | |
3360 predicate(Assembler::is_simm(n->get_int(), 8)); | |
3361 match(ConI); | |
3362 op_cost(0); | |
3363 format %{ %} | |
3364 interface(CONST_INTER); | |
3365 %} | |
3366 | |
0 | 3367 // Integer Immediate: 13-bit |
3368 operand immI13() %{ | |
3369 predicate(Assembler::is_simm13(n->get_int())); | |
3370 match(ConI); | |
3371 op_cost(0); | |
3372 | |
3373 format %{ %} | |
3374 interface(CONST_INTER); | |
3375 %} | |
3376 | |
785 | 3377 // Integer Immediate: 13-bit minus 7 |
3378 operand immI13m7() %{ | |
3379 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); | |
3380 match(ConI); | |
3381 op_cost(0); | |
3382 | |
3383 format %{ %} | |
3384 interface(CONST_INTER); | |
3385 %} | |
3386 | |
824 | 3387 // Integer Immediate: 16-bit |
3388 operand immI16() %{ | |
3389 predicate(Assembler::is_simm(n->get_int(), 16)); | |
3390 match(ConI); | |
3391 op_cost(0); | |
3392 format %{ %} | |
3393 interface(CONST_INTER); | |
3394 %} | |
3395 | |
0 | 3396 // Unsigned (positive) Integer Immediate: 13-bit |
3397 operand immU13() %{ | |
3398 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); | |
3399 match(ConI); | |
3400 op_cost(0); | |
3401 | |
3402 format %{ %} | |
3403 interface(CONST_INTER); | |
3404 %} | |
3405 | |
3406 // Integer Immediate: 6-bit | |
3407 operand immU6() %{ | |
3408 predicate(n->get_int() >= 0 && n->get_int() <= 63); | |
3409 match(ConI); | |
3410 op_cost(0); | |
3411 format %{ %} | |
3412 interface(CONST_INTER); | |
3413 %} | |
3414 | |
3415 // Integer Immediate: 11-bit | |
3416 operand immI11() %{ | |
3417 predicate(Assembler::is_simm(n->get_int(),11)); | |
3418 match(ConI); | |
3419 op_cost(0); | |
3420 format %{ %} | |
3421 interface(CONST_INTER); | |
3422 %} | |
3423 | |
3424 // Integer Immediate: 0-bit | |
3425 operand immI0() %{ | |
3426 predicate(n->get_int() == 0); | |
3427 match(ConI); | |
3428 op_cost(0); | |
3429 | |
3430 format %{ %} | |
3431 interface(CONST_INTER); | |
3432 %} | |
3433 | |
3434 // Integer Immediate: the value 10 | |
3435 operand immI10() %{ | |
3436 predicate(n->get_int() == 10); | |
3437 match(ConI); | |
3438 op_cost(0); | |
3439 | |
3440 format %{ %} | |
3441 interface(CONST_INTER); | |
3442 %} | |
3443 | |
3444 // Integer Immediate: the values 0-31 | |
3445 operand immU5() %{ | |
3446 predicate(n->get_int() >= 0 && n->get_int() <= 31); | |
3447 match(ConI); | |
3448 op_cost(0); | |
3449 | |
3450 format %{ %} | |
3451 interface(CONST_INTER); | |
3452 %} | |
3453 | |
3454 // Integer Immediate: the values 1-31 | |
3455 operand immI_1_31() %{ | |
3456 predicate(n->get_int() >= 1 && n->get_int() <= 31); | |
3457 match(ConI); | |
3458 op_cost(0); | |
3459 | |
3460 format %{ %} | |
3461 interface(CONST_INTER); | |
3462 %} | |
3463 | |
3464 // Integer Immediate: the values 32-63 | |
3465 operand immI_32_63() %{ | |
3466 predicate(n->get_int() >= 32 && n->get_int() <= 63); | |
3467 match(ConI); | |
3468 op_cost(0); | |
3469 | |
3470 format %{ %} | |
3471 interface(CONST_INTER); | |
3472 %} | |
3473 | |
785 | 3474 // Immediates for special shifts (sign extend) |
3475 | |
3476 // Integer Immediate: the value 16 | |
3477 operand immI_16() %{ | |
3478 predicate(n->get_int() == 16); | |
3479 match(ConI); | |
3480 op_cost(0); | |
3481 | |
3482 format %{ %} | |
3483 interface(CONST_INTER); | |
3484 %} | |
3485 | |
3486 // Integer Immediate: the value 24 | |
3487 operand immI_24() %{ | |
3488 predicate(n->get_int() == 24); | |
3489 match(ConI); | |
3490 op_cost(0); | |
3491 | |
3492 format %{ %} | |
3493 interface(CONST_INTER); | |
3494 %} | |
3495 | |
0 | 3496 // Integer Immediate: the value 255 |
3497 operand immI_255() %{ | |
3498 predicate( n->get_int() == 255 ); | |
3499 match(ConI); | |
3500 op_cost(0); | |
3501 | |
3502 format %{ %} | |
3503 interface(CONST_INTER); | |
3504 %} | |
3505 | |
785 | 3506 // Integer Immediate: the value 65535 |
3507 operand immI_65535() %{ | |
3508 predicate(n->get_int() == 65535); | |
3509 match(ConI); | |
3510 op_cost(0); | |
3511 | |
3512 format %{ %} | |
3513 interface(CONST_INTER); | |
3514 %} | |
3515 | |
0 | 3516 // Long Immediate: the value FF |
3517 operand immL_FF() %{ | |
3518 predicate( n->get_long() == 0xFFL ); | |
3519 match(ConL); | |
3520 op_cost(0); | |
3521 | |
3522 format %{ %} | |
3523 interface(CONST_INTER); | |
3524 %} | |
3525 | |
3526 // Long Immediate: the value FFFF | |
3527 operand immL_FFFF() %{ | |
3528 predicate( n->get_long() == 0xFFFFL ); | |
3529 match(ConL); | |
3530 op_cost(0); | |
3531 | |
3532 format %{ %} | |
3533 interface(CONST_INTER); | |
3534 %} | |
3535 | |
3536 // Pointer Immediate: 32 or 64-bit | |
3537 operand immP() %{ | |
3538 match(ConP); | |
3539 | |
3540 op_cost(5); | |
3541 // formats are generated automatically for constants and base registers | |
3542 format %{ %} | |
3543 interface(CONST_INTER); | |
3544 %} | |
3545 | |
3546 operand immP13() %{ | |
3547 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); | |
3548 match(ConP); | |
3549 op_cost(0); | |
3550 | |
3551 format %{ %} | |
3552 interface(CONST_INTER); | |
3553 %} | |
3554 | |
3555 operand immP0() %{ | |
3556 predicate(n->get_ptr() == 0); | |
3557 match(ConP); | |
3558 op_cost(0); | |
3559 | |
3560 format %{ %} | |
3561 interface(CONST_INTER); | |
3562 %} | |
3563 | |
3564 operand immP_poll() %{ | |
3565 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); | |
3566 match(ConP); | |
3567 | |
3568 // formats are generated automatically for constants and base registers | |
3569 format %{ %} | |
3570 interface(CONST_INTER); | |
3571 %} | |
3572 | |
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3573 // Pointer Immediate |
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3574 operand immN() |
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3575 %{ |
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3576 match(ConN); |
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3577 |
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3578 op_cost(10); |
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3579 format %{ %} |
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3580 interface(CONST_INTER); |
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3581 %} |
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3582 |
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3583 // NULL Pointer Immediate |
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3584 operand immN0() |
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3585 %{ |
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3586 predicate(n->get_narrowcon() == 0); |
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3587 match(ConN); |
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3588 |
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3589 op_cost(0); |
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3590 format %{ %} |
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3591 interface(CONST_INTER); |
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3592 %} |
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3593 |
0 | 3594 operand immL() %{ |
3595 match(ConL); | |
3596 op_cost(40); | |
3597 // formats are generated automatically for constants and base registers | |
3598 format %{ %} | |
3599 interface(CONST_INTER); | |
3600 %} | |
3601 | |
3602 operand immL0() %{ | |
3603 predicate(n->get_long() == 0L); | |
3604 match(ConL); | |
3605 op_cost(0); | |
3606 // formats are generated automatically for constants and base registers | |
3607 format %{ %} | |
3608 interface(CONST_INTER); | |
3609 %} | |
3610 | |
3611 // Long Immediate: 13-bit | |
3612 operand immL13() %{ | |
3613 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); | |
3614 match(ConL); | |
3615 op_cost(0); | |
3616 | |
3617 format %{ %} | |
3618 interface(CONST_INTER); | |
3619 %} | |
3620 | |
785 | 3621 // Long Immediate: 13-bit minus 7 |
3622 operand immL13m7() %{ | |
3623 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); | |
3624 match(ConL); | |
3625 op_cost(0); | |
3626 | |
3627 format %{ %} | |
3628 interface(CONST_INTER); | |
3629 %} | |
3630 | |
0 | 3631 // Long Immediate: low 32-bit mask |
3632 operand immL_32bits() %{ | |
3633 predicate(n->get_long() == 0xFFFFFFFFL); | |
3634 match(ConL); | |
3635 op_cost(0); | |
3636 | |
3637 format %{ %} | |
3638 interface(CONST_INTER); | |
3639 %} | |
3640 | |
3641 // Double Immediate | |
3642 operand immD() %{ | |
3643 match(ConD); | |
3644 | |
3645 op_cost(40); | |
3646 format %{ %} | |
3647 interface(CONST_INTER); | |
3648 %} | |
3649 | |
3650 operand immD0() %{ | |
3651 #ifdef _LP64 | |
3652 // on 64-bit architectures this comparision is faster | |
3653 predicate(jlong_cast(n->getd()) == 0); | |
3654 #else | |
3655 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); | |
3656 #endif | |
3657 match(ConD); | |
3658 | |
3659 op_cost(0); | |
3660 format %{ %} | |
3661 interface(CONST_INTER); | |
3662 %} | |
3663 | |
3664 // Float Immediate | |
3665 operand immF() %{ | |
3666 match(ConF); | |
3667 | |
3668 op_cost(20); | |
3669 format %{ %} | |
3670 interface(CONST_INTER); | |
3671 %} | |
3672 | |
3673 // Float Immediate: 0 | |
3674 operand immF0() %{ | |
3675 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); | |
3676 match(ConF); | |
3677 | |
3678 op_cost(0); | |
3679 format %{ %} | |
3680 interface(CONST_INTER); | |
3681 %} | |
3682 | |
3683 // Integer Register Operands | |
3684 // Integer Register | |
3685 operand iRegI() %{ | |
3686 constraint(ALLOC_IN_RC(int_reg)); | |
3687 match(RegI); | |
3688 | |
3689 match(notemp_iRegI); | |
3690 match(g1RegI); | |
3691 match(o0RegI); | |
3692 match(iRegIsafe); | |
3693 | |
3694 format %{ %} | |
3695 interface(REG_INTER); | |
3696 %} | |
3697 | |
3698 operand notemp_iRegI() %{ | |
3699 constraint(ALLOC_IN_RC(notemp_int_reg)); | |
3700 match(RegI); | |
3701 | |
3702 match(o0RegI); | |
3703 | |
3704 format %{ %} | |
3705 interface(REG_INTER); | |
3706 %} | |
3707 | |
3708 operand o0RegI() %{ | |
3709 constraint(ALLOC_IN_RC(o0_regI)); | |
3710 match(iRegI); | |
3711 | |
3712 format %{ %} | |
3713 interface(REG_INTER); | |
3714 %} | |
3715 | |
3716 // Pointer Register | |
3717 operand iRegP() %{ | |
3718 constraint(ALLOC_IN_RC(ptr_reg)); | |
3719 match(RegP); | |
3720 | |
3721 match(lock_ptr_RegP); | |
3722 match(g1RegP); | |
3723 match(g2RegP); | |
3724 match(g3RegP); | |
3725 match(g4RegP); | |
3726 match(i0RegP); | |
3727 match(o0RegP); | |
3728 match(o1RegP); | |
3729 match(l7RegP); | |
3730 | |
3731 format %{ %} | |
3732 interface(REG_INTER); | |
3733 %} | |
3734 | |
3735 operand sp_ptr_RegP() %{ | |
3736 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
3737 match(RegP); | |
3738 match(iRegP); | |
3739 | |
3740 format %{ %} | |
3741 interface(REG_INTER); | |
3742 %} | |
3743 | |
3744 operand lock_ptr_RegP() %{ | |
3745 constraint(ALLOC_IN_RC(lock_ptr_reg)); | |
3746 match(RegP); | |
3747 match(i0RegP); | |
3748 match(o0RegP); | |
3749 match(o1RegP); | |
3750 match(l7RegP); | |
3751 | |
3752 format %{ %} | |
3753 interface(REG_INTER); | |
3754 %} | |
3755 | |
3756 operand g1RegP() %{ | |
3757 constraint(ALLOC_IN_RC(g1_regP)); | |
3758 match(iRegP); | |
3759 | |
3760 format %{ %} | |
3761 interface(REG_INTER); | |
3762 %} | |
3763 | |
3764 operand g2RegP() %{ | |
3765 constraint(ALLOC_IN_RC(g2_regP)); | |
3766 match(iRegP); | |
3767 | |
3768 format %{ %} | |
3769 interface(REG_INTER); | |
3770 %} | |
3771 | |
3772 operand g3RegP() %{ | |
3773 constraint(ALLOC_IN_RC(g3_regP)); | |
3774 match(iRegP); | |
3775 | |
3776 format %{ %} | |
3777 interface(REG_INTER); | |
3778 %} | |
3779 | |
3780 operand g1RegI() %{ | |
3781 constraint(ALLOC_IN_RC(g1_regI)); | |
3782 match(iRegI); | |
3783 | |
3784 format %{ %} | |
3785 interface(REG_INTER); | |
3786 %} | |
3787 | |
3788 operand g3RegI() %{ | |
3789 constraint(ALLOC_IN_RC(g3_regI)); | |
3790 match(iRegI); | |
3791 | |
3792 format %{ %} | |
3793 interface(REG_INTER); | |
3794 %} | |
3795 | |
3796 operand g4RegI() %{ | |
3797 constraint(ALLOC_IN_RC(g4_regI)); | |
3798 match(iRegI); | |
3799 | |
3800 format %{ %} | |
3801 interface(REG_INTER); | |
3802 %} | |
3803 | |
3804 operand g4RegP() %{ | |
3805 constraint(ALLOC_IN_RC(g4_regP)); | |
3806 match(iRegP); | |
3807 | |
3808 format %{ %} | |
3809 interface(REG_INTER); | |
3810 %} | |
3811 | |
3812 operand i0RegP() %{ | |
3813 constraint(ALLOC_IN_RC(i0_regP)); | |
3814 match(iRegP); | |
3815 | |
3816 format %{ %} | |
3817 interface(REG_INTER); | |
3818 %} | |
3819 | |
3820 operand o0RegP() %{ | |
3821 constraint(ALLOC_IN_RC(o0_regP)); | |
3822 match(iRegP); | |
3823 | |
3824 format %{ %} | |
3825 interface(REG_INTER); | |
3826 %} | |
3827 | |
3828 operand o1RegP() %{ | |
3829 constraint(ALLOC_IN_RC(o1_regP)); | |
3830 match(iRegP); | |
3831 | |
3832 format %{ %} | |
3833 interface(REG_INTER); | |
3834 %} | |
3835 | |
3836 operand o2RegP() %{ | |
3837 constraint(ALLOC_IN_RC(o2_regP)); | |
3838 match(iRegP); | |
3839 | |
3840 format %{ %} | |
3841 interface(REG_INTER); | |
3842 %} | |
3843 | |
3844 operand o7RegP() %{ | |
3845 constraint(ALLOC_IN_RC(o7_regP)); | |
3846 match(iRegP); | |
3847 | |
3848 format %{ %} | |
3849 interface(REG_INTER); | |
3850 %} | |
3851 | |
3852 operand l7RegP() %{ | |
3853 constraint(ALLOC_IN_RC(l7_regP)); | |
3854 match(iRegP); | |
3855 | |
3856 format %{ %} | |
3857 interface(REG_INTER); | |
3858 %} | |
3859 | |
3860 operand o7RegI() %{ | |
3861 constraint(ALLOC_IN_RC(o7_regI)); | |
3862 match(iRegI); | |
3863 | |
3864 format %{ %} | |
3865 interface(REG_INTER); | |
3866 %} | |
3867 | |
113
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3868 operand iRegN() %{ |
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3869 constraint(ALLOC_IN_RC(int_reg)); |
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3870 match(RegN); |
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3871 |
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3872 format %{ %} |
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3873 interface(REG_INTER); |
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3874 %} |
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3875 |
0 | 3876 // Long Register |
3877 operand iRegL() %{ | |
3878 constraint(ALLOC_IN_RC(long_reg)); | |
3879 match(RegL); | |
3880 | |
3881 format %{ %} | |
3882 interface(REG_INTER); | |
3883 %} | |
3884 | |
3885 operand o2RegL() %{ | |
3886 constraint(ALLOC_IN_RC(o2_regL)); | |
3887 match(iRegL); | |
3888 | |
3889 format %{ %} | |
3890 interface(REG_INTER); | |
3891 %} | |
3892 | |
3893 operand o7RegL() %{ | |
3894 constraint(ALLOC_IN_RC(o7_regL)); | |
3895 match(iRegL); | |
3896 | |
3897 format %{ %} | |
3898 interface(REG_INTER); | |
3899 %} | |
3900 | |
3901 operand g1RegL() %{ | |
3902 constraint(ALLOC_IN_RC(g1_regL)); | |
3903 match(iRegL); | |
3904 | |
3905 format %{ %} | |
3906 interface(REG_INTER); | |
3907 %} | |
3908 | |
420
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3909 operand g3RegL() %{ |
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3910 constraint(ALLOC_IN_RC(g3_regL)); |
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3911 match(iRegL); |
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3912 |
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3913 format %{ %} |
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3914 interface(REG_INTER); |
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3915 %} |
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3916 |
0 | 3917 // Int Register safe |
3918 // This is 64bit safe | |
3919 operand iRegIsafe() %{ | |
3920 constraint(ALLOC_IN_RC(long_reg)); | |
3921 | |
3922 match(iRegI); | |
3923 | |
3924 format %{ %} | |
3925 interface(REG_INTER); | |
3926 %} | |
3927 | |
3928 // Condition Code Flag Register | |
3929 operand flagsReg() %{ | |
3930 constraint(ALLOC_IN_RC(int_flags)); | |
3931 match(RegFlags); | |
3932 | |
3933 format %{ "ccr" %} // both ICC and XCC | |
3934 interface(REG_INTER); | |
3935 %} | |
3936 | |
3937 // Condition Code Register, unsigned comparisons. | |
3938 operand flagsRegU() %{ | |
3939 constraint(ALLOC_IN_RC(int_flags)); | |
3940 match(RegFlags); | |
3941 | |
3942 format %{ "icc_U" %} | |
3943 interface(REG_INTER); | |
3944 %} | |
3945 | |
3946 // Condition Code Register, pointer comparisons. | |
3947 operand flagsRegP() %{ | |
3948 constraint(ALLOC_IN_RC(int_flags)); | |
3949 match(RegFlags); | |
3950 | |
3951 #ifdef _LP64 | |
3952 format %{ "xcc_P" %} | |
3953 #else | |
3954 format %{ "icc_P" %} | |
3955 #endif | |
3956 interface(REG_INTER); | |
3957 %} | |
3958 | |
3959 // Condition Code Register, long comparisons. | |
3960 operand flagsRegL() %{ | |
3961 constraint(ALLOC_IN_RC(int_flags)); | |
3962 match(RegFlags); | |
3963 | |
3964 format %{ "xcc_L" %} | |
3965 interface(REG_INTER); | |
3966 %} | |
3967 | |
3968 // Condition Code Register, floating comparisons, unordered same as "less". | |
3969 operand flagsRegF() %{ | |
3970 constraint(ALLOC_IN_RC(float_flags)); | |
3971 match(RegFlags); | |
3972 match(flagsRegF0); | |
3973 | |
3974 format %{ %} | |
3975 interface(REG_INTER); | |
3976 %} | |
3977 | |
3978 operand flagsRegF0() %{ | |
3979 constraint(ALLOC_IN_RC(float_flag0)); | |
3980 match(RegFlags); | |
3981 | |
3982 format %{ %} | |
3983 interface(REG_INTER); | |
3984 %} | |
3985 | |
3986 | |
3987 // Condition Code Flag Register used by long compare | |
3988 operand flagsReg_long_LTGE() %{ | |
3989 constraint(ALLOC_IN_RC(int_flags)); | |
3990 match(RegFlags); | |
3991 format %{ "icc_LTGE" %} | |
3992 interface(REG_INTER); | |
3993 %} | |
3994 operand flagsReg_long_EQNE() %{ | |
3995 constraint(ALLOC_IN_RC(int_flags)); | |
3996 match(RegFlags); | |
3997 format %{ "icc_EQNE" %} | |
3998 interface(REG_INTER); | |
3999 %} | |
4000 operand flagsReg_long_LEGT() %{ | |
4001 constraint(ALLOC_IN_RC(int_flags)); | |
4002 match(RegFlags); | |
4003 format %{ "icc_LEGT" %} | |
4004 interface(REG_INTER); | |
4005 %} | |
4006 | |
4007 | |
4008 operand regD() %{ | |
4009 constraint(ALLOC_IN_RC(dflt_reg)); | |
4010 match(RegD); | |
4011 | |
551 | 4012 match(regD_low); |
4013 | |
0 | 4014 format %{ %} |
4015 interface(REG_INTER); | |
4016 %} | |
4017 | |
4018 operand regF() %{ | |
4019 constraint(ALLOC_IN_RC(sflt_reg)); | |
4020 match(RegF); | |
4021 | |
4022 format %{ %} | |
4023 interface(REG_INTER); | |
4024 %} | |
4025 | |
4026 operand regD_low() %{ | |
4027 constraint(ALLOC_IN_RC(dflt_low_reg)); | |
551 | 4028 match(regD); |
0 | 4029 |
4030 format %{ %} | |
4031 interface(REG_INTER); | |
4032 %} | |
4033 | |
4034 // Special Registers | |
4035 | |
4036 // Method Register | |
4037 operand inline_cache_regP(iRegP reg) %{ | |
4038 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 | |
4039 match(reg); | |
4040 format %{ %} | |
4041 interface(REG_INTER); | |
4042 %} | |
4043 | |
4044 operand interpreter_method_oop_regP(iRegP reg) %{ | |
4045 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 | |
4046 match(reg); | |
4047 format %{ %} | |
4048 interface(REG_INTER); | |
4049 %} | |
4050 | |
4051 | |
4052 //----------Complex Operands--------------------------------------------------- | |
4053 // Indirect Memory Reference | |
4054 operand indirect(sp_ptr_RegP reg) %{ | |
4055 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4056 match(reg); | |
4057 | |
4058 op_cost(100); | |
4059 format %{ "[$reg]" %} | |
4060 interface(MEMORY_INTER) %{ | |
4061 base($reg); | |
4062 index(0x0); | |
4063 scale(0x0); | |
4064 disp(0x0); | |
4065 %} | |
4066 %} | |
4067 | |
785 | 4068 // Indirect with simm13 Offset |
0 | 4069 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ |
4070 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4071 match(AddP reg offset); | |
4072 | |
4073 op_cost(100); | |
4074 format %{ "[$reg + $offset]" %} | |
4075 interface(MEMORY_INTER) %{ | |
4076 base($reg); | |
4077 index(0x0); | |
4078 scale(0x0); | |
4079 disp($offset); | |
4080 %} | |
4081 %} | |
4082 | |
785 | 4083 // Indirect with simm13 Offset minus 7 |
4084 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ | |
4085 constraint(ALLOC_IN_RC(sp_ptr_reg)); | |
4086 match(AddP reg offset); | |
4087 | |
4088 op_cost(100); | |
4089 format %{ "[$reg + $offset]" %} | |
4090 interface(MEMORY_INTER) %{ | |
4091 base($reg); | |
4092 index(0x0); | |
4093 scale(0x0); | |
4094 disp($offset); | |
4095 %} | |
4096 %} | |
4097 | |
0 | 4098 // Note: Intel has a swapped version also, like this: |
4099 //operand indOffsetX(iRegI reg, immP offset) %{ | |
4100 // constraint(ALLOC_IN_RC(int_reg)); | |
4101 // match(AddP offset reg); | |
4102 // | |
4103 // op_cost(100); | |
4104 // format %{ "[$reg + $offset]" %} | |
4105 // interface(MEMORY_INTER) %{ | |
4106 // base($reg); | |
4107 // index(0x0); | |
4108 // scale(0x0); | |
4109 // disp($offset); | |
4110 // %} | |
4111 //%} | |
4112 //// However, it doesn't make sense for SPARC, since | |
4113 // we have no particularly good way to embed oops in | |
4114 // single instructions. | |
4115 | |
4116 // Indirect with Register Index | |
4117 operand indIndex(iRegP addr, iRegX index) %{ | |
4118 constraint(ALLOC_IN_RC(ptr_reg)); | |
4119 match(AddP addr index); | |
4120 | |
4121 op_cost(100); | |
4122 format %{ "[$addr + $index]" %} | |
4123 interface(MEMORY_INTER) %{ | |
4124 base($addr); | |
4125 index($index); | |
4126 scale(0x0); | |
4127 disp(0x0); | |
4128 %} | |
4129 %} | |
4130 | |
4131 //----------Special Memory Operands-------------------------------------------- | |
4132 // Stack Slot Operand - This operand is used for loading and storing temporary | |
4133 // values on the stack where a match requires a value to | |
4134 // flow through memory. | |
4135 operand stackSlotI(sRegI reg) %{ | |
4136 constraint(ALLOC_IN_RC(stack_slots)); | |
4137 op_cost(100); | |
4138 //match(RegI); | |
4139 format %{ "[$reg]" %} | |
4140 interface(MEMORY_INTER) %{ | |
4141 base(0xE); // R_SP | |
4142 index(0x0); | |
4143 scale(0x0); | |
4144 disp($reg); // Stack Offset | |
4145 %} | |
4146 %} | |
4147 | |
4148 operand stackSlotP(sRegP reg) %{ | |
4149 constraint(ALLOC_IN_RC(stack_slots)); | |
4150 op_cost(100); | |
4151 //match(RegP); | |
4152 format %{ "[$reg]" %} | |
4153 interface(MEMORY_INTER) %{ | |
4154 base(0xE); // R_SP | |
4155 index(0x0); | |
4156 scale(0x0); | |
4157 disp($reg); // Stack Offset | |
4158 %} | |
4159 %} | |
4160 | |
4161 operand stackSlotF(sRegF reg) %{ | |
4162 constraint(ALLOC_IN_RC(stack_slots)); | |
4163 op_cost(100); | |
4164 //match(RegF); | |
4165 format %{ "[$reg]" %} | |
4166 interface(MEMORY_INTER) %{ | |
4167 base(0xE); // R_SP | |
4168 index(0x0); | |
4169 scale(0x0); | |
4170 disp($reg); // Stack Offset | |
4171 %} | |
4172 %} | |
4173 operand stackSlotD(sRegD reg) %{ | |
4174 constraint(ALLOC_IN_RC(stack_slots)); | |
4175 op_cost(100); | |
4176 //match(RegD); | |
4177 format %{ "[$reg]" %} | |
4178 interface(MEMORY_INTER) %{ | |
4179 base(0xE); // R_SP | |
4180 index(0x0); | |
4181 scale(0x0); | |
4182 disp($reg); // Stack Offset | |
4183 %} | |
4184 %} | |
4185 operand stackSlotL(sRegL reg) %{ | |
4186 constraint(ALLOC_IN_RC(stack_slots)); | |
4187 op_cost(100); | |
4188 //match(RegL); | |
4189 format %{ "[$reg]" %} | |
4190 interface(MEMORY_INTER) %{ | |
4191 base(0xE); // R_SP | |
4192 index(0x0); | |
4193 scale(0x0); | |
4194 disp($reg); // Stack Offset | |
4195 %} | |
4196 %} | |
4197 | |
4198 // Operands for expressing Control Flow | |
4199 // NOTE: Label is a predefined operand which should not be redefined in | |
4200 // the AD file. It is generically handled within the ADLC. | |
4201 | |
4202 //----------Conditional Branch Operands---------------------------------------- | |
4203 // Comparison Op - This is the operation of the comparison, and is limited to | |
4204 // the following set of codes: | |
4205 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
4206 // | |
4207 // Other attributes of the comparison, such as unsignedness, are specified | |
4208 // by the comparison instruction that sets a condition code flags register. | |
4209 // That result is represented by a flags operand whose subtype is appropriate | |
4210 // to the unsignedness (etc.) of the comparison. | |
4211 // | |
4212 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
4213 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
4214 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
4215 | |
4216 operand cmpOp() %{ | |
4217 match(Bool); | |
4218 | |
4219 format %{ "" %} | |
4220 interface(COND_INTER) %{ | |
4221 equal(0x1); | |
4222 not_equal(0x9); | |
4223 less(0x3); | |
4224 greater_equal(0xB); | |
4225 less_equal(0x2); | |
4226 greater(0xA); | |
4227 %} | |
4228 %} | |
4229 | |
4230 // Comparison Op, unsigned | |
4231 operand cmpOpU() %{ | |
4232 match(Bool); | |
4233 | |
4234 format %{ "u" %} | |
4235 interface(COND_INTER) %{ | |
4236 equal(0x1); | |
4237 not_equal(0x9); | |
4238 less(0x5); | |
4239 greater_equal(0xD); | |
4240 less_equal(0x4); | |
4241 greater(0xC); | |
4242 %} | |
4243 %} | |
4244 | |
4245 // Comparison Op, pointer (same as unsigned) | |
4246 operand cmpOpP() %{ | |
4247 match(Bool); | |
4248 | |
4249 format %{ "p" %} | |
4250 interface(COND_INTER) %{ | |
4251 equal(0x1); | |
4252 not_equal(0x9); | |
4253 less(0x5); | |
4254 greater_equal(0xD); | |
4255 less_equal(0x4); | |
4256 greater(0xC); | |
4257 %} | |
4258 %} | |
4259 | |
4260 // Comparison Op, branch-register encoding | |
4261 operand cmpOp_reg() %{ | |
4262 match(Bool); | |
4263 | |
4264 format %{ "" %} | |
4265 interface(COND_INTER) %{ | |
4266 equal (0x1); | |
4267 not_equal (0x5); | |
4268 less (0x3); | |
4269 greater_equal(0x7); | |
4270 less_equal (0x2); | |
4271 greater (0x6); | |
4272 %} | |
4273 %} | |
4274 | |
4275 // Comparison Code, floating, unordered same as less | |
4276 operand cmpOpF() %{ | |
4277 match(Bool); | |
4278 | |
4279 format %{ "fl" %} | |
4280 interface(COND_INTER) %{ | |
4281 equal(0x9); | |
4282 not_equal(0x1); | |
4283 less(0x3); | |
4284 greater_equal(0xB); | |
4285 less_equal(0xE); | |
4286 greater(0x6); | |
4287 %} | |
4288 %} | |
4289 | |
4290 // Used by long compare | |
4291 operand cmpOp_commute() %{ | |
4292 match(Bool); | |
4293 | |
4294 format %{ "" %} | |
4295 interface(COND_INTER) %{ | |
4296 equal(0x1); | |
4297 not_equal(0x9); | |
4298 less(0xA); | |
4299 greater_equal(0x2); | |
4300 less_equal(0xB); | |
4301 greater(0x3); | |
4302 %} | |
4303 %} | |
4304 | |
4305 //----------OPERAND CLASSES---------------------------------------------------- | |
4306 // Operand Classes are groups of operands that are used to simplify | |
605 | 4307 // instruction definitions by not requiring the AD writer to specify separate |
0 | 4308 // instructions for every form of operand when the instruction accepts |
4309 // multiple operand types with the same basic encoding and format. The classic | |
4310 // case of this is memory operands. | |
4311 // Indirect is not included since its use is limited to Compare & Swap | |
4312 opclass memory( indirect, indOffset13, indIndex ); | |
4313 | |
4314 //----------PIPELINE----------------------------------------------------------- | |
4315 pipeline %{ | |
4316 | |
4317 //----------ATTRIBUTES--------------------------------------------------------- | |
4318 attributes %{ | |
4319 fixed_size_instructions; // Fixed size instructions | |
4320 branch_has_delay_slot; // Branch has delay slot following | |
4321 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle | |
4322 instruction_unit_size = 4; // An instruction is 4 bytes long | |
4323 instruction_fetch_unit_size = 16; // The processor fetches one line | |
4324 instruction_fetch_units = 1; // of 16 bytes | |
4325 | |
4326 // List of nop instructions | |
4327 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); | |
4328 %} | |
4329 | |
4330 //----------RESOURCES---------------------------------------------------------- | |
4331 // Resources are the functional units available to the machine | |
4332 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); | |
4333 | |
4334 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
4335 // Pipeline Description specifies the stages in the machine's pipeline | |
4336 | |
4337 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); | |
4338 | |
4339 //----------PIPELINE CLASSES--------------------------------------------------- | |
4340 // Pipeline Classes describe the stages in which input and output are | |
4341 // referenced by the hardware pipeline. | |
4342 | |
4343 // Integer ALU reg-reg operation | |
4344 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4345 single_instruction; | |
4346 dst : E(write); | |
4347 src1 : R(read); | |
4348 src2 : R(read); | |
4349 IALU : R; | |
4350 %} | |
4351 | |
4352 // Integer ALU reg-reg long operation | |
4353 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
4354 instruction_count(2); | |
4355 dst : E(write); | |
4356 src1 : R(read); | |
4357 src2 : R(read); | |
4358 IALU : R; | |
4359 IALU : R; | |
4360 %} | |
4361 | |
4362 // Integer ALU reg-reg long dependent operation | |
4363 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ | |
4364 instruction_count(1); multiple_bundles; | |
4365 dst : E(write); | |
4366 src1 : R(read); | |
4367 src2 : R(read); | |
4368 cr : E(write); | |
4369 IALU : R(2); | |
4370 %} | |
4371 | |
4372 // Integer ALU reg-imm operaion | |
4373 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4374 single_instruction; | |
4375 dst : E(write); | |
4376 src1 : R(read); | |
4377 IALU : R; | |
4378 %} | |
4379 | |
4380 // Integer ALU reg-reg operation with condition code | |
4381 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ | |
4382 single_instruction; | |
4383 dst : E(write); | |
4384 cr : E(write); | |
4385 src1 : R(read); | |
4386 src2 : R(read); | |
4387 IALU : R; | |
4388 %} | |
4389 | |
4390 // Integer ALU reg-imm operation with condition code | |
4391 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ | |
4392 single_instruction; | |
4393 dst : E(write); | |
4394 cr : E(write); | |
4395 src1 : R(read); | |
4396 IALU : R; | |
4397 %} | |
4398 | |
4399 // Integer ALU zero-reg operation | |
4400 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
4401 single_instruction; | |
4402 dst : E(write); | |
4403 src2 : R(read); | |
4404 IALU : R; | |
4405 %} | |
4406 | |
4407 // Integer ALU zero-reg operation with condition code only | |
4408 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ | |
4409 single_instruction; | |
4410 cr : E(write); | |
4411 src : R(read); | |
4412 IALU : R; | |
4413 %} | |
4414 | |
4415 // Integer ALU reg-reg operation with condition code only | |
4416 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4417 single_instruction; | |
4418 cr : E(write); | |
4419 src1 : R(read); | |
4420 src2 : R(read); | |
4421 IALU : R; | |
4422 %} | |
4423 | |
4424 // Integer ALU reg-imm operation with condition code only | |
4425 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4426 single_instruction; | |
4427 cr : E(write); | |
4428 src1 : R(read); | |
4429 IALU : R; | |
4430 %} | |
4431 | |
4432 // Integer ALU reg-reg-zero operation with condition code only | |
4433 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ | |
4434 single_instruction; | |
4435 cr : E(write); | |
4436 src1 : R(read); | |
4437 src2 : R(read); | |
4438 IALU : R; | |
4439 %} | |
4440 | |
4441 // Integer ALU reg-imm-zero operation with condition code only | |
4442 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ | |
4443 single_instruction; | |
4444 cr : E(write); | |
4445 src1 : R(read); | |
4446 IALU : R; | |
4447 %} | |
4448 | |
4449 // Integer ALU reg-reg operation with condition code, src1 modified | |
4450 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ | |
4451 single_instruction; | |
4452 cr : E(write); | |
4453 src1 : E(write); | |
4454 src1 : R(read); | |
4455 src2 : R(read); | |
4456 IALU : R; | |
4457 %} | |
4458 | |
4459 // Integer ALU reg-imm operation with condition code, src1 modified | |
4460 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ | |
4461 single_instruction; | |
4462 cr : E(write); | |
4463 src1 : E(write); | |
4464 src1 : R(read); | |
4465 IALU : R; | |
4466 %} | |
4467 | |
4468 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ | |
4469 multiple_bundles; | |
4470 dst : E(write)+4; | |
4471 cr : E(write); | |
4472 src1 : R(read); | |
4473 src2 : R(read); | |
4474 IALU : R(3); | |
4475 BR : R(2); | |
4476 %} | |
4477 | |
4478 // Integer ALU operation | |
4479 pipe_class ialu_none(iRegI dst) %{ | |
4480 single_instruction; | |
4481 dst : E(write); | |
4482 IALU : R; | |
4483 %} | |
4484 | |
4485 // Integer ALU reg operation | |
4486 pipe_class ialu_reg(iRegI dst, iRegI src) %{ | |
4487 single_instruction; may_have_no_code; | |
4488 dst : E(write); | |
4489 src : R(read); | |
4490 IALU : R; | |
4491 %} | |
4492 | |
4493 // Integer ALU reg conditional operation | |
4494 // This instruction has a 1 cycle stall, and cannot execute | |
4495 // in the same cycle as the instruction setting the condition | |
4496 // code. We kludge this by pretending to read the condition code | |
4497 // 1 cycle earlier, and by marking the functional units as busy | |
4498 // for 2 cycles with the result available 1 cycle later than | |
4499 // is really the case. | |
4500 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ | |
4501 single_instruction; | |
4502 op2_out : C(write); | |
4503 op1 : R(read); | |
4504 cr : R(read); // This is really E, with a 1 cycle stall | |
4505 BR : R(2); | |
4506 MS : R(2); | |
4507 %} | |
4508 | |
4509 #ifdef _LP64 | |
4510 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ | |
4511 instruction_count(1); multiple_bundles; | |
4512 dst : C(write)+1; | |
4513 src : R(read)+1; | |
4514 IALU : R(1); | |
4515 BR : E(2); | |
4516 MS : E(2); | |
4517 %} | |
4518 #endif | |
4519 | |
4520 // Integer ALU reg operation | |
4521 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ | |
4522 single_instruction; may_have_no_code; | |
4523 dst : E(write); | |
4524 src : R(read); | |
4525 IALU : R; | |
4526 %} | |
4527 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ | |
4528 single_instruction; may_have_no_code; | |
4529 dst : E(write); | |
4530 src : R(read); | |
4531 IALU : R; | |
4532 %} | |
4533 | |
4534 // Two integer ALU reg operations | |
4535 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ | |
4536 instruction_count(2); | |
4537 dst : E(write); | |
4538 src : R(read); | |
4539 A0 : R; | |
4540 A1 : R; | |
4541 %} | |
4542 | |
4543 // Two integer ALU reg operations | |
4544 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ | |
4545 instruction_count(2); may_have_no_code; | |
4546 dst : E(write); | |
4547 src : R(read); | |
4548 A0 : R; | |
4549 A1 : R; | |
4550 %} | |
4551 | |
4552 // Integer ALU imm operation | |
4553 pipe_class ialu_imm(iRegI dst, immI13 src) %{ | |
4554 single_instruction; | |
4555 dst : E(write); | |
4556 IALU : R; | |
4557 %} | |
4558 | |
4559 // Integer ALU reg-reg with carry operation | |
4560 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ | |
4561 single_instruction; | |
4562 dst : E(write); | |
4563 src1 : R(read); | |
4564 src2 : R(read); | |
4565 IALU : R; | |
4566 %} | |
4567 | |
4568 // Integer ALU cc operation | |
4569 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ | |
4570 single_instruction; | |
4571 dst : E(write); | |
4572 cc : R(read); | |
4573 IALU : R; | |
4574 %} | |
4575 | |
4576 // Integer ALU cc / second IALU operation | |
4577 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ | |
4578 instruction_count(1); multiple_bundles; | |
4579 dst : E(write)+1; | |
4580 src : R(read); | |
4581 IALU : R; | |
4582 %} | |
4583 | |
4584 // Integer ALU cc / second IALU operation | |
4585 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ | |
4586 instruction_count(1); multiple_bundles; | |
4587 dst : E(write)+1; | |
4588 p : R(read); | |
4589 q : R(read); | |
4590 IALU : R; | |
4591 %} | |
4592 | |
4593 // Integer ALU hi-lo-reg operation | |
4594 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ | |
4595 instruction_count(1); multiple_bundles; | |
4596 dst : E(write)+1; | |
4597 IALU : R(2); | |
4598 %} | |
4599 | |
4600 // Float ALU hi-lo-reg operation (with temp) | |
4601 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ | |
4602 instruction_count(1); multiple_bundles; | |
4603 dst : E(write)+1; | |
4604 IALU : R(2); | |
4605 %} | |
4606 | |
4607 // Long Constant | |
4608 pipe_class loadConL( iRegL dst, immL src ) %{ | |
4609 instruction_count(2); multiple_bundles; | |
4610 dst : E(write)+1; | |
4611 IALU : R(2); | |
4612 IALU : R(2); | |
4613 %} | |
4614 | |
4615 // Pointer Constant | |
4616 pipe_class loadConP( iRegP dst, immP src ) %{ | |
4617 instruction_count(0); multiple_bundles; | |
4618 fixed_latency(6); | |
4619 %} | |
4620 | |
4621 // Polling Address | |
4622 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ | |
4623 #ifdef _LP64 | |
4624 instruction_count(0); multiple_bundles; | |
4625 fixed_latency(6); | |
4626 #else | |
4627 dst : E(write); | |
4628 IALU : R; | |
4629 #endif | |
4630 %} | |
4631 | |
4632 // Long Constant small | |
4633 pipe_class loadConLlo( iRegL dst, immL src ) %{ | |
4634 instruction_count(2); | |
4635 dst : E(write); | |
4636 IALU : R; | |
4637 IALU : R; | |
4638 %} | |
4639 | |
4640 // [PHH] This is wrong for 64-bit. See LdImmF/D. | |
4641 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ | |
4642 instruction_count(1); multiple_bundles; | |
4643 src : R(read); | |
4644 dst : M(write)+1; | |
4645 IALU : R; | |
4646 MS : E; | |
4647 %} | |
4648 | |
4649 // Integer ALU nop operation | |
4650 pipe_class ialu_nop() %{ | |
4651 single_instruction; | |
4652 IALU : R; | |
4653 %} | |
4654 | |
4655 // Integer ALU nop operation | |
4656 pipe_class ialu_nop_A0() %{ | |
4657 single_instruction; | |
4658 A0 : R; | |
4659 %} | |
4660 | |
4661 // Integer ALU nop operation | |
4662 pipe_class ialu_nop_A1() %{ | |
4663 single_instruction; | |
4664 A1 : R; | |
4665 %} | |
4666 | |
4667 // Integer Multiply reg-reg operation | |
4668 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
4669 single_instruction; | |
4670 dst : E(write); | |
4671 src1 : R(read); | |
4672 src2 : R(read); | |
4673 MS : R(5); | |
4674 %} | |
4675 | |
4676 // Integer Multiply reg-imm operation | |
4677 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ | |
4678 single_instruction; | |
4679 dst : E(write); | |
4680 src1 : R(read); | |
4681 MS : R(5); | |
4682 %} | |
4683 | |
4684 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4685 single_instruction; | |
4686 dst : E(write)+4; | |
4687 src1 : R(read); | |
4688 src2 : R(read); | |
4689 MS : R(6); | |
4690 %} | |
4691 | |
4692 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4693 single_instruction; | |
4694 dst : E(write)+4; | |
4695 src1 : R(read); | |
4696 MS : R(6); | |
4697 %} | |
4698 | |
4699 // Integer Divide reg-reg | |
4700 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ | |
4701 instruction_count(1); multiple_bundles; | |
4702 dst : E(write); | |
4703 temp : E(write); | |
4704 src1 : R(read); | |
4705 src2 : R(read); | |
4706 temp : R(read); | |
4707 MS : R(38); | |
4708 %} | |
4709 | |
4710 // Integer Divide reg-imm | |
4711 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ | |
4712 instruction_count(1); multiple_bundles; | |
4713 dst : E(write); | |
4714 temp : E(write); | |
4715 src1 : R(read); | |
4716 temp : R(read); | |
4717 MS : R(38); | |
4718 %} | |
4719 | |
4720 // Long Divide | |
4721 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
4722 dst : E(write)+71; | |
4723 src1 : R(read); | |
4724 src2 : R(read)+1; | |
4725 MS : R(70); | |
4726 %} | |
4727 | |
4728 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ | |
4729 dst : E(write)+71; | |
4730 src1 : R(read); | |
4731 MS : R(70); | |
4732 %} | |
4733 | |
4734 // Floating Point Add Float | |
4735 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4736 single_instruction; | |
4737 dst : X(write); | |
4738 src1 : E(read); | |
4739 src2 : E(read); | |
4740 FA : R; | |
4741 %} | |
4742 | |
4743 // Floating Point Add Double | |
4744 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4745 single_instruction; | |
4746 dst : X(write); | |
4747 src1 : E(read); | |
4748 src2 : E(read); | |
4749 FA : R; | |
4750 %} | |
4751 | |
4752 // Floating Point Conditional Move based on integer flags | |
4753 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ | |
4754 single_instruction; | |
4755 dst : X(write); | |
4756 src : E(read); | |
4757 cr : R(read); | |
4758 FA : R(2); | |
4759 BR : R(2); | |
4760 %} | |
4761 | |
4762 // Floating Point Conditional Move based on integer flags | |
4763 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ | |
4764 single_instruction; | |
4765 dst : X(write); | |
4766 src : E(read); | |
4767 cr : R(read); | |
4768 FA : R(2); | |
4769 BR : R(2); | |
4770 %} | |
4771 | |
4772 // Floating Point Multiply Float | |
4773 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4774 single_instruction; | |
4775 dst : X(write); | |
4776 src1 : E(read); | |
4777 src2 : E(read); | |
4778 FM : R; | |
4779 %} | |
4780 | |
4781 // Floating Point Multiply Double | |
4782 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4783 single_instruction; | |
4784 dst : X(write); | |
4785 src1 : E(read); | |
4786 src2 : E(read); | |
4787 FM : R; | |
4788 %} | |
4789 | |
4790 // Floating Point Divide Float | |
4791 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ | |
4792 single_instruction; | |
4793 dst : X(write); | |
4794 src1 : E(read); | |
4795 src2 : E(read); | |
4796 FM : R; | |
4797 FDIV : C(14); | |
4798 %} | |
4799 | |
4800 // Floating Point Divide Double | |
4801 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ | |
4802 single_instruction; | |
4803 dst : X(write); | |
4804 src1 : E(read); | |
4805 src2 : E(read); | |
4806 FM : R; | |
4807 FDIV : C(17); | |
4808 %} | |
4809 | |
4810 // Floating Point Move/Negate/Abs Float | |
4811 pipe_class faddF_reg(regF dst, regF src) %{ | |
4812 single_instruction; | |
4813 dst : W(write); | |
4814 src : E(read); | |
4815 FA : R(1); | |
4816 %} | |
4817 | |
4818 // Floating Point Move/Negate/Abs Double | |
4819 pipe_class faddD_reg(regD dst, regD src) %{ | |
4820 single_instruction; | |
4821 dst : W(write); | |
4822 src : E(read); | |
4823 FA : R; | |
4824 %} | |
4825 | |
4826 // Floating Point Convert F->D | |
4827 pipe_class fcvtF2D(regD dst, regF src) %{ | |
4828 single_instruction; | |
4829 dst : X(write); | |
4830 src : E(read); | |
4831 FA : R; | |
4832 %} | |
4833 | |
4834 // Floating Point Convert I->D | |
4835 pipe_class fcvtI2D(regD dst, regF src) %{ | |
4836 single_instruction; | |
4837 dst : X(write); | |
4838 src : E(read); | |
4839 FA : R; | |
4840 %} | |
4841 | |
4842 // Floating Point Convert LHi->D | |
4843 pipe_class fcvtLHi2D(regD dst, regD src) %{ | |
4844 single_instruction; | |
4845 dst : X(write); | |
4846 src : E(read); | |
4847 FA : R; | |
4848 %} | |
4849 | |
4850 // Floating Point Convert L->D | |
4851 pipe_class fcvtL2D(regD dst, regF src) %{ | |
4852 single_instruction; | |
4853 dst : X(write); | |
4854 src : E(read); | |
4855 FA : R; | |
4856 %} | |
4857 | |
4858 // Floating Point Convert L->F | |
4859 pipe_class fcvtL2F(regD dst, regF src) %{ | |
4860 single_instruction; | |
4861 dst : X(write); | |
4862 src : E(read); | |
4863 FA : R; | |
4864 %} | |
4865 | |
4866 // Floating Point Convert D->F | |
4867 pipe_class fcvtD2F(regD dst, regF src) %{ | |
4868 single_instruction; | |
4869 dst : X(write); | |
4870 src : E(read); | |
4871 FA : R; | |
4872 %} | |
4873 | |
4874 // Floating Point Convert I->L | |
4875 pipe_class fcvtI2L(regD dst, regF src) %{ | |
4876 single_instruction; | |
4877 dst : X(write); | |
4878 src : E(read); | |
4879 FA : R; | |
4880 %} | |
4881 | |
4882 // Floating Point Convert D->F | |
4883 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ | |
4884 instruction_count(1); multiple_bundles; | |
4885 dst : X(write)+6; | |
4886 src : E(read); | |
4887 FA : R; | |
4888 %} | |
4889 | |
4890 // Floating Point Convert D->L | |
4891 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ | |
4892 instruction_count(1); multiple_bundles; | |
4893 dst : X(write)+6; | |
4894 src : E(read); | |
4895 FA : R; | |
4896 %} | |
4897 | |
4898 // Floating Point Convert F->I | |
4899 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ | |
4900 instruction_count(1); multiple_bundles; | |
4901 dst : X(write)+6; | |
4902 src : E(read); | |
4903 FA : R; | |
4904 %} | |
4905 | |
4906 // Floating Point Convert F->L | |
4907 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ | |
4908 instruction_count(1); multiple_bundles; | |
4909 dst : X(write)+6; | |
4910 src : E(read); | |
4911 FA : R; | |
4912 %} | |
4913 | |
4914 // Floating Point Convert I->F | |
4915 pipe_class fcvtI2F(regF dst, regF src) %{ | |
4916 single_instruction; | |
4917 dst : X(write); | |
4918 src : E(read); | |
4919 FA : R; | |
4920 %} | |
4921 | |
4922 // Floating Point Compare | |
4923 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ | |
4924 single_instruction; | |
4925 cr : X(write); | |
4926 src1 : E(read); | |
4927 src2 : E(read); | |
4928 FA : R; | |
4929 %} | |
4930 | |
4931 // Floating Point Compare | |
4932 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ | |
4933 single_instruction; | |
4934 cr : X(write); | |
4935 src1 : E(read); | |
4936 src2 : E(read); | |
4937 FA : R; | |
4938 %} | |
4939 | |
4940 // Floating Add Nop | |
4941 pipe_class fadd_nop() %{ | |
4942 single_instruction; | |
4943 FA : R; | |
4944 %} | |
4945 | |
4946 // Integer Store to Memory | |
4947 pipe_class istore_mem_reg(memory mem, iRegI src) %{ | |
4948 single_instruction; | |
4949 mem : R(read); | |
4950 src : C(read); | |
4951 MS : R; | |
4952 %} | |
4953 | |
4954 // Integer Store to Memory | |
4955 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ | |
4956 single_instruction; | |
4957 mem : R(read); | |
4958 src : C(read); | |
4959 MS : R; | |
4960 %} | |
4961 | |
4962 // Integer Store Zero to Memory | |
4963 pipe_class istore_mem_zero(memory mem, immI0 src) %{ | |
4964 single_instruction; | |
4965 mem : R(read); | |
4966 MS : R; | |
4967 %} | |
4968 | |
4969 // Special Stack Slot Store | |
4970 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ | |
4971 single_instruction; | |
4972 stkSlot : R(read); | |
4973 src : C(read); | |
4974 MS : R; | |
4975 %} | |
4976 | |
4977 // Special Stack Slot Store | |
4978 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ | |
4979 instruction_count(2); multiple_bundles; | |
4980 stkSlot : R(read); | |
4981 src : C(read); | |
4982 MS : R(2); | |
4983 %} | |
4984 | |
4985 // Float Store | |
4986 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ | |
4987 single_instruction; | |
4988 mem : R(read); | |
4989 src : C(read); | |
4990 MS : R; | |
4991 %} | |
4992 | |
4993 // Float Store | |
4994 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ | |
4995 single_instruction; | |
4996 mem : R(read); | |
4997 MS : R; | |
4998 %} | |
4999 | |
5000 // Double Store | |
5001 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ | |
5002 instruction_count(1); | |
5003 mem : R(read); | |
5004 src : C(read); | |
5005 MS : R; | |
5006 %} | |
5007 | |
5008 // Double Store | |
5009 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ | |
5010 single_instruction; | |
5011 mem : R(read); | |
5012 MS : R; | |
5013 %} | |
5014 | |
5015 // Special Stack Slot Float Store | |
5016 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ | |
5017 single_instruction; | |
5018 stkSlot : R(read); | |
5019 src : C(read); | |
5020 MS : R; | |
5021 %} | |
5022 | |
5023 // Special Stack Slot Double Store | |
5024 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ | |
5025 single_instruction; | |
5026 stkSlot : R(read); | |
5027 src : C(read); | |
5028 MS : R; | |
5029 %} | |
5030 | |
5031 // Integer Load (when sign bit propagation not needed) | |
5032 pipe_class iload_mem(iRegI dst, memory mem) %{ | |
5033 single_instruction; | |
5034 mem : R(read); | |
5035 dst : C(write); | |
5036 MS : R; | |
5037 %} | |
5038 | |
5039 // Integer Load from stack operand | |
5040 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ | |
5041 single_instruction; | |
5042 mem : R(read); | |
5043 dst : C(write); | |
5044 MS : R; | |
5045 %} | |
5046 | |
5047 // Integer Load (when sign bit propagation or masking is needed) | |
5048 pipe_class iload_mask_mem(iRegI dst, memory mem) %{ | |
5049 single_instruction; | |
5050 mem : R(read); | |
5051 dst : M(write); | |
5052 MS : R; | |
5053 %} | |
5054 | |
5055 // Float Load | |
5056 pipe_class floadF_mem(regF dst, memory mem) %{ | |
5057 single_instruction; | |
5058 mem : R(read); | |
5059 dst : M(write); | |
5060 MS : R; | |
5061 %} | |
5062 | |
5063 // Float Load | |
5064 pipe_class floadD_mem(regD dst, memory mem) %{ | |
5065 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case | |
5066 mem : R(read); | |
5067 dst : M(write); | |
5068 MS : R; | |
5069 %} | |
5070 | |
5071 // Float Load | |
5072 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ | |
5073 single_instruction; | |
5074 stkSlot : R(read); | |
5075 dst : M(write); | |
5076 MS : R; | |
5077 %} | |
5078 | |
5079 // Float Load | |
5080 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ | |
5081 single_instruction; | |
5082 stkSlot : R(read); | |
5083 dst : M(write); | |
5084 MS : R; | |
5085 %} | |
5086 | |
5087 // Memory Nop | |
5088 pipe_class mem_nop() %{ | |
5089 single_instruction; | |
5090 MS : R; | |
5091 %} | |
5092 | |
5093 pipe_class sethi(iRegP dst, immI src) %{ | |
5094 single_instruction; | |
5095 dst : E(write); | |
5096 IALU : R; | |
5097 %} | |
5098 | |
5099 pipe_class loadPollP(iRegP poll) %{ | |
5100 single_instruction; | |
5101 poll : R(read); | |
5102 MS : R; | |
5103 %} | |
5104 | |
5105 pipe_class br(Universe br, label labl) %{ | |
5106 single_instruction_with_delay_slot; | |
5107 BR : R; | |
5108 %} | |
5109 | |
5110 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ | |
5111 single_instruction_with_delay_slot; | |
5112 cr : E(read); | |
5113 BR : R; | |
5114 %} | |
5115 | |
5116 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ | |
5117 single_instruction_with_delay_slot; | |
5118 op1 : E(read); | |
5119 BR : R; | |
5120 MS : R; | |
5121 %} | |
5122 | |
5123 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ | |
5124 single_instruction_with_delay_slot; | |
5125 cr : E(read); | |
5126 BR : R; | |
5127 %} | |
5128 | |
5129 pipe_class br_nop() %{ | |
5130 single_instruction; | |
5131 BR : R; | |
5132 %} | |
5133 | |
5134 pipe_class simple_call(method meth) %{ | |
5135 instruction_count(2); multiple_bundles; force_serialization; | |
5136 fixed_latency(100); | |
5137 BR : R(1); | |
5138 MS : R(1); | |
5139 A0 : R(1); | |
5140 %} | |
5141 | |
5142 pipe_class compiled_call(method meth) %{ | |
5143 instruction_count(1); multiple_bundles; force_serialization; | |
5144 fixed_latency(100); | |
5145 MS : R(1); | |
5146 %} | |
5147 | |
5148 pipe_class call(method meth) %{ | |
5149 instruction_count(0); multiple_bundles; force_serialization; | |
5150 fixed_latency(100); | |
5151 %} | |
5152 | |
5153 pipe_class tail_call(Universe ignore, label labl) %{ | |
5154 single_instruction; has_delay_slot; | |
5155 fixed_latency(100); | |
5156 BR : R(1); | |
5157 MS : R(1); | |
5158 %} | |
5159 | |
5160 pipe_class ret(Universe ignore) %{ | |
5161 single_instruction; has_delay_slot; | |
5162 BR : R(1); | |
5163 MS : R(1); | |
5164 %} | |
5165 | |
5166 pipe_class ret_poll(g3RegP poll) %{ | |
5167 instruction_count(3); has_delay_slot; | |
5168 poll : E(read); | |
5169 MS : R; | |
5170 %} | |
5171 | |
5172 // The real do-nothing guy | |
5173 pipe_class empty( ) %{ | |
5174 instruction_count(0); | |
5175 %} | |
5176 | |
5177 pipe_class long_memory_op() %{ | |
5178 instruction_count(0); multiple_bundles; force_serialization; | |
5179 fixed_latency(25); | |
5180 MS : R(1); | |
5181 %} | |
5182 | |
5183 // Check-cast | |
5184 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ | |
5185 array : R(read); | |
5186 match : R(read); | |
5187 IALU : R(2); | |
5188 BR : R(2); | |
5189 MS : R; | |
5190 %} | |
5191 | |
5192 // Convert FPU flags into +1,0,-1 | |
5193 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ | |
5194 src1 : E(read); | |
5195 src2 : E(read); | |
5196 dst : E(write); | |
5197 FA : R; | |
5198 MS : R(2); | |
5199 BR : R(2); | |
5200 %} | |
5201 | |
5202 // Compare for p < q, and conditionally add y | |
5203 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ | |
5204 p : E(read); | |
5205 q : E(read); | |
5206 y : E(read); | |
5207 IALU : R(3) | |
5208 %} | |
5209 | |
5210 // Perform a compare, then move conditionally in a branch delay slot. | |
5211 pipe_class min_max( iRegI src2, iRegI srcdst ) %{ | |
5212 src2 : E(read); | |
5213 srcdst : E(read); | |
5214 IALU : R; | |
5215 BR : R; | |
5216 %} | |
5217 | |
5218 // Define the class for the Nop node | |
5219 define %{ | |
5220 MachNop = ialu_nop; | |
5221 %} | |
5222 | |
5223 %} | |
5224 | |
5225 //----------INSTRUCTIONS------------------------------------------------------- | |
5226 | |
5227 //------------Special Stack Slot instructions - no match rules----------------- | |
5228 instruct stkI_to_regF(regF dst, stackSlotI src) %{ | |
5229 // No match rule to avoid chain rule match. | |
5230 effect(DEF dst, USE src); | |
5231 ins_cost(MEMORY_REF_COST); | |
5232 size(4); | |
5233 format %{ "LDF $src,$dst\t! stkI to regF" %} | |
5234 opcode(Assembler::ldf_op3); | |
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5235 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5236 ins_pipe(floadF_stk); |
5237 %} | |
5238 | |
5239 instruct stkL_to_regD(regD dst, stackSlotL src) %{ | |
5240 // No match rule to avoid chain rule match. | |
5241 effect(DEF dst, USE src); | |
5242 ins_cost(MEMORY_REF_COST); | |
5243 size(4); | |
5244 format %{ "LDDF $src,$dst\t! stkL to regD" %} | |
5245 opcode(Assembler::lddf_op3); | |
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5246 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 5247 ins_pipe(floadD_stk); |
5248 %} | |
5249 | |
5250 instruct regF_to_stkI(stackSlotI dst, regF src) %{ | |
5251 // No match rule to avoid chain rule match. | |
5252 effect(DEF dst, USE src); | |
5253 ins_cost(MEMORY_REF_COST); | |
5254 size(4); | |
5255 format %{ "STF $src,$dst\t! regF to stkI" %} | |
5256 opcode(Assembler::stf_op3); | |
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5257 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5258 ins_pipe(fstoreF_stk_reg); |
5259 %} | |
5260 | |
5261 instruct regD_to_stkL(stackSlotL dst, regD src) %{ | |
5262 // No match rule to avoid chain rule match. | |
5263 effect(DEF dst, USE src); | |
5264 ins_cost(MEMORY_REF_COST); | |
5265 size(4); | |
5266 format %{ "STDF $src,$dst\t! regD to stkL" %} | |
5267 opcode(Assembler::stdf_op3); | |
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5268 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 5269 ins_pipe(fstoreD_stk_reg); |
5270 %} | |
5271 | |
5272 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ | |
5273 effect(DEF dst, USE src); | |
5274 ins_cost(MEMORY_REF_COST*2); | |
5275 size(8); | |
5276 format %{ "STW $src,$dst.hi\t! long\n\t" | |
5277 "STW R_G0,$dst.lo" %} | |
5278 opcode(Assembler::stw_op3); | |
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5279 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); |
0 | 5280 ins_pipe(lstoreI_stk_reg); |
5281 %} | |
5282 | |
5283 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ | |
5284 // No match rule to avoid chain rule match. | |
5285 effect(DEF dst, USE src); | |
5286 ins_cost(MEMORY_REF_COST); | |
5287 size(4); | |
5288 format %{ "STX $src,$dst\t! regL to stkD" %} | |
5289 opcode(Assembler::stx_op3); | |
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5290 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5291 ins_pipe(istore_stk_reg); |
5292 %} | |
5293 | |
5294 //---------- Chain stack slots between similar types -------- | |
5295 | |
5296 // Load integer from stack slot | |
5297 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ | |
5298 match(Set dst src); | |
5299 ins_cost(MEMORY_REF_COST); | |
5300 | |
5301 size(4); | |
5302 format %{ "LDUW $src,$dst\t!stk" %} | |
5303 opcode(Assembler::lduw_op3); | |
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5304 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5305 ins_pipe(iload_mem); |
5306 %} | |
5307 | |
5308 // Store integer to stack slot | |
5309 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ | |
5310 match(Set dst src); | |
5311 ins_cost(MEMORY_REF_COST); | |
5312 | |
5313 size(4); | |
5314 format %{ "STW $src,$dst\t!stk" %} | |
5315 opcode(Assembler::stw_op3); | |
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5316 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5317 ins_pipe(istore_mem_reg); |
5318 %} | |
5319 | |
5320 // Load long from stack slot | |
5321 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ | |
5322 match(Set dst src); | |
5323 | |
5324 ins_cost(MEMORY_REF_COST); | |
5325 size(4); | |
5326 format %{ "LDX $src,$dst\t! long" %} | |
5327 opcode(Assembler::ldx_op3); | |
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5328 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5329 ins_pipe(iload_mem); |
5330 %} | |
5331 | |
5332 // Store long to stack slot | |
5333 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ | |
5334 match(Set dst src); | |
5335 | |
5336 ins_cost(MEMORY_REF_COST); | |
5337 size(4); | |
5338 format %{ "STX $src,$dst\t! long" %} | |
5339 opcode(Assembler::stx_op3); | |
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5340 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5341 ins_pipe(istore_mem_reg); |
5342 %} | |
5343 | |
5344 #ifdef _LP64 | |
5345 // Load pointer from stack slot, 64-bit encoding | |
5346 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5347 match(Set dst src); | |
5348 ins_cost(MEMORY_REF_COST); | |
5349 size(4); | |
5350 format %{ "LDX $src,$dst\t!ptr" %} | |
5351 opcode(Assembler::ldx_op3); | |
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5352 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5353 ins_pipe(iload_mem); |
5354 %} | |
5355 | |
5356 // Store pointer to stack slot | |
5357 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5358 match(Set dst src); | |
5359 ins_cost(MEMORY_REF_COST); | |
5360 size(4); | |
5361 format %{ "STX $src,$dst\t!ptr" %} | |
5362 opcode(Assembler::stx_op3); | |
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5363 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5364 ins_pipe(istore_mem_reg); |
5365 %} | |
5366 #else // _LP64 | |
5367 // Load pointer from stack slot, 32-bit encoding | |
5368 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ | |
5369 match(Set dst src); | |
5370 ins_cost(MEMORY_REF_COST); | |
5371 format %{ "LDUW $src,$dst\t!ptr" %} | |
5372 opcode(Assembler::lduw_op3, Assembler::ldst_op); | |
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5373 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 5374 ins_pipe(iload_mem); |
5375 %} | |
5376 | |
5377 // Store pointer to stack slot | |
5378 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ | |
5379 match(Set dst src); | |
5380 ins_cost(MEMORY_REF_COST); | |
5381 format %{ "STW $src,$dst\t!ptr" %} | |
5382 opcode(Assembler::stw_op3, Assembler::ldst_op); | |
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5383 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 5384 ins_pipe(istore_mem_reg); |
5385 %} | |
5386 #endif // _LP64 | |
5387 | |
5388 //------------Special Nop instructions for bundling - no match rules----------- | |
5389 // Nop using the A0 functional unit | |
5390 instruct Nop_A0() %{ | |
5391 ins_cost(0); | |
5392 | |
5393 format %{ "NOP ! Alu Pipeline" %} | |
5394 opcode(Assembler::or_op3, Assembler::arith_op); | |
5395 ins_encode( form2_nop() ); | |
5396 ins_pipe(ialu_nop_A0); | |
5397 %} | |
5398 | |
5399 // Nop using the A1 functional unit | |
5400 instruct Nop_A1( ) %{ | |
5401 ins_cost(0); | |
5402 | |
5403 format %{ "NOP ! Alu Pipeline" %} | |
5404 opcode(Assembler::or_op3, Assembler::arith_op); | |
5405 ins_encode( form2_nop() ); | |
5406 ins_pipe(ialu_nop_A1); | |
5407 %} | |
5408 | |
5409 // Nop using the memory functional unit | |
5410 instruct Nop_MS( ) %{ | |
5411 ins_cost(0); | |
5412 | |
5413 format %{ "NOP ! Memory Pipeline" %} | |
5414 ins_encode( emit_mem_nop ); | |
5415 ins_pipe(mem_nop); | |
5416 %} | |
5417 | |
5418 // Nop using the floating add functional unit | |
5419 instruct Nop_FA( ) %{ | |
5420 ins_cost(0); | |
5421 | |
5422 format %{ "NOP ! Floating Add Pipeline" %} | |
5423 ins_encode( emit_fadd_nop ); | |
5424 ins_pipe(fadd_nop); | |
5425 %} | |
5426 | |
5427 // Nop using the branch functional unit | |
5428 instruct Nop_BR( ) %{ | |
5429 ins_cost(0); | |
5430 | |
5431 format %{ "NOP ! Branch Pipeline" %} | |
5432 ins_encode( emit_br_nop ); | |
5433 ins_pipe(br_nop); | |
5434 %} | |
5435 | |
5436 //----------Load/Store/Move Instructions--------------------------------------- | |
5437 //----------Load Instructions-------------------------------------------------- | |
5438 // Load Byte (8bit signed) | |
5439 instruct loadB(iRegI dst, memory mem) %{ | |
5440 match(Set dst (LoadB mem)); | |
5441 ins_cost(MEMORY_REF_COST); | |
5442 | |
5443 size(4); | |
624 | 5444 format %{ "LDSB $mem,$dst\t! byte" %} |
727 | 5445 ins_encode %{ |
5446 __ ldsb($mem$$Address, $dst$$Register); | |
5447 %} | |
624 | 5448 ins_pipe(iload_mask_mem); |
5449 %} | |
5450 | |
5451 // Load Byte (8bit signed) into a Long Register | |
5452 instruct loadB2L(iRegL dst, memory mem) %{ | |
5453 match(Set dst (ConvI2L (LoadB mem))); | |
5454 ins_cost(MEMORY_REF_COST); | |
5455 | |
5456 size(4); | |
5457 format %{ "LDSB $mem,$dst\t! byte -> long" %} | |
727 | 5458 ins_encode %{ |
5459 __ ldsb($mem$$Address, $dst$$Register); | |
5460 %} | |
0 | 5461 ins_pipe(iload_mask_mem); |
5462 %} | |
5463 | |
624 | 5464 // Load Unsigned Byte (8bit UNsigned) into an int reg |
5465 instruct loadUB(iRegI dst, memory mem) %{ | |
5466 match(Set dst (LoadUB mem)); | |
0 | 5467 ins_cost(MEMORY_REF_COST); |
5468 | |
5469 size(4); | |
624 | 5470 format %{ "LDUB $mem,$dst\t! ubyte" %} |
727 | 5471 ins_encode %{ |
5472 __ ldub($mem$$Address, $dst$$Register); | |
5473 %} | |
824 | 5474 ins_pipe(iload_mem); |
624 | 5475 %} |
5476 | |
5477 // Load Unsigned Byte (8bit UNsigned) into a Long Register | |
5478 instruct loadUB2L(iRegL dst, memory mem) %{ | |
5479 match(Set dst (ConvI2L (LoadUB mem))); | |
5480 ins_cost(MEMORY_REF_COST); | |
5481 | |
5482 size(4); | |
5483 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} | |
727 | 5484 ins_encode %{ |
5485 __ ldub($mem$$Address, $dst$$Register); | |
5486 %} | |
824 | 5487 ins_pipe(iload_mem); |
5488 %} | |
5489 | |
5490 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register | |
5491 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ | |
5492 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
5493 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5494 | |
5495 size(2*4); | |
5496 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" | |
5497 "AND $dst,$mask,$dst" %} | |
5498 ins_encode %{ | |
5499 __ ldub($mem$$Address, $dst$$Register); | |
5500 __ and3($dst$$Register, $mask$$constant, $dst$$Register); | |
5501 %} | |
5502 ins_pipe(iload_mem); | |
0 | 5503 %} |
5504 | |
624 | 5505 // Load Short (16bit signed) |
5506 instruct loadS(iRegI dst, memory mem) %{ | |
5507 match(Set dst (LoadS mem)); | |
5508 ins_cost(MEMORY_REF_COST); | |
5509 | |
5510 size(4); | |
5511 format %{ "LDSH $mem,$dst\t! short" %} | |
727 | 5512 ins_encode %{ |
5513 __ ldsh($mem$$Address, $dst$$Register); | |
5514 %} | |
624 | 5515 ins_pipe(iload_mask_mem); |
5516 %} | |
5517 | |
785 | 5518 // Load Short (16 bit signed) to Byte (8 bit signed) |
5519 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5520 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
5521 ins_cost(MEMORY_REF_COST); | |
5522 | |
5523 size(4); | |
5524 | |
5525 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} | |
5526 ins_encode %{ | |
5527 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5528 %} | |
5529 ins_pipe(iload_mask_mem); | |
5530 %} | |
5531 | |
624 | 5532 // Load Short (16bit signed) into a Long Register |
5533 instruct loadS2L(iRegL dst, memory mem) %{ | |
5534 match(Set dst (ConvI2L (LoadS mem))); | |
0 | 5535 ins_cost(MEMORY_REF_COST); |
5536 | |
5537 size(4); | |
624 | 5538 format %{ "LDSH $mem,$dst\t! short -> long" %} |
727 | 5539 ins_encode %{ |
5540 __ ldsh($mem$$Address, $dst$$Register); | |
5541 %} | |
624 | 5542 ins_pipe(iload_mask_mem); |
5543 %} | |
5544 | |
5545 // Load Unsigned Short/Char (16bit UNsigned) | |
5546 instruct loadUS(iRegI dst, memory mem) %{ | |
5547 match(Set dst (LoadUS mem)); | |
5548 ins_cost(MEMORY_REF_COST); | |
5549 | |
5550 size(4); | |
5551 format %{ "LDUH $mem,$dst\t! ushort/char" %} | |
727 | 5552 ins_encode %{ |
5553 __ lduh($mem$$Address, $dst$$Register); | |
5554 %} | |
824 | 5555 ins_pipe(iload_mem); |
0 | 5556 %} |
5557 | |
785 | 5558 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
5559 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5560 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
5561 ins_cost(MEMORY_REF_COST); | |
5562 | |
5563 size(4); | |
5564 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} | |
5565 ins_encode %{ | |
5566 __ ldsb($mem$$Address, $dst$$Register, 1); | |
5567 %} | |
5568 ins_pipe(iload_mask_mem); | |
5569 %} | |
5570 | |
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diff
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|
5571 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register |
624 | 5572 instruct loadUS2L(iRegL dst, memory mem) %{ |
5573 match(Set dst (ConvI2L (LoadUS mem))); | |
0 | 5574 ins_cost(MEMORY_REF_COST); |
5575 | |
5576 size(4); | |
624 | 5577 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} |
727 | 5578 ins_encode %{ |
5579 __ lduh($mem$$Address, $dst$$Register); | |
5580 %} | |
824 | 5581 ins_pipe(iload_mem); |
5582 %} | |
5583 | |
5584 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register | |
5585 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5586 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5587 ins_cost(MEMORY_REF_COST); | |
5588 | |
5589 size(4); | |
5590 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} | |
5591 ins_encode %{ | |
5592 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE | |
5593 %} | |
5594 ins_pipe(iload_mem); | |
5595 %} | |
5596 | |
5597 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register | |
5598 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5599 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5600 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5601 | |
5602 size(2*4); | |
5603 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" | |
5604 "AND $dst,$mask,$dst" %} | |
5605 ins_encode %{ | |
5606 Register Rdst = $dst$$Register; | |
5607 __ lduh($mem$$Address, Rdst); | |
5608 __ and3(Rdst, $mask$$constant, Rdst); | |
5609 %} | |
5610 ins_pipe(iload_mem); | |
5611 %} | |
5612 | |
5613 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register | |
5614 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ | |
5615 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
5616 effect(TEMP dst, TEMP tmp); | |
5617 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5618 | |
951
1fbd5d696bf4
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824
diff
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|
5619 size((3+1)*4); // set may use two instructions. |
824 | 5620 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" |
5621 "SET $mask,$tmp\n\t" | |
5622 "AND $dst,$tmp,$dst" %} | |
5623 ins_encode %{ | |
5624 Register Rdst = $dst$$Register; | |
5625 Register Rtmp = $tmp$$Register; | |
5626 __ lduh($mem$$Address, Rdst); | |
5627 __ set($mask$$constant, Rtmp); | |
5628 __ and3(Rdst, Rtmp, Rdst); | |
5629 %} | |
5630 ins_pipe(iload_mem); | |
0 | 5631 %} |
5632 | |
5633 // Load Integer | |
5634 instruct loadI(iRegI dst, memory mem) %{ | |
5635 match(Set dst (LoadI mem)); | |
5636 ins_cost(MEMORY_REF_COST); | |
624 | 5637 |
5638 size(4); | |
5639 format %{ "LDUW $mem,$dst\t! int" %} | |
727 | 5640 ins_encode %{ |
5641 __ lduw($mem$$Address, $dst$$Register); | |
5642 %} | |
624 | 5643 ins_pipe(iload_mem); |
5644 %} | |
5645 | |
785 | 5646 // Load Integer to Byte (8 bit signed) |
5647 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ | |
5648 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
5649 ins_cost(MEMORY_REF_COST); | |
5650 | |
5651 size(4); | |
5652 | |
5653 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} | |
5654 ins_encode %{ | |
5655 __ ldsb($mem$$Address, $dst$$Register, 3); | |
5656 %} | |
5657 ins_pipe(iload_mask_mem); | |
5658 %} | |
5659 | |
5660 // Load Integer to Unsigned Byte (8 bit UNsigned) | |
5661 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ | |
5662 match(Set dst (AndI (LoadI mem) mask)); | |
5663 ins_cost(MEMORY_REF_COST); | |
5664 | |
5665 size(4); | |
5666 | |
5667 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} | |
5668 ins_encode %{ | |
5669 __ ldub($mem$$Address, $dst$$Register, 3); | |
5670 %} | |
5671 ins_pipe(iload_mask_mem); | |
5672 %} | |
5673 | |
5674 // Load Integer to Short (16 bit signed) | |
5675 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ | |
5676 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
5677 ins_cost(MEMORY_REF_COST); | |
5678 | |
5679 size(4); | |
5680 | |
5681 format %{ "LDSH $mem+2,$dst\t! int -> short" %} | |
5682 ins_encode %{ | |
5683 __ ldsh($mem$$Address, $dst$$Register, 2); | |
5684 %} | |
5685 ins_pipe(iload_mask_mem); | |
5686 %} | |
5687 | |
5688 // Load Integer to Unsigned Short (16 bit UNsigned) | |
5689 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5690 match(Set dst (AndI (LoadI mem) mask)); | |
5691 ins_cost(MEMORY_REF_COST); | |
5692 | |
5693 size(4); | |
5694 | |
5695 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} | |
5696 ins_encode %{ | |
5697 __ lduh($mem$$Address, $dst$$Register, 2); | |
5698 %} | |
5699 ins_pipe(iload_mask_mem); | |
5700 %} | |
5701 | |
624 | 5702 // Load Integer into a Long Register |
5703 instruct loadI2L(iRegL dst, memory mem) %{ | |
5704 match(Set dst (ConvI2L (LoadI mem))); | |
5705 ins_cost(MEMORY_REF_COST); | |
5706 | |
5707 size(4); | |
5708 format %{ "LDSW $mem,$dst\t! int -> long" %} | |
727 | 5709 ins_encode %{ |
5710 __ ldsw($mem$$Address, $dst$$Register); | |
5711 %} | |
824 | 5712 ins_pipe(iload_mask_mem); |
5713 %} | |
5714 | |
5715 // Load Integer with mask 0xFF into a Long Register | |
5716 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ | |
5717 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5718 ins_cost(MEMORY_REF_COST); | |
5719 | |
5720 size(4); | |
5721 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} | |
5722 ins_encode %{ | |
5723 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE | |
5724 %} | |
5725 ins_pipe(iload_mem); | |
5726 %} | |
5727 | |
5728 // Load Integer with mask 0xFFFF into a Long Register | |
5729 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ | |
5730 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5731 ins_cost(MEMORY_REF_COST); | |
5732 | |
5733 size(4); | |
5734 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} | |
5735 ins_encode %{ | |
5736 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE | |
5737 %} | |
5738 ins_pipe(iload_mem); | |
5739 %} | |
5740 | |
5741 // Load Integer with a 13-bit mask into a Long Register | |
5742 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ | |
5743 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5744 ins_cost(MEMORY_REF_COST + DEFAULT_COST); | |
5745 | |
5746 size(2*4); | |
5747 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" | |
5748 "AND $dst,$mask,$dst" %} | |
5749 ins_encode %{ | |
5750 Register Rdst = $dst$$Register; | |
5751 __ lduw($mem$$Address, Rdst); | |
5752 __ and3(Rdst, $mask$$constant, Rdst); | |
5753 %} | |
5754 ins_pipe(iload_mem); | |
5755 %} | |
5756 | |
5757 // Load Integer with a 32-bit mask into a Long Register | |
5758 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ | |
5759 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
5760 effect(TEMP dst, TEMP tmp); | |
5761 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); | |
5762 | |
951
1fbd5d696bf4
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824
diff
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|
5763 size((3+1)*4); // set may use two instructions. |
824 | 5764 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" |
5765 "SET $mask,$tmp\n\t" | |
5766 "AND $dst,$tmp,$dst" %} | |
5767 ins_encode %{ | |
5768 Register Rdst = $dst$$Register; | |
5769 Register Rtmp = $tmp$$Register; | |
5770 __ lduw($mem$$Address, Rdst); | |
5771 __ set($mask$$constant, Rtmp); | |
5772 __ and3(Rdst, Rtmp, Rdst); | |
5773 %} | |
624 | 5774 ins_pipe(iload_mem); |
5775 %} | |
5776 | |
5777 // Load Unsigned Integer into a Long Register | |
5778 instruct loadUI2L(iRegL dst, memory mem) %{ | |
5779 match(Set dst (LoadUI2L mem)); | |
5780 ins_cost(MEMORY_REF_COST); | |
5781 | |
5782 size(4); | |
5783 format %{ "LDUW $mem,$dst\t! uint -> long" %} | |
727 | 5784 ins_encode %{ |
5785 __ lduw($mem$$Address, $dst$$Register); | |
5786 %} | |
0 | 5787 ins_pipe(iload_mem); |
5788 %} | |
5789 | |
5790 // Load Long - aligned | |
5791 instruct loadL(iRegL dst, memory mem ) %{ | |
5792 match(Set dst (LoadL mem)); | |
5793 ins_cost(MEMORY_REF_COST); | |
624 | 5794 |
0 | 5795 size(4); |
5796 format %{ "LDX $mem,$dst\t! long" %} | |
727 | 5797 ins_encode %{ |
5798 __ ldx($mem$$Address, $dst$$Register); | |
5799 %} | |
0 | 5800 ins_pipe(iload_mem); |
5801 %} | |
5802 | |
5803 // Load Long - UNaligned | |
5804 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ | |
5805 match(Set dst (LoadL_unaligned mem)); | |
5806 effect(KILL tmp); | |
5807 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5808 size(16); | |
5809 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" | |
5810 "\tLDUW $mem ,$dst\n" | |
5811 "\tSLLX #32, $dst, $dst\n" | |
5812 "\tOR $dst, R_O7, $dst" %} | |
5813 opcode(Assembler::lduw_op3); | |
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235
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|
5814 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); |
0 | 5815 ins_pipe(iload_mem); |
5816 %} | |
5817 | |
5818 // Load Aligned Packed Byte into a Double Register | |
5819 instruct loadA8B(regD dst, memory mem) %{ | |
5820 match(Set dst (Load8B mem)); | |
5821 ins_cost(MEMORY_REF_COST); | |
5822 size(4); | |
5823 format %{ "LDDF $mem,$dst\t! packed8B" %} | |
5824 opcode(Assembler::lddf_op3); | |
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4d9884b01ba6
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235
diff
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|
5825 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5826 ins_pipe(floadD_mem); |
5827 %} | |
5828 | |
5829 // Load Aligned Packed Char into a Double Register | |
5830 instruct loadA4C(regD dst, memory mem) %{ | |
5831 match(Set dst (Load4C mem)); | |
5832 ins_cost(MEMORY_REF_COST); | |
5833 size(4); | |
5834 format %{ "LDDF $mem,$dst\t! packed4C" %} | |
5835 opcode(Assembler::lddf_op3); | |
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235
diff
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|
5836 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5837 ins_pipe(floadD_mem); |
5838 %} | |
5839 | |
5840 // Load Aligned Packed Short into a Double Register | |
5841 instruct loadA4S(regD dst, memory mem) %{ | |
5842 match(Set dst (Load4S mem)); | |
5843 ins_cost(MEMORY_REF_COST); | |
5844 size(4); | |
5845 format %{ "LDDF $mem,$dst\t! packed4S" %} | |
5846 opcode(Assembler::lddf_op3); | |
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235
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|
5847 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5848 ins_pipe(floadD_mem); |
5849 %} | |
5850 | |
5851 // Load Aligned Packed Int into a Double Register | |
5852 instruct loadA2I(regD dst, memory mem) %{ | |
5853 match(Set dst (Load2I mem)); | |
5854 ins_cost(MEMORY_REF_COST); | |
5855 size(4); | |
5856 format %{ "LDDF $mem,$dst\t! packed2I" %} | |
5857 opcode(Assembler::lddf_op3); | |
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235
diff
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|
5858 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5859 ins_pipe(floadD_mem); |
5860 %} | |
5861 | |
5862 // Load Range | |
5863 instruct loadRange(iRegI dst, memory mem) %{ | |
5864 match(Set dst (LoadRange mem)); | |
5865 ins_cost(MEMORY_REF_COST); | |
5866 | |
5867 size(4); | |
5868 format %{ "LDUW $mem,$dst\t! range" %} | |
5869 opcode(Assembler::lduw_op3); | |
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235
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|
5870 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5871 ins_pipe(iload_mem); |
5872 %} | |
5873 | |
5874 // Load Integer into %f register (for fitos/fitod) | |
5875 instruct loadI_freg(regF dst, memory mem) %{ | |
5876 match(Set dst (LoadI mem)); | |
5877 ins_cost(MEMORY_REF_COST); | |
5878 size(4); | |
5879 | |
5880 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} | |
5881 opcode(Assembler::ldf_op3); | |
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|
5882 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5883 ins_pipe(floadF_mem); |
5884 %} | |
5885 | |
5886 // Load Pointer | |
5887 instruct loadP(iRegP dst, memory mem) %{ | |
5888 match(Set dst (LoadP mem)); | |
5889 ins_cost(MEMORY_REF_COST); | |
5890 size(4); | |
5891 | |
5892 #ifndef _LP64 | |
5893 format %{ "LDUW $mem,$dst\t! ptr" %} | |
727 | 5894 ins_encode %{ |
5895 __ lduw($mem$$Address, $dst$$Register); | |
5896 %} | |
0 | 5897 #else |
5898 format %{ "LDX $mem,$dst\t! ptr" %} | |
727 | 5899 ins_encode %{ |
5900 __ ldx($mem$$Address, $dst$$Register); | |
5901 %} | |
0 | 5902 #endif |
5903 ins_pipe(iload_mem); | |
5904 %} | |
5905 | |
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|
5906 // Load Compressed Pointer |
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|
5907 instruct loadN(iRegN dst, memory mem) %{ |
727 | 5908 match(Set dst (LoadN mem)); |
5909 ins_cost(MEMORY_REF_COST); | |
5910 size(4); | |
5911 | |
5912 format %{ "LDUW $mem,$dst\t! compressed ptr" %} | |
5913 ins_encode %{ | |
5914 __ lduw($mem$$Address, $dst$$Register); | |
5915 %} | |
5916 ins_pipe(iload_mem); | |
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|
5917 %} |
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|
5918 |
0 | 5919 // Load Klass Pointer |
5920 instruct loadKlass(iRegP dst, memory mem) %{ | |
5921 match(Set dst (LoadKlass mem)); | |
5922 ins_cost(MEMORY_REF_COST); | |
5923 size(4); | |
5924 | |
5925 #ifndef _LP64 | |
5926 format %{ "LDUW $mem,$dst\t! klass ptr" %} | |
727 | 5927 ins_encode %{ |
5928 __ lduw($mem$$Address, $dst$$Register); | |
5929 %} | |
0 | 5930 #else |
5931 format %{ "LDX $mem,$dst\t! klass ptr" %} | |
727 | 5932 ins_encode %{ |
5933 __ ldx($mem$$Address, $dst$$Register); | |
5934 %} | |
0 | 5935 #endif |
5936 ins_pipe(iload_mem); | |
5937 %} | |
5938 | |
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|
5939 // Load narrow Klass Pointer |
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|
5940 instruct loadNKlass(iRegN dst, memory mem) %{ |
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|
5941 match(Set dst (LoadNKlass mem)); |
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|
5942 ins_cost(MEMORY_REF_COST); |
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5943 size(4); |
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5944 |
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5945 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} |
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5946 ins_encode %{ |
727 | 5947 __ lduw($mem$$Address, $dst$$Register); |
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5948 %} |
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5949 ins_pipe(iload_mem); |
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5950 %} |
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5951 |
0 | 5952 // Load Double |
5953 instruct loadD(regD dst, memory mem) %{ | |
5954 match(Set dst (LoadD mem)); | |
5955 ins_cost(MEMORY_REF_COST); | |
5956 | |
5957 size(4); | |
5958 format %{ "LDDF $mem,$dst" %} | |
5959 opcode(Assembler::lddf_op3); | |
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5960 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5961 ins_pipe(floadD_mem); |
5962 %} | |
5963 | |
5964 // Load Double - UNaligned | |
5965 instruct loadD_unaligned(regD_low dst, memory mem ) %{ | |
5966 match(Set dst (LoadD_unaligned mem)); | |
5967 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); | |
5968 size(8); | |
5969 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" | |
5970 "\tLDF $mem+4,$dst.lo\t!" %} | |
5971 opcode(Assembler::ldf_op3); | |
5972 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); | |
5973 ins_pipe(iload_mem); | |
5974 %} | |
5975 | |
5976 // Load Float | |
5977 instruct loadF(regF dst, memory mem) %{ | |
5978 match(Set dst (LoadF mem)); | |
5979 ins_cost(MEMORY_REF_COST); | |
5980 | |
5981 size(4); | |
5982 format %{ "LDF $mem,$dst" %} | |
5983 opcode(Assembler::ldf_op3); | |
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5984 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 5985 ins_pipe(floadF_mem); |
5986 %} | |
5987 | |
5988 // Load Constant | |
5989 instruct loadConI( iRegI dst, immI src ) %{ | |
5990 match(Set dst src); | |
5991 ins_cost(DEFAULT_COST * 3/2); | |
5992 format %{ "SET $src,$dst" %} | |
5993 ins_encode( Set32(src, dst) ); | |
5994 ins_pipe(ialu_hi_lo_reg); | |
5995 %} | |
5996 | |
5997 instruct loadConI13( iRegI dst, immI13 src ) %{ | |
5998 match(Set dst src); | |
5999 | |
6000 size(4); | |
6001 format %{ "MOV $src,$dst" %} | |
6002 ins_encode( Set13( src, dst ) ); | |
6003 ins_pipe(ialu_imm); | |
6004 %} | |
6005 | |
6006 instruct loadConP(iRegP dst, immP src) %{ | |
6007 match(Set dst src); | |
6008 ins_cost(DEFAULT_COST * 3/2); | |
6009 format %{ "SET $src,$dst\t!ptr" %} | |
6010 // This rule does not use "expand" unlike loadConI because then | |
6011 // the result type is not known to be an Oop. An ADLC | |
6012 // enhancement will be needed to make that work - not worth it! | |
6013 | |
6014 ins_encode( SetPtr( src, dst ) ); | |
6015 ins_pipe(loadConP); | |
6016 | |
6017 %} | |
6018 | |
6019 instruct loadConP0(iRegP dst, immP0 src) %{ | |
6020 match(Set dst src); | |
6021 | |
6022 size(4); | |
6023 format %{ "CLR $dst\t!ptr" %} | |
6024 ins_encode( SetNull( dst ) ); | |
6025 ins_pipe(ialu_imm); | |
6026 %} | |
6027 | |
6028 instruct loadConP_poll(iRegP dst, immP_poll src) %{ | |
6029 match(Set dst src); | |
6030 ins_cost(DEFAULT_COST); | |
6031 format %{ "SET $src,$dst\t!ptr" %} | |
6032 ins_encode %{ | |
727 | 6033 AddressLiteral polling_page(os::get_polling_page()); |
6034 __ sethi(polling_page, reg_to_register_object($dst$$reg)); | |
0 | 6035 %} |
6036 ins_pipe(loadConP_poll); | |
6037 %} | |
6038 | |
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6039 instruct loadConN0(iRegN dst, immN0 src) %{ |
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6040 match(Set dst src); |
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6041 |
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6042 size(4); |
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6043 format %{ "CLR $dst\t! compressed NULL ptr" %} |
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6044 ins_encode( SetNull( dst ) ); |
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6045 ins_pipe(ialu_imm); |
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6046 %} |
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6047 |
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6048 instruct loadConN(iRegN dst, immN src) %{ |
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6049 match(Set dst src); |
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6050 ins_cost(DEFAULT_COST * 3/2); |
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6051 format %{ "SET $src,$dst\t! compressed ptr" %} |
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6052 ins_encode %{ |
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6053 Register dst = $dst$$Register; |
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6054 __ set_narrow_oop((jobject)$src$$constant, dst); |
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6055 %} |
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6056 ins_pipe(ialu_hi_lo_reg); |
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6057 %} |
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6058 |
0 | 6059 instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ |
6060 // %%% maybe this should work like loadConD | |
6061 match(Set dst src); | |
6062 effect(KILL tmp); | |
6063 ins_cost(DEFAULT_COST * 4); | |
6064 format %{ "SET64 $src,$dst KILL $tmp\t! long" %} | |
6065 ins_encode( LdImmL(src, dst, tmp) ); | |
6066 ins_pipe(loadConL); | |
6067 %} | |
6068 | |
6069 instruct loadConL0( iRegL dst, immL0 src ) %{ | |
6070 match(Set dst src); | |
6071 ins_cost(DEFAULT_COST); | |
6072 size(4); | |
6073 format %{ "CLR $dst\t! long" %} | |
6074 ins_encode( Set13( src, dst ) ); | |
6075 ins_pipe(ialu_imm); | |
6076 %} | |
6077 | |
6078 instruct loadConL13( iRegL dst, immL13 src ) %{ | |
6079 match(Set dst src); | |
6080 ins_cost(DEFAULT_COST * 2); | |
6081 | |
6082 size(4); | |
6083 format %{ "MOV $src,$dst\t! long" %} | |
6084 ins_encode( Set13( src, dst ) ); | |
6085 ins_pipe(ialu_imm); | |
6086 %} | |
6087 | |
6088 instruct loadConF(regF dst, immF src, o7RegP tmp) %{ | |
6089 match(Set dst src); | |
6090 effect(KILL tmp); | |
6091 | |
6092 #ifdef _LP64 | |
727 | 6093 size(8*4); |
0 | 6094 #else |
727 | 6095 size(2*4); |
0 | 6096 #endif |
6097 | |
6098 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" | |
6099 "LDF [$tmp+lo(&$src)],$dst" %} | |
727 | 6100 ins_encode %{ |
6101 address float_address = __ float_constant($src$$constant); | |
6102 RelocationHolder rspec = internal_word_Relocation::spec(float_address); | |
6103 AddressLiteral addrlit(float_address, rspec); | |
6104 | |
6105 __ sethi(addrlit, $tmp$$Register); | |
6106 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); | |
6107 %} | |
0 | 6108 ins_pipe(loadConFD); |
6109 %} | |
6110 | |
6111 instruct loadConD(regD dst, immD src, o7RegP tmp) %{ | |
6112 match(Set dst src); | |
6113 effect(KILL tmp); | |
6114 | |
6115 #ifdef _LP64 | |
727 | 6116 size(8*4); |
0 | 6117 #else |
727 | 6118 size(2*4); |
0 | 6119 #endif |
6120 | |
6121 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" | |
6122 "LDDF [$tmp+lo(&$src)],$dst" %} | |
727 | 6123 ins_encode %{ |
6124 address double_address = __ double_constant($src$$constant); | |
6125 RelocationHolder rspec = internal_word_Relocation::spec(double_address); | |
6126 AddressLiteral addrlit(double_address, rspec); | |
6127 | |
6128 __ sethi(addrlit, $tmp$$Register); | |
732
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6129 // XXX This is a quick fix for 6833573. |
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6130 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); |
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6131 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); |
727 | 6132 %} |
0 | 6133 ins_pipe(loadConFD); |
6134 %} | |
6135 | |
6136 // Prefetch instructions. | |
6137 // Must be safe to execute with invalid address (cannot fault). | |
6138 | |
6139 instruct prefetchr( memory mem ) %{ | |
6140 match( PrefetchRead mem ); | |
6141 ins_cost(MEMORY_REF_COST); | |
6142 | |
6143 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} | |
6144 opcode(Assembler::prefetch_op3); | |
6145 ins_encode( form3_mem_prefetch_read( mem ) ); | |
6146 ins_pipe(iload_mem); | |
6147 %} | |
6148 | |
6149 instruct prefetchw( memory mem ) %{ | |
6150 match( PrefetchWrite mem ); | |
6151 ins_cost(MEMORY_REF_COST); | |
6152 | |
6153 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} | |
6154 opcode(Assembler::prefetch_op3); | |
6155 ins_encode( form3_mem_prefetch_write( mem ) ); | |
6156 ins_pipe(iload_mem); | |
6157 %} | |
6158 | |
6159 | |
6160 //----------Store Instructions------------------------------------------------- | |
6161 // Store Byte | |
6162 instruct storeB(memory mem, iRegI src) %{ | |
6163 match(Set mem (StoreB mem src)); | |
6164 ins_cost(MEMORY_REF_COST); | |
6165 | |
6166 size(4); | |
6167 format %{ "STB $src,$mem\t! byte" %} | |
6168 opcode(Assembler::stb_op3); | |
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6169 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6170 ins_pipe(istore_mem_reg); |
6171 %} | |
6172 | |
6173 instruct storeB0(memory mem, immI0 src) %{ | |
6174 match(Set mem (StoreB mem src)); | |
6175 ins_cost(MEMORY_REF_COST); | |
6176 | |
6177 size(4); | |
6178 format %{ "STB $src,$mem\t! byte" %} | |
6179 opcode(Assembler::stb_op3); | |
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6180 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6181 ins_pipe(istore_mem_zero); |
6182 %} | |
6183 | |
6184 instruct storeCM0(memory mem, immI0 src) %{ | |
6185 match(Set mem (StoreCM mem src)); | |
6186 ins_cost(MEMORY_REF_COST); | |
6187 | |
6188 size(4); | |
6189 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} | |
6190 opcode(Assembler::stb_op3); | |
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6191 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6192 ins_pipe(istore_mem_zero); |
6193 %} | |
6194 | |
6195 // Store Char/Short | |
6196 instruct storeC(memory mem, iRegI src) %{ | |
6197 match(Set mem (StoreC mem src)); | |
6198 ins_cost(MEMORY_REF_COST); | |
6199 | |
6200 size(4); | |
6201 format %{ "STH $src,$mem\t! short" %} | |
6202 opcode(Assembler::sth_op3); | |
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6203 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6204 ins_pipe(istore_mem_reg); |
6205 %} | |
6206 | |
6207 instruct storeC0(memory mem, immI0 src) %{ | |
6208 match(Set mem (StoreC mem src)); | |
6209 ins_cost(MEMORY_REF_COST); | |
6210 | |
6211 size(4); | |
6212 format %{ "STH $src,$mem\t! short" %} | |
6213 opcode(Assembler::sth_op3); | |
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6214 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6215 ins_pipe(istore_mem_zero); |
6216 %} | |
6217 | |
6218 // Store Integer | |
6219 instruct storeI(memory mem, iRegI src) %{ | |
6220 match(Set mem (StoreI mem src)); | |
6221 ins_cost(MEMORY_REF_COST); | |
6222 | |
6223 size(4); | |
6224 format %{ "STW $src,$mem" %} | |
6225 opcode(Assembler::stw_op3); | |
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6226 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6227 ins_pipe(istore_mem_reg); |
6228 %} | |
6229 | |
6230 // Store Long | |
6231 instruct storeL(memory mem, iRegL src) %{ | |
6232 match(Set mem (StoreL mem src)); | |
6233 ins_cost(MEMORY_REF_COST); | |
6234 size(4); | |
6235 format %{ "STX $src,$mem\t! long" %} | |
6236 opcode(Assembler::stx_op3); | |
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6237 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6238 ins_pipe(istore_mem_reg); |
6239 %} | |
6240 | |
6241 instruct storeI0(memory mem, immI0 src) %{ | |
6242 match(Set mem (StoreI mem src)); | |
6243 ins_cost(MEMORY_REF_COST); | |
6244 | |
6245 size(4); | |
6246 format %{ "STW $src,$mem" %} | |
6247 opcode(Assembler::stw_op3); | |
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6248 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6249 ins_pipe(istore_mem_zero); |
6250 %} | |
6251 | |
6252 instruct storeL0(memory mem, immL0 src) %{ | |
6253 match(Set mem (StoreL mem src)); | |
6254 ins_cost(MEMORY_REF_COST); | |
6255 | |
6256 size(4); | |
6257 format %{ "STX $src,$mem" %} | |
6258 opcode(Assembler::stx_op3); | |
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6259 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6260 ins_pipe(istore_mem_zero); |
6261 %} | |
6262 | |
6263 // Store Integer from float register (used after fstoi) | |
6264 instruct storeI_Freg(memory mem, regF src) %{ | |
6265 match(Set mem (StoreI mem src)); | |
6266 ins_cost(MEMORY_REF_COST); | |
6267 | |
6268 size(4); | |
6269 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} | |
6270 opcode(Assembler::stf_op3); | |
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6271 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6272 ins_pipe(fstoreF_mem_reg); |
6273 %} | |
6274 | |
6275 // Store Pointer | |
6276 instruct storeP(memory dst, sp_ptr_RegP src) %{ | |
6277 match(Set dst (StoreP dst src)); | |
6278 ins_cost(MEMORY_REF_COST); | |
6279 size(4); | |
6280 | |
6281 #ifndef _LP64 | |
6282 format %{ "STW $src,$dst\t! ptr" %} | |
6283 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6284 #else | |
6285 format %{ "STX $src,$dst\t! ptr" %} | |
6286 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6287 #endif | |
6288 ins_encode( form3_mem_reg( dst, src ) ); | |
6289 ins_pipe(istore_mem_spORreg); | |
6290 %} | |
6291 | |
6292 instruct storeP0(memory dst, immP0 src) %{ | |
6293 match(Set dst (StoreP dst src)); | |
6294 ins_cost(MEMORY_REF_COST); | |
6295 size(4); | |
6296 | |
6297 #ifndef _LP64 | |
6298 format %{ "STW $src,$dst\t! ptr" %} | |
6299 opcode(Assembler::stw_op3, 0, REGP_OP); | |
6300 #else | |
6301 format %{ "STX $src,$dst\t! ptr" %} | |
6302 opcode(Assembler::stx_op3, 0, REGP_OP); | |
6303 #endif | |
6304 ins_encode( form3_mem_reg( dst, R_G0 ) ); | |
6305 ins_pipe(istore_mem_zero); | |
6306 %} | |
6307 | |
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6308 // Store Compressed Pointer |
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6309 instruct storeN(memory dst, iRegN src) %{ |
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6310 match(Set dst (StoreN dst src)); |
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6311 ins_cost(MEMORY_REF_COST); |
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6312 size(4); |
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6313 |
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6314 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6315 ins_encode %{ |
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6316 Register base = as_Register($dst$$base); |
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6317 Register index = as_Register($dst$$index); |
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6318 Register src = $src$$Register; |
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6319 if (index != G0) { |
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6320 __ stw(src, base, index); |
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6321 } else { |
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6322 __ stw(src, base, $dst$$disp); |
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6323 } |
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6324 %} |
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6325 ins_pipe(istore_mem_spORreg); |
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6326 %} |
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6327 |
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6328 instruct storeN0(memory dst, immN0 src) %{ |
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6329 match(Set dst (StoreN dst src)); |
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6330 ins_cost(MEMORY_REF_COST); |
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6331 size(4); |
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6332 |
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6333 format %{ "STW $src,$dst\t! compressed ptr" %} |
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6334 ins_encode %{ |
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6335 Register base = as_Register($dst$$base); |
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6336 Register index = as_Register($dst$$index); |
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6337 if (index != G0) { |
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6338 __ stw(0, base, index); |
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6339 } else { |
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6340 __ stw(0, base, $dst$$disp); |
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6341 } |
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6342 %} |
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6343 ins_pipe(istore_mem_zero); |
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6344 %} |
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6345 |
0 | 6346 // Store Double |
6347 instruct storeD( memory mem, regD src) %{ | |
6348 match(Set mem (StoreD mem src)); | |
6349 ins_cost(MEMORY_REF_COST); | |
6350 | |
6351 size(4); | |
6352 format %{ "STDF $src,$mem" %} | |
6353 opcode(Assembler::stdf_op3); | |
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6354 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6355 ins_pipe(fstoreD_mem_reg); |
6356 %} | |
6357 | |
6358 instruct storeD0( memory mem, immD0 src) %{ | |
6359 match(Set mem (StoreD mem src)); | |
6360 ins_cost(MEMORY_REF_COST); | |
6361 | |
6362 size(4); | |
6363 format %{ "STX $src,$mem" %} | |
6364 opcode(Assembler::stx_op3); | |
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6365 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6366 ins_pipe(fstoreD_mem_zero); |
6367 %} | |
6368 | |
6369 // Store Float | |
6370 instruct storeF( memory mem, regF src) %{ | |
6371 match(Set mem (StoreF mem src)); | |
6372 ins_cost(MEMORY_REF_COST); | |
6373 | |
6374 size(4); | |
6375 format %{ "STF $src,$mem" %} | |
6376 opcode(Assembler::stf_op3); | |
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6377 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6378 ins_pipe(fstoreF_mem_reg); |
6379 %} | |
6380 | |
6381 instruct storeF0( memory mem, immF0 src) %{ | |
6382 match(Set mem (StoreF mem src)); | |
6383 ins_cost(MEMORY_REF_COST); | |
6384 | |
6385 size(4); | |
6386 format %{ "STW $src,$mem\t! storeF0" %} | |
6387 opcode(Assembler::stw_op3); | |
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6388 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6389 ins_pipe(fstoreF_mem_zero); |
6390 %} | |
6391 | |
6392 // Store Aligned Packed Bytes in Double register to memory | |
6393 instruct storeA8B(memory mem, regD src) %{ | |
6394 match(Set mem (Store8B mem src)); | |
6395 ins_cost(MEMORY_REF_COST); | |
6396 size(4); | |
6397 format %{ "STDF $src,$mem\t! packed8B" %} | |
6398 opcode(Assembler::stdf_op3); | |
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6399 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6400 ins_pipe(fstoreD_mem_reg); |
6401 %} | |
6402 | |
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6403 // Convert oop pointer into compressed form |
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6404 instruct encodeHeapOop(iRegN dst, iRegP src) %{ |
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6405 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
113
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6406 match(Set dst (EncodeP src)); |
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6407 format %{ "encode_heap_oop $src, $dst" %} |
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6408 ins_encode %{ |
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6409 __ encode_heap_oop($src$$Register, $dst$$Register); |
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6410 %} |
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6411 ins_pipe(ialu_reg); |
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6412 %} |
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6413 |
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6414 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ |
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6415 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
124
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6416 match(Set dst (EncodeP src)); |
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6417 format %{ "encode_heap_oop_not_null $src, $dst" %} |
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6418 ins_encode %{ |
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6419 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); |
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6420 %} |
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6421 ins_pipe(ialu_reg); |
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6422 %} |
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6423 |
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6424 instruct decodeHeapOop(iRegP dst, iRegN src) %{ |
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6425 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
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6426 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
113
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6427 match(Set dst (DecodeN src)); |
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6428 format %{ "decode_heap_oop $src, $dst" %} |
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6429 ins_encode %{ |
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6430 __ decode_heap_oop($src$$Register, $dst$$Register); |
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6431 %} |
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6432 ins_pipe(ialu_reg); |
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6433 %} |
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6434 |
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6435 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ |
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6436 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
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6437 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
124
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|
6438 match(Set dst (DecodeN src)); |
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6439 format %{ "decode_heap_oop_not_null $src, $dst" %} |
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|
6440 ins_encode %{ |
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6441 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); |
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6442 %} |
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|
6443 ins_pipe(ialu_reg); |
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|
6444 %} |
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|
6445 |
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6446 |
0 | 6447 // Store Zero into Aligned Packed Bytes |
6448 instruct storeA8B0(memory mem, immI0 zero) %{ | |
6449 match(Set mem (Store8B mem zero)); | |
6450 ins_cost(MEMORY_REF_COST); | |
6451 size(4); | |
6452 format %{ "STX $zero,$mem\t! packed8B" %} | |
6453 opcode(Assembler::stx_op3); | |
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6454 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6455 ins_pipe(fstoreD_mem_zero); |
6456 %} | |
6457 | |
6458 // Store Aligned Packed Chars/Shorts in Double register to memory | |
6459 instruct storeA4C(memory mem, regD src) %{ | |
6460 match(Set mem (Store4C mem src)); | |
6461 ins_cost(MEMORY_REF_COST); | |
6462 size(4); | |
6463 format %{ "STDF $src,$mem\t! packed4C" %} | |
6464 opcode(Assembler::stdf_op3); | |
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6465 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6466 ins_pipe(fstoreD_mem_reg); |
6467 %} | |
6468 | |
6469 // Store Zero into Aligned Packed Chars/Shorts | |
6470 instruct storeA4C0(memory mem, immI0 zero) %{ | |
6471 match(Set mem (Store4C mem (Replicate4C zero))); | |
6472 ins_cost(MEMORY_REF_COST); | |
6473 size(4); | |
6474 format %{ "STX $zero,$mem\t! packed4C" %} | |
6475 opcode(Assembler::stx_op3); | |
415
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|
6476 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6477 ins_pipe(fstoreD_mem_zero); |
6478 %} | |
6479 | |
6480 // Store Aligned Packed Ints in Double register to memory | |
6481 instruct storeA2I(memory mem, regD src) %{ | |
6482 match(Set mem (Store2I mem src)); | |
6483 ins_cost(MEMORY_REF_COST); | |
6484 size(4); | |
6485 format %{ "STDF $src,$mem\t! packed2I" %} | |
6486 opcode(Assembler::stdf_op3); | |
415
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6487 ins_encode(simple_form3_mem_reg( mem, src ) ); |
0 | 6488 ins_pipe(fstoreD_mem_reg); |
6489 %} | |
6490 | |
6491 // Store Zero into Aligned Packed Ints | |
6492 instruct storeA2I0(memory mem, immI0 zero) %{ | |
6493 match(Set mem (Store2I mem zero)); | |
6494 ins_cost(MEMORY_REF_COST); | |
6495 size(4); | |
6496 format %{ "STX $zero,$mem\t! packed2I" %} | |
6497 opcode(Assembler::stx_op3); | |
415
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|
6498 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); |
0 | 6499 ins_pipe(fstoreD_mem_zero); |
6500 %} | |
6501 | |
6502 | |
6503 //----------MemBar Instructions----------------------------------------------- | |
6504 // Memory barrier flavors | |
6505 | |
6506 instruct membar_acquire() %{ | |
6507 match(MemBarAcquire); | |
6508 ins_cost(4*MEMORY_REF_COST); | |
6509 | |
6510 size(0); | |
6511 format %{ "MEMBAR-acquire" %} | |
6512 ins_encode( enc_membar_acquire ); | |
6513 ins_pipe(long_memory_op); | |
6514 %} | |
6515 | |
6516 instruct membar_acquire_lock() %{ | |
6517 match(MemBarAcquire); | |
6518 predicate(Matcher::prior_fast_lock(n)); | |
6519 ins_cost(0); | |
6520 | |
6521 size(0); | |
6522 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} | |
6523 ins_encode( ); | |
6524 ins_pipe(empty); | |
6525 %} | |
6526 | |
6527 instruct membar_release() %{ | |
6528 match(MemBarRelease); | |
6529 ins_cost(4*MEMORY_REF_COST); | |
6530 | |
6531 size(0); | |
6532 format %{ "MEMBAR-release" %} | |
6533 ins_encode( enc_membar_release ); | |
6534 ins_pipe(long_memory_op); | |
6535 %} | |
6536 | |
6537 instruct membar_release_lock() %{ | |
6538 match(MemBarRelease); | |
6539 predicate(Matcher::post_fast_unlock(n)); | |
6540 ins_cost(0); | |
6541 | |
6542 size(0); | |
6543 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} | |
6544 ins_encode( ); | |
6545 ins_pipe(empty); | |
6546 %} | |
6547 | |
6548 instruct membar_volatile() %{ | |
6549 match(MemBarVolatile); | |
6550 ins_cost(4*MEMORY_REF_COST); | |
6551 | |
6552 size(4); | |
6553 format %{ "MEMBAR-volatile" %} | |
6554 ins_encode( enc_membar_volatile ); | |
6555 ins_pipe(long_memory_op); | |
6556 %} | |
6557 | |
6558 instruct unnecessary_membar_volatile() %{ | |
6559 match(MemBarVolatile); | |
6560 predicate(Matcher::post_store_load_barrier(n)); | |
6561 ins_cost(0); | |
6562 | |
6563 size(0); | |
6564 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} | |
6565 ins_encode( ); | |
6566 ins_pipe(empty); | |
6567 %} | |
6568 | |
6569 //----------Register Move Instructions----------------------------------------- | |
6570 instruct roundDouble_nop(regD dst) %{ | |
6571 match(Set dst (RoundDouble dst)); | |
6572 ins_cost(0); | |
6573 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6574 ins_encode( ); | |
6575 ins_pipe(empty); | |
6576 %} | |
6577 | |
6578 | |
6579 instruct roundFloat_nop(regF dst) %{ | |
6580 match(Set dst (RoundFloat dst)); | |
6581 ins_cost(0); | |
6582 // SPARC results are already "rounded" (i.e., normal-format IEEE) | |
6583 ins_encode( ); | |
6584 ins_pipe(empty); | |
6585 %} | |
6586 | |
6587 | |
6588 // Cast Index to Pointer for unsafe natives | |
6589 instruct castX2P(iRegX src, iRegP dst) %{ | |
6590 match(Set dst (CastX2P src)); | |
6591 | |
6592 format %{ "MOV $src,$dst\t! IntX->Ptr" %} | |
6593 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6594 ins_pipe(ialu_reg); | |
6595 %} | |
6596 | |
6597 // Cast Pointer to Index for unsafe natives | |
6598 instruct castP2X(iRegP src, iRegX dst) %{ | |
6599 match(Set dst (CastP2X src)); | |
6600 | |
6601 format %{ "MOV $src,$dst\t! Ptr->IntX" %} | |
6602 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); | |
6603 ins_pipe(ialu_reg); | |
6604 %} | |
6605 | |
6606 instruct stfSSD(stackSlotD stkSlot, regD src) %{ | |
6607 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6608 match(Set stkSlot src); // chain rule | |
6609 ins_cost(MEMORY_REF_COST); | |
6610 format %{ "STDF $src,$stkSlot\t!stk" %} | |
6611 opcode(Assembler::stdf_op3); | |
415
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|
6612 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6613 ins_pipe(fstoreD_stk_reg); |
6614 %} | |
6615 | |
6616 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ | |
6617 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6618 match(Set dst stkSlot); // chain rule | |
6619 ins_cost(MEMORY_REF_COST); | |
6620 format %{ "LDDF $stkSlot,$dst\t!stk" %} | |
6621 opcode(Assembler::lddf_op3); | |
415
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diff
changeset
|
6622 ins_encode(simple_form3_mem_reg(stkSlot, dst)); |
0 | 6623 ins_pipe(floadD_stk); |
6624 %} | |
6625 | |
6626 instruct stfSSF(stackSlotF stkSlot, regF src) %{ | |
6627 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! | |
6628 match(Set stkSlot src); // chain rule | |
6629 ins_cost(MEMORY_REF_COST); | |
6630 format %{ "STF $src,$stkSlot\t!stk" %} | |
6631 opcode(Assembler::stf_op3); | |
415
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|
6632 ins_encode(simple_form3_mem_reg(stkSlot, src)); |
0 | 6633 ins_pipe(fstoreF_stk_reg); |
6634 %} | |
6635 | |
6636 //----------Conditional Move--------------------------------------------------- | |
6637 // Conditional move | |
6638 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ | |
6639 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6640 ins_cost(150); | |
6641 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6642 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6643 ins_pipe(ialu_reg); | |
6644 %} | |
6645 | |
6646 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ | |
6647 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); | |
6648 ins_cost(140); | |
6649 format %{ "MOV$cmp $pcc,$src,$dst" %} | |
6650 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6651 ins_pipe(ialu_imm); | |
6652 %} | |
6653 | |
6654 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ | |
6655 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6656 ins_cost(150); | |
6657 size(4); | |
6658 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6659 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6660 ins_pipe(ialu_reg); | |
6661 %} | |
6662 | |
6663 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ | |
6664 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); | |
6665 ins_cost(140); | |
6666 size(4); | |
6667 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6668 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6669 ins_pipe(ialu_imm); | |
6670 %} | |
6671 | |
1160
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1137
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|
6672 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ |
0 | 6673 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6674 ins_cost(150); | |
6675 size(4); | |
6676 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6677 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6678 ins_pipe(ialu_reg); | |
6679 %} | |
6680 | |
1160
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1137
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changeset
|
6681 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ |
0 | 6682 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); |
6683 ins_cost(140); | |
6684 size(4); | |
6685 format %{ "MOV$cmp $icc,$src,$dst" %} | |
6686 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6687 ins_pipe(ialu_imm); | |
6688 %} | |
6689 | |
6690 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ | |
6691 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6692 ins_cost(150); | |
6693 size(4); | |
6694 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6695 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6696 ins_pipe(ialu_reg); | |
6697 %} | |
6698 | |
6699 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ | |
6700 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); | |
6701 ins_cost(140); | |
6702 size(4); | |
6703 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6704 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6705 ins_pipe(ialu_imm); | |
6706 %} | |
6707 | |
164
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163
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|
6708 // Conditional move for RegN. Only cmov(reg,reg). |
c436414a719e
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parents:
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changeset
|
6709 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ |
c436414a719e
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diff
changeset
|
6710 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); |
c436414a719e
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parents:
163
diff
changeset
|
6711 ins_cost(150); |
c436414a719e
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parents:
163
diff
changeset
|
6712 format %{ "MOV$cmp $pcc,$src,$dst" %} |
c436414a719e
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parents:
163
diff
changeset
|
6713 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); |
c436414a719e
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parents:
163
diff
changeset
|
6714 ins_pipe(ialu_reg); |
c436414a719e
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parents:
163
diff
changeset
|
6715 %} |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6716 |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6717 // This instruction also works with CmpN so we don't need cmovNN_reg. |
c436414a719e
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kvn
parents:
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diff
changeset
|
6718 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ |
c436414a719e
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diff
changeset
|
6719 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6720 ins_cost(150); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6721 size(4); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6722 format %{ "MOV$cmp $icc,$src,$dst" %} |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6723 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6724 ins_pipe(ialu_reg); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6725 %} |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6726 |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6727 // This instruction also works with CmpN so we don't need cmovNN_reg. |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6728 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6729 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6730 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6731 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6732 format %{ "MOV$cmp $icc,$src,$dst" %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6733 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6734 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6735 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6736 |
164
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6737 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
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parents:
163
diff
changeset
|
6738 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6739 ins_cost(150); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6740 size(4); |
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
6741 format %{ "MOV$cmp $fcc,$src,$dst" %} |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6742 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); |
c436414a719e
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kvn
parents:
163
diff
changeset
|
6743 ins_pipe(ialu_reg); |
c436414a719e
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parents:
163
diff
changeset
|
6744 %} |
c436414a719e
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163
diff
changeset
|
6745 |
0 | 6746 // Conditional move |
6747 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ | |
6748 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6749 ins_cost(150); | |
6750 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6751 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6752 ins_pipe(ialu_reg); | |
6753 %} | |
6754 | |
6755 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ | |
6756 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); | |
6757 ins_cost(140); | |
6758 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} | |
6759 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6760 ins_pipe(ialu_imm); | |
6761 %} | |
6762 | |
164
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163
diff
changeset
|
6763 // This instruction also works with CmpN so we don't need cmovPN_reg. |
0 | 6764 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ |
6765 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6766 ins_cost(150); | |
6767 | |
6768 size(4); | |
6769 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6770 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6771 ins_pipe(ialu_reg); | |
6772 %} | |
6773 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6774 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6775 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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parents:
1137
diff
changeset
|
6776 ins_cost(150); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6777 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6778 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6779 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
f24201449cac
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1137
diff
changeset
|
6780 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6781 ins_pipe(ialu_reg); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6782 %} |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6783 |
0 | 6784 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ |
6785 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); | |
6786 ins_cost(140); | |
6787 | |
6788 size(4); | |
6789 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} | |
6790 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); | |
6791 ins_pipe(ialu_imm); | |
6792 %} | |
6793 | |
1160
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
parents:
1137
diff
changeset
|
6794 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6795 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6796 ins_cost(140); |
f24201449cac
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never
parents:
1137
diff
changeset
|
6797 |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
never
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1137
diff
changeset
|
6798 size(4); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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1137
diff
changeset
|
6799 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} |
f24201449cac
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1137
diff
changeset
|
6800 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); |
f24201449cac
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1137
diff
changeset
|
6801 ins_pipe(ialu_imm); |
f24201449cac
6909839: missing unsigned compare cases for some cmoves in sparc.ad
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diff
changeset
|
6802 %} |
f24201449cac
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1137
diff
changeset
|
6803 |
0 | 6804 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ |
6805 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6806 ins_cost(150); | |
6807 size(4); | |
6808 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6809 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6810 ins_pipe(ialu_imm); | |
6811 %} | |
6812 | |
6813 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ | |
6814 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); | |
6815 ins_cost(140); | |
6816 size(4); | |
6817 format %{ "MOV$cmp $fcc,$src,$dst" %} | |
6818 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); | |
6819 ins_pipe(ialu_imm); | |
6820 %} | |
6821 | |
6822 // Conditional move | |
6823 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ | |
6824 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); | |
6825 ins_cost(150); | |
6826 opcode(0x101); | |
6827 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6828 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6829 ins_pipe(int_conditional_float_move); | |
6830 %} | |
6831 | |
6832 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ | |
6833 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); | |
6834 ins_cost(150); | |
6835 | |
6836 size(4); | |
6837 format %{ "FMOVS$cmp $icc,$src,$dst" %} | |
6838 opcode(0x101); | |
6839 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6840 ins_pipe(int_conditional_float_move); | |
6841 %} | |
6842 | |
1160
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6843 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ |
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|
6844 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); |
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|
6845 ins_cost(150); |
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changeset
|
6846 |
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changeset
|
6847 size(4); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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|
6848 format %{ "FMOVS$cmp $icc,$src,$dst" %} |
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|
6849 opcode(0x101); |
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6850 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
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6851 ins_pipe(int_conditional_float_move); |
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|
6852 %} |
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|
6853 |
0 | 6854 // Conditional move, |
6855 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ | |
6856 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); | |
6857 ins_cost(150); | |
6858 size(4); | |
6859 format %{ "FMOVF$cmp $fcc,$src,$dst" %} | |
6860 opcode(0x1); | |
6861 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
6862 ins_pipe(int_conditional_double_move); | |
6863 %} | |
6864 | |
6865 // Conditional move | |
6866 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ | |
6867 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); | |
6868 ins_cost(150); | |
6869 size(4); | |
6870 opcode(0x102); | |
6871 format %{ "FMOVD$cmp $pcc,$src,$dst" %} | |
6872 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6873 ins_pipe(int_conditional_double_move); | |
6874 %} | |
6875 | |
6876 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ | |
6877 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); | |
6878 ins_cost(150); | |
6879 | |
6880 size(4); | |
6881 format %{ "FMOVD$cmp $icc,$src,$dst" %} | |
6882 opcode(0x102); | |
6883 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); | |
6884 ins_pipe(int_conditional_double_move); | |
6885 %} | |
6886 | |
1160
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6887 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ |
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6888 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); |
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6889 ins_cost(150); |
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changeset
|
6890 |
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changeset
|
6891 size(4); |
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6892 format %{ "FMOVD$cmp $icc,$src,$dst" %} |
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|
6893 opcode(0x102); |
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6894 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); |
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6895 ins_pipe(int_conditional_double_move); |
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|
6896 %} |
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|
6897 |
0 | 6898 // Conditional move, |
6899 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ | |
6900 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); | |
6901 ins_cost(150); | |
6902 size(4); | |
6903 format %{ "FMOVD$cmp $fcc,$src,$dst" %} | |
6904 opcode(0x2); | |
6905 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); | |
6906 ins_pipe(int_conditional_double_move); | |
6907 %} | |
6908 | |
6909 // Conditional move | |
6910 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ | |
6911 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
6912 ins_cost(150); | |
6913 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
6914 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6915 ins_pipe(ialu_reg); | |
6916 %} | |
6917 | |
6918 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ | |
6919 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); | |
6920 ins_cost(140); | |
6921 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} | |
6922 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); | |
6923 ins_pipe(ialu_imm); | |
6924 %} | |
6925 | |
6926 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ | |
6927 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); | |
6928 ins_cost(150); | |
6929 | |
6930 size(4); | |
6931 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} | |
6932 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); | |
6933 ins_pipe(ialu_reg); | |
6934 %} | |
6935 | |
6936 | |
1160
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|
6937 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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6938 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); |
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changeset
|
6939 ins_cost(150); |
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changeset
|
6940 |
f24201449cac
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changeset
|
6941 size(4); |
f24201449cac
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changeset
|
6942 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} |
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|
6943 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); |
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|
6944 ins_pipe(ialu_reg); |
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6909839: missing unsigned compare cases for some cmoves in sparc.ad
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changeset
|
6945 %} |
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changeset
|
6946 |
f24201449cac
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|
6947 |
0 | 6948 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ |
6949 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); | |
6950 ins_cost(150); | |
6951 | |
6952 size(4); | |
6953 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} | |
6954 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); | |
6955 ins_pipe(ialu_reg); | |
6956 %} | |
6957 | |
6958 | |
6959 | |
6960 //----------OS and Locking Instructions---------------------------------------- | |
6961 | |
6962 // This name is KNOWN by the ADLC and cannot be changed. | |
6963 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type | |
6964 // for this guy. | |
6965 instruct tlsLoadP(g2RegP dst) %{ | |
6966 match(Set dst (ThreadLocal)); | |
6967 | |
6968 size(0); | |
6969 ins_cost(0); | |
6970 format %{ "# TLS is in G2" %} | |
6971 ins_encode( /*empty encoding*/ ); | |
6972 ins_pipe(ialu_none); | |
6973 %} | |
6974 | |
6975 instruct checkCastPP( iRegP dst ) %{ | |
6976 match(Set dst (CheckCastPP dst)); | |
6977 | |
6978 size(0); | |
6979 format %{ "# checkcastPP of $dst" %} | |
6980 ins_encode( /*empty encoding*/ ); | |
6981 ins_pipe(empty); | |
6982 %} | |
6983 | |
6984 | |
6985 instruct castPP( iRegP dst ) %{ | |
6986 match(Set dst (CastPP dst)); | |
6987 format %{ "# castPP of $dst" %} | |
6988 ins_encode( /*empty encoding*/ ); | |
6989 ins_pipe(empty); | |
6990 %} | |
6991 | |
6992 instruct castII( iRegI dst ) %{ | |
6993 match(Set dst (CastII dst)); | |
6994 format %{ "# castII of $dst" %} | |
6995 ins_encode( /*empty encoding*/ ); | |
6996 ins_cost(0); | |
6997 ins_pipe(empty); | |
6998 %} | |
6999 | |
7000 //----------Arithmetic Instructions-------------------------------------------- | |
7001 // Addition Instructions | |
7002 // Register Addition | |
7003 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7004 match(Set dst (AddI src1 src2)); | |
7005 | |
7006 size(4); | |
7007 format %{ "ADD $src1,$src2,$dst" %} | |
7008 ins_encode %{ | |
7009 __ add($src1$$Register, $src2$$Register, $dst$$Register); | |
7010 %} | |
7011 ins_pipe(ialu_reg_reg); | |
7012 %} | |
7013 | |
7014 // Immediate Addition | |
7015 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7016 match(Set dst (AddI src1 src2)); | |
7017 | |
7018 size(4); | |
7019 format %{ "ADD $src1,$src2,$dst" %} | |
7020 opcode(Assembler::add_op3, Assembler::arith_op); | |
7021 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7022 ins_pipe(ialu_reg_imm); | |
7023 %} | |
7024 | |
7025 // Pointer Register Addition | |
7026 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ | |
7027 match(Set dst (AddP src1 src2)); | |
7028 | |
7029 size(4); | |
7030 format %{ "ADD $src1,$src2,$dst" %} | |
7031 opcode(Assembler::add_op3, Assembler::arith_op); | |
7032 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7033 ins_pipe(ialu_reg_reg); | |
7034 %} | |
7035 | |
7036 // Pointer Immediate Addition | |
7037 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ | |
7038 match(Set dst (AddP src1 src2)); | |
7039 | |
7040 size(4); | |
7041 format %{ "ADD $src1,$src2,$dst" %} | |
7042 opcode(Assembler::add_op3, Assembler::arith_op); | |
7043 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7044 ins_pipe(ialu_reg_imm); | |
7045 %} | |
7046 | |
7047 // Long Addition | |
7048 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7049 match(Set dst (AddL src1 src2)); | |
7050 | |
7051 size(4); | |
7052 format %{ "ADD $src1,$src2,$dst\t! long" %} | |
7053 opcode(Assembler::add_op3, Assembler::arith_op); | |
7054 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7055 ins_pipe(ialu_reg_reg); | |
7056 %} | |
7057 | |
7058 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7059 match(Set dst (AddL src1 con)); | |
7060 | |
7061 size(4); | |
7062 format %{ "ADD $src1,$con,$dst" %} | |
7063 opcode(Assembler::add_op3, Assembler::arith_op); | |
7064 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7065 ins_pipe(ialu_reg_imm); | |
7066 %} | |
7067 | |
7068 //----------Conditional_store-------------------------------------------------- | |
7069 // Conditional-store of the updated heap-top. | |
7070 // Used during allocation of the shared heap. | |
7071 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. | |
7072 | |
7073 // LoadP-locked. Same as a regular pointer load when used with a compare-swap | |
7074 instruct loadPLocked(iRegP dst, memory mem) %{ | |
7075 match(Set dst (LoadPLocked mem)); | |
7076 ins_cost(MEMORY_REF_COST); | |
7077 | |
7078 #ifndef _LP64 | |
7079 size(4); | |
7080 format %{ "LDUW $mem,$dst\t! ptr" %} | |
7081 opcode(Assembler::lduw_op3, 0, REGP_OP); | |
7082 #else | |
7083 format %{ "LDX $mem,$dst\t! ptr" %} | |
7084 opcode(Assembler::ldx_op3, 0, REGP_OP); | |
7085 #endif | |
7086 ins_encode( form3_mem_reg( mem, dst ) ); | |
7087 ins_pipe(iload_mem); | |
7088 %} | |
7089 | |
7090 // LoadL-locked. Same as a regular long load when used with a compare-swap | |
7091 instruct loadLLocked(iRegL dst, memory mem) %{ | |
7092 match(Set dst (LoadLLocked mem)); | |
7093 ins_cost(MEMORY_REF_COST); | |
7094 size(4); | |
7095 format %{ "LDX $mem,$dst\t! long" %} | |
7096 opcode(Assembler::ldx_op3); | |
415
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7097 ins_encode(simple_form3_mem_reg( mem, dst ) ); |
0 | 7098 ins_pipe(iload_mem); |
7099 %} | |
7100 | |
7101 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ | |
7102 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); | |
7103 effect( KILL newval ); | |
7104 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" | |
7105 "CMP R_G3,$oldval\t\t! See if we made progress" %} | |
7106 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); | |
7107 ins_pipe( long_memory_op ); | |
7108 %} | |
7109 | |
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a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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7110 // Conditional-store of an int value. |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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7111 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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7112 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7113 effect( KILL newval ); |
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6462850: generate biased locking code in C2 ideal graph
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|
7114 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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|
7115 "CMP $oldval,$newval\t\t! See if we made progress" %} |
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|
7116 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7117 ins_pipe( long_memory_op ); |
7118 %} | |
7119 | |
420
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6462850: generate biased locking code in C2 ideal graph
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|
7120 // Conditional-store of a long value. |
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7121 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ |
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6462850: generate biased locking code in C2 ideal graph
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7122 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); |
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
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|
7123 effect( KILL newval ); |
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7124 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" |
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7125 "CMP $oldval,$newval\t\t! See if we made progress" %} |
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7126 ins_encode( enc_cas(mem_ptr,oldval,newval) ); |
0 | 7127 ins_pipe( long_memory_op ); |
7128 %} | |
7129 | |
7130 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them | |
7131 | |
7132 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7133 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
7134 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7135 format %{ | |
7136 "MOV $newval,O7\n\t" | |
7137 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7138 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7139 "MOV 1,$res\n\t" | |
7140 "MOVne xcc,R_G0,$res" | |
7141 %} | |
7142 ins_encode( enc_casx(mem_ptr, oldval, newval), | |
7143 enc_lflags_ne_to_boolean(res) ); | |
7144 ins_pipe( long_memory_op ); | |
7145 %} | |
7146 | |
7147 | |
7148 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7149 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
7150 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7151 format %{ | |
7152 "MOV $newval,O7\n\t" | |
7153 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7154 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7155 "MOV 1,$res\n\t" | |
7156 "MOVne icc,R_G0,$res" | |
7157 %} | |
7158 ins_encode( enc_casi(mem_ptr, oldval, newval), | |
7159 enc_iflags_ne_to_boolean(res) ); | |
7160 ins_pipe( long_memory_op ); | |
7161 %} | |
7162 | |
7163 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ | |
7164 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
7165 effect( USE mem_ptr, KILL ccr, KILL tmp1); | |
7166 format %{ | |
7167 "MOV $newval,O7\n\t" | |
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7168 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" |
0 | 7169 "CMP $oldval,O7\t\t! See if we made progress\n\t" |
7170 "MOV 1,$res\n\t" | |
7171 "MOVne xcc,R_G0,$res" | |
7172 %} | |
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7173 #ifdef _LP64 |
0 | 7174 ins_encode( enc_casx(mem_ptr, oldval, newval), |
7175 enc_lflags_ne_to_boolean(res) ); | |
7176 #else | |
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7177 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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7178 enc_iflags_ne_to_boolean(res) ); |
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7179 #endif |
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7180 ins_pipe( long_memory_op ); |
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7181 %} |
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7182 |
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7183 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ |
113
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7184 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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7185 effect( USE mem_ptr, KILL ccr, KILL tmp1); |
0 | 7186 format %{ |
7187 "MOV $newval,O7\n\t" | |
7188 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" | |
7189 "CMP $oldval,O7\t\t! See if we made progress\n\t" | |
7190 "MOV 1,$res\n\t" | |
7191 "MOVne icc,R_G0,$res" | |
7192 %} | |
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|
7193 ins_encode( enc_casi(mem_ptr, oldval, newval), |
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7194 enc_iflags_ne_to_boolean(res) ); |
0 | 7195 ins_pipe( long_memory_op ); |
7196 %} | |
7197 | |
7198 //--------------------- | |
7199 // Subtraction Instructions | |
7200 // Register Subtraction | |
7201 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7202 match(Set dst (SubI src1 src2)); | |
7203 | |
7204 size(4); | |
7205 format %{ "SUB $src1,$src2,$dst" %} | |
7206 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7207 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7208 ins_pipe(ialu_reg_reg); | |
7209 %} | |
7210 | |
7211 // Immediate Subtraction | |
7212 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7213 match(Set dst (SubI src1 src2)); | |
7214 | |
7215 size(4); | |
7216 format %{ "SUB $src1,$src2,$dst" %} | |
7217 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7218 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7219 ins_pipe(ialu_reg_imm); | |
7220 %} | |
7221 | |
7222 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ | |
7223 match(Set dst (SubI zero src2)); | |
7224 | |
7225 size(4); | |
7226 format %{ "NEG $src2,$dst" %} | |
7227 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7228 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7229 ins_pipe(ialu_zero_reg); | |
7230 %} | |
7231 | |
7232 // Long subtraction | |
7233 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7234 match(Set dst (SubL src1 src2)); | |
7235 | |
7236 size(4); | |
7237 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7238 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7239 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7240 ins_pipe(ialu_reg_reg); | |
7241 %} | |
7242 | |
7243 // Immediate Subtraction | |
7244 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7245 match(Set dst (SubL src1 con)); | |
7246 | |
7247 size(4); | |
7248 format %{ "SUB $src1,$con,$dst\t! long" %} | |
7249 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7250 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7251 ins_pipe(ialu_reg_imm); | |
7252 %} | |
7253 | |
7254 // Long negation | |
7255 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ | |
7256 match(Set dst (SubL zero src2)); | |
7257 | |
7258 size(4); | |
7259 format %{ "NEG $src2,$dst\t! long" %} | |
7260 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7261 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); | |
7262 ins_pipe(ialu_zero_reg); | |
7263 %} | |
7264 | |
7265 // Multiplication Instructions | |
7266 // Integer Multiplication | |
7267 // Register Multiplication | |
7268 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7269 match(Set dst (MulI src1 src2)); | |
7270 | |
7271 size(4); | |
7272 format %{ "MULX $src1,$src2,$dst" %} | |
7273 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7274 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7275 ins_pipe(imul_reg_reg); | |
7276 %} | |
7277 | |
7278 // Immediate Multiplication | |
7279 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7280 match(Set dst (MulI src1 src2)); | |
7281 | |
7282 size(4); | |
7283 format %{ "MULX $src1,$src2,$dst" %} | |
7284 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7285 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7286 ins_pipe(imul_reg_imm); | |
7287 %} | |
7288 | |
7289 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7290 match(Set dst (MulL src1 src2)); | |
7291 ins_cost(DEFAULT_COST * 5); | |
7292 size(4); | |
7293 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7294 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7295 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7296 ins_pipe(mulL_reg_reg); | |
7297 %} | |
7298 | |
7299 // Immediate Multiplication | |
7300 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7301 match(Set dst (MulL src1 src2)); | |
7302 ins_cost(DEFAULT_COST * 5); | |
7303 size(4); | |
7304 format %{ "MULX $src1,$src2,$dst" %} | |
7305 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7306 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7307 ins_pipe(mulL_reg_imm); | |
7308 %} | |
7309 | |
7310 // Integer Division | |
7311 // Register Division | |
7312 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ | |
7313 match(Set dst (DivI src1 src2)); | |
7314 ins_cost((2+71)*DEFAULT_COST); | |
7315 | |
7316 format %{ "SRA $src2,0,$src2\n\t" | |
7317 "SRA $src1,0,$src1\n\t" | |
7318 "SDIVX $src1,$src2,$dst" %} | |
7319 ins_encode( idiv_reg( src1, src2, dst ) ); | |
7320 ins_pipe(sdiv_reg_reg); | |
7321 %} | |
7322 | |
7323 // Immediate Division | |
7324 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ | |
7325 match(Set dst (DivI src1 src2)); | |
7326 ins_cost((2+71)*DEFAULT_COST); | |
7327 | |
7328 format %{ "SRA $src1,0,$src1\n\t" | |
7329 "SDIVX $src1,$src2,$dst" %} | |
7330 ins_encode( idiv_imm( src1, src2, dst ) ); | |
7331 ins_pipe(sdiv_reg_imm); | |
7332 %} | |
7333 | |
7334 //----------Div-By-10-Expansion------------------------------------------------ | |
7335 // Extract hi bits of a 32x32->64 bit multiply. | |
7336 // Expand rule only, not matched | |
7337 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ | |
7338 effect( DEF dst, USE src1, USE src2 ); | |
7339 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" | |
7340 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} | |
7341 ins_encode( enc_mul_hi(dst,src1,src2)); | |
7342 ins_pipe(sdiv_reg_reg); | |
7343 %} | |
7344 | |
605 | 7345 // Magic constant, reciprocal of 10 |
0 | 7346 instruct loadConI_x66666667(iRegIsafe dst) %{ |
7347 effect( DEF dst ); | |
7348 | |
7349 size(8); | |
7350 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} | |
7351 ins_encode( Set32(0x66666667, dst) ); | |
7352 ins_pipe(ialu_hi_lo_reg); | |
7353 %} | |
7354 | |
605 | 7355 // Register Shift Right Arithmetic Long by 32-63 |
0 | 7356 instruct sra_31( iRegI dst, iRegI src ) %{ |
7357 effect( DEF dst, USE src ); | |
7358 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} | |
7359 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); | |
7360 ins_pipe(ialu_reg_reg); | |
7361 %} | |
7362 | |
7363 // Arithmetic Shift Right by 8-bit immediate | |
7364 instruct sra_reg_2( iRegI dst, iRegI src ) %{ | |
7365 effect( DEF dst, USE src ); | |
7366 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} | |
7367 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7368 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); | |
7369 ins_pipe(ialu_reg_imm); | |
7370 %} | |
7371 | |
7372 // Integer DIV with 10 | |
7373 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ | |
7374 match(Set dst (DivI src div)); | |
7375 ins_cost((6+6)*DEFAULT_COST); | |
7376 expand %{ | |
7377 iRegIsafe tmp1; // Killed temps; | |
7378 iRegIsafe tmp2; // Killed temps; | |
7379 iRegI tmp3; // Killed temps; | |
7380 iRegI tmp4; // Killed temps; | |
7381 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 | |
7382 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 | |
7383 sra_31( tmp3, src ); // SRA src,31 -> tmp3 | |
7384 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 | |
7385 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst | |
7386 %} | |
7387 %} | |
7388 | |
7389 // Register Long Division | |
7390 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7391 match(Set dst (DivL src1 src2)); | |
7392 ins_cost(DEFAULT_COST*71); | |
7393 size(4); | |
7394 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7395 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7396 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7397 ins_pipe(divL_reg_reg); | |
7398 %} | |
7399 | |
7400 // Register Long Division | |
7401 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7402 match(Set dst (DivL src1 src2)); | |
7403 ins_cost(DEFAULT_COST*71); | |
7404 size(4); | |
7405 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7406 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7407 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7408 ins_pipe(divL_reg_imm); | |
7409 %} | |
7410 | |
7411 // Integer Remainder | |
7412 // Register Remainder | |
7413 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ | |
7414 match(Set dst (ModI src1 src2)); | |
7415 effect( KILL ccr, KILL temp); | |
7416 | |
7417 format %{ "SREM $src1,$src2,$dst" %} | |
7418 ins_encode( irem_reg(src1, src2, dst, temp) ); | |
7419 ins_pipe(sdiv_reg_reg); | |
7420 %} | |
7421 | |
7422 // Immediate Remainder | |
7423 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ | |
7424 match(Set dst (ModI src1 src2)); | |
7425 effect( KILL ccr, KILL temp); | |
7426 | |
7427 format %{ "SREM $src1,$src2,$dst" %} | |
7428 ins_encode( irem_imm(src1, src2, dst, temp) ); | |
7429 ins_pipe(sdiv_reg_imm); | |
7430 %} | |
7431 | |
7432 // Register Long Remainder | |
7433 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7434 effect(DEF dst, USE src1, USE src2); | |
7435 size(4); | |
7436 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7437 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7438 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7439 ins_pipe(divL_reg_reg); | |
7440 %} | |
7441 | |
7442 // Register Long Division | |
7443 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7444 effect(DEF dst, USE src1, USE src2); | |
7445 size(4); | |
7446 format %{ "SDIVX $src1,$src2,$dst\t! long" %} | |
7447 opcode(Assembler::sdivx_op3, Assembler::arith_op); | |
7448 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7449 ins_pipe(divL_reg_imm); | |
7450 %} | |
7451 | |
7452 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7453 effect(DEF dst, USE src1, USE src2); | |
7454 size(4); | |
7455 format %{ "MULX $src1,$src2,$dst\t! long" %} | |
7456 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7457 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7458 ins_pipe(mulL_reg_reg); | |
7459 %} | |
7460 | |
7461 // Immediate Multiplication | |
7462 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ | |
7463 effect(DEF dst, USE src1, USE src2); | |
7464 size(4); | |
7465 format %{ "MULX $src1,$src2,$dst" %} | |
7466 opcode(Assembler::mulx_op3, Assembler::arith_op); | |
7467 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7468 ins_pipe(mulL_reg_imm); | |
7469 %} | |
7470 | |
7471 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ | |
7472 effect(DEF dst, USE src1, USE src2); | |
7473 size(4); | |
7474 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7475 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7476 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7477 ins_pipe(ialu_reg_reg); | |
7478 %} | |
7479 | |
7480 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ | |
7481 effect(DEF dst, USE src1, USE src2); | |
7482 size(4); | |
7483 format %{ "SUB $src1,$src2,$dst\t! long" %} | |
7484 opcode(Assembler::sub_op3, Assembler::arith_op); | |
7485 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7486 ins_pipe(ialu_reg_reg); | |
7487 %} | |
7488 | |
7489 // Register Long Remainder | |
7490 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7491 match(Set dst (ModL src1 src2)); | |
7492 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7493 expand %{ | |
7494 iRegL tmp1; | |
7495 iRegL tmp2; | |
7496 divL_reg_reg_1(tmp1, src1, src2); | |
7497 mulL_reg_reg_1(tmp2, tmp1, src2); | |
7498 subL_reg_reg_1(dst, src1, tmp2); | |
7499 %} | |
7500 %} | |
7501 | |
7502 // Register Long Remainder | |
7503 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ | |
7504 match(Set dst (ModL src1 src2)); | |
7505 ins_cost(DEFAULT_COST*(71 + 6 + 1)); | |
7506 expand %{ | |
7507 iRegL tmp1; | |
7508 iRegL tmp2; | |
7509 divL_reg_imm13_1(tmp1, src1, src2); | |
7510 mulL_reg_imm13_1(tmp2, tmp1, src2); | |
7511 subL_reg_reg_2 (dst, src1, tmp2); | |
7512 %} | |
7513 %} | |
7514 | |
7515 // Integer Shift Instructions | |
7516 // Register Shift Left | |
7517 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7518 match(Set dst (LShiftI src1 src2)); | |
7519 | |
7520 size(4); | |
7521 format %{ "SLL $src1,$src2,$dst" %} | |
7522 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7523 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7524 ins_pipe(ialu_reg_reg); | |
7525 %} | |
7526 | |
7527 // Register Shift Left Immediate | |
7528 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7529 match(Set dst (LShiftI src1 src2)); | |
7530 | |
7531 size(4); | |
7532 format %{ "SLL $src1,$src2,$dst" %} | |
7533 opcode(Assembler::sll_op3, Assembler::arith_op); | |
7534 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7535 ins_pipe(ialu_reg_imm); | |
7536 %} | |
7537 | |
7538 // Register Shift Left | |
7539 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7540 match(Set dst (LShiftL src1 src2)); | |
7541 | |
7542 size(4); | |
7543 format %{ "SLLX $src1,$src2,$dst" %} | |
7544 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7545 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7546 ins_pipe(ialu_reg_reg); | |
7547 %} | |
7548 | |
7549 // Register Shift Left Immediate | |
7550 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7551 match(Set dst (LShiftL src1 src2)); | |
7552 | |
7553 size(4); | |
7554 format %{ "SLLX $src1,$src2,$dst" %} | |
7555 opcode(Assembler::sllx_op3, Assembler::arith_op); | |
7556 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7557 ins_pipe(ialu_reg_imm); | |
7558 %} | |
7559 | |
7560 // Register Arithmetic Shift Right | |
7561 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7562 match(Set dst (RShiftI src1 src2)); | |
7563 size(4); | |
7564 format %{ "SRA $src1,$src2,$dst" %} | |
7565 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7566 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7567 ins_pipe(ialu_reg_reg); | |
7568 %} | |
7569 | |
7570 // Register Arithmetic Shift Right Immediate | |
7571 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7572 match(Set dst (RShiftI src1 src2)); | |
7573 | |
7574 size(4); | |
7575 format %{ "SRA $src1,$src2,$dst" %} | |
7576 opcode(Assembler::sra_op3, Assembler::arith_op); | |
7577 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7578 ins_pipe(ialu_reg_imm); | |
7579 %} | |
7580 | |
7581 // Register Shift Right Arithmatic Long | |
7582 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7583 match(Set dst (RShiftL src1 src2)); | |
7584 | |
7585 size(4); | |
7586 format %{ "SRAX $src1,$src2,$dst" %} | |
7587 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7588 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7589 ins_pipe(ialu_reg_reg); | |
7590 %} | |
7591 | |
7592 // Register Shift Left Immediate | |
7593 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7594 match(Set dst (RShiftL src1 src2)); | |
7595 | |
7596 size(4); | |
7597 format %{ "SRAX $src1,$src2,$dst" %} | |
7598 opcode(Assembler::srax_op3, Assembler::arith_op); | |
7599 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7600 ins_pipe(ialu_reg_imm); | |
7601 %} | |
7602 | |
7603 // Register Shift Right | |
7604 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7605 match(Set dst (URShiftI src1 src2)); | |
7606 | |
7607 size(4); | |
7608 format %{ "SRL $src1,$src2,$dst" %} | |
7609 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7610 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7611 ins_pipe(ialu_reg_reg); | |
7612 %} | |
7613 | |
7614 // Register Shift Right Immediate | |
7615 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ | |
7616 match(Set dst (URShiftI src1 src2)); | |
7617 | |
7618 size(4); | |
7619 format %{ "SRL $src1,$src2,$dst" %} | |
7620 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7621 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7622 ins_pipe(ialu_reg_imm); | |
7623 %} | |
7624 | |
7625 // Register Shift Right | |
7626 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ | |
7627 match(Set dst (URShiftL src1 src2)); | |
7628 | |
7629 size(4); | |
7630 format %{ "SRLX $src1,$src2,$dst" %} | |
7631 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7632 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); | |
7633 ins_pipe(ialu_reg_reg); | |
7634 %} | |
7635 | |
7636 // Register Shift Right Immediate | |
7637 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ | |
7638 match(Set dst (URShiftL src1 src2)); | |
7639 | |
7640 size(4); | |
7641 format %{ "SRLX $src1,$src2,$dst" %} | |
7642 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7643 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7644 ins_pipe(ialu_reg_imm); | |
7645 %} | |
7646 | |
7647 // Register Shift Right Immediate with a CastP2X | |
7648 #ifdef _LP64 | |
7649 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ | |
7650 match(Set dst (URShiftL (CastP2X src1) src2)); | |
7651 size(4); | |
7652 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} | |
7653 opcode(Assembler::srlx_op3, Assembler::arith_op); | |
7654 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); | |
7655 ins_pipe(ialu_reg_imm); | |
7656 %} | |
7657 #else | |
7658 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ | |
7659 match(Set dst (URShiftI (CastP2X src1) src2)); | |
7660 size(4); | |
7661 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} | |
7662 opcode(Assembler::srl_op3, Assembler::arith_op); | |
7663 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); | |
7664 ins_pipe(ialu_reg_imm); | |
7665 %} | |
7666 #endif | |
7667 | |
7668 | |
7669 //----------Floating Point Arithmetic Instructions----------------------------- | |
7670 | |
7671 // Add float single precision | |
7672 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7673 match(Set dst (AddF src1 src2)); | |
7674 | |
7675 size(4); | |
7676 format %{ "FADDS $src1,$src2,$dst" %} | |
7677 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); | |
7678 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7679 ins_pipe(faddF_reg_reg); | |
7680 %} | |
7681 | |
7682 // Add float double precision | |
7683 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7684 match(Set dst (AddD src1 src2)); | |
7685 | |
7686 size(4); | |
7687 format %{ "FADDD $src1,$src2,$dst" %} | |
7688 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
7689 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7690 ins_pipe(faddD_reg_reg); | |
7691 %} | |
7692 | |
7693 // Sub float single precision | |
7694 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7695 match(Set dst (SubF src1 src2)); | |
7696 | |
7697 size(4); | |
7698 format %{ "FSUBS $src1,$src2,$dst" %} | |
7699 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); | |
7700 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7701 ins_pipe(faddF_reg_reg); | |
7702 %} | |
7703 | |
7704 // Sub float double precision | |
7705 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7706 match(Set dst (SubD src1 src2)); | |
7707 | |
7708 size(4); | |
7709 format %{ "FSUBD $src1,$src2,$dst" %} | |
7710 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
7711 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7712 ins_pipe(faddD_reg_reg); | |
7713 %} | |
7714 | |
7715 // Mul float single precision | |
7716 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7717 match(Set dst (MulF src1 src2)); | |
7718 | |
7719 size(4); | |
7720 format %{ "FMULS $src1,$src2,$dst" %} | |
7721 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); | |
7722 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7723 ins_pipe(fmulF_reg_reg); | |
7724 %} | |
7725 | |
7726 // Mul float double precision | |
7727 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7728 match(Set dst (MulD src1 src2)); | |
7729 | |
7730 size(4); | |
7731 format %{ "FMULD $src1,$src2,$dst" %} | |
7732 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
7733 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7734 ins_pipe(fmulD_reg_reg); | |
7735 %} | |
7736 | |
7737 // Div float single precision | |
7738 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ | |
7739 match(Set dst (DivF src1 src2)); | |
7740 | |
7741 size(4); | |
7742 format %{ "FDIVS $src1,$src2,$dst" %} | |
7743 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); | |
7744 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); | |
7745 ins_pipe(fdivF_reg_reg); | |
7746 %} | |
7747 | |
7748 // Div float double precision | |
7749 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ | |
7750 match(Set dst (DivD src1 src2)); | |
7751 | |
7752 size(4); | |
7753 format %{ "FDIVD $src1,$src2,$dst" %} | |
7754 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); | |
7755 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
7756 ins_pipe(fdivD_reg_reg); | |
7757 %} | |
7758 | |
7759 // Absolute float double precision | |
7760 instruct absD_reg(regD dst, regD src) %{ | |
7761 match(Set dst (AbsD src)); | |
7762 | |
7763 format %{ "FABSd $src,$dst" %} | |
7764 ins_encode(fabsd(dst, src)); | |
7765 ins_pipe(faddD_reg); | |
7766 %} | |
7767 | |
7768 // Absolute float single precision | |
7769 instruct absF_reg(regF dst, regF src) %{ | |
7770 match(Set dst (AbsF src)); | |
7771 | |
7772 format %{ "FABSs $src,$dst" %} | |
7773 ins_encode(fabss(dst, src)); | |
7774 ins_pipe(faddF_reg); | |
7775 %} | |
7776 | |
7777 instruct negF_reg(regF dst, regF src) %{ | |
7778 match(Set dst (NegF src)); | |
7779 | |
7780 size(4); | |
7781 format %{ "FNEGs $src,$dst" %} | |
7782 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); | |
7783 ins_encode(form3_opf_rs2F_rdF(src, dst)); | |
7784 ins_pipe(faddF_reg); | |
7785 %} | |
7786 | |
7787 instruct negD_reg(regD dst, regD src) %{ | |
7788 match(Set dst (NegD src)); | |
7789 | |
7790 format %{ "FNEGd $src,$dst" %} | |
7791 ins_encode(fnegd(dst, src)); | |
7792 ins_pipe(faddD_reg); | |
7793 %} | |
7794 | |
7795 // Sqrt float double precision | |
7796 instruct sqrtF_reg_reg(regF dst, regF src) %{ | |
7797 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
7798 | |
7799 size(4); | |
7800 format %{ "FSQRTS $src,$dst" %} | |
7801 ins_encode(fsqrts(dst, src)); | |
7802 ins_pipe(fdivF_reg_reg); | |
7803 %} | |
7804 | |
7805 // Sqrt float double precision | |
7806 instruct sqrtD_reg_reg(regD dst, regD src) %{ | |
7807 match(Set dst (SqrtD src)); | |
7808 | |
7809 size(4); | |
7810 format %{ "FSQRTD $src,$dst" %} | |
7811 ins_encode(fsqrtd(dst, src)); | |
7812 ins_pipe(fdivD_reg_reg); | |
7813 %} | |
7814 | |
7815 //----------Logical Instructions----------------------------------------------- | |
7816 // And Instructions | |
7817 // Register And | |
7818 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7819 match(Set dst (AndI src1 src2)); | |
7820 | |
7821 size(4); | |
7822 format %{ "AND $src1,$src2,$dst" %} | |
7823 opcode(Assembler::and_op3, Assembler::arith_op); | |
7824 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7825 ins_pipe(ialu_reg_reg); | |
7826 %} | |
7827 | |
7828 // Immediate And | |
7829 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7830 match(Set dst (AndI src1 src2)); | |
7831 | |
7832 size(4); | |
7833 format %{ "AND $src1,$src2,$dst" %} | |
7834 opcode(Assembler::and_op3, Assembler::arith_op); | |
7835 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7836 ins_pipe(ialu_reg_imm); | |
7837 %} | |
7838 | |
7839 // Register And Long | |
7840 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7841 match(Set dst (AndL src1 src2)); | |
7842 | |
7843 ins_cost(DEFAULT_COST); | |
7844 size(4); | |
7845 format %{ "AND $src1,$src2,$dst\t! long" %} | |
7846 opcode(Assembler::and_op3, Assembler::arith_op); | |
7847 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7848 ins_pipe(ialu_reg_reg); | |
7849 %} | |
7850 | |
7851 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7852 match(Set dst (AndL src1 con)); | |
7853 | |
7854 ins_cost(DEFAULT_COST); | |
7855 size(4); | |
7856 format %{ "AND $src1,$con,$dst\t! long" %} | |
7857 opcode(Assembler::and_op3, Assembler::arith_op); | |
7858 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7859 ins_pipe(ialu_reg_imm); | |
7860 %} | |
7861 | |
7862 // Or Instructions | |
7863 // Register Or | |
7864 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7865 match(Set dst (OrI src1 src2)); | |
7866 | |
7867 size(4); | |
7868 format %{ "OR $src1,$src2,$dst" %} | |
7869 opcode(Assembler::or_op3, Assembler::arith_op); | |
7870 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7871 ins_pipe(ialu_reg_reg); | |
7872 %} | |
7873 | |
7874 // Immediate Or | |
7875 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7876 match(Set dst (OrI src1 src2)); | |
7877 | |
7878 size(4); | |
7879 format %{ "OR $src1,$src2,$dst" %} | |
7880 opcode(Assembler::or_op3, Assembler::arith_op); | |
7881 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7882 ins_pipe(ialu_reg_imm); | |
7883 %} | |
7884 | |
7885 // Register Or Long | |
7886 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7887 match(Set dst (OrL src1 src2)); | |
7888 | |
7889 ins_cost(DEFAULT_COST); | |
7890 size(4); | |
7891 format %{ "OR $src1,$src2,$dst\t! long" %} | |
7892 opcode(Assembler::or_op3, Assembler::arith_op); | |
7893 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7894 ins_pipe(ialu_reg_reg); | |
7895 %} | |
7896 | |
7897 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7898 match(Set dst (OrL src1 con)); | |
7899 ins_cost(DEFAULT_COST*2); | |
7900 | |
7901 ins_cost(DEFAULT_COST); | |
7902 size(4); | |
7903 format %{ "OR $src1,$con,$dst\t! long" %} | |
7904 opcode(Assembler::or_op3, Assembler::arith_op); | |
7905 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7906 ins_pipe(ialu_reg_imm); | |
7907 %} | |
7908 | |
420
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7909 #ifndef _LP64 |
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7910 |
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7911 // Use sp_ptr_RegP to match G2 (TLS register) without spilling. |
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7912 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ |
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7913 match(Set dst (OrI src1 (CastP2X src2))); |
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7914 |
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7915 size(4); |
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7916 format %{ "OR $src1,$src2,$dst" %} |
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7917 opcode(Assembler::or_op3, Assembler::arith_op); |
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7918 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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7919 ins_pipe(ialu_reg_reg); |
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7920 %} |
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7921 |
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7922 #else |
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7923 |
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7924 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ |
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7925 match(Set dst (OrL src1 (CastP2X src2))); |
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7926 |
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7927 ins_cost(DEFAULT_COST); |
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7928 size(4); |
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7929 format %{ "OR $src1,$src2,$dst\t! long" %} |
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7930 opcode(Assembler::or_op3, Assembler::arith_op); |
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7931 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); |
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7932 ins_pipe(ialu_reg_reg); |
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7933 %} |
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7934 |
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7935 #endif |
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7936 |
0 | 7937 // Xor Instructions |
7938 // Register Xor | |
7939 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ | |
7940 match(Set dst (XorI src1 src2)); | |
7941 | |
7942 size(4); | |
7943 format %{ "XOR $src1,$src2,$dst" %} | |
7944 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7945 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7946 ins_pipe(ialu_reg_reg); | |
7947 %} | |
7948 | |
7949 // Immediate Xor | |
7950 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ | |
7951 match(Set dst (XorI src1 src2)); | |
7952 | |
7953 size(4); | |
7954 format %{ "XOR $src1,$src2,$dst" %} | |
7955 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7956 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); | |
7957 ins_pipe(ialu_reg_imm); | |
7958 %} | |
7959 | |
7960 // Register Xor Long | |
7961 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ | |
7962 match(Set dst (XorL src1 src2)); | |
7963 | |
7964 ins_cost(DEFAULT_COST); | |
7965 size(4); | |
7966 format %{ "XOR $src1,$src2,$dst\t! long" %} | |
7967 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7968 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); | |
7969 ins_pipe(ialu_reg_reg); | |
7970 %} | |
7971 | |
7972 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ | |
7973 match(Set dst (XorL src1 con)); | |
7974 | |
7975 ins_cost(DEFAULT_COST); | |
7976 size(4); | |
7977 format %{ "XOR $src1,$con,$dst\t! long" %} | |
7978 opcode(Assembler::xor_op3, Assembler::arith_op); | |
7979 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); | |
7980 ins_pipe(ialu_reg_imm); | |
7981 %} | |
7982 | |
7983 //----------Convert to Boolean------------------------------------------------- | |
7984 // Nice hack for 32-bit tests but doesn't work for | |
7985 // 64-bit pointers. | |
7986 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ | |
7987 match(Set dst (Conv2B src)); | |
7988 effect( KILL ccr ); | |
7989 ins_cost(DEFAULT_COST*2); | |
7990 format %{ "CMP R_G0,$src\n\t" | |
7991 "ADDX R_G0,0,$dst" %} | |
7992 ins_encode( enc_to_bool( src, dst ) ); | |
7993 ins_pipe(ialu_reg_ialu); | |
7994 %} | |
7995 | |
7996 #ifndef _LP64 | |
7997 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ | |
7998 match(Set dst (Conv2B src)); | |
7999 effect( KILL ccr ); | |
8000 ins_cost(DEFAULT_COST*2); | |
8001 format %{ "CMP R_G0,$src\n\t" | |
8002 "ADDX R_G0,0,$dst" %} | |
8003 ins_encode( enc_to_bool( src, dst ) ); | |
8004 ins_pipe(ialu_reg_ialu); | |
8005 %} | |
8006 #else | |
8007 instruct convP2B( iRegI dst, iRegP src ) %{ | |
8008 match(Set dst (Conv2B src)); | |
8009 ins_cost(DEFAULT_COST*2); | |
8010 format %{ "MOV $src,$dst\n\t" | |
8011 "MOVRNZ $src,1,$dst" %} | |
8012 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); | |
8013 ins_pipe(ialu_clr_and_mover); | |
8014 %} | |
8015 #endif | |
8016 | |
8017 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ | |
8018 match(Set dst (CmpLTMask p q)); | |
8019 effect( KILL ccr ); | |
8020 ins_cost(DEFAULT_COST*4); | |
8021 format %{ "CMP $p,$q\n\t" | |
8022 "MOV #0,$dst\n\t" | |
8023 "BLT,a .+8\n\t" | |
8024 "MOV #-1,$dst" %} | |
8025 ins_encode( enc_ltmask(p,q,dst) ); | |
8026 ins_pipe(ialu_reg_reg_ialu); | |
8027 %} | |
8028 | |
8029 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
8030 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
8031 effect(KILL ccr, TEMP tmp); | |
8032 ins_cost(DEFAULT_COST*3); | |
8033 | |
8034 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
8035 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
8036 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
8037 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
8038 ins_pipe( cadd_cmpltmask ); | |
8039 %} | |
8040 | |
8041 instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ | |
8042 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); | |
8043 effect( KILL ccr, TEMP tmp); | |
8044 ins_cost(DEFAULT_COST*3); | |
8045 | |
8046 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" | |
8047 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" | |
8048 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} | |
8049 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); | |
8050 ins_pipe( cadd_cmpltmask ); | |
8051 %} | |
8052 | |
8053 //----------Arithmetic Conversion Instructions--------------------------------- | |
8054 // The conversions operations are all Alpha sorted. Please keep it that way! | |
8055 | |
8056 instruct convD2F_reg(regF dst, regD src) %{ | |
8057 match(Set dst (ConvD2F src)); | |
8058 size(4); | |
8059 format %{ "FDTOS $src,$dst" %} | |
8060 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); | |
8061 ins_encode(form3_opf_rs2D_rdF(src, dst)); | |
8062 ins_pipe(fcvtD2F); | |
8063 %} | |
8064 | |
8065 | |
8066 // Convert a double to an int in a float register. | |
8067 // If the double is a NAN, stuff a zero in instead. | |
8068 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ | |
8069 effect(DEF dst, USE src, KILL fcc0); | |
8070 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8071 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8072 "FDTOI $src,$dst\t! convert in delay slot\n\t" | |
8073 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8074 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8075 "skip:" %} | |
8076 ins_encode(form_d2i_helper(src,dst)); | |
8077 ins_pipe(fcvtD2I); | |
8078 %} | |
8079 | |
8080 instruct convD2I_reg(stackSlotI dst, regD src) %{ | |
8081 match(Set dst (ConvD2I src)); | |
8082 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8083 expand %{ | |
8084 regF tmp; | |
8085 convD2I_helper(tmp, src); | |
8086 regF_to_stkI(dst, tmp); | |
8087 %} | |
8088 %} | |
8089 | |
8090 // Convert a double to a long in a double register. | |
8091 // If the double is a NAN, stuff a zero in instead. | |
8092 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ | |
8093 effect(DEF dst, USE src, KILL fcc0); | |
8094 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" | |
8095 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8096 "FDTOX $src,$dst\t! convert in delay slot\n\t" | |
8097 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8098 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8099 "skip:" %} | |
8100 ins_encode(form_d2l_helper(src,dst)); | |
8101 ins_pipe(fcvtD2L); | |
8102 %} | |
8103 | |
8104 | |
8105 // Double to Long conversion | |
8106 instruct convD2L_reg(stackSlotL dst, regD src) %{ | |
8107 match(Set dst (ConvD2L src)); | |
8108 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8109 expand %{ | |
8110 regD tmp; | |
8111 convD2L_helper(tmp, src); | |
8112 regD_to_stkL(dst, tmp); | |
8113 %} | |
8114 %} | |
8115 | |
8116 | |
8117 instruct convF2D_reg(regD dst, regF src) %{ | |
8118 match(Set dst (ConvF2D src)); | |
8119 format %{ "FSTOD $src,$dst" %} | |
8120 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); | |
8121 ins_encode(form3_opf_rs2F_rdD(src, dst)); | |
8122 ins_pipe(fcvtF2D); | |
8123 %} | |
8124 | |
8125 | |
8126 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ | |
8127 effect(DEF dst, USE src, KILL fcc0); | |
8128 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8129 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8130 "FSTOI $src,$dst\t! convert in delay slot\n\t" | |
8131 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" | |
8132 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" | |
8133 "skip:" %} | |
8134 ins_encode(form_f2i_helper(src,dst)); | |
8135 ins_pipe(fcvtF2I); | |
8136 %} | |
8137 | |
8138 instruct convF2I_reg(stackSlotI dst, regF src) %{ | |
8139 match(Set dst (ConvF2I src)); | |
8140 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8141 expand %{ | |
8142 regF tmp; | |
8143 convF2I_helper(tmp, src); | |
8144 regF_to_stkI(dst, tmp); | |
8145 %} | |
8146 %} | |
8147 | |
8148 | |
8149 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ | |
8150 effect(DEF dst, USE src, KILL fcc0); | |
8151 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" | |
8152 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" | |
8153 "FSTOX $src,$dst\t! convert in delay slot\n\t" | |
8154 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" | |
8155 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" | |
8156 "skip:" %} | |
8157 ins_encode(form_f2l_helper(src,dst)); | |
8158 ins_pipe(fcvtF2L); | |
8159 %} | |
8160 | |
8161 // Float to Long conversion | |
8162 instruct convF2L_reg(stackSlotL dst, regF src) %{ | |
8163 match(Set dst (ConvF2L src)); | |
8164 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); | |
8165 expand %{ | |
8166 regD tmp; | |
8167 convF2L_helper(tmp, src); | |
8168 regD_to_stkL(dst, tmp); | |
8169 %} | |
8170 %} | |
8171 | |
8172 | |
8173 instruct convI2D_helper(regD dst, regF tmp) %{ | |
8174 effect(USE tmp, DEF dst); | |
8175 format %{ "FITOD $tmp,$dst" %} | |
8176 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8177 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); | |
8178 ins_pipe(fcvtI2D); | |
8179 %} | |
8180 | |
8181 instruct convI2D_reg(stackSlotI src, regD dst) %{ | |
8182 match(Set dst (ConvI2D src)); | |
8183 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8184 expand %{ | |
8185 regF tmp; | |
8186 stkI_to_regF( tmp, src); | |
8187 convI2D_helper( dst, tmp); | |
8188 %} | |
8189 %} | |
8190 | |
8191 instruct convI2D_mem( regD_low dst, memory mem ) %{ | |
8192 match(Set dst (ConvI2D (LoadI mem))); | |
8193 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8194 size(8); | |
8195 format %{ "LDF $mem,$dst\n\t" | |
8196 "FITOD $dst,$dst" %} | |
8197 opcode(Assembler::ldf_op3, Assembler::fitod_opf); | |
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8198 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
0 | 8199 ins_pipe(floadF_mem); |
8200 %} | |
8201 | |
8202 | |
8203 instruct convI2F_helper(regF dst, regF tmp) %{ | |
8204 effect(DEF dst, USE tmp); | |
8205 format %{ "FITOS $tmp,$dst" %} | |
8206 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); | |
8207 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); | |
8208 ins_pipe(fcvtI2F); | |
8209 %} | |
8210 | |
8211 instruct convI2F_reg( regF dst, stackSlotI src ) %{ | |
8212 match(Set dst (ConvI2F src)); | |
8213 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8214 expand %{ | |
8215 regF tmp; | |
8216 stkI_to_regF(tmp,src); | |
8217 convI2F_helper(dst, tmp); | |
8218 %} | |
8219 %} | |
8220 | |
8221 instruct convI2F_mem( regF dst, memory mem ) %{ | |
8222 match(Set dst (ConvI2F (LoadI mem))); | |
8223 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8224 size(8); | |
8225 format %{ "LDF $mem,$dst\n\t" | |
8226 "FITOS $dst,$dst" %} | |
8227 opcode(Assembler::ldf_op3, Assembler::fitos_opf); | |
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8228 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); |
0 | 8229 ins_pipe(floadF_mem); |
8230 %} | |
8231 | |
8232 | |
8233 instruct convI2L_reg(iRegL dst, iRegI src) %{ | |
8234 match(Set dst (ConvI2L src)); | |
8235 size(4); | |
8236 format %{ "SRA $src,0,$dst\t! int->long" %} | |
8237 opcode(Assembler::sra_op3, Assembler::arith_op); | |
8238 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8239 ins_pipe(ialu_reg_reg); | |
8240 %} | |
8241 | |
8242 // Zero-extend convert int to long | |
8243 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ | |
8244 match(Set dst (AndL (ConvI2L src) mask) ); | |
8245 size(4); | |
8246 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} | |
8247 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8248 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8249 ins_pipe(ialu_reg_reg); | |
8250 %} | |
8251 | |
8252 // Zero-extend long | |
8253 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ | |
8254 match(Set dst (AndL src mask) ); | |
8255 size(4); | |
8256 format %{ "SRL $src,0,$dst\t! zero-extend long" %} | |
8257 opcode(Assembler::srl_op3, Assembler::arith_op); | |
8258 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); | |
8259 ins_pipe(ialu_reg_reg); | |
8260 %} | |
8261 | |
8262 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ | |
8263 match(Set dst (MoveF2I src)); | |
8264 effect(DEF dst, USE src); | |
8265 ins_cost(MEMORY_REF_COST); | |
8266 | |
8267 size(4); | |
8268 format %{ "LDUW $src,$dst\t! MoveF2I" %} | |
8269 opcode(Assembler::lduw_op3); | |
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8270 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8271 ins_pipe(iload_mem); |
8272 %} | |
8273 | |
8274 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
8275 match(Set dst (MoveI2F src)); | |
8276 effect(DEF dst, USE src); | |
8277 ins_cost(MEMORY_REF_COST); | |
8278 | |
8279 size(4); | |
8280 format %{ "LDF $src,$dst\t! MoveI2F" %} | |
8281 opcode(Assembler::ldf_op3); | |
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8282 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8283 ins_pipe(floadF_stk); |
8284 %} | |
8285 | |
8286 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ | |
8287 match(Set dst (MoveD2L src)); | |
8288 effect(DEF dst, USE src); | |
8289 ins_cost(MEMORY_REF_COST); | |
8290 | |
8291 size(4); | |
8292 format %{ "LDX $src,$dst\t! MoveD2L" %} | |
8293 opcode(Assembler::ldx_op3); | |
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8294 ins_encode(simple_form3_mem_reg( src, dst ) ); |
0 | 8295 ins_pipe(iload_mem); |
8296 %} | |
8297 | |
8298 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
8299 match(Set dst (MoveL2D src)); | |
8300 effect(DEF dst, USE src); | |
8301 ins_cost(MEMORY_REF_COST); | |
8302 | |
8303 size(4); | |
8304 format %{ "LDDF $src,$dst\t! MoveL2D" %} | |
8305 opcode(Assembler::lddf_op3); | |
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8306 ins_encode(simple_form3_mem_reg(src, dst)); |
0 | 8307 ins_pipe(floadD_stk); |
8308 %} | |
8309 | |
8310 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
8311 match(Set dst (MoveF2I src)); | |
8312 effect(DEF dst, USE src); | |
8313 ins_cost(MEMORY_REF_COST); | |
8314 | |
8315 size(4); | |
8316 format %{ "STF $src,$dst\t!MoveF2I" %} | |
8317 opcode(Assembler::stf_op3); | |
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8318 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8319 ins_pipe(fstoreF_stk_reg); |
8320 %} | |
8321 | |
8322 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ | |
8323 match(Set dst (MoveI2F src)); | |
8324 effect(DEF dst, USE src); | |
8325 ins_cost(MEMORY_REF_COST); | |
8326 | |
8327 size(4); | |
8328 format %{ "STW $src,$dst\t!MoveI2F" %} | |
8329 opcode(Assembler::stw_op3); | |
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8330 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8331 ins_pipe(istore_mem_reg); |
8332 %} | |
8333 | |
8334 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
8335 match(Set dst (MoveD2L src)); | |
8336 effect(DEF dst, USE src); | |
8337 ins_cost(MEMORY_REF_COST); | |
8338 | |
8339 size(4); | |
8340 format %{ "STDF $src,$dst\t!MoveD2L" %} | |
8341 opcode(Assembler::stdf_op3); | |
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8342 ins_encode(simple_form3_mem_reg(dst, src)); |
0 | 8343 ins_pipe(fstoreD_stk_reg); |
8344 %} | |
8345 | |
8346 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ | |
8347 match(Set dst (MoveL2D src)); | |
8348 effect(DEF dst, USE src); | |
8349 ins_cost(MEMORY_REF_COST); | |
8350 | |
8351 size(4); | |
8352 format %{ "STX $src,$dst\t!MoveL2D" %} | |
8353 opcode(Assembler::stx_op3); | |
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8354 ins_encode(simple_form3_mem_reg( dst, src ) ); |
0 | 8355 ins_pipe(istore_mem_reg); |
8356 %} | |
8357 | |
8358 | |
8359 //----------- | |
8360 // Long to Double conversion using V8 opcodes. | |
8361 // Still useful because cheetah traps and becomes | |
8362 // amazingly slow for some common numbers. | |
8363 | |
8364 // Magic constant, 0x43300000 | |
8365 instruct loadConI_x43300000(iRegI dst) %{ | |
8366 effect(DEF dst); | |
8367 size(4); | |
8368 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} | |
8369 ins_encode(SetHi22(0x43300000, dst)); | |
8370 ins_pipe(ialu_none); | |
8371 %} | |
8372 | |
8373 // Magic constant, 0x41f00000 | |
8374 instruct loadConI_x41f00000(iRegI dst) %{ | |
8375 effect(DEF dst); | |
8376 size(4); | |
8377 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} | |
8378 ins_encode(SetHi22(0x41f00000, dst)); | |
8379 ins_pipe(ialu_none); | |
8380 %} | |
8381 | |
8382 // Construct a double from two float halves | |
8383 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ | |
8384 effect(DEF dst, USE src1, USE src2); | |
8385 size(8); | |
8386 format %{ "FMOVS $src1.hi,$dst.hi\n\t" | |
8387 "FMOVS $src2.lo,$dst.lo" %} | |
8388 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); | |
8389 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); | |
8390 ins_pipe(faddD_reg_reg); | |
8391 %} | |
8392 | |
8393 // Convert integer in high half of a double register (in the lower half of | |
8394 // the double register file) to double | |
8395 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ | |
8396 effect(DEF dst, USE src); | |
8397 size(4); | |
8398 format %{ "FITOD $src,$dst" %} | |
8399 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); | |
8400 ins_encode(form3_opf_rs2D_rdD(src, dst)); | |
8401 ins_pipe(fcvtLHi2D); | |
8402 %} | |
8403 | |
8404 // Add float double precision | |
8405 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8406 effect(DEF dst, USE src1, USE src2); | |
8407 size(4); | |
8408 format %{ "FADDD $src1,$src2,$dst" %} | |
8409 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); | |
8410 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8411 ins_pipe(faddD_reg_reg); | |
8412 %} | |
8413 | |
8414 // Sub float double precision | |
8415 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8416 effect(DEF dst, USE src1, USE src2); | |
8417 size(4); | |
8418 format %{ "FSUBD $src1,$src2,$dst" %} | |
8419 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); | |
8420 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8421 ins_pipe(faddD_reg_reg); | |
8422 %} | |
8423 | |
8424 // Mul float double precision | |
8425 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ | |
8426 effect(DEF dst, USE src1, USE src2); | |
8427 size(4); | |
8428 format %{ "FMULD $src1,$src2,$dst" %} | |
8429 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); | |
8430 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); | |
8431 ins_pipe(fmulD_reg_reg); | |
8432 %} | |
8433 | |
8434 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ | |
8435 match(Set dst (ConvL2D src)); | |
8436 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); | |
8437 | |
8438 expand %{ | |
8439 regD_low tmpsrc; | |
8440 iRegI ix43300000; | |
8441 iRegI ix41f00000; | |
8442 stackSlotL lx43300000; | |
8443 stackSlotL lx41f00000; | |
8444 regD_low dx43300000; | |
8445 regD dx41f00000; | |
8446 regD tmp1; | |
8447 regD_low tmp2; | |
8448 regD tmp3; | |
8449 regD tmp4; | |
8450 | |
8451 stkL_to_regD(tmpsrc, src); | |
8452 | |
8453 loadConI_x43300000(ix43300000); | |
8454 loadConI_x41f00000(ix41f00000); | |
8455 regI_to_stkLHi(lx43300000, ix43300000); | |
8456 regI_to_stkLHi(lx41f00000, ix41f00000); | |
8457 stkL_to_regD(dx43300000, lx43300000); | |
8458 stkL_to_regD(dx41f00000, lx41f00000); | |
8459 | |
8460 convI2D_regDHi_regD(tmp1, tmpsrc); | |
8461 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); | |
8462 subD_regD_regD(tmp3, tmp2, dx43300000); | |
8463 mulD_regD_regD(tmp4, tmp1, dx41f00000); | |
8464 addD_regD_regD(dst, tmp3, tmp4); | |
8465 %} | |
8466 %} | |
8467 | |
8468 // Long to Double conversion using fast fxtof | |
8469 instruct convL2D_helper(regD dst, regD tmp) %{ | |
8470 effect(DEF dst, USE tmp); | |
8471 size(4); | |
8472 format %{ "FXTOD $tmp,$dst" %} | |
8473 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); | |
8474 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); | |
8475 ins_pipe(fcvtL2D); | |
8476 %} | |
8477 | |
8478 instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ | |
8479 predicate(VM_Version::has_fast_fxtof()); | |
8480 match(Set dst (ConvL2D src)); | |
8481 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); | |
8482 expand %{ | |
8483 regD tmp; | |
8484 stkL_to_regD(tmp, src); | |
8485 convL2D_helper(dst, tmp); | |
8486 %} | |
8487 %} | |
8488 | |
8489 //----------- | |
8490 // Long to Float conversion using V8 opcodes. | |
8491 // Still useful because cheetah traps and becomes | |
8492 // amazingly slow for some common numbers. | |
8493 | |
8494 // Long to Float conversion using fast fxtof | |
8495 instruct convL2F_helper(regF dst, regD tmp) %{ | |
8496 effect(DEF dst, USE tmp); | |
8497 size(4); | |
8498 format %{ "FXTOS $tmp,$dst" %} | |
8499 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); | |
8500 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); | |
8501 ins_pipe(fcvtL2F); | |
8502 %} | |
8503 | |
8504 instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ | |
8505 match(Set dst (ConvL2F src)); | |
8506 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
8507 expand %{ | |
8508 regD tmp; | |
8509 stkL_to_regD(tmp, src); | |
8510 convL2F_helper(dst, tmp); | |
8511 %} | |
8512 %} | |
8513 //----------- | |
8514 | |
8515 instruct convL2I_reg(iRegI dst, iRegL src) %{ | |
8516 match(Set dst (ConvL2I src)); | |
8517 #ifndef _LP64 | |
8518 format %{ "MOV $src.lo,$dst\t! long->int" %} | |
8519 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); | |
8520 ins_pipe(ialu_move_reg_I_to_L); | |
8521 #else | |
8522 size(4); | |
8523 format %{ "SRA $src,R_G0,$dst\t! long->int" %} | |
8524 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); | |
8525 ins_pipe(ialu_reg); | |
8526 #endif | |
8527 %} | |
8528 | |
8529 // Register Shift Right Immediate | |
8530 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ | |
8531 match(Set dst (ConvL2I (RShiftL src cnt))); | |
8532 | |
8533 size(4); | |
8534 format %{ "SRAX $src,$cnt,$dst" %} | |
8535 opcode(Assembler::srax_op3, Assembler::arith_op); | |
8536 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); | |
8537 ins_pipe(ialu_reg_imm); | |
8538 %} | |
8539 | |
8540 // Replicate scalar to packed byte values in Double register | |
8541 instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ | |
8542 effect(DEF dst, USE src); | |
8543 format %{ "SLLX $src,56,$dst\n\t" | |
8544 "SRLX $dst, 8,O7\n\t" | |
8545 "OR $dst,O7,$dst\n\t" | |
8546 "SRLX $dst,16,O7\n\t" | |
8547 "OR $dst,O7,$dst\n\t" | |
8548 "SRLX $dst,32,O7\n\t" | |
8549 "OR $dst,O7,$dst\t! replicate8B" %} | |
8550 ins_encode( enc_repl8b(src, dst)); | |
8551 ins_pipe(ialu_reg); | |
8552 %} | |
8553 | |
8554 // Replicate scalar to packed byte values in Double register | |
8555 instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ | |
8556 match(Set dst (Replicate8B src)); | |
8557 expand %{ | |
8558 iRegL tmp; | |
8559 Repl8B_reg_helper(tmp, src); | |
8560 regL_to_stkD(dst, tmp); | |
8561 %} | |
8562 %} | |
8563 | |
8564 // Replicate scalar constant to packed byte values in Double register | |
8565 instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{ | |
8566 match(Set dst (Replicate8B src)); | |
8567 #ifdef _LP64 | |
8568 size(36); | |
8569 #else | |
8570 size(8); | |
8571 #endif | |
8572 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t" | |
8573 "LDDF [$tmp+lo(&Repl8($src))],$dst" %} | |
8574 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) ); | |
8575 ins_pipe(loadConFD); | |
8576 %} | |
8577 | |
8578 // Replicate scalar to packed char values into stack slot | |
8579 instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ | |
8580 effect(DEF dst, USE src); | |
8581 format %{ "SLLX $src,48,$dst\n\t" | |
8582 "SRLX $dst,16,O7\n\t" | |
8583 "OR $dst,O7,$dst\n\t" | |
8584 "SRLX $dst,32,O7\n\t" | |
8585 "OR $dst,O7,$dst\t! replicate4C" %} | |
8586 ins_encode( enc_repl4s(src, dst) ); | |
8587 ins_pipe(ialu_reg); | |
8588 %} | |
8589 | |
8590 // Replicate scalar to packed char values into stack slot | |
8591 instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ | |
8592 match(Set dst (Replicate4C src)); | |
8593 expand %{ | |
8594 iRegL tmp; | |
8595 Repl4C_reg_helper(tmp, src); | |
8596 regL_to_stkD(dst, tmp); | |
8597 %} | |
8598 %} | |
8599 | |
8600 // Replicate scalar constant to packed char values in Double register | |
8601 instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{ | |
8602 match(Set dst (Replicate4C src)); | |
8603 #ifdef _LP64 | |
8604 size(36); | |
8605 #else | |
8606 size(8); | |
8607 #endif | |
8608 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t" | |
8609 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
8610 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
8611 ins_pipe(loadConFD); | |
8612 %} | |
8613 | |
8614 // Replicate scalar to packed short values into stack slot | |
8615 instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ | |
8616 effect(DEF dst, USE src); | |
8617 format %{ "SLLX $src,48,$dst\n\t" | |
8618 "SRLX $dst,16,O7\n\t" | |
8619 "OR $dst,O7,$dst\n\t" | |
8620 "SRLX $dst,32,O7\n\t" | |
8621 "OR $dst,O7,$dst\t! replicate4S" %} | |
8622 ins_encode( enc_repl4s(src, dst) ); | |
8623 ins_pipe(ialu_reg); | |
8624 %} | |
8625 | |
8626 // Replicate scalar to packed short values into stack slot | |
8627 instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ | |
8628 match(Set dst (Replicate4S src)); | |
8629 expand %{ | |
8630 iRegL tmp; | |
8631 Repl4S_reg_helper(tmp, src); | |
8632 regL_to_stkD(dst, tmp); | |
8633 %} | |
8634 %} | |
8635 | |
8636 // Replicate scalar constant to packed short values in Double register | |
8637 instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{ | |
8638 match(Set dst (Replicate4S src)); | |
8639 #ifdef _LP64 | |
8640 size(36); | |
8641 #else | |
8642 size(8); | |
8643 #endif | |
8644 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t" | |
8645 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} | |
8646 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); | |
8647 ins_pipe(loadConFD); | |
8648 %} | |
8649 | |
8650 // Replicate scalar to packed int values in Double register | |
8651 instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ | |
8652 effect(DEF dst, USE src); | |
8653 format %{ "SLLX $src,32,$dst\n\t" | |
8654 "SRLX $dst,32,O7\n\t" | |
8655 "OR $dst,O7,$dst\t! replicate2I" %} | |
8656 ins_encode( enc_repl2i(src, dst)); | |
8657 ins_pipe(ialu_reg); | |
8658 %} | |
8659 | |
8660 // Replicate scalar to packed int values in Double register | |
8661 instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ | |
8662 match(Set dst (Replicate2I src)); | |
8663 expand %{ | |
8664 iRegL tmp; | |
8665 Repl2I_reg_helper(tmp, src); | |
8666 regL_to_stkD(dst, tmp); | |
8667 %} | |
8668 %} | |
8669 | |
8670 // Replicate scalar zero constant to packed int values in Double register | |
8671 instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{ | |
8672 match(Set dst (Replicate2I src)); | |
8673 #ifdef _LP64 | |
8674 size(36); | |
8675 #else | |
8676 size(8); | |
8677 #endif | |
8678 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t" | |
8679 "LDDF [$tmp+lo(&Repl2($src))],$dst" %} | |
8680 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) ); | |
8681 ins_pipe(loadConFD); | |
8682 %} | |
8683 | |
8684 //----------Control Flow Instructions------------------------------------------ | |
8685 // Compare Instructions | |
8686 // Compare Integers | |
8687 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ | |
8688 match(Set icc (CmpI op1 op2)); | |
8689 effect( DEF icc, USE op1, USE op2 ); | |
8690 | |
8691 size(4); | |
8692 format %{ "CMP $op1,$op2" %} | |
8693 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8694 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8695 ins_pipe(ialu_cconly_reg_reg); | |
8696 %} | |
8697 | |
8698 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ | |
8699 match(Set icc (CmpU op1 op2)); | |
8700 | |
8701 size(4); | |
8702 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8703 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8704 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8705 ins_pipe(ialu_cconly_reg_reg); | |
8706 %} | |
8707 | |
8708 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ | |
8709 match(Set icc (CmpI op1 op2)); | |
8710 effect( DEF icc, USE op1 ); | |
8711 | |
8712 size(4); | |
8713 format %{ "CMP $op1,$op2" %} | |
8714 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8715 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8716 ins_pipe(ialu_cconly_reg_imm); | |
8717 %} | |
8718 | |
8719 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ | |
8720 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8721 | |
8722 size(4); | |
8723 format %{ "BTST $op2,$op1" %} | |
8724 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8725 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8726 ins_pipe(ialu_cconly_reg_reg_zero); | |
8727 %} | |
8728 | |
8729 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ | |
8730 match(Set icc (CmpI (AndI op1 op2) zero)); | |
8731 | |
8732 size(4); | |
8733 format %{ "BTST $op2,$op1" %} | |
8734 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8735 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8736 ins_pipe(ialu_cconly_reg_imm_zero); | |
8737 %} | |
8738 | |
8739 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ | |
8740 match(Set xcc (CmpL op1 op2)); | |
8741 effect( DEF xcc, USE op1, USE op2 ); | |
8742 | |
8743 size(4); | |
8744 format %{ "CMP $op1,$op2\t\t! long" %} | |
8745 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8746 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8747 ins_pipe(ialu_cconly_reg_reg); | |
8748 %} | |
8749 | |
8750 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ | |
8751 match(Set xcc (CmpL op1 con)); | |
8752 effect( DEF xcc, USE op1, USE con ); | |
8753 | |
8754 size(4); | |
8755 format %{ "CMP $op1,$con\t\t! long" %} | |
8756 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8757 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8758 ins_pipe(ialu_cconly_reg_reg); | |
8759 %} | |
8760 | |
8761 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ | |
8762 match(Set xcc (CmpL (AndL op1 op2) zero)); | |
8763 effect( DEF xcc, USE op1, USE op2 ); | |
8764 | |
8765 size(4); | |
8766 format %{ "BTST $op1,$op2\t\t! long" %} | |
8767 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8768 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8769 ins_pipe(ialu_cconly_reg_reg); | |
8770 %} | |
8771 | |
8772 // useful for checking the alignment of a pointer: | |
8773 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ | |
8774 match(Set xcc (CmpL (AndL op1 con) zero)); | |
8775 effect( DEF xcc, USE op1, USE con ); | |
8776 | |
8777 size(4); | |
8778 format %{ "BTST $op1,$con\t\t! long" %} | |
8779 opcode(Assembler::andcc_op3, Assembler::arith_op); | |
8780 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); | |
8781 ins_pipe(ialu_cconly_reg_reg); | |
8782 %} | |
8783 | |
8784 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ | |
8785 match(Set icc (CmpU op1 op2)); | |
8786 | |
8787 size(4); | |
8788 format %{ "CMP $op1,$op2\t! unsigned" %} | |
8789 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8790 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8791 ins_pipe(ialu_cconly_reg_imm); | |
8792 %} | |
8793 | |
8794 // Compare Pointers | |
8795 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ | |
8796 match(Set pcc (CmpP op1 op2)); | |
8797 | |
8798 size(4); | |
8799 format %{ "CMP $op1,$op2\t! ptr" %} | |
8800 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8801 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); | |
8802 ins_pipe(ialu_cconly_reg_reg); | |
8803 %} | |
8804 | |
8805 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ | |
8806 match(Set pcc (CmpP op1 op2)); | |
8807 | |
8808 size(4); | |
8809 format %{ "CMP $op1,$op2\t! ptr" %} | |
8810 opcode(Assembler::subcc_op3, Assembler::arith_op); | |
8811 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); | |
8812 ins_pipe(ialu_cconly_reg_imm); | |
8813 %} | |
8814 | |
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8815 // Compare Narrow oops |
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8816 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ |
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8817 match(Set icc (CmpN op1 op2)); |
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8818 |
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8819 size(4); |
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8820 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8821 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8822 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); |
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8823 ins_pipe(ialu_cconly_reg_reg); |
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8824 %} |
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8825 |
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8826 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ |
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8827 match(Set icc (CmpN op1 op2)); |
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8828 |
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8829 size(4); |
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8830 format %{ "CMP $op1,$op2\t! compressed ptr" %} |
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8831 opcode(Assembler::subcc_op3, Assembler::arith_op); |
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8832 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); |
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8833 ins_pipe(ialu_cconly_reg_imm); |
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8834 %} |
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8835 |
0 | 8836 //----------Max and Min-------------------------------------------------------- |
8837 // Min Instructions | |
8838 // Conditional move for min | |
8839 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
8840 effect( USE_DEF op2, USE op1, USE icc ); | |
8841 | |
8842 size(4); | |
8843 format %{ "MOVlt icc,$op1,$op2\t! min" %} | |
8844 opcode(Assembler::less); | |
8845 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
8846 ins_pipe(ialu_reg_flags); | |
8847 %} | |
8848 | |
8849 // Min Register with Register. | |
8850 instruct minI_eReg(iRegI op1, iRegI op2) %{ | |
8851 match(Set op2 (MinI op1 op2)); | |
8852 ins_cost(DEFAULT_COST*2); | |
8853 expand %{ | |
8854 flagsReg icc; | |
8855 compI_iReg(icc,op1,op2); | |
8856 cmovI_reg_lt(op2,op1,icc); | |
8857 %} | |
8858 %} | |
8859 | |
8860 // Max Instructions | |
8861 // Conditional move for max | |
8862 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ | |
8863 effect( USE_DEF op2, USE op1, USE icc ); | |
8864 format %{ "MOVgt icc,$op1,$op2\t! max" %} | |
8865 opcode(Assembler::greater); | |
8866 ins_encode( enc_cmov_reg_minmax(op2,op1) ); | |
8867 ins_pipe(ialu_reg_flags); | |
8868 %} | |
8869 | |
8870 // Max Register with Register | |
8871 instruct maxI_eReg(iRegI op1, iRegI op2) %{ | |
8872 match(Set op2 (MaxI op1 op2)); | |
8873 ins_cost(DEFAULT_COST*2); | |
8874 expand %{ | |
8875 flagsReg icc; | |
8876 compI_iReg(icc,op1,op2); | |
8877 cmovI_reg_gt(op2,op1,icc); | |
8878 %} | |
8879 %} | |
8880 | |
8881 | |
8882 //----------Float Compares---------------------------------------------------- | |
8883 // Compare floating, generate condition code | |
8884 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ | |
8885 match(Set fcc (CmpF src1 src2)); | |
8886 | |
8887 size(4); | |
8888 format %{ "FCMPs $fcc,$src1,$src2" %} | |
8889 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); | |
8890 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); | |
8891 ins_pipe(faddF_fcc_reg_reg_zero); | |
8892 %} | |
8893 | |
8894 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ | |
8895 match(Set fcc (CmpD src1 src2)); | |
8896 | |
8897 size(4); | |
8898 format %{ "FCMPd $fcc,$src1,$src2" %} | |
8899 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); | |
8900 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); | |
8901 ins_pipe(faddD_fcc_reg_reg_zero); | |
8902 %} | |
8903 | |
8904 | |
8905 // Compare floating, generate -1,0,1 | |
8906 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ | |
8907 match(Set dst (CmpF3 src1 src2)); | |
8908 effect(KILL fcc0); | |
8909 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
8910 format %{ "fcmpl $dst,$src1,$src2" %} | |
8911 // Primary = float | |
8912 opcode( true ); | |
8913 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
8914 ins_pipe( floating_cmp ); | |
8915 %} | |
8916 | |
8917 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ | |
8918 match(Set dst (CmpD3 src1 src2)); | |
8919 effect(KILL fcc0); | |
8920 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); | |
8921 format %{ "dcmpl $dst,$src1,$src2" %} | |
8922 // Primary = double (not float) | |
8923 opcode( false ); | |
8924 ins_encode( floating_cmp( dst, src1, src2 ) ); | |
8925 ins_pipe( floating_cmp ); | |
8926 %} | |
8927 | |
8928 //----------Branches--------------------------------------------------------- | |
8929 // Jump | |
8930 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above) | |
8931 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ | |
8932 match(Jump switch_val); | |
8933 | |
8934 ins_cost(350); | |
8935 | |
8936 format %{ "SETHI [hi(table_base)],O7\n\t" | |
8937 "ADD O7, lo(table_base), O7\n\t" | |
8938 "LD [O7+$switch_val], O7\n\t" | |
8939 "JUMP O7" | |
8940 %} | |
8941 ins_encode( jump_enc( switch_val, table) ); | |
8942 ins_pc_relative(1); | |
8943 ins_pipe(ialu_reg_reg); | |
8944 %} | |
8945 | |
8946 // Direct Branch. Use V8 version with longer range. | |
8947 instruct branch(label labl) %{ | |
8948 match(Goto); | |
8949 effect(USE labl); | |
8950 | |
8951 size(8); | |
8952 ins_cost(BRANCH_COST); | |
8953 format %{ "BA $labl" %} | |
8954 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond | |
8955 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); | |
8956 ins_encode( enc_ba( labl ) ); | |
8957 ins_pc_relative(1); | |
8958 ins_pipe(br); | |
8959 %} | |
8960 | |
8961 // Conditional Direct Branch | |
8962 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ | |
8963 match(If cmp icc); | |
8964 effect(USE labl); | |
8965 | |
8966 size(8); | |
8967 ins_cost(BRANCH_COST); | |
8968 format %{ "BP$cmp $icc,$labl" %} | |
8969 // Prim = bits 24-22, Secnd = bits 31-30 | |
8970 ins_encode( enc_bp( labl, cmp, icc ) ); | |
8971 ins_pc_relative(1); | |
8972 ins_pipe(br_cc); | |
8973 %} | |
8974 | |
8975 // Branch-on-register tests all 64 bits. We assume that values | |
8976 // in 64-bit registers always remains zero or sign extended | |
8977 // unless our code munges the high bits. Interrupts can chop | |
8978 // the high order bits to zero or sign at any time. | |
8979 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ | |
8980 match(If cmp (CmpI op1 zero)); | |
8981 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
8982 effect(USE labl); | |
8983 | |
8984 size(8); | |
8985 ins_cost(BRANCH_COST); | |
8986 format %{ "BR$cmp $op1,$labl" %} | |
8987 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
8988 ins_pc_relative(1); | |
8989 ins_pipe(br_reg); | |
8990 %} | |
8991 | |
8992 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ | |
8993 match(If cmp (CmpP op1 null)); | |
8994 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
8995 effect(USE labl); | |
8996 | |
8997 size(8); | |
8998 ins_cost(BRANCH_COST); | |
8999 format %{ "BR$cmp $op1,$labl" %} | |
9000 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9001 ins_pc_relative(1); | |
9002 ins_pipe(br_reg); | |
9003 %} | |
9004 | |
9005 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ | |
9006 match(If cmp (CmpL op1 zero)); | |
9007 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); | |
9008 effect(USE labl); | |
9009 | |
9010 size(8); | |
9011 ins_cost(BRANCH_COST); | |
9012 format %{ "BR$cmp $op1,$labl" %} | |
9013 ins_encode( enc_bpr( labl, cmp, op1 ) ); | |
9014 ins_pc_relative(1); | |
9015 ins_pipe(br_reg); | |
9016 %} | |
9017 | |
9018 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9019 match(If cmp icc); | |
9020 effect(USE labl); | |
9021 | |
9022 format %{ "BP$cmp $icc,$labl" %} | |
9023 // Prim = bits 24-22, Secnd = bits 31-30 | |
9024 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9025 ins_pc_relative(1); | |
9026 ins_pipe(br_cc); | |
9027 %} | |
9028 | |
9029 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ | |
9030 match(If cmp pcc); | |
9031 effect(USE labl); | |
9032 | |
9033 size(8); | |
9034 ins_cost(BRANCH_COST); | |
9035 format %{ "BP$cmp $pcc,$labl" %} | |
9036 // Prim = bits 24-22, Secnd = bits 31-30 | |
9037 ins_encode( enc_bpx( labl, cmp, pcc ) ); | |
9038 ins_pc_relative(1); | |
9039 ins_pipe(br_cc); | |
9040 %} | |
9041 | |
9042 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ | |
9043 match(If cmp fcc); | |
9044 effect(USE labl); | |
9045 | |
9046 size(8); | |
9047 ins_cost(BRANCH_COST); | |
9048 format %{ "FBP$cmp $fcc,$labl" %} | |
9049 // Prim = bits 24-22, Secnd = bits 31-30 | |
9050 ins_encode( enc_fbp( labl, cmp, fcc ) ); | |
9051 ins_pc_relative(1); | |
9052 ins_pipe(br_fcc); | |
9053 %} | |
9054 | |
9055 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ | |
9056 match(CountedLoopEnd cmp icc); | |
9057 effect(USE labl); | |
9058 | |
9059 size(8); | |
9060 ins_cost(BRANCH_COST); | |
9061 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9062 // Prim = bits 24-22, Secnd = bits 31-30 | |
9063 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9064 ins_pc_relative(1); | |
9065 ins_pipe(br_cc); | |
9066 %} | |
9067 | |
9068 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ | |
9069 match(CountedLoopEnd cmp icc); | |
9070 effect(USE labl); | |
9071 | |
9072 size(8); | |
9073 ins_cost(BRANCH_COST); | |
9074 format %{ "BP$cmp $icc,$labl\t! Loop end" %} | |
9075 // Prim = bits 24-22, Secnd = bits 31-30 | |
9076 ins_encode( enc_bp( labl, cmp, icc ) ); | |
9077 ins_pc_relative(1); | |
9078 ins_pipe(br_cc); | |
9079 %} | |
9080 | |
9081 // ============================================================================ | |
9082 // Long Compare | |
9083 // | |
9084 // Currently we hold longs in 2 registers. Comparing such values efficiently | |
9085 // is tricky. The flavor of compare used depends on whether we are testing | |
9086 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. | |
9087 // The GE test is the negated LT test. The LE test can be had by commuting | |
9088 // the operands (yielding a GE test) and then negating; negate again for the | |
9089 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the | |
9090 // NE test is negated from that. | |
9091 | |
9092 // Due to a shortcoming in the ADLC, it mixes up expressions like: | |
9093 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the | |
9094 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections | |
9095 // are collapsed internally in the ADLC's dfa-gen code. The match for | |
9096 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the | |
9097 // foo match ends up with the wrong leaf. One fix is to not match both | |
9098 // reg-reg and reg-zero forms of long-compare. This is unfortunate because | |
9099 // both forms beat the trinary form of long-compare and both are very useful | |
9100 // on Intel which has so few registers. | |
9101 | |
9102 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ | |
9103 match(If cmp xcc); | |
9104 effect(USE labl); | |
9105 | |
9106 size(8); | |
9107 ins_cost(BRANCH_COST); | |
9108 format %{ "BP$cmp $xcc,$labl" %} | |
9109 // Prim = bits 24-22, Secnd = bits 31-30 | |
9110 ins_encode( enc_bpl( labl, cmp, xcc ) ); | |
9111 ins_pc_relative(1); | |
9112 ins_pipe(br_cc); | |
9113 %} | |
9114 | |
9115 // Manifest a CmpL3 result in an integer register. Very painful. | |
9116 // This is the test to avoid. | |
9117 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ | |
9118 match(Set dst (CmpL3 src1 src2) ); | |
9119 effect( KILL ccr ); | |
9120 ins_cost(6*DEFAULT_COST); | |
9121 size(24); | |
9122 format %{ "CMP $src1,$src2\t\t! long\n" | |
9123 "\tBLT,a,pn done\n" | |
9124 "\tMOV -1,$dst\t! delay slot\n" | |
9125 "\tBGT,a,pn done\n" | |
9126 "\tMOV 1,$dst\t! delay slot\n" | |
9127 "\tCLR $dst\n" | |
9128 "done:" %} | |
9129 ins_encode( cmpl_flag(src1,src2,dst) ); | |
9130 ins_pipe(cmpL_reg); | |
9131 %} | |
9132 | |
9133 // Conditional move | |
9134 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ | |
9135 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9136 ins_cost(150); | |
9137 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9138 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9139 ins_pipe(ialu_reg); | |
9140 %} | |
9141 | |
9142 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ | |
9143 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); | |
9144 ins_cost(140); | |
9145 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} | |
9146 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9147 ins_pipe(ialu_imm); | |
9148 %} | |
9149 | |
9150 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ | |
9151 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9152 ins_cost(150); | |
9153 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9154 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9155 ins_pipe(ialu_reg); | |
9156 %} | |
9157 | |
9158 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ | |
9159 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); | |
9160 ins_cost(140); | |
9161 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9162 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9163 ins_pipe(ialu_imm); | |
9164 %} | |
9165 | |
164
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9166 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ |
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9167 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); |
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9168 ins_cost(150); |
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9169 format %{ "MOV$cmp $xcc,$src,$dst" %} |
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9170 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); |
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9171 ins_pipe(ialu_reg); |
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9172 %} |
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9173 |
0 | 9174 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ |
9175 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9176 ins_cost(150); | |
9177 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9178 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9179 ins_pipe(ialu_reg); | |
9180 %} | |
9181 | |
9182 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ | |
9183 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); | |
9184 ins_cost(140); | |
9185 format %{ "MOV$cmp $xcc,$src,$dst" %} | |
9186 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); | |
9187 ins_pipe(ialu_imm); | |
9188 %} | |
9189 | |
9190 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ | |
9191 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); | |
9192 ins_cost(150); | |
9193 opcode(0x101); | |
9194 format %{ "FMOVS$cmp $xcc,$src,$dst" %} | |
9195 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9196 ins_pipe(int_conditional_float_move); | |
9197 %} | |
9198 | |
9199 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ | |
9200 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); | |
9201 ins_cost(150); | |
9202 opcode(0x102); | |
9203 format %{ "FMOVD$cmp $xcc,$src,$dst" %} | |
9204 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); | |
9205 ins_pipe(int_conditional_float_move); | |
9206 %} | |
9207 | |
9208 // ============================================================================ | |
9209 // Safepoint Instruction | |
9210 instruct safePoint_poll(iRegP poll) %{ | |
9211 match(SafePoint poll); | |
9212 effect(USE poll); | |
9213 | |
9214 size(4); | |
9215 #ifdef _LP64 | |
9216 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9217 #else | |
9218 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} | |
9219 #endif | |
9220 ins_encode %{ | |
9221 __ relocate(relocInfo::poll_type); | |
9222 __ ld_ptr($poll$$Register, 0, G0); | |
9223 %} | |
9224 ins_pipe(loadPollP); | |
9225 %} | |
9226 | |
9227 // ============================================================================ | |
9228 // Call Instructions | |
9229 // Call Java Static Instruction | |
9230 instruct CallStaticJavaDirect( method meth ) %{ | |
9231 match(CallStaticJava); | |
9232 effect(USE meth); | |
9233 | |
9234 size(8); | |
9235 ins_cost(CALL_COST); | |
9236 format %{ "CALL,static ; NOP ==> " %} | |
9237 ins_encode( Java_Static_Call( meth ), call_epilog ); | |
9238 ins_pc_relative(1); | |
9239 ins_pipe(simple_call); | |
9240 %} | |
9241 | |
9242 // Call Java Dynamic Instruction | |
9243 instruct CallDynamicJavaDirect( method meth ) %{ | |
9244 match(CallDynamicJava); | |
9245 effect(USE meth); | |
9246 | |
9247 ins_cost(CALL_COST); | |
9248 format %{ "SET (empty),R_G5\n\t" | |
9249 "CALL,dynamic ; NOP ==> " %} | |
9250 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); | |
9251 ins_pc_relative(1); | |
9252 ins_pipe(call); | |
9253 %} | |
9254 | |
9255 // Call Runtime Instruction | |
9256 instruct CallRuntimeDirect(method meth, l7RegP l7) %{ | |
9257 match(CallRuntime); | |
9258 effect(USE meth, KILL l7); | |
9259 ins_cost(CALL_COST); | |
9260 format %{ "CALL,runtime" %} | |
9261 ins_encode( Java_To_Runtime( meth ), | |
9262 call_epilog, adjust_long_from_native_call ); | |
9263 ins_pc_relative(1); | |
9264 ins_pipe(simple_call); | |
9265 %} | |
9266 | |
9267 // Call runtime without safepoint - same as CallRuntime | |
9268 instruct CallLeafDirect(method meth, l7RegP l7) %{ | |
9269 match(CallLeaf); | |
9270 effect(USE meth, KILL l7); | |
9271 ins_cost(CALL_COST); | |
9272 format %{ "CALL,runtime leaf" %} | |
9273 ins_encode( Java_To_Runtime( meth ), | |
9274 call_epilog, | |
9275 adjust_long_from_native_call ); | |
9276 ins_pc_relative(1); | |
9277 ins_pipe(simple_call); | |
9278 %} | |
9279 | |
9280 // Call runtime without safepoint - same as CallLeaf | |
9281 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ | |
9282 match(CallLeafNoFP); | |
9283 effect(USE meth, KILL l7); | |
9284 ins_cost(CALL_COST); | |
9285 format %{ "CALL,runtime leaf nofp" %} | |
9286 ins_encode( Java_To_Runtime( meth ), | |
9287 call_epilog, | |
9288 adjust_long_from_native_call ); | |
9289 ins_pc_relative(1); | |
9290 ins_pipe(simple_call); | |
9291 %} | |
9292 | |
9293 // Tail Call; Jump from runtime stub to Java code. | |
9294 // Also known as an 'interprocedural jump'. | |
9295 // Target of jump will eventually return to caller. | |
9296 // TailJump below removes the return address. | |
9297 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ | |
9298 match(TailCall jump_target method_oop ); | |
9299 | |
9300 ins_cost(CALL_COST); | |
9301 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} | |
9302 ins_encode(form_jmpl(jump_target)); | |
9303 ins_pipe(tail_call); | |
9304 %} | |
9305 | |
9306 | |
9307 // Return Instruction | |
9308 instruct Ret() %{ | |
9309 match(Return); | |
9310 | |
9311 // The epilogue node did the ret already. | |
9312 size(0); | |
9313 format %{ "! return" %} | |
9314 ins_encode(); | |
9315 ins_pipe(empty); | |
9316 %} | |
9317 | |
9318 | |
9319 // Tail Jump; remove the return address; jump to target. | |
9320 // TailCall above leaves the return address around. | |
9321 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). | |
9322 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a | |
9323 // "restore" before this instruction (in Epilogue), we need to materialize it | |
9324 // in %i0. | |
9325 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ | |
9326 match( TailJump jump_target ex_oop ); | |
9327 ins_cost(CALL_COST); | |
9328 format %{ "! discard R_O7\n\t" | |
9329 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} | |
9330 ins_encode(form_jmpl_set_exception_pc(jump_target)); | |
9331 // opcode(Assembler::jmpl_op3, Assembler::arith_op); | |
9332 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. | |
9333 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); | |
9334 ins_pipe(tail_call); | |
9335 %} | |
9336 | |
9337 // Create exception oop: created by stack-crawling runtime code. | |
9338 // Created exception is now available to this handler, and is setup | |
9339 // just prior to jumping to this handler. No code emitted. | |
9340 instruct CreateException( o0RegP ex_oop ) | |
9341 %{ | |
9342 match(Set ex_oop (CreateEx)); | |
9343 ins_cost(0); | |
9344 | |
9345 size(0); | |
9346 // use the following format syntax | |
9347 format %{ "! exception oop is in R_O0; no code emitted" %} | |
9348 ins_encode(); | |
9349 ins_pipe(empty); | |
9350 %} | |
9351 | |
9352 | |
9353 // Rethrow exception: | |
9354 // The exception oop will come in the first argument position. | |
9355 // Then JUMP (not call) to the rethrow stub code. | |
9356 instruct RethrowException() | |
9357 %{ | |
9358 match(Rethrow); | |
9359 ins_cost(CALL_COST); | |
9360 | |
9361 // use the following format syntax | |
9362 format %{ "Jmp rethrow_stub" %} | |
9363 ins_encode(enc_rethrow); | |
9364 ins_pipe(tail_call); | |
9365 %} | |
9366 | |
9367 | |
9368 // Die now | |
9369 instruct ShouldNotReachHere( ) | |
9370 %{ | |
9371 match(Halt); | |
9372 ins_cost(CALL_COST); | |
9373 | |
9374 size(4); | |
9375 // Use the following format syntax | |
9376 format %{ "ILLTRAP ; ShouldNotReachHere" %} | |
9377 ins_encode( form2_illtrap() ); | |
9378 ins_pipe(tail_call); | |
9379 %} | |
9380 | |
9381 // ============================================================================ | |
9382 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass | |
9383 // array for an instance of the superklass. Set a hidden internal cache on a | |
9384 // hit (cache is checked with exposed code in gen_subtype_check()). Return | |
9385 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. | |
9386 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ | |
9387 match(Set index (PartialSubtypeCheck sub super)); | |
9388 effect( KILL pcc, KILL o7 ); | |
9389 ins_cost(DEFAULT_COST*10); | |
9390 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} | |
9391 ins_encode( enc_PartialSubtypeCheck() ); | |
9392 ins_pipe(partial_subtype_check_pipe); | |
9393 %} | |
9394 | |
9395 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ | |
9396 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); | |
9397 effect( KILL idx, KILL o7 ); | |
9398 ins_cost(DEFAULT_COST*10); | |
9399 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} | |
9400 ins_encode( enc_PartialSubtypeCheck() ); | |
9401 ins_pipe(partial_subtype_check_pipe); | |
9402 %} | |
9403 | |
113
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|
9404 |
0 | 9405 // ============================================================================ |
9406 // inlined locking and unlocking | |
9407 | |
9408 instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
9409 match(Set pcc (FastLock object box)); | |
9410 | |
9411 effect(KILL scratch, TEMP scratch2); | |
9412 ins_cost(100); | |
9413 | |
9414 size(4*112); // conservative overestimation ... | |
9415 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
9416 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); | |
9417 ins_pipe(long_memory_op); | |
9418 %} | |
9419 | |
9420 | |
9421 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ | |
9422 match(Set pcc (FastUnlock object box)); | |
9423 effect(KILL scratch, TEMP scratch2); | |
9424 ins_cost(100); | |
9425 | |
9426 size(4*120); // conservative overestimation ... | |
9427 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} | |
9428 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); | |
9429 ins_pipe(long_memory_op); | |
9430 %} | |
9431 | |
9432 // Count and Base registers are fixed because the allocator cannot | |
9433 // kill unknown registers. The encodings are generic. | |
9434 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ | |
9435 match(Set dummy (ClearArray cnt base)); | |
9436 effect(TEMP temp, KILL ccr); | |
9437 ins_cost(300); | |
9438 format %{ "MOV $cnt,$temp\n" | |
9439 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" | |
9440 " BRge loop\t\t! Clearing loop\n" | |
9441 " STX G0,[$base+$temp]\t! delay slot" %} | |
9442 ins_encode( enc_Clear_Array(cnt, base, temp) ); | |
9443 ins_pipe(long_memory_op); | |
9444 %} | |
9445 | |
986
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
9446 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
9447 o7RegI tmp, flagsReg ccr) %{ |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
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|
9448 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
62001a362ce9
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diff
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|
9449 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); |
0 | 9450 ins_cost(300); |
986
62001a362ce9
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diff
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|
9451 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} |
62001a362ce9
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diff
changeset
|
9452 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); |
0 | 9453 ins_pipe(long_memory_op); |
9454 %} | |
9455 | |
986
62001a362ce9
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diff
changeset
|
9456 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
9457 o7RegI tmp, flagsReg ccr) %{ |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
9458 match(Set result (StrEquals (Binary str1 str2) cnt)); |
62001a362ce9
6827605: new String intrinsics may prevent EA scalar replacement
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diff
changeset
|
9459 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); |
681 | 9460 ins_cost(300); |
986
62001a362ce9
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diff
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|
9461 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} |
62001a362ce9
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diff
changeset
|
9462 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); |
681 | 9463 ins_pipe(long_memory_op); |
9464 %} | |
9465 | |
986
62001a362ce9
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diff
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|
9466 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, |
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diff
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|
9467 o7RegI tmp2, flagsReg ccr) %{ |
681 | 9468 match(Set result (AryEq ary1 ary2)); |
9469 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); | |
9470 ins_cost(300); | |
986
62001a362ce9
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951
diff
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|
9471 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} |
62001a362ce9
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diff
changeset
|
9472 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); |
681 | 9473 ins_pipe(long_memory_op); |
9474 %} | |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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642
diff
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|
9475 |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
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diff
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|
9476 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
9477 //---------- Zeros Count Instructions ------------------------------------------ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
9478 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
9479 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
9480 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
changeset
|
9481 match(Set dst (CountLeadingZerosI src)); |
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
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|
9482 effect(TEMP dst, TEMP tmp, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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diff
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|
9483 |
93c14e5562c4
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diff
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|
9484 // x |= (x >> 1); |
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diff
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|
9485 // x |= (x >> 2); |
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|
9486 // x |= (x >> 4); |
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|
9487 // x |= (x >> 8); |
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|
9488 // x |= (x >> 16); |
93c14e5562c4
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|
9489 // return (WORDBITS - popc(x)); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
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diff
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|
9490 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" |
f875b4f472f7
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diff
changeset
|
9491 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" |
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
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diff
changeset
|
9492 "OR $dst,$tmp,$dst\n\t" |
775
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|
9493 "SRL $dst,2,$tmp\n\t" |
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|
9494 "OR $dst,$tmp,$dst\n\t" |
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|
9495 "SRL $dst,4,$tmp\n\t" |
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|
9496 "OR $dst,$tmp,$dst\n\t" |
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|
9497 "SRL $dst,8,$tmp\n\t" |
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|
9498 "OR $dst,$tmp,$dst\n\t" |
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|
9499 "SRL $dst,16,$tmp\n\t" |
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6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
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|
9500 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
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|
9501 "POPC $dst,$dst\n\t" |
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|
9502 "MOV 32,$tmp\n\t" |
93c14e5562c4
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twisti
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|
9503 "SUB $tmp,$dst,$dst" %} |
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|
9504 ins_encode %{ |
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|
9505 Register Rdst = $dst$$Register; |
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|
9506 Register Rsrc = $src$$Register; |
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|
9507 Register Rtmp = $tmp$$Register; |
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|
9508 __ srl(Rsrc, 1, Rtmp); |
1041
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|
9509 __ srl(Rsrc, 0, Rdst); |
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diff
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|
9510 __ or3(Rdst, Rtmp, Rdst); |
775
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|
9511 __ srl(Rdst, 2, Rtmp); |
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|
9512 __ or3(Rdst, Rtmp, Rdst); |
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|
9513 __ srl(Rdst, 4, Rtmp); |
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|
9514 __ or3(Rdst, Rtmp, Rdst); |
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|
9515 __ srl(Rdst, 8, Rtmp); |
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|
9516 __ or3(Rdst, Rtmp, Rdst); |
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|
9517 __ srl(Rdst, 16, Rtmp); |
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|
9518 __ or3(Rdst, Rtmp, Rdst); |
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|
9519 __ popc(Rdst, Rdst); |
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|
9520 __ mov(BitsPerInt, Rtmp); |
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|
9521 __ sub(Rtmp, Rdst, Rdst); |
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|
9522 %} |
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|
9523 ins_pipe(ialu_reg); |
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|
9524 %} |
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|
9525 |
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|
9526 instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{ |
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|
9527 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
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|
9528 match(Set dst (CountLeadingZerosL src)); |
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|
9529 effect(TEMP dst, TEMP tmp, KILL cr); |
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|
9530 |
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|
9531 // x |= (x >> 1); |
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|
9532 // x |= (x >> 2); |
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changeset
|
9533 // x |= (x >> 4); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9534 // x |= (x >> 8); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9535 // x |= (x >> 16); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9536 // x |= (x >> 32); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9537 // return (WORDBITS - popc(x)); |
1041
f875b4f472f7
6893554: SPECjvm2008 mpegaudio fails with SecurityException
twisti
parents:
1016
diff
changeset
|
9538 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" |
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9539 "OR $src,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9540 "SRLX $dst,2,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9541 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9542 "SRLX $dst,4,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9543 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9544 "SRLX $dst,8,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9545 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9546 "SRLX $dst,16,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9547 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9548 "SRLX $dst,32,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9549 "OR $dst,$tmp,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9550 "POPC $dst,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9551 "MOV 64,$tmp\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9552 "SUB $tmp,$dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9553 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9554 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9555 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9556 Register Rtmp = $tmp$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9557 __ srlx(Rsrc, 1, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9558 __ or3(Rsrc, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9559 __ srlx(Rdst, 2, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9560 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9561 __ srlx(Rdst, 4, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9562 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9563 __ srlx(Rdst, 8, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9564 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9565 __ srlx(Rdst, 16, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9566 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9567 __ srlx(Rdst, 32, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9568 __ or3(Rdst, Rtmp, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9569 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9570 __ mov(BitsPerLong, Rtmp); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9571 __ sub(Rtmp, Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9572 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9573 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9574 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9575 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9576 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9577 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9578 match(Set dst (CountTrailingZerosI src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9579 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9580 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9581 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9582 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9583 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9584 "SRL $dst,R_G0,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9585 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9586 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9587 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9588 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9589 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9590 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9591 __ srl(Rdst, G0, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9592 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9593 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9594 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9595 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9596 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9597 instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9598 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9599 match(Set dst (CountTrailingZerosL src)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9600 effect(TEMP dst, KILL cr); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9601 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9602 // return popc(~x & (x - 1)); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9603 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9604 "ANDN $dst,$src,$dst\n\t" |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9605 "POPC $dst,$dst" %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9606 ins_encode %{ |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9607 Register Rdst = $dst$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9608 Register Rsrc = $src$$Register; |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9609 __ sub(Rsrc, 1, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9610 __ andn(Rdst, Rsrc, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9611 __ popc(Rdst, Rdst); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9612 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9613 ins_pipe(ialu_reg); |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9614 %} |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9615 |
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
732
diff
changeset
|
9616 |
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9617 //---------- Population Count Instructions ------------------------------------- |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9618 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9619 instruct popCountI(iRegI dst, iRegI src) %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9620 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9621 match(Set dst (PopCountI src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9622 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9623 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9624 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9625 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9626 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9627 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9628 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9629 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9630 // Note: Long.bitCount(long) returns an int. |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9631 instruct popCountL(iRegI dst, iRegL src) %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9632 predicate(UsePopCountInstruction); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9633 match(Set dst (PopCountL src)); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9634 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9635 format %{ "POPC $src, $dst" %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9636 ins_encode %{ |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9637 __ popc($src$$Register, $dst$$Register); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9638 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9639 ins_pipe(ialu_reg); |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9640 %} |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9641 |
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
9642 |
0 | 9643 // ============================================================================ |
9644 //------------Bytes reverse-------------------------------------------------- | |
9645 | |
9646 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ | |
9647 match(Set dst (ReverseBytesI src)); | |
9648 effect(DEF dst, USE src); | |
9649 | |
9650 // Op cost is artificially doubled to make sure that load or store | |
9651 // instructions are preferred over this one which requires a spill | |
9652 // onto a stack slot. | |
9653 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
9654 size(8); | |
9655 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} | |
9656 opcode(Assembler::lduwa_op3); | |
9657 ins_encode( form3_mem_reg_little(src, dst) ); | |
9658 ins_pipe( iload_mem ); | |
9659 %} | |
9660 | |
9661 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ | |
9662 match(Set dst (ReverseBytesL src)); | |
9663 effect(DEF dst, USE src); | |
9664 | |
9665 // Op cost is artificially doubled to make sure that load or store | |
9666 // instructions are preferred over this one which requires a spill | |
9667 // onto a stack slot. | |
9668 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); | |
9669 size(8); | |
9670 format %{ "LDXA $src, $dst\t!asi=primary_little" %} | |
9671 | |
9672 opcode(Assembler::ldxa_op3); | |
9673 ins_encode( form3_mem_reg_little(src, dst) ); | |
9674 ins_pipe( iload_mem ); | |
9675 %} | |
9676 | |
9677 // Load Integer reversed byte order | |
9678 instruct loadI_reversed(iRegI dst, memory src) %{ | |
9679 match(Set dst (ReverseBytesI (LoadI src))); | |
9680 | |
9681 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
9682 size(8); | |
9683 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} | |
9684 | |
9685 opcode(Assembler::lduwa_op3); | |
9686 ins_encode( form3_mem_reg_little( src, dst) ); | |
9687 ins_pipe(iload_mem); | |
9688 %} | |
9689 | |
9690 // Load Long - aligned and reversed | |
9691 instruct loadL_reversed(iRegL dst, memory src) %{ | |
9692 match(Set dst (ReverseBytesL (LoadL src))); | |
9693 | |
9694 ins_cost(DEFAULT_COST + MEMORY_REF_COST); | |
9695 size(8); | |
9696 format %{ "LDXA $src, $dst\t!asi=primary_little" %} | |
9697 | |
9698 opcode(Assembler::ldxa_op3); | |
9699 ins_encode( form3_mem_reg_little( src, dst ) ); | |
9700 ins_pipe(iload_mem); | |
9701 %} | |
9702 | |
9703 // Store Integer reversed byte order | |
9704 instruct storeI_reversed(memory dst, iRegI src) %{ | |
9705 match(Set dst (StoreI dst (ReverseBytesI src))); | |
9706 | |
9707 ins_cost(MEMORY_REF_COST); | |
9708 size(8); | |
9709 format %{ "STWA $src, $dst\t!asi=primary_little" %} | |
9710 | |
9711 opcode(Assembler::stwa_op3); | |
9712 ins_encode( form3_mem_reg_little( dst, src) ); | |
9713 ins_pipe(istore_mem_reg); | |
9714 %} | |
9715 | |
9716 // Store Long reversed byte order | |
9717 instruct storeL_reversed(memory dst, iRegL src) %{ | |
9718 match(Set dst (StoreL dst (ReverseBytesL src))); | |
9719 | |
9720 ins_cost(MEMORY_REF_COST); | |
9721 size(8); | |
9722 format %{ "STXA $src, $dst\t!asi=primary_little" %} | |
9723 | |
9724 opcode(Assembler::stxa_op3); | |
9725 ins_encode( form3_mem_reg_little( dst, src) ); | |
9726 ins_pipe(istore_mem_reg); | |
9727 %} | |
9728 | |
9729 //----------PEEPHOLE RULES----------------------------------------------------- | |
9730 // These must follow all instruction definitions as they use the names | |
9731 // defined in the instructions definitions. | |
9732 // | |
605 | 9733 // peepmatch ( root_instr_name [preceding_instruction]* ); |
0 | 9734 // |
9735 // peepconstraint %{ | |
9736 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
9737 // [, ...] ); | |
9738 // // instruction numbers are zero-based using left to right order in peepmatch | |
9739 // | |
9740 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
9741 // // provide an instruction_number.operand_name for each operand that appears | |
9742 // // in the replacement instruction's match rule | |
9743 // | |
9744 // ---------VM FLAGS--------------------------------------------------------- | |
9745 // | |
9746 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
9747 // | |
9748 // Each peephole rule is given an identifying number starting with zero and | |
9749 // increasing by one in the order seen by the parser. An individual peephole | |
9750 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
9751 // on the command-line. | |
9752 // | |
9753 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
9754 // | |
9755 // Only match adjacent instructions in same basic block | |
9756 // Only equality constraints | |
9757 // Only constraints between operands, not (0.dest_reg == EAX_enc) | |
9758 // Only one replacement instruction | |
9759 // | |
9760 // ---------EXAMPLE---------------------------------------------------------- | |
9761 // | |
9762 // // pertinent parts of existing instructions in architecture description | |
9763 // instruct movI(eRegI dst, eRegI src) %{ | |
9764 // match(Set dst (CopyI src)); | |
9765 // %} | |
9766 // | |
9767 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ | |
9768 // match(Set dst (AddI dst src)); | |
9769 // effect(KILL cr); | |
9770 // %} | |
9771 // | |
9772 // // Change (inc mov) to lea | |
9773 // peephole %{ | |
9774 // // increment preceeded by register-register move | |
9775 // peepmatch ( incI_eReg movI ); | |
9776 // // require that the destination register of the increment | |
9777 // // match the destination register of the move | |
9778 // peepconstraint ( 0.dst == 1.dst ); | |
9779 // // construct a replacement instruction that sets | |
9780 // // the destination to ( move's source register + one ) | |
9781 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); | |
9782 // %} | |
9783 // | |
9784 | |
9785 // // Change load of spilled value to only a spill | |
9786 // instruct storeI(memory mem, eRegI src) %{ | |
9787 // match(Set mem (StoreI mem src)); | |
9788 // %} | |
9789 // | |
9790 // instruct loadI(eRegI dst, memory mem) %{ | |
9791 // match(Set dst (LoadI mem)); | |
9792 // %} | |
9793 // | |
9794 // peephole %{ | |
9795 // peepmatch ( loadI storeI ); | |
9796 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); | |
9797 // peepreplace ( storeI( 1.mem 1.mem 1.src ) ); | |
9798 // %} | |
9799 | |
9800 //----------SMARTSPILL RULES--------------------------------------------------- | |
9801 // These must follow all instruction definitions as they use the names | |
9802 // defined in the instructions definitions. | |
9803 // | |
9804 // SPARC will probably not have any of these rules due to RISC instruction set. | |
9805 | |
9806 //----------PIPELINE----------------------------------------------------------- | |
9807 // Rules which define the behavior of the target architectures pipeline. |