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annotate graal/com.oracle.graal.lir.amd64/src/com/oracle/graal/lir/amd64/AMD64Binary.java @ 21673:5024c80224c7

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moved com.oracle.graal.[amd64|sparc] to com.oracle.jvmci.[amd64|sparc] (JBS:GRAAL-53)
author Doug Simon <doug.simon@oracle.com>
date Tue, 02 Jun 2015 22:11:52 +0200
parents 48c1ebd24120
children 6df25b1418be
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
19971
46dde3e92715 Restructure AMD64 LIR classes.
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1 /*
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2 * Copyright (c) 2015, 2015, Oracle and/or its affiliates. All rights reserved.
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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4 *
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5 * This code is free software; you can redistribute it and/or modify it
46dde3e92715 Restructure AMD64 LIR classes.
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6 * under the terms of the GNU General Public License version 2 only, as
46dde3e92715 Restructure AMD64 LIR classes.
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7 * published by the Free Software Foundation.
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8 *
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9 * This code is distributed in the hope that it will be useful, but WITHOUT
46dde3e92715 Restructure AMD64 LIR classes.
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
46dde3e92715 Restructure AMD64 LIR classes.
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
46dde3e92715 Restructure AMD64 LIR classes.
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12 * version 2 for more details (a copy is included in the LICENSE file that
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13 * accompanied this code).
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14 *
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15 * You should have received a copy of the GNU General Public License version
46dde3e92715 Restructure AMD64 LIR classes.
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16 * 2 along with this work; if not, write to the Free Software Foundation,
46dde3e92715 Restructure AMD64 LIR classes.
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17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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18 *
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
46dde3e92715 Restructure AMD64 LIR classes.
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20 * or visit www.oracle.com if you need additional information or have any
46dde3e92715 Restructure AMD64 LIR classes.
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21 * questions.
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22 */
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23 package com.oracle.graal.lir.amd64;
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24
21556
48c1ebd24120 renamed com.oracle.graal.api[meta|code] modules to com.oracle.jvmci.[meta|code] (JBS:GRAAL-53)
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25 import com.oracle.jvmci.meta.AllocatableValue;
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26 import com.oracle.jvmci.meta.Value;
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27 import com.oracle.jvmci.meta.JavaConstant;
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28 import static com.oracle.jvmci.code.ValueUtil.*;
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29 import static com.oracle.graal.lir.LIRInstruction.OperandFlag.*;
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30
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31 import com.oracle.jvmci.code.CompilationResult.DataSectionReference;
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32 import com.oracle.graal.asm.*;
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33 import com.oracle.graal.asm.amd64.*;
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34 import com.oracle.graal.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic;
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35 import com.oracle.graal.asm.amd64.AMD64Assembler.AMD64MIOp;
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36 import com.oracle.graal.asm.amd64.AMD64Assembler.AMD64RMIOp;
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37 import com.oracle.graal.asm.amd64.AMD64Assembler.AMD64RMOp;
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38 import com.oracle.graal.asm.amd64.AMD64Assembler.OperandSize;
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39 import com.oracle.graal.lir.*;
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40 import com.oracle.graal.lir.StandardOp.ImplicitNullCheck;
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41 import com.oracle.graal.lir.asm.*;
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42
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43 /**
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44 * AMD64 LIR instructions that have two inputs and one output.
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45 */
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46 public class AMD64Binary {
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47
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48 /**
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49 * Instruction that has two {@link AllocatableValue} operands.
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50 */
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51 public static class Op extends AMD64LIRInstruction {
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52 public static final LIRInstructionClass<Op> TYPE = LIRInstructionClass.create(Op.class);
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53
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54 @Opcode private final AMD64RMOp opcode;
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55 private final OperandSize size;
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56
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57 @Def({REG, HINT}) protected AllocatableValue result;
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58 @Use({REG, STACK}) protected AllocatableValue x;
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59 @Alive({REG, STACK}) protected AllocatableValue y;
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60
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61 public Op(AMD64RMOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y) {
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62 super(TYPE);
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63 this.opcode = opcode;
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64 this.size = size;
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65
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66 this.result = result;
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67 this.x = x;
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68 this.y = y;
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69 }
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70
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71 @Override
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72 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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73 AMD64Move.move(crb, masm, result, x);
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74 if (isRegister(y)) {
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75 opcode.emit(masm, size, asRegister(result), asRegister(y));
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76 } else {
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77 assert isStackSlot(y);
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78 opcode.emit(masm, size, asRegister(result), (AMD64Address) crb.asAddress(y));
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79 }
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80 }
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81 }
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82
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83 /**
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84 * Commutative instruction that has two {@link AllocatableValue} operands.
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85 */
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86 public static class CommutativeOp extends AMD64LIRInstruction {
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87 public static final LIRInstructionClass<CommutativeOp> TYPE = LIRInstructionClass.create(CommutativeOp.class);
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88
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89 @Opcode private final AMD64RMOp opcode;
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90 private final OperandSize size;
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91
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92 @Def({REG, HINT}) protected AllocatableValue result;
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93 @Use({REG, STACK}) protected AllocatableValue x;
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94 @Use({REG, STACK}) protected AllocatableValue y;
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95
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96 public CommutativeOp(AMD64RMOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y) {
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97 super(TYPE);
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98 this.opcode = opcode;
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99 this.size = size;
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100
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101 this.result = result;
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102 this.x = x;
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103 this.y = y;
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104 }
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105
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106 @Override
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107 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
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108 AllocatableValue input;
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109 if (sameRegister(result, y)) {
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110 input = x;
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111 } else {
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112 AMD64Move.move(crb, masm, result, x);
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113 input = y;
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114 }
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115
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116 if (isRegister(input)) {
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117 opcode.emit(masm, size, asRegister(result), asRegister(input));
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118 } else {
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119 assert isStackSlot(input);
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120 opcode.emit(masm, size, asRegister(result), (AMD64Address) crb.asAddress(input));
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121 }
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122 }
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123 }
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124
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125 /**
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126 * Instruction that has one {@link AllocatableValue} operand and one 32-bit immediate operand.
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127 */
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128 public static class ConstOp extends AMD64LIRInstruction {
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129 public static final LIRInstructionClass<ConstOp> TYPE = LIRInstructionClass.create(ConstOp.class);
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130
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131 @Opcode private final AMD64MIOp opcode;
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132 private final OperandSize size;
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133
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134 @Def({REG, HINT}) protected AllocatableValue result;
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135 @Use({REG, STACK}) protected AllocatableValue x;
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136 private final int y;
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137
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138 public ConstOp(AMD64BinaryArithmetic opcode, OperandSize size, AllocatableValue result, AllocatableValue x, int y) {
46dde3e92715 Restructure AMD64 LIR classes.
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parents:
diff changeset
139 this(opcode.getMIOpcode(size, NumUtil.isByte(y)), size, result, x, y);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
140 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
141
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
142 public ConstOp(AMD64MIOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, int y) {
46dde3e92715 Restructure AMD64 LIR classes.
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parents:
diff changeset
143 super(TYPE);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
144 this.opcode = opcode;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
145 this.size = size;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
146
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
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diff changeset
147 this.result = result;
46dde3e92715 Restructure AMD64 LIR classes.
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diff changeset
148 this.x = x;
46dde3e92715 Restructure AMD64 LIR classes.
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parents:
diff changeset
149 this.y = y;
46dde3e92715 Restructure AMD64 LIR classes.
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parents:
diff changeset
150 }
46dde3e92715 Restructure AMD64 LIR classes.
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parents:
diff changeset
151
46dde3e92715 Restructure AMD64 LIR classes.
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diff changeset
152 @Override
46dde3e92715 Restructure AMD64 LIR classes.
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153 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
46dde3e92715 Restructure AMD64 LIR classes.
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diff changeset
154 AMD64Move.move(crb, masm, result, x);
46dde3e92715 Restructure AMD64 LIR classes.
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parents:
diff changeset
155 opcode.emit(masm, size, asRegister(result), y);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
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156 }
46dde3e92715 Restructure AMD64 LIR classes.
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parents:
diff changeset
157 }
46dde3e92715 Restructure AMD64 LIR classes.
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parents:
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158
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
159 /**
46dde3e92715 Restructure AMD64 LIR classes.
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160 * Instruction that has one {@link AllocatableValue} operand and one
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
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161 * {@link DataSectionReference} operand.
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
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162 */
46dde3e92715 Restructure AMD64 LIR classes.
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163 public static class DataOp extends AMD64LIRInstruction {
46dde3e92715 Restructure AMD64 LIR classes.
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164 public static final LIRInstructionClass<DataOp> TYPE = LIRInstructionClass.create(DataOp.class);
46dde3e92715 Restructure AMD64 LIR classes.
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165
46dde3e92715 Restructure AMD64 LIR classes.
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166 @Opcode private final AMD64RMOp opcode;
46dde3e92715 Restructure AMD64 LIR classes.
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167 private final OperandSize size;
46dde3e92715 Restructure AMD64 LIR classes.
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168
46dde3e92715 Restructure AMD64 LIR classes.
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diff changeset
169 @Def({REG, HINT}) protected AllocatableValue result;
46dde3e92715 Restructure AMD64 LIR classes.
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diff changeset
170 @Use({REG, STACK}) protected AllocatableValue x;
46dde3e92715 Restructure AMD64 LIR classes.
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diff changeset
171 private final JavaConstant y;
46dde3e92715 Restructure AMD64 LIR classes.
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172
46dde3e92715 Restructure AMD64 LIR classes.
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173 private final int alignment;
46dde3e92715 Restructure AMD64 LIR classes.
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174
46dde3e92715 Restructure AMD64 LIR classes.
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175 public DataOp(AMD64RMOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, JavaConstant y) {
46dde3e92715 Restructure AMD64 LIR classes.
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parents:
diff changeset
176 this(opcode, size, result, x, y, y.getKind().getByteCount());
46dde3e92715 Restructure AMD64 LIR classes.
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177 }
46dde3e92715 Restructure AMD64 LIR classes.
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178
46dde3e92715 Restructure AMD64 LIR classes.
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diff changeset
179 public DataOp(AMD64RMOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, JavaConstant y, int alignment) {
46dde3e92715 Restructure AMD64 LIR classes.
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parents:
diff changeset
180 super(TYPE);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
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181 this.opcode = opcode;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
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182 this.size = size;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
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diff changeset
183
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
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diff changeset
184 this.result = result;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
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diff changeset
185 this.x = x;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
186 this.y = y;
46dde3e92715 Restructure AMD64 LIR classes.
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diff changeset
187
46dde3e92715 Restructure AMD64 LIR classes.
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188 this.alignment = alignment;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
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189 }
46dde3e92715 Restructure AMD64 LIR classes.
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parents:
diff changeset
190
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
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diff changeset
191 @Override
46dde3e92715 Restructure AMD64 LIR classes.
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192 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
193 AMD64Move.move(crb, masm, result, x);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
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diff changeset
194 opcode.emit(masm, size, asRegister(result), (AMD64Address) crb.recordDataReferenceInCode(y, alignment));
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
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195 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
196 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
197
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
198 /**
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
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199 * Instruction that has one {@link AllocatableValue} operand and one {@link AMD64AddressValue
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
200 * memory} operand.
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
201 */
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
202 public static class MemoryOp extends AMD64LIRInstruction implements ImplicitNullCheck {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
203 public static final LIRInstructionClass<MemoryOp> TYPE = LIRInstructionClass.create(MemoryOp.class);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
204
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
205 @Opcode private final AMD64RMOp opcode;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
206 private final OperandSize size;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
207
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
208 @Def({REG, HINT}) protected AllocatableValue result;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
209 @Use({REG, STACK}) protected AllocatableValue x;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
210 @Alive({COMPOSITE}) protected AMD64AddressValue y;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
211
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
212 @State protected LIRFrameState state;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
213
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
214 public MemoryOp(AMD64RMOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, AMD64AddressValue y, LIRFrameState state) {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
215 super(TYPE);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
216 this.opcode = opcode;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
217 this.size = size;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
218
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
219 this.result = result;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
220 this.x = x;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
221 this.y = y;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
222
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
223 this.state = state;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
224 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
225
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
226 @Override
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
227 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
228 AMD64Move.move(crb, masm, result, x);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
229 if (state != null) {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
230 crb.recordImplicitException(masm.position(), state);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
231 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
232 opcode.emit(masm, size, asRegister(result), y.toAddress());
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
233 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
234
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
235 @Override
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
236 public void verify() {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
237 super.verify();
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
238 assert differentRegisters(result, y) || sameRegister(x, y);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
239 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
240
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
241 @Override
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
242 public boolean makeNullCheckFor(Value value, LIRFrameState nullCheckState, int implicitNullCheckLimit) {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
243 if (state == null && y.isValidImplicitNullCheckFor(value, implicitNullCheckLimit)) {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
244 state = nullCheckState;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
245 return true;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
246 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
247 return false;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
248 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
249 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
250
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
251 /**
46dde3e92715 Restructure AMD64 LIR classes.
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parents:
diff changeset
252 * Instruction with a separate result operand, one {@link AllocatableValue} input and one 32-bit
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
253 * immediate input.
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
254 */
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
255 public static class RMIOp extends AMD64LIRInstruction {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
256 public static final LIRInstructionClass<RMIOp> TYPE = LIRInstructionClass.create(RMIOp.class);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
257
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
258 @Opcode private final AMD64RMIOp opcode;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
259 private final OperandSize size;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
260
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
261 @Def({REG}) protected AllocatableValue result;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
262 @Use({REG, STACK}) protected AllocatableValue x;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
263 private final int y;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
264
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
265 public RMIOp(AMD64RMIOp opcode, OperandSize size, AllocatableValue result, AllocatableValue x, int y) {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
266 super(TYPE);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
267 this.opcode = opcode;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
268 this.size = size;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
269
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
270 this.result = result;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
271 this.x = x;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
272 this.y = y;
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
273 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
274
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
275 @Override
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
276 public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm) {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
277 if (isRegister(x)) {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
278 opcode.emit(masm, size, asRegister(result), asRegister(x), y);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
279 } else {
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
280 assert isStackSlot(x);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
281 opcode.emit(masm, size, asRegister(result), (AMD64Address) crb.asAddress(x), y);
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
282 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
283 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
284 }
46dde3e92715 Restructure AMD64 LIR classes.
Roland Schatz <roland.schatz@oracle.com>
parents:
diff changeset
285 }