Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/vm_version_x86.hpp @ 13020:60a32bb8ff99
8027444: mathExact: assert(i < _max) failed: oob: i=1, _max=1
Reviewed-by: duke
author | rbackman |
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date | Wed, 30 Oct 2013 13:14:09 +0100 |
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rev | line source |
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585 | 1 /* |
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2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. |
585 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
585 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP |
26 #define CPU_X86_VM_VM_VERSION_X86_HPP | |
27 | |
28 #include "runtime/globals_extension.hpp" | |
29 #include "runtime/vm_version.hpp" | |
30 | |
585 | 31 class VM_Version : public Abstract_VM_Version { |
32 public: | |
33 // cpuid result register layouts. These are all unions of a uint32_t | |
34 // (in case anyone wants access to the register as a whole) and a bitfield. | |
35 | |
36 union StdCpuid1Eax { | |
37 uint32_t value; | |
38 struct { | |
39 uint32_t stepping : 4, | |
40 model : 4, | |
41 family : 4, | |
42 proc_type : 2, | |
43 : 2, | |
44 ext_model : 4, | |
45 ext_family : 8, | |
46 : 4; | |
47 } bits; | |
48 }; | |
49 | |
50 union StdCpuid1Ebx { // example, unused | |
51 uint32_t value; | |
52 struct { | |
53 uint32_t brand_id : 8, | |
54 clflush_size : 8, | |
55 threads_per_cpu : 8, | |
56 apic_id : 8; | |
57 } bits; | |
58 }; | |
59 | |
60 union StdCpuid1Ecx { | |
61 uint32_t value; | |
62 struct { | |
63 uint32_t sse3 : 1, | |
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64 clmul : 1, |
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65 : 1, |
585 | 66 monitor : 1, |
67 : 1, | |
68 vmx : 1, | |
69 : 1, | |
70 est : 1, | |
71 : 1, | |
72 ssse3 : 1, | |
73 cid : 1, | |
74 : 2, | |
75 cmpxchg16: 1, | |
76 : 4, | |
77 dca : 1, | |
78 sse4_1 : 1, | |
79 sse4_2 : 1, | |
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80 : 2, |
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81 popcnt : 1, |
6894 | 82 : 1, |
83 aes : 1, | |
84 : 1, | |
4759 | 85 osxsave : 1, |
86 avx : 1, | |
87 : 3; | |
585 | 88 } bits; |
89 }; | |
90 | |
91 union StdCpuid1Edx { | |
92 uint32_t value; | |
93 struct { | |
94 uint32_t : 4, | |
95 tsc : 1, | |
96 : 3, | |
97 cmpxchg8 : 1, | |
98 : 6, | |
99 cmov : 1, | |
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100 : 3, |
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101 clflush : 1, |
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102 : 3, |
585 | 103 mmx : 1, |
104 fxsr : 1, | |
105 sse : 1, | |
106 sse2 : 1, | |
107 : 1, | |
108 ht : 1, | |
109 : 3; | |
110 } bits; | |
111 }; | |
112 | |
113 union DcpCpuid4Eax { | |
114 uint32_t value; | |
115 struct { | |
116 uint32_t cache_type : 5, | |
117 : 21, | |
118 cores_per_cpu : 6; | |
119 } bits; | |
120 }; | |
121 | |
122 union DcpCpuid4Ebx { | |
123 uint32_t value; | |
124 struct { | |
125 uint32_t L1_line_size : 12, | |
126 partitions : 10, | |
127 associativity : 10; | |
128 } bits; | |
129 }; | |
130 | |
1622 | 131 union TplCpuidBEbx { |
132 uint32_t value; | |
133 struct { | |
134 uint32_t logical_cpus : 16, | |
135 : 16; | |
136 } bits; | |
137 }; | |
138 | |
585 | 139 union ExtCpuid1Ecx { |
140 uint32_t value; | |
141 struct { | |
142 uint32_t LahfSahf : 1, | |
143 CmpLegacy : 1, | |
144 : 4, | |
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145 lzcnt : 1, |
585 | 146 sse4a : 1, |
147 misalignsse : 1, | |
148 prefetchw : 1, | |
149 : 22; | |
150 } bits; | |
151 }; | |
152 | |
153 union ExtCpuid1Edx { | |
154 uint32_t value; | |
155 struct { | |
156 uint32_t : 22, | |
157 mmx_amd : 1, | |
158 mmx : 1, | |
159 fxsr : 1, | |
160 : 4, | |
161 long_mode : 1, | |
162 tdnow2 : 1, | |
163 tdnow : 1; | |
164 } bits; | |
165 }; | |
166 | |
167 union ExtCpuid5Ex { | |
168 uint32_t value; | |
169 struct { | |
170 uint32_t L1_line_size : 8, | |
171 L1_tag_lines : 8, | |
172 L1_assoc : 8, | |
173 L1_size : 8; | |
174 } bits; | |
175 }; | |
176 | |
4771 | 177 union ExtCpuid7Edx { |
178 uint32_t value; | |
179 struct { | |
180 uint32_t : 8, | |
181 tsc_invariance : 1, | |
182 : 23; | |
183 } bits; | |
184 }; | |
185 | |
585 | 186 union ExtCpuid8Ecx { |
187 uint32_t value; | |
188 struct { | |
189 uint32_t cores_per_cpu : 8, | |
190 : 24; | |
191 } bits; | |
192 }; | |
193 | |
4759 | 194 union SefCpuid7Eax { |
195 uint32_t value; | |
196 }; | |
197 | |
198 union SefCpuid7Ebx { | |
199 uint32_t value; | |
200 struct { | |
201 uint32_t fsgsbase : 1, | |
202 : 2, | |
203 bmi1 : 1, | |
204 : 1, | |
205 avx2 : 1, | |
206 : 2, | |
207 bmi2 : 1, | |
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208 erms : 1, |
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209 : 22; |
4759 | 210 } bits; |
211 }; | |
212 | |
213 union XemXcr0Eax { | |
214 uint32_t value; | |
215 struct { | |
216 uint32_t x87 : 1, | |
217 sse : 1, | |
218 ymm : 1, | |
219 : 29; | |
220 } bits; | |
221 }; | |
222 | |
585 | 223 protected: |
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224 static int _cpu; |
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225 static int _model; |
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226 static int _stepping; |
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227 static int _cpuFeatures; // features returned by the "cpuid" instruction |
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228 // 0 if this instruction is not available |
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229 static const char* _features_str; |
585 | 230 |
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231 enum { |
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232 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) |
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233 CPU_CMOV = (1 << 1), |
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234 CPU_FXSR = (1 << 2), |
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235 CPU_HT = (1 << 3), |
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236 CPU_MMX = (1 << 4), |
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237 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions |
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238 // may not necessarily support other 3dnow instructions |
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239 CPU_SSE = (1 << 6), |
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240 CPU_SSE2 = (1 << 7), |
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241 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) |
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242 CPU_SSSE3 = (1 << 9), |
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243 CPU_SSE4A = (1 << 10), |
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244 CPU_SSE4_1 = (1 << 11), |
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245 CPU_SSE4_2 = (1 << 12), |
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246 CPU_POPCNT = (1 << 13), |
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247 CPU_LZCNT = (1 << 14), |
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248 CPU_TSC = (1 << 15), |
4771 | 249 CPU_TSCINV = (1 << 16), |
250 CPU_AVX = (1 << 17), | |
6894 | 251 CPU_AVX2 = (1 << 18), |
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252 CPU_AES = (1 << 19), |
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253 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions |
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254 CPU_CLMUL = (1 << 21) // carryless multiply for CRC |
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255 } cpuFeatureFlags; |
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256 |
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257 enum { |
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258 // AMD |
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259 CPU_FAMILY_AMD_11H = 0x11, |
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260 // Intel |
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261 CPU_FAMILY_INTEL_CORE = 6, |
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262 CPU_MODEL_NEHALEM = 0x1e, |
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263 CPU_MODEL_NEHALEM_EP = 0x1a, |
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264 CPU_MODEL_NEHALEM_EX = 0x2e, |
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265 CPU_MODEL_WESTMERE = 0x25, |
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266 CPU_MODEL_WESTMERE_EP = 0x2c, |
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267 CPU_MODEL_WESTMERE_EX = 0x2f, |
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268 CPU_MODEL_SANDYBRIDGE = 0x2a, |
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269 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, |
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270 CPU_MODEL_IVYBRIDGE_EP = 0x3a |
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271 } cpuExtendedFamily; |
585 | 272 |
273 // cpuid information block. All info derived from executing cpuid with | |
274 // various function numbers is stored here. Intel and AMD info is | |
275 // merged in this block: accessor methods disentangle it. | |
276 // | |
277 // The info block is laid out in subblocks of 4 dwords corresponding to | |
278 // eax, ebx, ecx and edx, whether or not they contain anything useful. | |
279 struct CpuidInfo { | |
280 // cpuid function 0 | |
281 uint32_t std_max_function; | |
282 uint32_t std_vendor_name_0; | |
283 uint32_t std_vendor_name_1; | |
284 uint32_t std_vendor_name_2; | |
285 | |
286 // cpuid function 1 | |
287 StdCpuid1Eax std_cpuid1_eax; | |
288 StdCpuid1Ebx std_cpuid1_ebx; | |
289 StdCpuid1Ecx std_cpuid1_ecx; | |
290 StdCpuid1Edx std_cpuid1_edx; | |
291 | |
292 // cpuid function 4 (deterministic cache parameters) | |
293 DcpCpuid4Eax dcp_cpuid4_eax; | |
294 DcpCpuid4Ebx dcp_cpuid4_ebx; | |
295 uint32_t dcp_cpuid4_ecx; // unused currently | |
296 uint32_t dcp_cpuid4_edx; // unused currently | |
297 | |
4759 | 298 // cpuid function 7 (structured extended features) |
299 SefCpuid7Eax sef_cpuid7_eax; | |
300 SefCpuid7Ebx sef_cpuid7_ebx; | |
301 uint32_t sef_cpuid7_ecx; // unused currently | |
302 uint32_t sef_cpuid7_edx; // unused currently | |
303 | |
1622 | 304 // cpuid function 0xB (processor topology) |
305 // ecx = 0 | |
306 uint32_t tpl_cpuidB0_eax; | |
307 TplCpuidBEbx tpl_cpuidB0_ebx; | |
308 uint32_t tpl_cpuidB0_ecx; // unused currently | |
309 uint32_t tpl_cpuidB0_edx; // unused currently | |
310 | |
311 // ecx = 1 | |
312 uint32_t tpl_cpuidB1_eax; | |
313 TplCpuidBEbx tpl_cpuidB1_ebx; | |
314 uint32_t tpl_cpuidB1_ecx; // unused currently | |
315 uint32_t tpl_cpuidB1_edx; // unused currently | |
316 | |
317 // ecx = 2 | |
318 uint32_t tpl_cpuidB2_eax; | |
319 TplCpuidBEbx tpl_cpuidB2_ebx; | |
320 uint32_t tpl_cpuidB2_ecx; // unused currently | |
321 uint32_t tpl_cpuidB2_edx; // unused currently | |
322 | |
585 | 323 // cpuid function 0x80000000 // example, unused |
324 uint32_t ext_max_function; | |
325 uint32_t ext_vendor_name_0; | |
326 uint32_t ext_vendor_name_1; | |
327 uint32_t ext_vendor_name_2; | |
328 | |
329 // cpuid function 0x80000001 | |
330 uint32_t ext_cpuid1_eax; // reserved | |
331 uint32_t ext_cpuid1_ebx; // reserved | |
332 ExtCpuid1Ecx ext_cpuid1_ecx; | |
333 ExtCpuid1Edx ext_cpuid1_edx; | |
334 | |
335 // cpuid functions 0x80000002 thru 0x80000004: example, unused | |
336 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; | |
337 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; | |
338 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; | |
339 | |
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340 // cpuid function 0x80000005 // AMD L1, Intel reserved |
585 | 341 uint32_t ext_cpuid5_eax; // unused currently |
342 uint32_t ext_cpuid5_ebx; // reserved | |
343 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) | |
344 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) | |
345 | |
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346 // cpuid function 0x80000007 |
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347 uint32_t ext_cpuid7_eax; // reserved |
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348 uint32_t ext_cpuid7_ebx; // reserved |
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349 uint32_t ext_cpuid7_ecx; // reserved |
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350 ExtCpuid7Edx ext_cpuid7_edx; // tscinv |
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351 |
585 | 352 // cpuid function 0x80000008 |
353 uint32_t ext_cpuid8_eax; // unused currently | |
354 uint32_t ext_cpuid8_ebx; // reserved | |
355 ExtCpuid8Ecx ext_cpuid8_ecx; | |
356 uint32_t ext_cpuid8_edx; // reserved | |
4759 | 357 |
358 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) | |
359 XemXcr0Eax xem_xcr0_eax; | |
360 uint32_t xem_xcr0_edx; // reserved | |
585 | 361 }; |
362 | |
363 // The actual cpuid info block | |
364 static CpuidInfo _cpuid_info; | |
365 | |
366 // Extractors and predicates | |
367 static uint32_t extended_cpu_family() { | |
368 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; | |
369 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; | |
370 return result; | |
371 } | |
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372 |
585 | 373 static uint32_t extended_cpu_model() { |
374 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; | |
375 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; | |
376 return result; | |
377 } | |
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378 |
585 | 379 static uint32_t cpu_stepping() { |
380 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; | |
381 return result; | |
382 } | |
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383 |
585 | 384 static uint logical_processor_count() { |
385 uint result = threads_per_core(); | |
386 return result; | |
387 } | |
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388 |
585 | 389 static uint32_t feature_flags() { |
390 uint32_t result = 0; | |
391 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) | |
392 result |= CPU_CX8; | |
393 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) | |
394 result |= CPU_CMOV; | |
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395 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && |
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396 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) |
585 | 397 result |= CPU_FXSR; |
398 // HT flag is set for multi-core processors also. | |
399 if (threads_per_core() > 1) | |
400 result |= CPU_HT; | |
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401 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && |
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402 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) |
585 | 403 result |= CPU_MMX; |
404 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) | |
405 result |= CPU_SSE; | |
406 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) | |
407 result |= CPU_SSE2; | |
408 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) | |
409 result |= CPU_SSE3; | |
410 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) | |
411 result |= CPU_SSSE3; | |
412 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) | |
413 result |= CPU_SSE4_1; | |
414 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) | |
415 result |= CPU_SSE4_2; | |
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416 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) |
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417 result |= CPU_POPCNT; |
4759 | 418 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && |
419 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && | |
420 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && | |
421 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { | |
422 result |= CPU_AVX; | |
423 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) | |
424 result |= CPU_AVX2; | |
425 } | |
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426 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) |
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427 result |= CPU_TSC; |
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428 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) |
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429 result |= CPU_TSCINV; |
6894 | 430 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) |
431 result |= CPU_AES; | |
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432 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) |
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433 result |= CPU_ERMS; |
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434 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) |
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435 result |= CPU_CLMUL; |
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436 |
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437 // AMD features. |
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438 if (is_amd()) { |
2479 | 439 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || |
440 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) | |
441 result |= CPU_3DNOW_PREFETCH; | |
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442 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) |
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443 result |= CPU_LZCNT; |
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444 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) |
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445 result |= CPU_SSE4A; |
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446 } |
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447 |
585 | 448 return result; |
449 } | |
450 | |
451 static void get_processor_features(); | |
452 | |
453 public: | |
454 // Offsets for cpuid asm stub | |
455 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } | |
456 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } | |
457 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } | |
4759 | 458 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } |
585 | 459 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } |
460 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } | |
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461 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } |
585 | 462 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } |
1622 | 463 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } |
464 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } | |
465 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } | |
4759 | 466 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } |
585 | 467 |
468 // Initialization | |
469 static void initialize(); | |
470 | |
471 // Asserts | |
472 static void assert_is_initialized() { | |
473 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); | |
474 } | |
475 | |
476 // | |
477 // Processor family: | |
478 // 3 - 386 | |
479 // 4 - 486 | |
480 // 5 - Pentium | |
481 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, | |
482 // Pentium M, Core Solo, Core Duo, Core2 Duo | |
483 // family 6 model: 9, 13, 14, 15 | |
484 // 0x0f - Pentium 4, Opteron | |
485 // | |
486 // Note: The cpu family should be used to select between | |
487 // instruction sequences which are valid on all Intel | |
488 // processors. Use the feature test functions below to | |
489 // determine whether a particular instruction is supported. | |
490 // | |
491 static int cpu_family() { return _cpu;} | |
492 static bool is_P6() { return cpu_family() >= 6; } | |
493 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' | |
494 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' | |
495 | |
1647 | 496 static bool supports_processor_topology() { |
497 return (_cpuid_info.std_max_function >= 0xB) && | |
498 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. | |
499 // Some cpus have max cpuid >= 0xB but do not support processor topology. | |
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500 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); |
1647 | 501 } |
502 | |
585 | 503 static uint cores_per_cpu() { |
504 uint result = 1; | |
505 if (is_intel()) { | |
1647 | 506 if (supports_processor_topology()) { |
1622 | 507 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / |
508 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; | |
509 } else { | |
510 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); | |
511 } | |
585 | 512 } else if (is_amd()) { |
513 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); | |
514 } | |
515 return result; | |
516 } | |
517 | |
518 static uint threads_per_core() { | |
519 uint result = 1; | |
1647 | 520 if (is_intel() && supports_processor_topology()) { |
1622 | 521 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; |
522 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { | |
585 | 523 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / |
524 cores_per_cpu(); | |
525 } | |
526 return result; | |
527 } | |
528 | |
3854 | 529 static intx prefetch_data_size() { |
585 | 530 intx result = 0; |
531 if (is_intel()) { | |
532 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); | |
533 } else if (is_amd()) { | |
534 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; | |
535 } | |
536 if (result < 32) // not defined ? | |
537 result = 32; // 32 bytes by default on x86 and other x64 | |
538 return result; | |
539 } | |
540 | |
541 // | |
542 // Feature identification | |
543 // | |
544 static bool supports_cpuid() { return _cpuFeatures != 0; } | |
545 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } | |
546 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } | |
547 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } | |
548 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } | |
549 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } | |
550 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } | |
551 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } | |
552 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } | |
553 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } | |
554 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } | |
555 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } | |
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556 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } |
4759 | 557 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } |
558 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } | |
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559 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } |
6894 | 560 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } |
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561 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } |
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562 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } |
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563 |
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564 // Intel features |
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565 static bool is_intel_family_core() { return is_intel() && |
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566 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } |
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567 |
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568 static bool is_intel_tsc_synched_at_init() { |
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569 if (is_intel_family_core()) { |
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570 uint32_t ext_model = extended_cpu_model(); |
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571 if (ext_model == CPU_MODEL_NEHALEM_EP || |
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572 ext_model == CPU_MODEL_WESTMERE_EP || |
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573 ext_model == CPU_MODEL_SANDYBRIDGE_EP || |
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574 ext_model == CPU_MODEL_IVYBRIDGE_EP) { |
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575 // <= 2-socket invariant tsc support. EX versions are usually used |
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576 // in > 2-socket systems and likely don't synchronize tscs at |
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577 // initialization. |
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578 // Code that uses tsc values must be prepared for them to arbitrarily |
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579 // jump forward or backward. |
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580 return true; |
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581 } |
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582 } |
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583 return false; |
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584 } |
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585 |
585 | 586 // AMD features |
2479 | 587 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } |
585 | 588 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } |
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589 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } |
585 | 590 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } |
591 | |
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592 static bool is_amd_Barcelona() { return is_amd() && |
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593 extended_cpu_family() == CPU_FAMILY_AMD_11H; } |
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594 |
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595 // Intel and AMD newer cores support fast timestamps well |
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596 static bool supports_tscinv_bit() { |
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597 return (_cpuFeatures & CPU_TSCINV) != 0; |
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598 } |
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599 static bool supports_tscinv() { |
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600 return supports_tscinv_bit() && |
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601 ( (is_amd() && !is_amd_Barcelona()) || |
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602 is_intel_tsc_synched_at_init() ); |
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603 } |
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604 |
1914
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605 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). |
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606 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && |
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607 supports_sse3() && _model != 0x1C; } |
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608 |
585 | 609 static bool supports_compare_and_exchange() { return true; } |
610 | |
611 static const char* cpu_features() { return _features_str; } | |
612 | |
613 static intx allocate_prefetch_distance() { | |
614 // This method should be called before allocate_prefetch_style(). | |
615 // | |
616 // Hardware prefetching (distance/size in bytes): | |
617 // Pentium 3 - 64 / 32 | |
618 // Pentium 4 - 256 / 128 | |
619 // Athlon - 64 / 32 ???? | |
620 // Opteron - 128 / 64 only when 2 sequential cache lines accessed | |
621 // Core - 128 / 64 | |
622 // | |
623 // Software prefetching (distance in bytes / instruction with best score): | |
624 // Pentium 3 - 128 / prefetchnta | |
625 // Pentium 4 - 512 / prefetchnta | |
626 // Athlon - 128 / prefetchnta | |
627 // Opteron - 256 / prefetchnta | |
628 // Core - 256 / prefetchnta | |
629 // It will be used only when AllocatePrefetchStyle > 0 | |
630 | |
631 intx count = AllocatePrefetchDistance; | |
632 if (count < 0) { // default ? | |
633 if (is_amd()) { // AMD | |
634 if (supports_sse2()) | |
635 count = 256; // Opteron | |
636 else | |
637 count = 128; // Athlon | |
638 } else { // Intel | |
639 if (supports_sse2()) | |
640 if (cpu_family() == 6) { | |
641 count = 256; // Pentium M, Core, Core2 | |
642 } else { | |
643 count = 512; // Pentium 4 | |
644 } | |
645 else | |
646 count = 128; // Pentium 3 (and all other old CPUs) | |
647 } | |
648 } | |
649 return count; | |
650 } | |
651 static intx allocate_prefetch_style() { | |
652 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); | |
653 // Return 0 if AllocatePrefetchDistance was not defined. | |
654 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; | |
655 } | |
656 | |
657 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from | |
658 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. | |
659 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. | |
660 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. | |
661 | |
662 // gc copy/scan is disabled if prefetchw isn't supported, because | |
663 // Prefetch::write emits an inlined prefetchw on Linux. | |
664 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. | |
665 // The used prefetcht0 instruction works for both amd64 and em64t. | |
666 static intx prefetch_copy_interval_in_bytes() { | |
667 intx interval = PrefetchCopyIntervalInBytes; | |
668 return interval >= 0 ? interval : 576; | |
669 } | |
670 static intx prefetch_scan_interval_in_bytes() { | |
671 intx interval = PrefetchScanIntervalInBytes; | |
672 return interval >= 0 ? interval : 576; | |
673 } | |
674 static intx prefetch_fields_ahead() { | |
675 intx count = PrefetchFieldsAhead; | |
676 return count >= 0 ? count : 1; | |
677 } | |
678 }; | |
1972 | 679 |
680 #endif // CPU_X86_VM_VM_VERSION_X86_HPP |