Mercurial > hg > graal-compiler
annotate src/cpu/x86/vm/x86_64.ad @ 1842:6e0aac35bfa9
6980838: G1: guarantee(false) failed: thread has an unexpected active value in its SATB queue
Summary: Under certain circumstances a safepoint could happen between a JavaThread object being created and that object being added to the Java threads list. This could cause the active field of that thread's SATB queue to get out-of-sync with respect to the other Java threads. The solution is to activate the SATB queue, when necessary, before adding the thread to the Java threads list, not when the JavaThread object is created. The changeset also includes a small fix to rename the surrogate locker thread from "Surrogate Locker Thread (CMS)" to "Surrogate Locker Thread (Concurrent GC)" since it's also used in G1.
Reviewed-by: iveresov, ysr, johnc, jcoomes
| author | tonyp |
|---|---|
| date | Fri, 01 Oct 2010 16:43:05 -0400 |
| parents | 3e8fbc61cee8 |
| children | 52e82a6bedaf |
| rev | line source |
|---|---|
| 0 | 1 // |
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2 // Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 // | |
| 5 // This code is free software; you can redistribute it and/or modify it | |
| 6 // under the terms of the GNU General Public License version 2 only, as | |
| 7 // published by the Free Software Foundation. | |
| 8 // | |
| 9 // This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 // version 2 for more details (a copy is included in the LICENSE file that | |
| 13 // accompanied this code). | |
| 14 // | |
| 15 // You should have received a copy of the GNU General Public License version | |
| 16 // 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 // | |
|
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19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 // or visit www.oracle.com if you need additional information or have any |
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21 // questions. |
| 0 | 22 // |
| 23 // | |
| 24 | |
| 25 // AMD64 Architecture Description File | |
| 26 | |
| 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ | |
| 28 // This information is used by the matcher and the register allocator to | |
| 29 // describe individual registers and classes of registers within the target | |
| 30 // archtecture. | |
| 31 | |
| 32 register %{ | |
| 33 //----------Architecture Description Register Definitions---------------------- | |
| 34 // General Registers | |
| 35 // "reg_def" name ( register save type, C convention save type, | |
| 36 // ideal register type, encoding ); | |
| 37 // Register Save Types: | |
| 38 // | |
| 39 // NS = No-Save: The register allocator assumes that these registers | |
| 40 // can be used without saving upon entry to the method, & | |
| 41 // that they do not need to be saved at call sites. | |
| 42 // | |
| 43 // SOC = Save-On-Call: The register allocator assumes that these registers | |
| 44 // can be used without saving upon entry to the method, | |
| 45 // but that they must be saved at call sites. | |
| 46 // | |
| 47 // SOE = Save-On-Entry: The register allocator assumes that these registers | |
| 48 // must be saved before using them upon entry to the | |
| 49 // method, but they do not need to be saved at call | |
| 50 // sites. | |
| 51 // | |
| 52 // AS = Always-Save: The register allocator assumes that these registers | |
| 53 // must be saved before using them upon entry to the | |
| 54 // method, & that they must be saved at call sites. | |
| 55 // | |
| 56 // Ideal Register Type is used to determine how to save & restore a | |
| 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get | |
| 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. | |
| 59 // | |
| 60 // The encoding number is the actual bit-pattern placed into the opcodes. | |
| 61 | |
| 62 // General Registers | |
| 63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when | |
| 64 // used as byte registers) | |
| 65 | |
| 66 // Previously set RBX, RSI, and RDI as save-on-entry for java code | |
| 67 // Turn off SOE in java-code due to frequent use of uncommon-traps. | |
| 68 // Now that allocator is better, turn on RSI and RDI as SOE registers. | |
| 69 | |
| 70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg()); | |
| 71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next()); | |
| 72 | |
| 73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); | |
| 74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next()); | |
| 75 | |
| 76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); | |
| 77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next()); | |
| 78 | |
| 79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); | |
| 80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next()); | |
| 81 | |
| 82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg()); | |
| 83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next()); | |
| 84 | |
| 85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code | |
| 86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg()); | |
| 87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next()); | |
| 88 | |
| 89 #ifdef _WIN64 | |
| 90 | |
| 91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); | |
| 92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 93 | |
| 94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); | |
| 95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 96 | |
| 97 #else | |
| 98 | |
| 99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg()); | |
| 100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next()); | |
| 101 | |
| 102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg()); | |
| 103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next()); | |
| 104 | |
| 105 #endif | |
| 106 | |
| 107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg()); | |
| 108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next()); | |
| 109 | |
| 110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg()); | |
| 111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next()); | |
| 112 | |
| 113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg()); | |
| 114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next()); | |
| 115 | |
| 116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg()); | |
| 117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next()); | |
| 118 | |
| 119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg()); | |
| 120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next()); | |
| 121 | |
| 122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg()); | |
| 123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next()); | |
| 124 | |
| 125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg()); | |
| 126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next()); | |
| 127 | |
| 128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg()); | |
| 129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next()); | |
| 130 | |
| 131 | |
| 132 // Floating Point Registers | |
| 133 | |
| 134 // XMM registers. 128-bit registers or 4 words each, labeled (a)-d. | |
| 135 // Word a in each register holds a Float, words ab hold a Double. We | |
| 136 // currently do not use the SIMD capabilities, so registers cd are | |
| 137 // unused at the moment. | |
| 138 // XMM8-XMM15 must be encoded with REX. | |
| 139 // Linux ABI: No register preserved across function calls | |
| 140 // XMM0-XMM7 might hold parameters | |
| 141 // Windows ABI: XMM6-XMM15 preserved across function calls | |
| 142 // XMM0-XMM3 might hold parameters | |
| 143 | |
| 144 reg_def XMM0 (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); | |
| 145 reg_def XMM0_H (SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); | |
| 146 | |
| 147 reg_def XMM1 (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); | |
| 148 reg_def XMM1_H (SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); | |
| 149 | |
| 150 reg_def XMM2 (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); | |
| 151 reg_def XMM2_H (SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); | |
| 152 | |
| 153 reg_def XMM3 (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); | |
| 154 reg_def XMM3_H (SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); | |
| 155 | |
| 156 reg_def XMM4 (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); | |
| 157 reg_def XMM4_H (SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); | |
| 158 | |
| 159 reg_def XMM5 (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); | |
| 160 reg_def XMM5_H (SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); | |
| 161 | |
| 162 #ifdef _WIN64 | |
| 163 | |
| 164 reg_def XMM6 (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()); | |
| 165 reg_def XMM6_H (SOC, SOE, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 166 | |
| 167 reg_def XMM7 (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()); | |
| 168 reg_def XMM7_H (SOC, SOE, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 169 | |
| 170 reg_def XMM8 (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()); | |
| 171 reg_def XMM8_H (SOC, SOE, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
| 172 | |
| 173 reg_def XMM9 (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()); | |
| 174 reg_def XMM9_H (SOC, SOE, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
| 175 | |
| 176 reg_def XMM10 (SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()); | |
| 177 reg_def XMM10_H(SOC, SOE, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
| 178 | |
| 179 reg_def XMM11 (SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()); | |
| 180 reg_def XMM11_H(SOC, SOE, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
| 181 | |
| 182 reg_def XMM12 (SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()); | |
| 183 reg_def XMM12_H(SOC, SOE, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
| 184 | |
| 185 reg_def XMM13 (SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()); | |
| 186 reg_def XMM13_H(SOC, SOE, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
| 187 | |
| 188 reg_def XMM14 (SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()); | |
| 189 reg_def XMM14_H(SOC, SOE, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
| 190 | |
| 191 reg_def XMM15 (SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()); | |
| 192 reg_def XMM15_H(SOC, SOE, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
| 193 | |
| 194 #else | |
| 195 | |
| 196 reg_def XMM6 (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); | |
| 197 reg_def XMM6_H (SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); | |
| 198 | |
| 199 reg_def XMM7 (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); | |
| 200 reg_def XMM7_H (SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); | |
| 201 | |
| 202 reg_def XMM8 (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()); | |
| 203 reg_def XMM8_H (SOC, SOC, Op_RegF, 8, xmm8->as_VMReg()->next()); | |
| 204 | |
| 205 reg_def XMM9 (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()); | |
| 206 reg_def XMM9_H (SOC, SOC, Op_RegF, 9, xmm9->as_VMReg()->next()); | |
| 207 | |
| 208 reg_def XMM10 (SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()); | |
| 209 reg_def XMM10_H(SOC, SOC, Op_RegF, 10, xmm10->as_VMReg()->next()); | |
| 210 | |
| 211 reg_def XMM11 (SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()); | |
| 212 reg_def XMM11_H(SOC, SOC, Op_RegF, 11, xmm11->as_VMReg()->next()); | |
| 213 | |
| 214 reg_def XMM12 (SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()); | |
| 215 reg_def XMM12_H(SOC, SOC, Op_RegF, 12, xmm12->as_VMReg()->next()); | |
| 216 | |
| 217 reg_def XMM13 (SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()); | |
| 218 reg_def XMM13_H(SOC, SOC, Op_RegF, 13, xmm13->as_VMReg()->next()); | |
| 219 | |
| 220 reg_def XMM14 (SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()); | |
| 221 reg_def XMM14_H(SOC, SOC, Op_RegF, 14, xmm14->as_VMReg()->next()); | |
| 222 | |
| 223 reg_def XMM15 (SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()); | |
| 224 reg_def XMM15_H(SOC, SOC, Op_RegF, 15, xmm15->as_VMReg()->next()); | |
| 225 | |
| 226 #endif // _WIN64 | |
| 227 | |
| 228 reg_def RFLAGS(SOC, SOC, 0, 16, VMRegImpl::Bad()); | |
| 229 | |
| 230 // Specify priority of register selection within phases of register | |
| 231 // allocation. Highest priority is first. A useful heuristic is to | |
| 232 // give registers a low priority when they are required by machine | |
| 233 // instructions, like EAX and EDX on I486, and choose no-save registers | |
| 234 // before save-on-call, & save-on-call before save-on-entry. Registers | |
| 235 // which participate in fixed calling sequences should come last. | |
| 236 // Registers which are used as pairs must fall on an even boundary. | |
| 237 | |
| 238 alloc_class chunk0(R10, R10_H, | |
| 239 R11, R11_H, | |
| 240 R8, R8_H, | |
| 241 R9, R9_H, | |
| 242 R12, R12_H, | |
| 243 RCX, RCX_H, | |
| 244 RBX, RBX_H, | |
| 245 RDI, RDI_H, | |
| 246 RDX, RDX_H, | |
| 247 RSI, RSI_H, | |
| 248 RAX, RAX_H, | |
| 249 RBP, RBP_H, | |
| 250 R13, R13_H, | |
| 251 R14, R14_H, | |
| 252 R15, R15_H, | |
| 253 RSP, RSP_H); | |
| 254 | |
| 255 // XXX probably use 8-15 first on Linux | |
| 256 alloc_class chunk1(XMM0, XMM0_H, | |
| 257 XMM1, XMM1_H, | |
| 258 XMM2, XMM2_H, | |
| 259 XMM3, XMM3_H, | |
| 260 XMM4, XMM4_H, | |
| 261 XMM5, XMM5_H, | |
| 262 XMM6, XMM6_H, | |
| 263 XMM7, XMM7_H, | |
| 264 XMM8, XMM8_H, | |
| 265 XMM9, XMM9_H, | |
| 266 XMM10, XMM10_H, | |
| 267 XMM11, XMM11_H, | |
| 268 XMM12, XMM12_H, | |
| 269 XMM13, XMM13_H, | |
| 270 XMM14, XMM14_H, | |
| 271 XMM15, XMM15_H); | |
| 272 | |
| 273 alloc_class chunk2(RFLAGS); | |
| 274 | |
| 275 | |
| 276 //----------Architecture Description Register Classes-------------------------- | |
| 277 // Several register classes are automatically defined based upon information in | |
| 278 // this architecture description. | |
| 279 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) | |
| 280 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) | |
| 281 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) | |
| 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) | |
| 283 // | |
| 284 | |
| 285 // Class for all pointer registers (including RSP) | |
| 286 reg_class any_reg(RAX, RAX_H, | |
| 287 RDX, RDX_H, | |
| 288 RBP, RBP_H, | |
| 289 RDI, RDI_H, | |
| 290 RSI, RSI_H, | |
| 291 RCX, RCX_H, | |
| 292 RBX, RBX_H, | |
| 293 RSP, RSP_H, | |
| 294 R8, R8_H, | |
| 295 R9, R9_H, | |
| 296 R10, R10_H, | |
| 297 R11, R11_H, | |
| 298 R12, R12_H, | |
| 299 R13, R13_H, | |
| 300 R14, R14_H, | |
| 301 R15, R15_H); | |
| 302 | |
| 303 // Class for all pointer registers except RSP | |
| 304 reg_class ptr_reg(RAX, RAX_H, | |
| 305 RDX, RDX_H, | |
| 306 RBP, RBP_H, | |
| 307 RDI, RDI_H, | |
| 308 RSI, RSI_H, | |
| 309 RCX, RCX_H, | |
| 310 RBX, RBX_H, | |
| 311 R8, R8_H, | |
| 312 R9, R9_H, | |
| 313 R10, R10_H, | |
| 314 R11, R11_H, | |
| 315 R13, R13_H, | |
| 316 R14, R14_H); | |
| 317 | |
| 318 // Class for all pointer registers except RAX and RSP | |
| 319 reg_class ptr_no_rax_reg(RDX, RDX_H, | |
| 320 RBP, RBP_H, | |
| 321 RDI, RDI_H, | |
| 322 RSI, RSI_H, | |
| 323 RCX, RCX_H, | |
| 324 RBX, RBX_H, | |
| 325 R8, R8_H, | |
| 326 R9, R9_H, | |
| 327 R10, R10_H, | |
| 328 R11, R11_H, | |
| 329 R13, R13_H, | |
| 330 R14, R14_H); | |
| 331 | |
| 332 reg_class ptr_no_rbp_reg(RDX, RDX_H, | |
| 333 RAX, RAX_H, | |
| 334 RDI, RDI_H, | |
| 335 RSI, RSI_H, | |
| 336 RCX, RCX_H, | |
| 337 RBX, RBX_H, | |
| 338 R8, R8_H, | |
| 339 R9, R9_H, | |
| 340 R10, R10_H, | |
| 341 R11, R11_H, | |
| 342 R13, R13_H, | |
| 343 R14, R14_H); | |
| 344 | |
| 345 // Class for all pointer registers except RAX, RBX and RSP | |
| 346 reg_class ptr_no_rax_rbx_reg(RDX, RDX_H, | |
| 347 RBP, RBP_H, | |
| 348 RDI, RDI_H, | |
| 349 RSI, RSI_H, | |
| 350 RCX, RCX_H, | |
| 351 R8, R8_H, | |
| 352 R9, R9_H, | |
| 353 R10, R10_H, | |
| 354 R11, R11_H, | |
| 355 R13, R13_H, | |
| 356 R14, R14_H); | |
| 357 | |
| 358 // Singleton class for RAX pointer register | |
| 359 reg_class ptr_rax_reg(RAX, RAX_H); | |
| 360 | |
| 361 // Singleton class for RBX pointer register | |
| 362 reg_class ptr_rbx_reg(RBX, RBX_H); | |
| 363 | |
| 364 // Singleton class for RSI pointer register | |
| 365 reg_class ptr_rsi_reg(RSI, RSI_H); | |
| 366 | |
| 367 // Singleton class for RDI pointer register | |
| 368 reg_class ptr_rdi_reg(RDI, RDI_H); | |
| 369 | |
| 370 // Singleton class for RBP pointer register | |
| 371 reg_class ptr_rbp_reg(RBP, RBP_H); | |
| 372 | |
| 373 // Singleton class for stack pointer | |
| 374 reg_class ptr_rsp_reg(RSP, RSP_H); | |
| 375 | |
| 376 // Singleton class for TLS pointer | |
| 377 reg_class ptr_r15_reg(R15, R15_H); | |
| 378 | |
| 379 // Class for all long registers (except RSP) | |
| 380 reg_class long_reg(RAX, RAX_H, | |
| 381 RDX, RDX_H, | |
| 382 RBP, RBP_H, | |
| 383 RDI, RDI_H, | |
| 384 RSI, RSI_H, | |
| 385 RCX, RCX_H, | |
| 386 RBX, RBX_H, | |
| 387 R8, R8_H, | |
| 388 R9, R9_H, | |
| 389 R10, R10_H, | |
| 390 R11, R11_H, | |
| 391 R13, R13_H, | |
| 392 R14, R14_H); | |
| 393 | |
| 394 // Class for all long registers except RAX, RDX (and RSP) | |
| 395 reg_class long_no_rax_rdx_reg(RBP, RBP_H, | |
| 396 RDI, RDI_H, | |
| 397 RSI, RSI_H, | |
| 398 RCX, RCX_H, | |
| 399 RBX, RBX_H, | |
| 400 R8, R8_H, | |
| 401 R9, R9_H, | |
| 402 R10, R10_H, | |
| 403 R11, R11_H, | |
| 404 R13, R13_H, | |
| 405 R14, R14_H); | |
| 406 | |
| 407 // Class for all long registers except RCX (and RSP) | |
| 408 reg_class long_no_rcx_reg(RBP, RBP_H, | |
| 409 RDI, RDI_H, | |
| 410 RSI, RSI_H, | |
| 411 RAX, RAX_H, | |
| 412 RDX, RDX_H, | |
| 413 RBX, RBX_H, | |
| 414 R8, R8_H, | |
| 415 R9, R9_H, | |
| 416 R10, R10_H, | |
| 417 R11, R11_H, | |
| 418 R13, R13_H, | |
| 419 R14, R14_H); | |
| 420 | |
| 421 // Class for all long registers except RAX (and RSP) | |
| 422 reg_class long_no_rax_reg(RBP, RBP_H, | |
| 423 RDX, RDX_H, | |
| 424 RDI, RDI_H, | |
| 425 RSI, RSI_H, | |
| 426 RCX, RCX_H, | |
| 427 RBX, RBX_H, | |
| 428 R8, R8_H, | |
| 429 R9, R9_H, | |
| 430 R10, R10_H, | |
| 431 R11, R11_H, | |
| 432 R13, R13_H, | |
| 433 R14, R14_H); | |
| 434 | |
| 435 // Singleton class for RAX long register | |
| 436 reg_class long_rax_reg(RAX, RAX_H); | |
| 437 | |
| 438 // Singleton class for RCX long register | |
| 439 reg_class long_rcx_reg(RCX, RCX_H); | |
| 440 | |
| 441 // Singleton class for RDX long register | |
| 442 reg_class long_rdx_reg(RDX, RDX_H); | |
| 443 | |
| 444 // Class for all int registers (except RSP) | |
| 445 reg_class int_reg(RAX, | |
| 446 RDX, | |
| 447 RBP, | |
| 448 RDI, | |
| 449 RSI, | |
| 450 RCX, | |
| 451 RBX, | |
| 452 R8, | |
| 453 R9, | |
| 454 R10, | |
| 455 R11, | |
| 456 R13, | |
| 457 R14); | |
| 458 | |
| 459 // Class for all int registers except RCX (and RSP) | |
| 460 reg_class int_no_rcx_reg(RAX, | |
| 461 RDX, | |
| 462 RBP, | |
| 463 RDI, | |
| 464 RSI, | |
| 465 RBX, | |
| 466 R8, | |
| 467 R9, | |
| 468 R10, | |
| 469 R11, | |
| 470 R13, | |
| 471 R14); | |
| 472 | |
| 473 // Class for all int registers except RAX, RDX (and RSP) | |
| 474 reg_class int_no_rax_rdx_reg(RBP, | |
| 304 | 475 RDI, |
| 0 | 476 RSI, |
| 477 RCX, | |
| 478 RBX, | |
| 479 R8, | |
| 480 R9, | |
| 481 R10, | |
| 482 R11, | |
| 483 R13, | |
| 484 R14); | |
| 485 | |
| 486 // Singleton class for RAX int register | |
| 487 reg_class int_rax_reg(RAX); | |
| 488 | |
| 489 // Singleton class for RBX int register | |
| 490 reg_class int_rbx_reg(RBX); | |
| 491 | |
| 492 // Singleton class for RCX int register | |
| 493 reg_class int_rcx_reg(RCX); | |
| 494 | |
| 495 // Singleton class for RCX int register | |
| 496 reg_class int_rdx_reg(RDX); | |
| 497 | |
| 498 // Singleton class for RCX int register | |
| 499 reg_class int_rdi_reg(RDI); | |
| 500 | |
| 501 // Singleton class for instruction pointer | |
| 502 // reg_class ip_reg(RIP); | |
| 503 | |
| 504 // Singleton class for condition codes | |
| 505 reg_class int_flags(RFLAGS); | |
| 506 | |
| 507 // Class for all float registers | |
| 508 reg_class float_reg(XMM0, | |
| 509 XMM1, | |
| 510 XMM2, | |
| 511 XMM3, | |
| 512 XMM4, | |
| 513 XMM5, | |
| 514 XMM6, | |
| 515 XMM7, | |
| 516 XMM8, | |
| 517 XMM9, | |
| 518 XMM10, | |
| 519 XMM11, | |
| 520 XMM12, | |
| 521 XMM13, | |
| 522 XMM14, | |
| 523 XMM15); | |
| 524 | |
| 525 // Class for all double registers | |
| 526 reg_class double_reg(XMM0, XMM0_H, | |
| 527 XMM1, XMM1_H, | |
| 528 XMM2, XMM2_H, | |
| 529 XMM3, XMM3_H, | |
| 530 XMM4, XMM4_H, | |
| 531 XMM5, XMM5_H, | |
| 532 XMM6, XMM6_H, | |
| 533 XMM7, XMM7_H, | |
| 534 XMM8, XMM8_H, | |
| 535 XMM9, XMM9_H, | |
| 536 XMM10, XMM10_H, | |
| 537 XMM11, XMM11_H, | |
| 538 XMM12, XMM12_H, | |
| 539 XMM13, XMM13_H, | |
| 540 XMM14, XMM14_H, | |
| 541 XMM15, XMM15_H); | |
| 542 %} | |
| 543 | |
| 544 | |
| 545 //----------SOURCE BLOCK------------------------------------------------------- | |
| 546 // This is a block of C++ code which provides values, functions, and | |
| 547 // definitions necessary in the rest of the architecture description | |
| 548 source %{ | |
| 304 | 549 #define RELOC_IMM64 Assembler::imm_operand |
| 0 | 550 #define RELOC_DISP32 Assembler::disp32_operand |
| 551 | |
| 552 #define __ _masm. | |
| 553 | |
|
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554 static int preserve_SP_size() { |
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555 return LP64_ONLY(1 +) 2; // [rex,] op, rm(reg/reg) |
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556 } |
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557 |
| 0 | 558 // !!!!! Special hack to get all types of calls to specify the byte offset |
| 559 // from the start of the call to the point where the return address | |
| 560 // will point. | |
| 561 int MachCallStaticJavaNode::ret_addr_offset() | |
| 562 { | |
|
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563 int offset = 5; // 5 bytes from start of call to where return address points |
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564 if (_method_handle_invoke) |
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565 offset += preserve_SP_size(); |
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566 return offset; |
| 0 | 567 } |
| 568 | |
| 569 int MachCallDynamicJavaNode::ret_addr_offset() | |
| 570 { | |
| 571 return 15; // 15 bytes from start of call to where return address points | |
| 572 } | |
| 573 | |
| 574 // In os_cpu .ad file | |
| 575 // int MachCallRuntimeNode::ret_addr_offset() | |
| 576 | |
| 577 // Indicate if the safepoint node needs the polling page as an input. | |
| 578 // Since amd64 does not have absolute addressing but RIP-relative | |
| 579 // addressing and the polling page is within 2G, it doesn't. | |
| 580 bool SafePointNode::needs_polling_address_input() | |
| 581 { | |
| 582 return false; | |
| 583 } | |
| 584 | |
| 585 // | |
| 586 // Compute padding required for nodes which need alignment | |
| 587 // | |
| 588 | |
| 589 // The address of the call instruction needs to be 4-byte aligned to | |
| 590 // ensure that it does not span a cache line so that it can be patched. | |
| 591 int CallStaticJavaDirectNode::compute_padding(int current_offset) const | |
| 592 { | |
| 593 current_offset += 1; // skip call opcode byte | |
| 594 return round_to(current_offset, alignment_required()) - current_offset; | |
| 595 } | |
| 596 | |
| 597 // The address of the call instruction needs to be 4-byte aligned to | |
| 598 // ensure that it does not span a cache line so that it can be patched. | |
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599 int CallStaticJavaHandleNode::compute_padding(int current_offset) const |
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600 { |
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601 current_offset += preserve_SP_size(); // skip mov rbp, rsp |
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602 current_offset += 1; // skip call opcode byte |
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603 return round_to(current_offset, alignment_required()) - current_offset; |
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604 } |
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605 |
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606 // The address of the call instruction needs to be 4-byte aligned to |
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607 // ensure that it does not span a cache line so that it can be patched. |
| 0 | 608 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const |
| 609 { | |
| 610 current_offset += 11; // skip movq instruction + call opcode byte | |
| 611 return round_to(current_offset, alignment_required()) - current_offset; | |
| 612 } | |
| 613 | |
| 614 #ifndef PRODUCT | |
| 615 void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const | |
| 616 { | |
| 617 st->print("INT3"); | |
| 618 } | |
| 619 #endif | |
| 620 | |
| 621 // EMIT_RM() | |
| 1748 | 622 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { |
| 0 | 623 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3); |
| 1748 | 624 cbuf.insts()->emit_int8(c); |
| 0 | 625 } |
| 626 | |
| 627 // EMIT_CC() | |
| 1748 | 628 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { |
| 0 | 629 unsigned char c = (unsigned char) (f1 | f2); |
| 1748 | 630 cbuf.insts()->emit_int8(c); |
| 0 | 631 } |
| 632 | |
| 633 // EMIT_OPCODE() | |
| 1748 | 634 void emit_opcode(CodeBuffer &cbuf, int code) { |
| 635 cbuf.insts()->emit_int8((unsigned char) code); | |
| 0 | 636 } |
| 637 | |
| 638 // EMIT_OPCODE() w/ relocation information | |
| 639 void emit_opcode(CodeBuffer &cbuf, | |
| 640 int code, relocInfo::relocType reloc, int offset, int format) | |
| 641 { | |
| 1748 | 642 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format); |
| 0 | 643 emit_opcode(cbuf, code); |
| 644 } | |
| 645 | |
| 646 // EMIT_D8() | |
| 1748 | 647 void emit_d8(CodeBuffer &cbuf, int d8) { |
| 648 cbuf.insts()->emit_int8((unsigned char) d8); | |
| 0 | 649 } |
| 650 | |
| 651 // EMIT_D16() | |
| 1748 | 652 void emit_d16(CodeBuffer &cbuf, int d16) { |
| 653 cbuf.insts()->emit_int16(d16); | |
| 0 | 654 } |
| 655 | |
| 656 // EMIT_D32() | |
| 1748 | 657 void emit_d32(CodeBuffer &cbuf, int d32) { |
| 658 cbuf.insts()->emit_int32(d32); | |
| 0 | 659 } |
| 660 | |
| 661 // EMIT_D64() | |
| 1748 | 662 void emit_d64(CodeBuffer &cbuf, int64_t d64) { |
| 663 cbuf.insts()->emit_int64(d64); | |
| 0 | 664 } |
| 665 | |
| 666 // emit 32 bit value and construct relocation entry from relocInfo::relocType | |
| 667 void emit_d32_reloc(CodeBuffer& cbuf, | |
| 668 int d32, | |
| 669 relocInfo::relocType reloc, | |
| 670 int format) | |
| 671 { | |
| 672 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc"); | |
| 1748 | 673 cbuf.relocate(cbuf.insts_mark(), reloc, format); |
| 674 cbuf.insts()->emit_int32(d32); | |
| 0 | 675 } |
| 676 | |
| 677 // emit 32 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 678 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) { |
| 0 | 679 #ifdef ASSERT |
| 680 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 681 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) { | |
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682 assert(oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code"); |
| 0 | 683 } |
| 684 #endif | |
| 1748 | 685 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 686 cbuf.insts()->emit_int32(d32); | |
| 0 | 687 } |
| 688 | |
| 689 void emit_d32_reloc(CodeBuffer& cbuf, address addr) { | |
| 1748 | 690 address next_ip = cbuf.insts_end() + 4; |
| 0 | 691 emit_d32_reloc(cbuf, (int) (addr - next_ip), |
| 692 external_word_Relocation::spec(addr), | |
| 693 RELOC_DISP32); | |
| 694 } | |
| 695 | |
| 696 | |
| 697 // emit 64 bit value and construct relocation entry from relocInfo::relocType | |
| 1748 | 698 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) { |
| 699 cbuf.relocate(cbuf.insts_mark(), reloc, format); | |
| 700 cbuf.insts()->emit_int64(d64); | |
| 0 | 701 } |
| 702 | |
| 703 // emit 64 bit value and construct relocation entry from RelocationHolder | |
| 1748 | 704 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) { |
| 0 | 705 #ifdef ASSERT |
| 706 if (rspec.reloc()->type() == relocInfo::oop_type && | |
| 707 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) { | |
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708 assert(oop(d64)->is_oop() && (ScavengeRootsInCode || !oop(d64)->is_scavengable()), |
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709 "cannot embed scavengable oops in code"); |
| 0 | 710 } |
| 711 #endif | |
| 1748 | 712 cbuf.relocate(cbuf.insts_mark(), rspec, format); |
| 713 cbuf.insts()->emit_int64(d64); | |
| 0 | 714 } |
| 715 | |
| 716 // Access stack slot for load or store | |
| 717 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) | |
| 718 { | |
| 719 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src]) | |
| 720 if (-0x80 <= disp && disp < 0x80) { | |
| 721 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte | |
| 722 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 723 emit_d8(cbuf, disp); // Displacement // R/M byte | |
| 724 } else { | |
| 725 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte | |
| 726 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte | |
| 727 emit_d32(cbuf, disp); // Displacement // R/M byte | |
| 728 } | |
| 729 } | |
| 730 | |
| 731 // rRegI ereg, memory mem) %{ // emit_reg_mem | |
| 732 void encode_RegMem(CodeBuffer &cbuf, | |
| 733 int reg, | |
| 734 int base, int index, int scale, int disp, bool disp_is_oop) | |
| 735 { | |
| 736 assert(!disp_is_oop, "cannot have disp"); | |
| 737 int regenc = reg & 7; | |
| 738 int baseenc = base & 7; | |
| 739 int indexenc = index & 7; | |
| 740 | |
| 741 // There is no index & no scale, use form without SIB byte | |
| 742 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) { | |
| 743 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 744 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 745 emit_rm(cbuf, 0x0, regenc, baseenc); // * | |
| 746 } else if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
| 747 // If 8-bit displacement, mode 0x1 | |
| 748 emit_rm(cbuf, 0x1, regenc, baseenc); // * | |
| 749 emit_d8(cbuf, disp); | |
| 750 } else { | |
| 751 // If 32-bit displacement | |
| 752 if (base == -1) { // Special flag for absolute address | |
| 753 emit_rm(cbuf, 0x0, regenc, 0x5); // * | |
| 754 if (disp_is_oop) { | |
| 755 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 756 } else { | |
| 757 emit_d32(cbuf, disp); | |
| 758 } | |
| 759 } else { | |
| 760 // Normal base + offset | |
| 761 emit_rm(cbuf, 0x2, regenc, baseenc); // * | |
| 762 if (disp_is_oop) { | |
| 763 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 764 } else { | |
| 765 emit_d32(cbuf, disp); | |
| 766 } | |
| 767 } | |
| 768 } | |
| 769 } else { | |
| 770 // Else, encode with the SIB byte | |
| 771 // If no displacement, mode is 0x0; unless base is [RBP] or [R13] | |
| 772 if (disp == 0 && base != RBP_enc && base != R13_enc) { | |
| 773 // If no displacement | |
| 774 emit_rm(cbuf, 0x0, regenc, 0x4); // * | |
| 775 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 776 } else { | |
| 777 if (-0x80 <= disp && disp < 0x80 && !disp_is_oop) { | |
| 778 // If 8-bit displacement, mode 0x1 | |
| 779 emit_rm(cbuf, 0x1, regenc, 0x4); // * | |
| 780 emit_rm(cbuf, scale, indexenc, baseenc); | |
| 781 emit_d8(cbuf, disp); | |
| 782 } else { | |
| 783 // If 32-bit displacement | |
| 784 if (base == 0x04 ) { | |
| 785 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 786 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid??? | |
| 787 } else { | |
| 788 emit_rm(cbuf, 0x2, regenc, 0x4); | |
| 789 emit_rm(cbuf, scale, indexenc, baseenc); // * | |
| 790 } | |
| 791 if (disp_is_oop) { | |
| 792 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32); | |
| 793 } else { | |
| 794 emit_d32(cbuf, disp); | |
| 795 } | |
| 796 } | |
| 797 } | |
| 798 } | |
| 799 } | |
| 800 | |
| 801 void encode_copy(CodeBuffer &cbuf, int dstenc, int srcenc) | |
| 802 { | |
| 803 if (dstenc != srcenc) { | |
| 804 if (dstenc < 8) { | |
| 805 if (srcenc >= 8) { | |
| 806 emit_opcode(cbuf, Assembler::REX_B); | |
| 807 srcenc -= 8; | |
| 808 } | |
| 809 } else { | |
| 810 if (srcenc < 8) { | |
| 811 emit_opcode(cbuf, Assembler::REX_R); | |
| 812 } else { | |
| 813 emit_opcode(cbuf, Assembler::REX_RB); | |
| 814 srcenc -= 8; | |
| 815 } | |
| 816 dstenc -= 8; | |
| 817 } | |
| 818 | |
| 819 emit_opcode(cbuf, 0x8B); | |
| 820 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
| 821 } | |
| 822 } | |
| 823 | |
| 824 void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { | |
| 825 if( dst_encoding == src_encoding ) { | |
| 826 // reg-reg copy, use an empty encoding | |
| 827 } else { | |
| 828 MacroAssembler _masm(&cbuf); | |
| 829 | |
| 830 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); | |
| 831 } | |
| 832 } | |
| 833 | |
| 834 | |
| 835 //============================================================================= | |
| 836 #ifndef PRODUCT | |
| 837 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 838 { | |
| 839 Compile* C = ra_->C; | |
| 840 | |
| 841 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 842 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 843 // Remove wordSize for return adr already pushed | |
| 844 // and another for the RBP we are going to save | |
| 845 framesize -= 2*wordSize; | |
| 846 bool need_nop = true; | |
| 847 | |
| 848 // Calls to C2R adapters often do not accept exceptional returns. | |
| 849 // We require that their callers must bang for them. But be | |
| 850 // careful, because some VM calls (such as call site linkage) can | |
| 851 // use several kilobytes of stack. But the stack safety zone should | |
| 852 // account for that. See bugs 4446381, 4468289, 4497237. | |
| 853 if (C->need_stack_bang(framesize)) { | |
| 854 st->print_cr("# stack bang"); st->print("\t"); | |
| 855 need_nop = false; | |
| 856 } | |
| 857 st->print_cr("pushq rbp"); st->print("\t"); | |
| 858 | |
| 859 if (VerifyStackAtCalls) { | |
| 860 // Majik cookie to verify stack depth | |
| 861 st->print_cr("pushq 0xffffffffbadb100d" | |
| 862 "\t# Majik cookie for stack depth check"); | |
| 863 st->print("\t"); | |
| 864 framesize -= wordSize; // Remove 2 for cookie | |
| 865 need_nop = false; | |
| 866 } | |
| 867 | |
| 868 if (framesize) { | |
| 869 st->print("subq rsp, #%d\t# Create frame", framesize); | |
| 870 if (framesize < 0x80 && need_nop) { | |
| 871 st->print("\n\tnop\t# nop for patch_verified_entry"); | |
| 872 } | |
| 873 } | |
| 874 } | |
| 875 #endif | |
| 876 | |
| 877 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
| 878 { | |
| 879 Compile* C = ra_->C; | |
| 880 | |
| 881 // WARNING: Initial instruction MUST be 5 bytes or longer so that | |
| 882 // NativeJump::patch_verified_entry will be able to patch out the entry | |
| 883 // code safely. The fldcw is ok at 6 bytes, the push to verify stack | |
| 884 // depth is ok at 5 bytes, the frame allocation can be either 3 or | |
| 885 // 6 bytes. So if we don't do the fldcw or the push then we must | |
| 886 // use the 6 byte frame allocation even if we have no frame. :-( | |
| 887 // If method sets FPU control word do it now | |
| 888 | |
| 889 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 890 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 891 // Remove wordSize for return adr already pushed | |
| 892 // and another for the RBP we are going to save | |
| 893 framesize -= 2*wordSize; | |
| 894 bool need_nop = true; | |
| 895 | |
| 896 // Calls to C2R adapters often do not accept exceptional returns. | |
| 897 // We require that their callers must bang for them. But be | |
| 898 // careful, because some VM calls (such as call site linkage) can | |
| 899 // use several kilobytes of stack. But the stack safety zone should | |
| 900 // account for that. See bugs 4446381, 4468289, 4497237. | |
| 901 if (C->need_stack_bang(framesize)) { | |
| 902 MacroAssembler masm(&cbuf); | |
| 903 masm.generate_stack_overflow_check(framesize); | |
| 904 need_nop = false; | |
| 905 } | |
| 906 | |
| 907 // We always push rbp so that on return to interpreter rbp will be | |
| 908 // restored correctly and we can correct the stack. | |
| 909 emit_opcode(cbuf, 0x50 | RBP_enc); | |
| 910 | |
| 911 if (VerifyStackAtCalls) { | |
| 912 // Majik cookie to verify stack depth | |
| 913 emit_opcode(cbuf, 0x68); // pushq (sign-extended) 0xbadb100d | |
| 914 emit_d32(cbuf, 0xbadb100d); | |
| 915 framesize -= wordSize; // Remove 2 for cookie | |
| 916 need_nop = false; | |
| 917 } | |
| 918 | |
| 919 if (framesize) { | |
| 920 emit_opcode(cbuf, Assembler::REX_W); | |
| 921 if (framesize < 0x80) { | |
| 922 emit_opcode(cbuf, 0x83); // sub SP,#framesize | |
| 923 emit_rm(cbuf, 0x3, 0x05, RSP_enc); | |
| 924 emit_d8(cbuf, framesize); | |
| 925 if (need_nop) { | |
| 926 emit_opcode(cbuf, 0x90); // nop | |
| 927 } | |
| 928 } else { | |
| 929 emit_opcode(cbuf, 0x81); // sub SP,#framesize | |
| 930 emit_rm(cbuf, 0x3, 0x05, RSP_enc); | |
| 931 emit_d32(cbuf, framesize); | |
| 932 } | |
| 933 } | |
| 934 | |
| 1748 | 935 C->set_frame_complete(cbuf.insts_size()); |
| 0 | 936 |
| 937 #ifdef ASSERT | |
| 938 if (VerifyStackAtCalls) { | |
| 939 Label L; | |
| 940 MacroAssembler masm(&cbuf); | |
| 304 | 941 masm.push(rax); |
| 942 masm.mov(rax, rsp); | |
| 943 masm.andptr(rax, StackAlignmentInBytes-1); | |
| 944 masm.cmpptr(rax, StackAlignmentInBytes-wordSize); | |
| 945 masm.pop(rax); | |
| 0 | 946 masm.jcc(Assembler::equal, L); |
| 947 masm.stop("Stack is not properly aligned!"); | |
| 948 masm.bind(L); | |
| 949 } | |
| 950 #endif | |
| 951 } | |
| 952 | |
| 953 uint MachPrologNode::size(PhaseRegAlloc* ra_) const | |
| 954 { | |
| 955 return MachNode::size(ra_); // too many variables; just compute it | |
| 956 // the hard way | |
| 957 } | |
| 958 | |
| 959 int MachPrologNode::reloc() const | |
| 960 { | |
| 961 return 0; // a large enough number | |
| 962 } | |
| 963 | |
| 964 //============================================================================= | |
| 965 #ifndef PRODUCT | |
| 966 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 967 { | |
| 968 Compile* C = ra_->C; | |
| 969 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 970 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 971 // Remove word for return adr already pushed | |
| 972 // and RBP | |
| 973 framesize -= 2*wordSize; | |
| 974 | |
| 975 if (framesize) { | |
| 976 st->print_cr("addq\trsp, %d\t# Destroy frame", framesize); | |
| 977 st->print("\t"); | |
| 978 } | |
| 979 | |
| 980 st->print_cr("popq\trbp"); | |
| 981 if (do_polling() && C->is_method_compilation()) { | |
| 982 st->print_cr("\ttestl\trax, [rip + #offset_to_poll_page]\t" | |
| 983 "# Safepoint: poll for GC"); | |
| 984 st->print("\t"); | |
| 985 } | |
| 986 } | |
| 987 #endif | |
| 988 | |
| 989 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 990 { | |
| 991 Compile* C = ra_->C; | |
| 992 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 993 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 994 // Remove word for return adr already pushed | |
| 995 // and RBP | |
| 996 framesize -= 2*wordSize; | |
| 997 | |
| 998 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here | |
| 999 | |
| 1000 if (framesize) { | |
| 1001 emit_opcode(cbuf, Assembler::REX_W); | |
| 1002 if (framesize < 0x80) { | |
| 1003 emit_opcode(cbuf, 0x83); // addq rsp, #framesize | |
| 1004 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 1005 emit_d8(cbuf, framesize); | |
| 1006 } else { | |
| 1007 emit_opcode(cbuf, 0x81); // addq rsp, #framesize | |
| 1008 emit_rm(cbuf, 0x3, 0x00, RSP_enc); | |
| 1009 emit_d32(cbuf, framesize); | |
| 1010 } | |
| 1011 } | |
| 1012 | |
| 1013 // popq rbp | |
| 1014 emit_opcode(cbuf, 0x58 | RBP_enc); | |
| 1015 | |
| 1016 if (do_polling() && C->is_method_compilation()) { | |
| 1017 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes | |
| 1018 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 1748 | 1019 cbuf.set_insts_mark(); |
| 1020 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_return_type, 0); // XXX | |
| 0 | 1021 emit_opcode(cbuf, 0x85); // testl |
| 1022 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5 | |
| 1748 | 1023 // cbuf.insts_mark() is beginning of instruction |
| 0 | 1024 emit_d32_reloc(cbuf, os::get_polling_page()); |
| 1025 // relocInfo::poll_return_type, | |
| 1026 } | |
| 1027 } | |
| 1028 | |
| 1029 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const | |
| 1030 { | |
| 1031 Compile* C = ra_->C; | |
| 1032 int framesize = C->frame_slots() << LogBytesPerInt; | |
| 1033 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); | |
| 1034 // Remove word for return adr already pushed | |
| 1035 // and RBP | |
| 1036 framesize -= 2*wordSize; | |
| 1037 | |
| 1038 uint size = 0; | |
| 1039 | |
| 1040 if (do_polling() && C->is_method_compilation()) { | |
| 1041 size += 6; | |
| 1042 } | |
| 1043 | |
| 1044 // count popq rbp | |
| 1045 size++; | |
| 1046 | |
| 1047 if (framesize) { | |
| 1048 if (framesize < 0x80) { | |
| 1049 size += 4; | |
| 1050 } else if (framesize) { | |
| 1051 size += 7; | |
| 1052 } | |
| 1053 } | |
| 1054 | |
| 1055 return size; | |
| 1056 } | |
| 1057 | |
| 1058 int MachEpilogNode::reloc() const | |
| 1059 { | |
| 1060 return 2; // a large enough number | |
| 1061 } | |
| 1062 | |
| 1063 const Pipeline* MachEpilogNode::pipeline() const | |
| 1064 { | |
| 1065 return MachNode::pipeline_class(); | |
| 1066 } | |
| 1067 | |
| 1068 int MachEpilogNode::safepoint_offset() const | |
| 1069 { | |
| 1070 return 0; | |
| 1071 } | |
| 1072 | |
| 1073 //============================================================================= | |
| 1074 | |
| 1075 enum RC { | |
| 1076 rc_bad, | |
| 1077 rc_int, | |
| 1078 rc_float, | |
| 1079 rc_stack | |
| 1080 }; | |
| 1081 | |
| 1082 static enum RC rc_class(OptoReg::Name reg) | |
| 1083 { | |
| 1084 if( !OptoReg::is_valid(reg) ) return rc_bad; | |
| 1085 | |
| 1086 if (OptoReg::is_stack(reg)) return rc_stack; | |
| 1087 | |
| 1088 VMReg r = OptoReg::as_VMReg(reg); | |
| 1089 | |
| 1090 if (r->is_Register()) return rc_int; | |
| 1091 | |
| 1092 assert(r->is_XMMRegister(), "must be"); | |
| 1093 return rc_float; | |
| 1094 } | |
| 1095 | |
| 1096 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf, | |
| 1097 PhaseRegAlloc* ra_, | |
| 1098 bool do_size, | |
| 1099 outputStream* st) const | |
| 1100 { | |
| 1101 | |
| 1102 // Get registers to move | |
| 1103 OptoReg::Name src_second = ra_->get_reg_second(in(1)); | |
| 1104 OptoReg::Name src_first = ra_->get_reg_first(in(1)); | |
| 1105 OptoReg::Name dst_second = ra_->get_reg_second(this); | |
| 1106 OptoReg::Name dst_first = ra_->get_reg_first(this); | |
| 1107 | |
| 1108 enum RC src_second_rc = rc_class(src_second); | |
| 1109 enum RC src_first_rc = rc_class(src_first); | |
| 1110 enum RC dst_second_rc = rc_class(dst_second); | |
| 1111 enum RC dst_first_rc = rc_class(dst_first); | |
| 1112 | |
| 1113 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), | |
| 1114 "must move at least 1 register" ); | |
| 1115 | |
| 1116 if (src_first == dst_first && src_second == dst_second) { | |
| 1117 // Self copy, no move | |
| 1118 return 0; | |
| 1119 } else if (src_first_rc == rc_stack) { | |
| 1120 // mem -> | |
| 1121 if (dst_first_rc == rc_stack) { | |
| 1122 // mem -> mem | |
| 1123 assert(src_second != dst_first, "overlap"); | |
| 1124 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1125 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1126 // 64-bit | |
| 1127 int src_offset = ra_->reg2offset(src_first); | |
| 1128 int dst_offset = ra_->reg2offset(dst_first); | |
| 1129 if (cbuf) { | |
| 1130 emit_opcode(*cbuf, 0xFF); | |
| 1131 encode_RegMem(*cbuf, RSI_enc, RSP_enc, 0x4, 0, src_offset, false); | |
| 1132 | |
| 1133 emit_opcode(*cbuf, 0x8F); | |
| 1134 encode_RegMem(*cbuf, RAX_enc, RSP_enc, 0x4, 0, dst_offset, false); | |
| 1135 | |
| 1136 #ifndef PRODUCT | |
| 1137 } else if (!do_size) { | |
| 1138 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t" | |
| 1139 "popq [rsp + #%d]", | |
| 1140 src_offset, | |
| 1141 dst_offset); | |
| 1142 #endif | |
| 1143 } | |
| 1144 return | |
| 1145 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + | |
| 1146 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)); | |
| 1147 } else { | |
| 1148 // 32-bit | |
| 1149 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1150 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1151 // No pushl/popl, so: | |
| 1152 int src_offset = ra_->reg2offset(src_first); | |
| 1153 int dst_offset = ra_->reg2offset(dst_first); | |
| 1154 if (cbuf) { | |
| 1155 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1156 emit_opcode(*cbuf, 0x89); | |
| 1157 emit_opcode(*cbuf, 0x44); | |
| 1158 emit_opcode(*cbuf, 0x24); | |
| 1159 emit_opcode(*cbuf, 0xF8); | |
| 1160 | |
| 1161 emit_opcode(*cbuf, 0x8B); | |
| 1162 encode_RegMem(*cbuf, | |
| 1163 RAX_enc, | |
| 1164 RSP_enc, 0x4, 0, src_offset, | |
| 1165 false); | |
| 1166 | |
| 1167 emit_opcode(*cbuf, 0x89); | |
| 1168 encode_RegMem(*cbuf, | |
| 1169 RAX_enc, | |
| 1170 RSP_enc, 0x4, 0, dst_offset, | |
| 1171 false); | |
| 1172 | |
| 1173 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1174 emit_opcode(*cbuf, 0x8B); | |
| 1175 emit_opcode(*cbuf, 0x44); | |
| 1176 emit_opcode(*cbuf, 0x24); | |
| 1177 emit_opcode(*cbuf, 0xF8); | |
| 1178 | |
| 1179 #ifndef PRODUCT | |
| 1180 } else if (!do_size) { | |
| 1181 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t" | |
| 1182 "movl rax, [rsp + #%d]\n\t" | |
| 1183 "movl [rsp + #%d], rax\n\t" | |
| 1184 "movq rax, [rsp - #8]", | |
| 1185 src_offset, | |
| 1186 dst_offset); | |
| 1187 #endif | |
| 1188 } | |
| 1189 return | |
| 1190 5 + // movq | |
| 1191 3 + ((src_offset == 0) ? 0 : (src_offset < 0x80 ? 1 : 4)) + // movl | |
| 1192 3 + ((dst_offset == 0) ? 0 : (dst_offset < 0x80 ? 1 : 4)) + // movl | |
| 1193 5; // movq | |
| 1194 } | |
| 1195 } else if (dst_first_rc == rc_int) { | |
| 1196 // mem -> gpr | |
| 1197 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1198 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1199 // 64-bit | |
| 1200 int offset = ra_->reg2offset(src_first); | |
| 1201 if (cbuf) { | |
| 1202 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1203 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1204 } else { | |
| 1205 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1206 } | |
| 1207 emit_opcode(*cbuf, 0x8B); | |
| 1208 encode_RegMem(*cbuf, | |
| 1209 Matcher::_regEncode[dst_first], | |
| 1210 RSP_enc, 0x4, 0, offset, | |
| 1211 false); | |
| 1212 #ifndef PRODUCT | |
| 1213 } else if (!do_size) { | |
| 1214 st->print("movq %s, [rsp + #%d]\t# spill", | |
| 1215 Matcher::regName[dst_first], | |
| 1216 offset); | |
| 1217 #endif | |
| 1218 } | |
| 1219 return | |
| 1220 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
| 1221 } else { | |
| 1222 // 32-bit | |
| 1223 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1224 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1225 int offset = ra_->reg2offset(src_first); | |
| 1226 if (cbuf) { | |
| 1227 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1228 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1229 } | |
| 1230 emit_opcode(*cbuf, 0x8B); | |
| 1231 encode_RegMem(*cbuf, | |
| 1232 Matcher::_regEncode[dst_first], | |
| 1233 RSP_enc, 0x4, 0, offset, | |
| 1234 false); | |
| 1235 #ifndef PRODUCT | |
| 1236 } else if (!do_size) { | |
| 1237 st->print("movl %s, [rsp + #%d]\t# spill", | |
| 1238 Matcher::regName[dst_first], | |
| 1239 offset); | |
| 1240 #endif | |
| 1241 } | |
| 1242 return | |
| 1243 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1244 ((Matcher::_regEncode[dst_first] < 8) | |
| 1245 ? 3 | |
| 1246 : 4); // REX | |
| 1247 } | |
| 1248 } else if (dst_first_rc == rc_float) { | |
| 1249 // mem-> xmm | |
| 1250 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1251 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1252 // 64-bit | |
| 1253 int offset = ra_->reg2offset(src_first); | |
| 1254 if (cbuf) { | |
| 1255 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 1256 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1257 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1258 } | |
| 1259 emit_opcode(*cbuf, 0x0F); | |
| 1260 emit_opcode(*cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 1261 encode_RegMem(*cbuf, | |
| 1262 Matcher::_regEncode[dst_first], | |
| 1263 RSP_enc, 0x4, 0, offset, | |
| 1264 false); | |
| 1265 #ifndef PRODUCT | |
| 1266 } else if (!do_size) { | |
| 1267 st->print("%s %s, [rsp + #%d]\t# spill", | |
| 1268 UseXmmLoadAndClearUpper ? "movsd " : "movlpd", | |
| 1269 Matcher::regName[dst_first], | |
| 1270 offset); | |
| 1271 #endif | |
| 1272 } | |
| 1273 return | |
| 1274 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1275 ((Matcher::_regEncode[dst_first] < 8) | |
| 1276 ? 5 | |
| 1277 : 6); // REX | |
| 1278 } else { | |
| 1279 // 32-bit | |
| 1280 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1281 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1282 int offset = ra_->reg2offset(src_first); | |
| 1283 if (cbuf) { | |
| 1284 emit_opcode(*cbuf, 0xF3); | |
| 1285 if (Matcher::_regEncode[dst_first] >= 8) { | |
| 1286 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1287 } | |
| 1288 emit_opcode(*cbuf, 0x0F); | |
| 1289 emit_opcode(*cbuf, 0x10); | |
| 1290 encode_RegMem(*cbuf, | |
| 1291 Matcher::_regEncode[dst_first], | |
| 1292 RSP_enc, 0x4, 0, offset, | |
| 1293 false); | |
| 1294 #ifndef PRODUCT | |
| 1295 } else if (!do_size) { | |
| 1296 st->print("movss %s, [rsp + #%d]\t# spill", | |
| 1297 Matcher::regName[dst_first], | |
| 1298 offset); | |
| 1299 #endif | |
| 1300 } | |
| 1301 return | |
| 1302 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1303 ((Matcher::_regEncode[dst_first] < 8) | |
| 1304 ? 5 | |
| 1305 : 6); // REX | |
| 1306 } | |
| 1307 } | |
| 1308 } else if (src_first_rc == rc_int) { | |
| 1309 // gpr -> | |
| 1310 if (dst_first_rc == rc_stack) { | |
| 1311 // gpr -> mem | |
| 1312 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1313 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1314 // 64-bit | |
| 1315 int offset = ra_->reg2offset(dst_first); | |
| 1316 if (cbuf) { | |
| 1317 if (Matcher::_regEncode[src_first] < 8) { | |
| 1318 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1319 } else { | |
| 1320 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1321 } | |
| 1322 emit_opcode(*cbuf, 0x89); | |
| 1323 encode_RegMem(*cbuf, | |
| 1324 Matcher::_regEncode[src_first], | |
| 1325 RSP_enc, 0x4, 0, offset, | |
| 1326 false); | |
| 1327 #ifndef PRODUCT | |
| 1328 } else if (!do_size) { | |
| 1329 st->print("movq [rsp + #%d], %s\t# spill", | |
| 1330 offset, | |
| 1331 Matcher::regName[src_first]); | |
| 1332 #endif | |
| 1333 } | |
| 1334 return ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + 4; // REX | |
| 1335 } else { | |
| 1336 // 32-bit | |
| 1337 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1338 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1339 int offset = ra_->reg2offset(dst_first); | |
| 1340 if (cbuf) { | |
| 1341 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1342 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1343 } | |
| 1344 emit_opcode(*cbuf, 0x89); | |
| 1345 encode_RegMem(*cbuf, | |
| 1346 Matcher::_regEncode[src_first], | |
| 1347 RSP_enc, 0x4, 0, offset, | |
| 1348 false); | |
| 1349 #ifndef PRODUCT | |
| 1350 } else if (!do_size) { | |
| 1351 st->print("movl [rsp + #%d], %s\t# spill", | |
| 1352 offset, | |
| 1353 Matcher::regName[src_first]); | |
| 1354 #endif | |
| 1355 } | |
| 1356 return | |
| 1357 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1358 ((Matcher::_regEncode[src_first] < 8) | |
| 1359 ? 3 | |
| 1360 : 4); // REX | |
| 1361 } | |
| 1362 } else if (dst_first_rc == rc_int) { | |
| 1363 // gpr -> gpr | |
| 1364 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1365 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1366 // 64-bit | |
| 1367 if (cbuf) { | |
| 1368 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1369 if (Matcher::_regEncode[src_first] < 8) { | |
| 1370 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1371 } else { | |
| 1372 emit_opcode(*cbuf, Assembler::REX_WB); | |
| 1373 } | |
| 1374 } else { | |
| 1375 if (Matcher::_regEncode[src_first] < 8) { | |
| 1376 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1377 } else { | |
| 1378 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1379 } | |
| 1380 } | |
| 1381 emit_opcode(*cbuf, 0x8B); | |
| 1382 emit_rm(*cbuf, 0x3, | |
| 1383 Matcher::_regEncode[dst_first] & 7, | |
| 1384 Matcher::_regEncode[src_first] & 7); | |
| 1385 #ifndef PRODUCT | |
| 1386 } else if (!do_size) { | |
| 1387 st->print("movq %s, %s\t# spill", | |
| 1388 Matcher::regName[dst_first], | |
| 1389 Matcher::regName[src_first]); | |
| 1390 #endif | |
| 1391 } | |
| 1392 return 3; // REX | |
| 1393 } else { | |
| 1394 // 32-bit | |
| 1395 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1396 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1397 if (cbuf) { | |
| 1398 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1399 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1400 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1401 } | |
| 1402 } else { | |
| 1403 if (Matcher::_regEncode[src_first] < 8) { | |
| 1404 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1405 } else { | |
| 1406 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1407 } | |
| 1408 } | |
| 1409 emit_opcode(*cbuf, 0x8B); | |
| 1410 emit_rm(*cbuf, 0x3, | |
| 1411 Matcher::_regEncode[dst_first] & 7, | |
| 1412 Matcher::_regEncode[src_first] & 7); | |
| 1413 #ifndef PRODUCT | |
| 1414 } else if (!do_size) { | |
| 1415 st->print("movl %s, %s\t# spill", | |
| 1416 Matcher::regName[dst_first], | |
| 1417 Matcher::regName[src_first]); | |
| 1418 #endif | |
| 1419 } | |
| 1420 return | |
| 1421 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1422 ? 2 | |
| 1423 : 3; // REX | |
| 1424 } | |
| 1425 } else if (dst_first_rc == rc_float) { | |
| 1426 // gpr -> xmm | |
| 1427 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1428 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1429 // 64-bit | |
| 1430 if (cbuf) { | |
| 1431 emit_opcode(*cbuf, 0x66); | |
| 1432 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1433 if (Matcher::_regEncode[src_first] < 8) { | |
| 1434 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1435 } else { | |
| 1436 emit_opcode(*cbuf, Assembler::REX_WB); | |
| 1437 } | |
| 1438 } else { | |
| 1439 if (Matcher::_regEncode[src_first] < 8) { | |
| 1440 emit_opcode(*cbuf, Assembler::REX_WR); | |
| 1441 } else { | |
| 1442 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1443 } | |
| 1444 } | |
| 1445 emit_opcode(*cbuf, 0x0F); | |
| 1446 emit_opcode(*cbuf, 0x6E); | |
| 1447 emit_rm(*cbuf, 0x3, | |
| 1448 Matcher::_regEncode[dst_first] & 7, | |
| 1449 Matcher::_regEncode[src_first] & 7); | |
| 1450 #ifndef PRODUCT | |
| 1451 } else if (!do_size) { | |
| 1452 st->print("movdq %s, %s\t# spill", | |
| 1453 Matcher::regName[dst_first], | |
| 1454 Matcher::regName[src_first]); | |
| 1455 #endif | |
| 1456 } | |
| 1457 return 5; // REX | |
| 1458 } else { | |
| 1459 // 32-bit | |
| 1460 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1461 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1462 if (cbuf) { | |
| 1463 emit_opcode(*cbuf, 0x66); | |
| 1464 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1465 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1466 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1467 } | |
| 1468 } else { | |
| 1469 if (Matcher::_regEncode[src_first] < 8) { | |
| 1470 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1471 } else { | |
| 1472 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1473 } | |
| 1474 } | |
| 1475 emit_opcode(*cbuf, 0x0F); | |
| 1476 emit_opcode(*cbuf, 0x6E); | |
| 1477 emit_rm(*cbuf, 0x3, | |
| 1478 Matcher::_regEncode[dst_first] & 7, | |
| 1479 Matcher::_regEncode[src_first] & 7); | |
| 1480 #ifndef PRODUCT | |
| 1481 } else if (!do_size) { | |
| 1482 st->print("movdl %s, %s\t# spill", | |
| 1483 Matcher::regName[dst_first], | |
| 1484 Matcher::regName[src_first]); | |
| 1485 #endif | |
| 1486 } | |
| 1487 return | |
| 1488 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1489 ? 4 | |
| 1490 : 5; // REX | |
| 1491 } | |
| 1492 } | |
| 1493 } else if (src_first_rc == rc_float) { | |
| 1494 // xmm -> | |
| 1495 if (dst_first_rc == rc_stack) { | |
| 1496 // xmm -> mem | |
| 1497 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1498 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1499 // 64-bit | |
| 1500 int offset = ra_->reg2offset(dst_first); | |
| 1501 if (cbuf) { | |
| 1502 emit_opcode(*cbuf, 0xF2); | |
| 1503 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1504 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1505 } | |
| 1506 emit_opcode(*cbuf, 0x0F); | |
| 1507 emit_opcode(*cbuf, 0x11); | |
| 1508 encode_RegMem(*cbuf, | |
| 1509 Matcher::_regEncode[src_first], | |
| 1510 RSP_enc, 0x4, 0, offset, | |
| 1511 false); | |
| 1512 #ifndef PRODUCT | |
| 1513 } else if (!do_size) { | |
| 1514 st->print("movsd [rsp + #%d], %s\t# spill", | |
| 1515 offset, | |
| 1516 Matcher::regName[src_first]); | |
| 1517 #endif | |
| 1518 } | |
| 1519 return | |
| 1520 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1521 ((Matcher::_regEncode[src_first] < 8) | |
| 1522 ? 5 | |
| 1523 : 6); // REX | |
| 1524 } else { | |
| 1525 // 32-bit | |
| 1526 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1527 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1528 int offset = ra_->reg2offset(dst_first); | |
| 1529 if (cbuf) { | |
| 1530 emit_opcode(*cbuf, 0xF3); | |
| 1531 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1532 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1533 } | |
| 1534 emit_opcode(*cbuf, 0x0F); | |
| 1535 emit_opcode(*cbuf, 0x11); | |
| 1536 encode_RegMem(*cbuf, | |
| 1537 Matcher::_regEncode[src_first], | |
| 1538 RSP_enc, 0x4, 0, offset, | |
| 1539 false); | |
| 1540 #ifndef PRODUCT | |
| 1541 } else if (!do_size) { | |
| 1542 st->print("movss [rsp + #%d], %s\t# spill", | |
| 1543 offset, | |
| 1544 Matcher::regName[src_first]); | |
| 1545 #endif | |
| 1546 } | |
| 1547 return | |
| 1548 ((offset == 0) ? 0 : (offset < 0x80 ? 1 : 4)) + | |
| 1549 ((Matcher::_regEncode[src_first] < 8) | |
| 1550 ? 5 | |
| 1551 : 6); // REX | |
| 1552 } | |
| 1553 } else if (dst_first_rc == rc_int) { | |
| 1554 // xmm -> gpr | |
| 1555 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1556 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1557 // 64-bit | |
| 1558 if (cbuf) { | |
| 1559 emit_opcode(*cbuf, 0x66); | |
| 1560 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1561 if (Matcher::_regEncode[src_first] < 8) { | |
| 1562 emit_opcode(*cbuf, Assembler::REX_W); | |
| 1563 } else { | |
| 1564 emit_opcode(*cbuf, Assembler::REX_WR); // attention! | |
| 1565 } | |
| 1566 } else { | |
| 1567 if (Matcher::_regEncode[src_first] < 8) { | |
| 1568 emit_opcode(*cbuf, Assembler::REX_WB); // attention! | |
| 1569 } else { | |
| 1570 emit_opcode(*cbuf, Assembler::REX_WRB); | |
| 1571 } | |
| 1572 } | |
| 1573 emit_opcode(*cbuf, 0x0F); | |
| 1574 emit_opcode(*cbuf, 0x7E); | |
| 1575 emit_rm(*cbuf, 0x3, | |
|
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1576 Matcher::_regEncode[src_first] & 7, |
|
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|
1577 Matcher::_regEncode[dst_first] & 7); |
| 0 | 1578 #ifndef PRODUCT |
| 1579 } else if (!do_size) { | |
| 1580 st->print("movdq %s, %s\t# spill", | |
| 1581 Matcher::regName[dst_first], | |
| 1582 Matcher::regName[src_first]); | |
| 1583 #endif | |
| 1584 } | |
| 1585 return 5; // REX | |
| 1586 } else { | |
| 1587 // 32-bit | |
| 1588 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1589 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1590 if (cbuf) { | |
| 1591 emit_opcode(*cbuf, 0x66); | |
| 1592 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1593 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1594 emit_opcode(*cbuf, Assembler::REX_R); // attention! | |
| 1595 } | |
| 1596 } else { | |
| 1597 if (Matcher::_regEncode[src_first] < 8) { | |
| 1598 emit_opcode(*cbuf, Assembler::REX_B); // attention! | |
| 1599 } else { | |
| 1600 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1601 } | |
| 1602 } | |
| 1603 emit_opcode(*cbuf, 0x0F); | |
| 1604 emit_opcode(*cbuf, 0x7E); | |
| 1605 emit_rm(*cbuf, 0x3, | |
|
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1606 Matcher::_regEncode[src_first] & 7, |
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|
1607 Matcher::_regEncode[dst_first] & 7); |
| 0 | 1608 #ifndef PRODUCT |
| 1609 } else if (!do_size) { | |
| 1610 st->print("movdl %s, %s\t# spill", | |
| 1611 Matcher::regName[dst_first], | |
| 1612 Matcher::regName[src_first]); | |
| 1613 #endif | |
| 1614 } | |
| 1615 return | |
| 1616 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1617 ? 4 | |
| 1618 : 5; // REX | |
| 1619 } | |
| 1620 } else if (dst_first_rc == rc_float) { | |
| 1621 // xmm -> xmm | |
| 1622 if ((src_first & 1) == 0 && src_first + 1 == src_second && | |
| 1623 (dst_first & 1) == 0 && dst_first + 1 == dst_second) { | |
| 1624 // 64-bit | |
| 1625 if (cbuf) { | |
| 1626 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2); | |
| 1627 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1628 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1629 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1630 } | |
| 1631 } else { | |
| 1632 if (Matcher::_regEncode[src_first] < 8) { | |
| 1633 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1634 } else { | |
| 1635 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1636 } | |
| 1637 } | |
| 1638 emit_opcode(*cbuf, 0x0F); | |
| 1639 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 1640 emit_rm(*cbuf, 0x3, | |
| 1641 Matcher::_regEncode[dst_first] & 7, | |
| 1642 Matcher::_regEncode[src_first] & 7); | |
| 1643 #ifndef PRODUCT | |
| 1644 } else if (!do_size) { | |
| 1645 st->print("%s %s, %s\t# spill", | |
| 1646 UseXmmRegToRegMoveAll ? "movapd" : "movsd ", | |
| 1647 Matcher::regName[dst_first], | |
| 1648 Matcher::regName[src_first]); | |
| 1649 #endif | |
| 1650 } | |
| 1651 return | |
| 1652 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1653 ? 4 | |
| 1654 : 5; // REX | |
| 1655 } else { | |
| 1656 // 32-bit | |
| 1657 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform"); | |
| 1658 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform"); | |
| 1659 if (cbuf) { | |
| 1660 if (!UseXmmRegToRegMoveAll) | |
| 1661 emit_opcode(*cbuf, 0xF3); | |
| 1662 if (Matcher::_regEncode[dst_first] < 8) { | |
| 1663 if (Matcher::_regEncode[src_first] >= 8) { | |
| 1664 emit_opcode(*cbuf, Assembler::REX_B); | |
| 1665 } | |
| 1666 } else { | |
| 1667 if (Matcher::_regEncode[src_first] < 8) { | |
| 1668 emit_opcode(*cbuf, Assembler::REX_R); | |
| 1669 } else { | |
| 1670 emit_opcode(*cbuf, Assembler::REX_RB); | |
| 1671 } | |
| 1672 } | |
| 1673 emit_opcode(*cbuf, 0x0F); | |
| 1674 emit_opcode(*cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 1675 emit_rm(*cbuf, 0x3, | |
| 1676 Matcher::_regEncode[dst_first] & 7, | |
| 1677 Matcher::_regEncode[src_first] & 7); | |
| 1678 #ifndef PRODUCT | |
| 1679 } else if (!do_size) { | |
| 1680 st->print("%s %s, %s\t# spill", | |
| 1681 UseXmmRegToRegMoveAll ? "movaps" : "movss ", | |
| 1682 Matcher::regName[dst_first], | |
| 1683 Matcher::regName[src_first]); | |
| 1684 #endif | |
| 1685 } | |
| 1686 return | |
| 1687 (Matcher::_regEncode[src_first] < 8 && Matcher::_regEncode[dst_first] < 8) | |
| 1688 ? (UseXmmRegToRegMoveAll ? 3 : 4) | |
| 1689 : (UseXmmRegToRegMoveAll ? 4 : 5); // REX | |
| 1690 } | |
| 1691 } | |
| 1692 } | |
| 1693 | |
| 1694 assert(0," foo "); | |
| 1695 Unimplemented(); | |
| 1696 | |
| 1697 return 0; | |
| 1698 } | |
| 1699 | |
| 1700 #ifndef PRODUCT | |
| 1701 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const | |
| 1702 { | |
| 1703 implementation(NULL, ra_, false, st); | |
| 1704 } | |
| 1705 #endif | |
| 1706 | |
| 1707 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const | |
| 1708 { | |
| 1709 implementation(&cbuf, ra_, false, NULL); | |
| 1710 } | |
| 1711 | |
| 1712 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const | |
| 1713 { | |
| 1714 return implementation(NULL, ra_, true, NULL); | |
| 1715 } | |
| 1716 | |
| 1717 //============================================================================= | |
| 1718 #ifndef PRODUCT | |
| 1719 void MachNopNode::format(PhaseRegAlloc*, outputStream* st) const | |
| 1720 { | |
| 1721 st->print("nop \t# %d bytes pad for loops and calls", _count); | |
| 1722 } | |
| 1723 #endif | |
| 1724 | |
| 1725 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const | |
| 1726 { | |
| 1727 MacroAssembler _masm(&cbuf); | |
| 1728 __ nop(_count); | |
| 1729 } | |
| 1730 | |
| 1731 uint MachNopNode::size(PhaseRegAlloc*) const | |
| 1732 { | |
| 1733 return _count; | |
| 1734 } | |
| 1735 | |
| 1736 | |
| 1737 //============================================================================= | |
| 1738 #ifndef PRODUCT | |
| 1739 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1740 { | |
| 1741 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1742 int reg = ra_->get_reg_first(this); | |
| 1743 st->print("leaq %s, [rsp + #%d]\t# box lock", | |
| 1744 Matcher::regName[reg], offset); | |
| 1745 } | |
| 1746 #endif | |
| 1747 | |
| 1748 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1749 { | |
| 1750 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1751 int reg = ra_->get_encode(this); | |
| 1752 if (offset >= 0x80) { | |
| 1753 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1754 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1755 emit_rm(cbuf, 0x2, reg & 7, 0x04); | |
| 1756 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1757 emit_d32(cbuf, offset); | |
| 1758 } else { | |
| 1759 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR); | |
| 1760 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] | |
| 1761 emit_rm(cbuf, 0x1, reg & 7, 0x04); | |
| 1762 emit_rm(cbuf, 0x0, 0x04, RSP_enc); | |
| 1763 emit_d8(cbuf, offset); | |
| 1764 } | |
| 1765 } | |
| 1766 | |
| 1767 uint BoxLockNode::size(PhaseRegAlloc *ra_) const | |
| 1768 { | |
| 1769 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); | |
| 1770 return (offset < 0x80) ? 5 : 8; // REX | |
| 1771 } | |
| 1772 | |
| 1773 //============================================================================= | |
| 1774 | |
| 1775 // emit call stub, compiled java to interpreter | |
| 1776 void emit_java_to_interp(CodeBuffer& cbuf) | |
| 1777 { | |
| 1778 // Stub is fixed up when the corresponding call is converted from | |
| 1779 // calling compiled code to calling interpreted code. | |
| 1780 // movq rbx, 0 | |
| 1781 // jmp -5 # to self | |
| 1782 | |
| 1748 | 1783 address mark = cbuf.insts_mark(); // get mark within main instrs section |
| 1784 | |
| 1785 // Note that the code buffer's insts_mark is always relative to insts. | |
| 0 | 1786 // That's why we must use the macroassembler to generate a stub. |
| 1787 MacroAssembler _masm(&cbuf); | |
| 1788 | |
| 1789 address base = | |
| 1790 __ start_a_stub(Compile::MAX_stubs_size); | |
| 1791 if (base == NULL) return; // CodeBuffer::expand failed | |
| 1792 // static stub relocation stores the instruction address of the call | |
| 1793 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM64); | |
| 1794 // static stub relocation also tags the methodOop in the code-stream. | |
| 1795 __ movoop(rbx, (jobject) NULL); // method is zapped till fixup time | |
| 304 | 1796 // This is recognized as unresolved by relocs/nativeinst/ic code |
| 0 | 1797 __ jump(RuntimeAddress(__ pc())); |
| 1798 | |
| 1748 | 1799 // Update current stubs pointer and restore insts_end. |
| 0 | 1800 __ end_a_stub(); |
| 1801 } | |
| 1802 | |
| 1803 // size of call stub, compiled java to interpretor | |
| 1804 uint size_java_to_interp() | |
| 1805 { | |
| 1806 return 15; // movq (1+1+8); jmp (1+4) | |
| 1807 } | |
| 1808 | |
| 1809 // relocation entries for call stub, compiled java to interpretor | |
| 1810 uint reloc_java_to_interp() | |
| 1811 { | |
| 1812 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call | |
| 1813 } | |
| 1814 | |
| 1815 //============================================================================= | |
| 1816 #ifndef PRODUCT | |
| 1817 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const | |
| 1818 { | |
|
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1819 if (UseCompressedOops) { |
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1820 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass"); |
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1821 if (Universe::narrow_oop_shift() != 0) { |
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1822 st->print_cr("\tdecode_heap_oop_not_null rscratch1, rscratch1"); |
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1823 } |
|
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1824 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check"); |
|
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1825 } else { |
|
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1826 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t" |
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1827 "# Inline cache check"); |
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1828 } |
| 0 | 1829 st->print_cr("\tjne SharedRuntime::_ic_miss_stub"); |
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1830 st->print_cr("\tnop\t# nops to align entry point"); |
| 0 | 1831 } |
| 1832 #endif | |
| 1833 | |
| 1834 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const | |
| 1835 { | |
| 1836 MacroAssembler masm(&cbuf); | |
| 1748 | 1837 uint insts_size = cbuf.insts_size(); |
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1838 if (UseCompressedOops) { |
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1839 masm.load_klass(rscratch1, j_rarg0); |
| 304 | 1840 masm.cmpptr(rax, rscratch1); |
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1841 } else { |
| 304 | 1842 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes())); |
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1843 } |
| 0 | 1844 |
| 1845 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub())); | |
| 1846 | |
| 1847 /* WARNING these NOPs are critical so that verified entry point is properly | |
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1848 4 bytes aligned for patching by NativeJump::patch_verified_entry() */ |
| 1748 | 1849 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3); |
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1850 if (OptoBreakpoint) { |
| 0 | 1851 // Leave space for int3 |
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1852 nops_cnt -= 1; |
| 0 | 1853 } |
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1854 nops_cnt &= 0x3; // Do not add nops if code is aligned. |
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1855 if (nops_cnt > 0) |
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1856 masm.nop(nops_cnt); |
| 0 | 1857 } |
| 1858 | |
| 1859 uint MachUEPNode::size(PhaseRegAlloc* ra_) const | |
| 1860 { | |
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1861 return MachNode::size(ra_); // too many variables; just compute it |
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1862 // the hard way |
| 0 | 1863 } |
| 1864 | |
| 1865 | |
| 1866 //============================================================================= | |
| 1867 uint size_exception_handler() | |
| 1868 { | |
| 1869 // NativeCall instruction size is the same as NativeJump. | |
| 1870 // Note that this value is also credited (in output.cpp) to | |
| 1871 // the size of the code section. | |
| 1872 return NativeJump::instruction_size; | |
| 1873 } | |
| 1874 | |
| 1875 // Emit exception handler code. | |
| 1876 int emit_exception_handler(CodeBuffer& cbuf) | |
| 1877 { | |
| 1878 | |
| 1748 | 1879 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1880 // That's why we must use the macroassembler to generate a handler. |
| 1881 MacroAssembler _masm(&cbuf); | |
| 1882 address base = | |
| 1883 __ start_a_stub(size_exception_handler()); | |
| 1884 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1885 int offset = __ offset(); | |
| 1748 | 1886 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); |
| 0 | 1887 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); |
| 1888 __ end_a_stub(); | |
| 1889 return offset; | |
| 1890 } | |
| 1891 | |
| 1892 uint size_deopt_handler() | |
| 1893 { | |
| 1894 // three 5 byte instructions | |
| 1895 return 15; | |
| 1896 } | |
| 1897 | |
| 1898 // Emit deopt handler code. | |
| 1899 int emit_deopt_handler(CodeBuffer& cbuf) | |
| 1900 { | |
| 1901 | |
| 1748 | 1902 // Note that the code buffer's insts_mark is always relative to insts. |
| 0 | 1903 // That's why we must use the macroassembler to generate a handler. |
| 1904 MacroAssembler _masm(&cbuf); | |
| 1905 address base = | |
| 1906 __ start_a_stub(size_deopt_handler()); | |
| 1907 if (base == NULL) return 0; // CodeBuffer::expand failed | |
| 1908 int offset = __ offset(); | |
| 1909 address the_pc = (address) __ pc(); | |
| 1910 Label next; | |
| 1911 // push a "the_pc" on the stack without destroying any registers | |
| 1912 // as they all may be live. | |
| 1913 | |
| 1914 // push address of "next" | |
| 1915 __ call(next, relocInfo::none); // reloc none is fine since it is a disp32 | |
| 1916 __ bind(next); | |
| 1917 // adjust it so it matches "the_pc" | |
| 304 | 1918 __ subptr(Address(rsp, 0), __ offset() - offset); |
| 0 | 1919 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); |
| 1920 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); | |
| 1921 __ end_a_stub(); | |
| 1922 return offset; | |
| 1923 } | |
| 1924 | |
| 1925 static void emit_double_constant(CodeBuffer& cbuf, double x) { | |
| 1926 int mark = cbuf.insts()->mark_off(); | |
| 1927 MacroAssembler _masm(&cbuf); | |
| 1928 address double_address = __ double_constant(x); | |
| 1929 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift | |
| 1930 emit_d32_reloc(cbuf, | |
| 1748 | 1931 (int) (double_address - cbuf.insts_end() - 4), |
| 0 | 1932 internal_word_Relocation::spec(double_address), |
| 1933 RELOC_DISP32); | |
| 1934 } | |
| 1935 | |
| 1936 static void emit_float_constant(CodeBuffer& cbuf, float x) { | |
| 1937 int mark = cbuf.insts()->mark_off(); | |
| 1938 MacroAssembler _masm(&cbuf); | |
| 1939 address float_address = __ float_constant(x); | |
| 1940 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift | |
| 1941 emit_d32_reloc(cbuf, | |
| 1748 | 1942 (int) (float_address - cbuf.insts_end() - 4), |
| 0 | 1943 internal_word_Relocation::spec(float_address), |
| 1944 RELOC_DISP32); | |
| 1945 } | |
| 1946 | |
| 1947 | |
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1948 const bool Matcher::match_rule_supported(int opcode) { |
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1949 if (!has_match_rule(opcode)) |
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1950 return false; |
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1951 |
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1952 return true; // Per default match rules are supported. |
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1953 } |
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1954 |
| 0 | 1955 int Matcher::regnum_to_fpu_offset(int regnum) |
| 1956 { | |
| 1957 return regnum - 32; // The FP registers are in the second chunk | |
| 1958 } | |
| 1959 | |
| 1960 // This is UltraSparc specific, true just means we have fast l2f conversion | |
| 1961 const bool Matcher::convL2FSupported(void) { | |
| 1962 return true; | |
| 1963 } | |
| 1964 | |
| 1965 // Vector width in bytes | |
| 1966 const uint Matcher::vector_width_in_bytes(void) { | |
| 1967 return 8; | |
| 1968 } | |
| 1969 | |
| 1970 // Vector ideal reg | |
| 1971 const uint Matcher::vector_ideal_reg(void) { | |
| 1972 return Op_RegD; | |
| 1973 } | |
| 1974 | |
| 1975 // Is this branch offset short enough that a short branch can be used? | |
| 1976 // | |
| 1977 // NOTE: If the platform does not provide any short branch variants, then | |
| 1978 // this method should return false for offset 0. | |
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1979 bool Matcher::is_short_branch_offset(int rule, int offset) { |
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1980 // the short version of jmpConUCF2 contains multiple branches, |
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1981 // making the reach slightly less |
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1982 if (rule == jmpConUCF2_rule) |
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1983 return (-126 <= offset && offset <= 125); |
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1984 return (-128 <= offset && offset <= 127); |
| 0 | 1985 } |
| 1986 | |
| 1987 const bool Matcher::isSimpleConstant64(jlong value) { | |
| 1988 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. | |
| 1989 //return value == (int) value; // Cf. storeImmL and immL32. | |
| 1990 | |
| 1991 // Probably always true, even if a temp register is required. | |
| 1992 return true; | |
| 1993 } | |
| 1994 | |
| 1995 // The ecx parameter to rep stosq for the ClearArray node is in words. | |
| 1996 const bool Matcher::init_array_count_is_in_bytes = false; | |
| 1997 | |
| 1998 // Threshold size for cleararray. | |
| 1999 const int Matcher::init_array_short_size = 8 * BytesPerLong; | |
| 2000 | |
| 2001 // Should the Matcher clone shifts on addressing modes, expecting them | |
| 2002 // to be subsumed into complex addressing expressions or compute them | |
| 2003 // into registers? True for Intel but false for most RISCs | |
| 2004 const bool Matcher::clone_shift_expressions = true; | |
| 2005 | |
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2006 bool Matcher::narrow_oop_use_complex_address() { |
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2007 assert(UseCompressedOops, "only for compressed oops code"); |
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2008 return (LogMinObjAlignmentInBytes <= 3); |
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2009 } |
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2010 |
| 0 | 2011 // Is it better to copy float constants, or load them directly from |
| 2012 // memory? Intel can load a float constant from a direct address, | |
| 2013 // requiring no extra registers. Most RISCs will have to materialize | |
| 2014 // an address into a register first, so they would do better to copy | |
| 2015 // the constant from stack. | |
| 2016 const bool Matcher::rematerialize_float_constants = true; // XXX | |
| 2017 | |
| 2018 // If CPU can load and store mis-aligned doubles directly then no | |
| 2019 // fixup is needed. Else we split the double into 2 integer pieces | |
| 2020 // and move it piece-by-piece. Only happens when passing doubles into | |
| 2021 // C code as the Java calling convention forces doubles to be aligned. | |
| 2022 const bool Matcher::misaligned_doubles_ok = true; | |
| 2023 | |
| 2024 // No-op on amd64 | |
| 2025 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {} | |
| 2026 | |
| 2027 // Advertise here if the CPU requires explicit rounding operations to | |
| 2028 // implement the UseStrictFP mode. | |
| 2029 const bool Matcher::strict_fp_requires_explicit_rounding = true; | |
| 2030 | |
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2031 // Are floats conerted to double when stored to stack during deoptimization? |
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2032 // On x64 it is stored without convertion so we can use normal access. |
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2033 bool Matcher::float_in_double() { return false; } |
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2034 |
| 0 | 2035 // Do ints take an entire long register or just half? |
| 2036 const bool Matcher::int_in_long = true; | |
| 2037 | |
| 2038 // Return whether or not this register is ever used as an argument. | |
| 2039 // This function is used on startup to build the trampoline stubs in | |
| 2040 // generateOptoStub. Registers not mentioned will be killed by the VM | |
| 2041 // call in the trampoline, and arguments in those registers not be | |
| 2042 // available to the callee. | |
| 2043 bool Matcher::can_be_java_arg(int reg) | |
| 2044 { | |
| 2045 return | |
| 2046 reg == RDI_num || reg == RDI_H_num || | |
| 2047 reg == RSI_num || reg == RSI_H_num || | |
| 2048 reg == RDX_num || reg == RDX_H_num || | |
| 2049 reg == RCX_num || reg == RCX_H_num || | |
| 2050 reg == R8_num || reg == R8_H_num || | |
| 2051 reg == R9_num || reg == R9_H_num || | |
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2052 reg == R12_num || reg == R12_H_num || |
| 0 | 2053 reg == XMM0_num || reg == XMM0_H_num || |
| 2054 reg == XMM1_num || reg == XMM1_H_num || | |
| 2055 reg == XMM2_num || reg == XMM2_H_num || | |
| 2056 reg == XMM3_num || reg == XMM3_H_num || | |
| 2057 reg == XMM4_num || reg == XMM4_H_num || | |
| 2058 reg == XMM5_num || reg == XMM5_H_num || | |
| 2059 reg == XMM6_num || reg == XMM6_H_num || | |
| 2060 reg == XMM7_num || reg == XMM7_H_num; | |
| 2061 } | |
| 2062 | |
| 2063 bool Matcher::is_spillable_arg(int reg) | |
| 2064 { | |
| 2065 return can_be_java_arg(reg); | |
| 2066 } | |
| 2067 | |
| 2068 // Register for DIVI projection of divmodI | |
| 2069 RegMask Matcher::divI_proj_mask() { | |
| 2070 return INT_RAX_REG_mask; | |
| 2071 } | |
| 2072 | |
| 2073 // Register for MODI projection of divmodI | |
| 2074 RegMask Matcher::modI_proj_mask() { | |
| 2075 return INT_RDX_REG_mask; | |
| 2076 } | |
| 2077 | |
| 2078 // Register for DIVL projection of divmodL | |
| 2079 RegMask Matcher::divL_proj_mask() { | |
| 2080 return LONG_RAX_REG_mask; | |
| 2081 } | |
| 2082 | |
| 2083 // Register for MODL projection of divmodL | |
| 2084 RegMask Matcher::modL_proj_mask() { | |
| 2085 return LONG_RDX_REG_mask; | |
| 2086 } | |
| 2087 | |
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2088 const RegMask Matcher::method_handle_invoke_SP_save_mask() { |
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2089 return PTR_RBP_REG_mask; |
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2090 } |
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2091 |
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2092 static Address build_address(int b, int i, int s, int d) { |
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2093 Register index = as_Register(i); |
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2094 Address::ScaleFactor scale = (Address::ScaleFactor)s; |
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2095 if (index == rsp) { |
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2096 index = noreg; |
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2097 scale = Address::no_scale; |
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2098 } |
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2099 Address addr(as_Register(b), index, scale, d); |
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2100 return addr; |
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2101 } |
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2102 |
| 0 | 2103 %} |
| 2104 | |
| 2105 //----------ENCODING BLOCK----------------------------------------------------- | |
| 2106 // This block specifies the encoding classes used by the compiler to | |
| 2107 // output byte streams. Encoding classes are parameterized macros | |
| 2108 // used by Machine Instruction Nodes in order to generate the bit | |
| 2109 // encoding of the instruction. Operands specify their base encoding | |
| 2110 // interface with the interface keyword. There are currently | |
| 2111 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, & | |
| 2112 // COND_INTER. REG_INTER causes an operand to generate a function | |
| 2113 // which returns its register number when queried. CONST_INTER causes | |
| 2114 // an operand to generate a function which returns the value of the | |
| 2115 // constant when queried. MEMORY_INTER causes an operand to generate | |
| 2116 // four functions which return the Base Register, the Index Register, | |
| 2117 // the Scale Value, and the Offset Value of the operand when queried. | |
| 2118 // COND_INTER causes an operand to generate six functions which return | |
| 2119 // the encoding code (ie - encoding bits for the instruction) | |
| 2120 // associated with each basic boolean condition for a conditional | |
| 2121 // instruction. | |
| 2122 // | |
| 2123 // Instructions specify two basic values for encoding. Again, a | |
| 2124 // function is available to check if the constant displacement is an | |
| 2125 // oop. They use the ins_encode keyword to specify their encoding | |
| 2126 // classes (which must be a sequence of enc_class names, and their | |
| 2127 // parameters, specified in the encoding block), and they use the | |
| 2128 // opcode keyword to specify, in order, their primary, secondary, and | |
| 2129 // tertiary opcode. Only the opcode sections which a particular | |
| 2130 // instruction needs for encoding need to be specified. | |
| 2131 encode %{ | |
| 2132 // Build emit functions for each basic byte or larger field in the | |
| 2133 // intel encoding scheme (opcode, rm, sib, immediate), and call them | |
| 2134 // from C++ code in the enc_class source block. Emit functions will | |
| 2135 // live in the main source block for now. In future, we can | |
| 2136 // generalize this by adding a syntax that specifies the sizes of | |
| 2137 // fields in an order, so that the adlc can build the emit functions | |
| 2138 // automagically | |
| 2139 | |
| 2140 // Emit primary opcode | |
| 2141 enc_class OpcP | |
| 2142 %{ | |
| 2143 emit_opcode(cbuf, $primary); | |
| 2144 %} | |
| 2145 | |
| 2146 // Emit secondary opcode | |
| 2147 enc_class OpcS | |
| 2148 %{ | |
| 2149 emit_opcode(cbuf, $secondary); | |
| 2150 %} | |
| 2151 | |
| 2152 // Emit tertiary opcode | |
| 2153 enc_class OpcT | |
| 2154 %{ | |
| 2155 emit_opcode(cbuf, $tertiary); | |
| 2156 %} | |
| 2157 | |
| 2158 // Emit opcode directly | |
| 2159 enc_class Opcode(immI d8) | |
| 2160 %{ | |
| 2161 emit_opcode(cbuf, $d8$$constant); | |
| 2162 %} | |
| 2163 | |
| 2164 // Emit size prefix | |
| 2165 enc_class SizePrefix | |
| 2166 %{ | |
| 2167 emit_opcode(cbuf, 0x66); | |
| 2168 %} | |
| 2169 | |
| 2170 enc_class reg(rRegI reg) | |
| 2171 %{ | |
| 2172 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7); | |
| 2173 %} | |
| 2174 | |
| 2175 enc_class reg_reg(rRegI dst, rRegI src) | |
| 2176 %{ | |
| 2177 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2178 %} | |
| 2179 | |
| 2180 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src) | |
| 2181 %{ | |
| 2182 emit_opcode(cbuf, $opcode$$constant); | |
| 2183 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2184 %} | |
| 2185 | |
| 2186 enc_class cmpfp_fixup() | |
| 2187 %{ | |
| 2188 // jnp,s exit | |
| 2189 emit_opcode(cbuf, 0x7B); | |
| 2190 emit_d8(cbuf, 0x0A); | |
| 2191 | |
| 2192 // pushfq | |
| 2193 emit_opcode(cbuf, 0x9C); | |
| 2194 | |
| 2195 // andq $0xffffff2b, (%rsp) | |
| 2196 emit_opcode(cbuf, Assembler::REX_W); | |
| 2197 emit_opcode(cbuf, 0x81); | |
| 2198 emit_opcode(cbuf, 0x24); | |
| 2199 emit_opcode(cbuf, 0x24); | |
| 2200 emit_d32(cbuf, 0xffffff2b); | |
| 2201 | |
| 2202 // popfq | |
| 2203 emit_opcode(cbuf, 0x9D); | |
| 2204 | |
| 2205 // nop (target for branch to avoid branch to branch) | |
| 2206 emit_opcode(cbuf, 0x90); | |
| 2207 %} | |
| 2208 | |
| 2209 enc_class cmpfp3(rRegI dst) | |
| 2210 %{ | |
| 2211 int dstenc = $dst$$reg; | |
| 2212 | |
| 2213 // movl $dst, -1 | |
| 2214 if (dstenc >= 8) { | |
| 2215 emit_opcode(cbuf, Assembler::REX_B); | |
| 2216 } | |
| 2217 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 2218 emit_d32(cbuf, -1); | |
| 2219 | |
| 2220 // jp,s done | |
| 2221 emit_opcode(cbuf, 0x7A); | |
| 2222 emit_d8(cbuf, dstenc < 4 ? 0x08 : 0x0A); | |
| 2223 | |
| 2224 // jb,s done | |
| 2225 emit_opcode(cbuf, 0x72); | |
| 2226 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 2227 | |
| 2228 // setne $dst | |
| 2229 if (dstenc >= 4) { | |
| 2230 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 2231 } | |
| 2232 emit_opcode(cbuf, 0x0F); | |
| 2233 emit_opcode(cbuf, 0x95); | |
| 2234 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 2235 | |
| 2236 // movzbl $dst, $dst | |
| 2237 if (dstenc >= 4) { | |
| 2238 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 2239 } | |
| 2240 emit_opcode(cbuf, 0x0F); | |
| 2241 emit_opcode(cbuf, 0xB6); | |
| 2242 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 2243 %} | |
| 2244 | |
| 2245 enc_class cdql_enc(no_rax_rdx_RegI div) | |
| 2246 %{ | |
| 2247 // Full implementation of Java idiv and irem; checks for | |
| 2248 // special case as described in JVM spec., p.243 & p.271. | |
| 2249 // | |
| 2250 // normal case special case | |
| 2251 // | |
| 2252 // input : rax: dividend min_int | |
| 2253 // reg: divisor -1 | |
| 2254 // | |
| 2255 // output: rax: quotient (= rax idiv reg) min_int | |
| 2256 // rdx: remainder (= rax irem reg) 0 | |
| 2257 // | |
| 2258 // Code sequnce: | |
| 2259 // | |
| 2260 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax | |
| 2261 // 5: 75 07/08 jne e <normal> | |
| 2262 // 7: 33 d2 xor %edx,%edx | |
| 2263 // [div >= 8 -> offset + 1] | |
| 2264 // [REX_B] | |
| 2265 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 2266 // c: 74 03/04 je 11 <done> | |
| 2267 // 000000000000000e <normal>: | |
| 2268 // e: 99 cltd | |
| 2269 // [div >= 8 -> offset + 1] | |
| 2270 // [REX_B] | |
| 2271 // f: f7 f9 idiv $div | |
| 2272 // 0000000000000011 <done>: | |
| 2273 | |
| 2274 // cmp $0x80000000,%eax | |
| 2275 emit_opcode(cbuf, 0x3d); | |
| 2276 emit_d8(cbuf, 0x00); | |
| 2277 emit_d8(cbuf, 0x00); | |
| 2278 emit_d8(cbuf, 0x00); | |
| 2279 emit_d8(cbuf, 0x80); | |
| 2280 | |
| 2281 // jne e <normal> | |
| 2282 emit_opcode(cbuf, 0x75); | |
| 2283 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08); | |
| 2284 | |
| 2285 // xor %edx,%edx | |
| 2286 emit_opcode(cbuf, 0x33); | |
| 2287 emit_d8(cbuf, 0xD2); | |
| 2288 | |
| 2289 // cmp $0xffffffffffffffff,%ecx | |
| 2290 if ($div$$reg >= 8) { | |
| 2291 emit_opcode(cbuf, Assembler::REX_B); | |
| 2292 } | |
| 2293 emit_opcode(cbuf, 0x83); | |
| 2294 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 2295 emit_d8(cbuf, 0xFF); | |
| 2296 | |
| 2297 // je 11 <done> | |
| 2298 emit_opcode(cbuf, 0x74); | |
| 2299 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04); | |
| 2300 | |
| 2301 // <normal> | |
| 2302 // cltd | |
| 2303 emit_opcode(cbuf, 0x99); | |
| 2304 | |
| 2305 // idivl (note: must be emitted by the user of this rule) | |
| 2306 // <done> | |
| 2307 %} | |
| 2308 | |
| 2309 enc_class cdqq_enc(no_rax_rdx_RegL div) | |
| 2310 %{ | |
| 2311 // Full implementation of Java ldiv and lrem; checks for | |
| 2312 // special case as described in JVM spec., p.243 & p.271. | |
| 2313 // | |
| 2314 // normal case special case | |
| 2315 // | |
| 2316 // input : rax: dividend min_long | |
| 2317 // reg: divisor -1 | |
| 2318 // | |
| 2319 // output: rax: quotient (= rax idiv reg) min_long | |
| 2320 // rdx: remainder (= rax irem reg) 0 | |
| 2321 // | |
| 2322 // Code sequnce: | |
| 2323 // | |
| 2324 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx | |
| 2325 // 7: 00 00 80 | |
| 2326 // a: 48 39 d0 cmp %rdx,%rax | |
| 2327 // d: 75 08 jne 17 <normal> | |
| 2328 // f: 33 d2 xor %edx,%edx | |
| 2329 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div | |
| 2330 // 15: 74 05 je 1c <done> | |
| 2331 // 0000000000000017 <normal>: | |
| 2332 // 17: 48 99 cqto | |
| 2333 // 19: 48 f7 f9 idiv $div | |
| 2334 // 000000000000001c <done>: | |
| 2335 | |
| 2336 // mov $0x8000000000000000,%rdx | |
| 2337 emit_opcode(cbuf, Assembler::REX_W); | |
| 2338 emit_opcode(cbuf, 0xBA); | |
| 2339 emit_d8(cbuf, 0x00); | |
| 2340 emit_d8(cbuf, 0x00); | |
| 2341 emit_d8(cbuf, 0x00); | |
| 2342 emit_d8(cbuf, 0x00); | |
| 2343 emit_d8(cbuf, 0x00); | |
| 2344 emit_d8(cbuf, 0x00); | |
| 2345 emit_d8(cbuf, 0x00); | |
| 2346 emit_d8(cbuf, 0x80); | |
| 2347 | |
| 2348 // cmp %rdx,%rax | |
| 2349 emit_opcode(cbuf, Assembler::REX_W); | |
| 2350 emit_opcode(cbuf, 0x39); | |
| 2351 emit_d8(cbuf, 0xD0); | |
| 2352 | |
| 2353 // jne 17 <normal> | |
| 2354 emit_opcode(cbuf, 0x75); | |
| 2355 emit_d8(cbuf, 0x08); | |
| 2356 | |
| 2357 // xor %edx,%edx | |
| 2358 emit_opcode(cbuf, 0x33); | |
| 2359 emit_d8(cbuf, 0xD2); | |
| 2360 | |
| 2361 // cmp $0xffffffffffffffff,$div | |
| 2362 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB); | |
| 2363 emit_opcode(cbuf, 0x83); | |
| 2364 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7); | |
| 2365 emit_d8(cbuf, 0xFF); | |
| 2366 | |
| 2367 // je 1e <done> | |
| 2368 emit_opcode(cbuf, 0x74); | |
| 2369 emit_d8(cbuf, 0x05); | |
| 2370 | |
| 2371 // <normal> | |
| 2372 // cqto | |
| 2373 emit_opcode(cbuf, Assembler::REX_W); | |
| 2374 emit_opcode(cbuf, 0x99); | |
| 2375 | |
| 2376 // idivq (note: must be emitted by the user of this rule) | |
| 2377 // <done> | |
| 2378 %} | |
| 2379 | |
| 2380 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension | |
| 2381 enc_class OpcSE(immI imm) | |
| 2382 %{ | |
| 2383 // Emit primary opcode and set sign-extend bit | |
| 2384 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2385 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2386 emit_opcode(cbuf, $primary | 0x02); | |
| 2387 } else { | |
| 2388 // 32-bit immediate | |
| 2389 emit_opcode(cbuf, $primary); | |
| 2390 } | |
| 2391 %} | |
| 2392 | |
| 2393 enc_class OpcSErm(rRegI dst, immI imm) | |
| 2394 %{ | |
| 2395 // OpcSEr/m | |
| 2396 int dstenc = $dst$$reg; | |
| 2397 if (dstenc >= 8) { | |
| 2398 emit_opcode(cbuf, Assembler::REX_B); | |
| 2399 dstenc -= 8; | |
| 2400 } | |
| 2401 // Emit primary opcode and set sign-extend bit | |
| 2402 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2403 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2404 emit_opcode(cbuf, $primary | 0x02); | |
| 2405 } else { | |
| 2406 // 32-bit immediate | |
| 2407 emit_opcode(cbuf, $primary); | |
| 2408 } | |
| 2409 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2410 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2411 %} | |
| 2412 | |
| 2413 enc_class OpcSErm_wide(rRegL dst, immI imm) | |
| 2414 %{ | |
| 2415 // OpcSEr/m | |
| 2416 int dstenc = $dst$$reg; | |
| 2417 if (dstenc < 8) { | |
| 2418 emit_opcode(cbuf, Assembler::REX_W); | |
| 2419 } else { | |
| 2420 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2421 dstenc -= 8; | |
| 2422 } | |
| 2423 // Emit primary opcode and set sign-extend bit | |
| 2424 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2425 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2426 emit_opcode(cbuf, $primary | 0x02); | |
| 2427 } else { | |
| 2428 // 32-bit immediate | |
| 2429 emit_opcode(cbuf, $primary); | |
| 2430 } | |
| 2431 // Emit r/m byte with secondary opcode, after primary opcode. | |
| 2432 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2433 %} | |
| 2434 | |
| 2435 enc_class Con8or32(immI imm) | |
| 2436 %{ | |
| 2437 // Check for 8-bit immediate, and set sign extend bit in opcode | |
| 2438 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) { | |
| 2439 $$$emit8$imm$$constant; | |
| 2440 } else { | |
| 2441 // 32-bit immediate | |
| 2442 $$$emit32$imm$$constant; | |
| 2443 } | |
| 2444 %} | |
| 2445 | |
| 2446 enc_class Lbl(label labl) | |
| 2447 %{ | |
| 2448 // JMP, CALL | |
| 2449 Label* l = $labl$$label; | |
| 1748 | 2450 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0); |
| 0 | 2451 %} |
| 2452 | |
| 2453 enc_class LblShort(label labl) | |
| 2454 %{ | |
| 2455 // JMP, CALL | |
| 2456 Label* l = $labl$$label; | |
| 1748 | 2457 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0; |
| 0 | 2458 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
| 2459 emit_d8(cbuf, disp); | |
| 2460 %} | |
| 2461 | |
| 2462 enc_class opc2_reg(rRegI dst) | |
| 2463 %{ | |
| 2464 // BSWAP | |
| 2465 emit_cc(cbuf, $secondary, $dst$$reg); | |
| 2466 %} | |
| 2467 | |
| 2468 enc_class opc3_reg(rRegI dst) | |
| 2469 %{ | |
| 2470 // BSWAP | |
| 2471 emit_cc(cbuf, $tertiary, $dst$$reg); | |
| 2472 %} | |
| 2473 | |
| 2474 enc_class reg_opc(rRegI div) | |
| 2475 %{ | |
| 2476 // INC, DEC, IDIV, IMOD, JMP indirect, ... | |
| 2477 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7); | |
| 2478 %} | |
| 2479 | |
| 2480 enc_class Jcc(cmpOp cop, label labl) | |
| 2481 %{ | |
| 2482 // JCC | |
| 2483 Label* l = $labl$$label; | |
| 2484 $$$emit8$primary; | |
| 2485 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 1748 | 2486 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0); |
| 0 | 2487 %} |
| 2488 | |
| 2489 enc_class JccShort (cmpOp cop, label labl) | |
| 2490 %{ | |
| 2491 // JCC | |
| 2492 Label *l = $labl$$label; | |
| 2493 emit_cc(cbuf, $primary, $cop$$cmpcode); | |
| 1748 | 2494 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0; |
| 0 | 2495 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
| 2496 emit_d8(cbuf, disp); | |
| 2497 %} | |
| 2498 | |
| 2499 enc_class enc_cmov(cmpOp cop) | |
| 2500 %{ | |
| 2501 // CMOV | |
| 2502 $$$emit8$primary; | |
| 2503 emit_cc(cbuf, $secondary, $cop$$cmpcode); | |
| 2504 %} | |
| 2505 | |
| 2506 enc_class enc_cmovf_branch(cmpOp cop, regF dst, regF src) | |
| 2507 %{ | |
| 2508 // Invert sense of branch from sense of cmov | |
| 2509 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1); | |
| 2510 emit_d8(cbuf, ($dst$$reg < 8 && $src$$reg < 8) | |
| 2511 ? (UseXmmRegToRegMoveAll ? 3 : 4) | |
| 2512 : (UseXmmRegToRegMoveAll ? 4 : 5) ); // REX | |
| 2513 // UseXmmRegToRegMoveAll ? movaps(dst, src) : movss(dst, src) | |
| 2514 if (!UseXmmRegToRegMoveAll) emit_opcode(cbuf, 0xF3); | |
| 2515 if ($dst$$reg < 8) { | |
| 2516 if ($src$$reg >= 8) { | |
| 2517 emit_opcode(cbuf, Assembler::REX_B); | |
| 2518 } | |
| 2519 } else { | |
| 2520 if ($src$$reg < 8) { | |
| 2521 emit_opcode(cbuf, Assembler::REX_R); | |
| 2522 } else { | |
| 2523 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2524 } | |
| 2525 } | |
| 2526 emit_opcode(cbuf, 0x0F); | |
| 2527 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 2528 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2529 %} | |
| 2530 | |
| 2531 enc_class enc_cmovd_branch(cmpOp cop, regD dst, regD src) | |
| 2532 %{ | |
| 2533 // Invert sense of branch from sense of cmov | |
| 2534 emit_cc(cbuf, 0x70, $cop$$cmpcode ^ 1); | |
| 2535 emit_d8(cbuf, $dst$$reg < 8 && $src$$reg < 8 ? 4 : 5); // REX | |
| 2536 | |
| 2537 // UseXmmRegToRegMoveAll ? movapd(dst, src) : movsd(dst, src) | |
| 2538 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x66 : 0xF2); | |
| 2539 if ($dst$$reg < 8) { | |
| 2540 if ($src$$reg >= 8) { | |
| 2541 emit_opcode(cbuf, Assembler::REX_B); | |
| 2542 } | |
| 2543 } else { | |
| 2544 if ($src$$reg < 8) { | |
| 2545 emit_opcode(cbuf, Assembler::REX_R); | |
| 2546 } else { | |
| 2547 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2548 } | |
| 2549 } | |
| 2550 emit_opcode(cbuf, 0x0F); | |
| 2551 emit_opcode(cbuf, UseXmmRegToRegMoveAll ? 0x28 : 0x10); | |
| 2552 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7); | |
| 2553 %} | |
| 2554 | |
| 2555 enc_class enc_PartialSubtypeCheck() | |
| 2556 %{ | |
| 2557 Register Rrdi = as_Register(RDI_enc); // result register | |
| 2558 Register Rrax = as_Register(RAX_enc); // super class | |
| 2559 Register Rrcx = as_Register(RCX_enc); // killed | |
| 2560 Register Rrsi = as_Register(RSI_enc); // sub class | |
|
644
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2561 Label miss; |
|
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2562 const bool set_cond_codes = true; |
| 0 | 2563 |
| 2564 MacroAssembler _masm(&cbuf); | |
|
644
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2565 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi, |
|
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2566 NULL, &miss, |
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2567 /*set_cond_codes:*/ true); |
| 0 | 2568 if ($primary) { |
| 304 | 2569 __ xorptr(Rrdi, Rrdi); |
| 0 | 2570 } |
| 2571 __ bind(miss); | |
| 2572 %} | |
| 2573 | |
| 2574 enc_class Java_To_Interpreter(method meth) | |
| 2575 %{ | |
| 2576 // CALL Java_To_Interpreter | |
| 2577 // This is the instruction starting address for relocation info. | |
| 1748 | 2578 cbuf.set_insts_mark(); |
| 0 | 2579 $$$emit8$primary; |
| 2580 // CALL directly to the runtime | |
| 2581 emit_d32_reloc(cbuf, | |
| 1748 | 2582 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2583 runtime_call_Relocation::spec(), |
| 2584 RELOC_DISP32); | |
| 2585 %} | |
| 2586 | |
|
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2587 enc_class preserve_SP %{ |
| 1748 | 2588 debug_only(int off0 = cbuf.insts_size()); |
|
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2589 MacroAssembler _masm(&cbuf); |
|
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2590 // RBP is preserved across all calls, even compiled calls. |
|
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2591 // Use it to preserve RSP in places where the callee might change the SP. |
| 1567 | 2592 __ movptr(rbp_mh_SP_save, rsp); |
| 1748 | 2593 debug_only(int off1 = cbuf.insts_size()); |
|
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2594 assert(off1 - off0 == preserve_SP_size(), "correct size prediction"); |
|
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|
2595 %} |
|
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|
2596 |
|
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2597 enc_class restore_SP %{ |
|
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2598 MacroAssembler _masm(&cbuf); |
| 1567 | 2599 __ movptr(rsp, rbp_mh_SP_save); |
|
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2600 %} |
|
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2601 |
| 0 | 2602 enc_class Java_Static_Call(method meth) |
| 2603 %{ | |
| 2604 // JAVA STATIC CALL | |
| 2605 // CALL to fixup routine. Fixup routine uses ScopeDesc info to | |
| 2606 // determine who we intended to call. | |
| 1748 | 2607 cbuf.set_insts_mark(); |
| 0 | 2608 $$$emit8$primary; |
| 2609 | |
| 2610 if (!_method) { | |
| 2611 emit_d32_reloc(cbuf, | |
| 1748 | 2612 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2613 runtime_call_Relocation::spec(), |
| 2614 RELOC_DISP32); | |
| 2615 } else if (_optimized_virtual) { | |
| 2616 emit_d32_reloc(cbuf, | |
| 1748 | 2617 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2618 opt_virtual_call_Relocation::spec(), |
| 2619 RELOC_DISP32); | |
| 2620 } else { | |
| 2621 emit_d32_reloc(cbuf, | |
| 1748 | 2622 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2623 static_call_Relocation::spec(), |
| 2624 RELOC_DISP32); | |
| 2625 } | |
| 2626 if (_method) { | |
| 2627 // Emit stub for static call | |
| 2628 emit_java_to_interp(cbuf); | |
| 2629 } | |
| 2630 %} | |
| 2631 | |
| 2632 enc_class Java_Dynamic_Call(method meth) | |
| 2633 %{ | |
| 2634 // JAVA DYNAMIC CALL | |
| 2635 // !!!!! | |
| 2636 // Generate "movq rax, -1", placeholder instruction to load oop-info | |
| 2637 // emit_call_dynamic_prologue( cbuf ); | |
| 1748 | 2638 cbuf.set_insts_mark(); |
| 0 | 2639 |
| 2640 // movq rax, -1 | |
| 2641 emit_opcode(cbuf, Assembler::REX_W); | |
| 2642 emit_opcode(cbuf, 0xB8 | RAX_enc); | |
| 2643 emit_d64_reloc(cbuf, | |
| 2644 (int64_t) Universe::non_oop_word(), | |
| 2645 oop_Relocation::spec_for_immediate(), RELOC_IMM64); | |
| 1748 | 2646 address virtual_call_oop_addr = cbuf.insts_mark(); |
| 0 | 2647 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine |
| 2648 // who we intended to call. | |
| 1748 | 2649 cbuf.set_insts_mark(); |
| 0 | 2650 $$$emit8$primary; |
| 2651 emit_d32_reloc(cbuf, | |
| 1748 | 2652 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4), |
| 0 | 2653 virtual_call_Relocation::spec(virtual_call_oop_addr), |
| 2654 RELOC_DISP32); | |
| 2655 %} | |
| 2656 | |
| 2657 enc_class Java_Compiled_Call(method meth) | |
| 2658 %{ | |
| 2659 // JAVA COMPILED CALL | |
| 2660 int disp = in_bytes(methodOopDesc:: from_compiled_offset()); | |
| 2661 | |
| 2662 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!! | |
| 2663 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small"); | |
| 2664 | |
| 2665 // callq *disp(%rax) | |
| 1748 | 2666 cbuf.set_insts_mark(); |
| 0 | 2667 $$$emit8$primary; |
| 2668 if (disp < 0x80) { | |
| 2669 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte | |
| 2670 emit_d8(cbuf, disp); // Displacement | |
| 2671 } else { | |
| 2672 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte | |
| 2673 emit_d32(cbuf, disp); // Displacement | |
| 2674 } | |
| 2675 %} | |
| 2676 | |
| 2677 enc_class reg_opc_imm(rRegI dst, immI8 shift) | |
| 2678 %{ | |
| 2679 // SAL, SAR, SHR | |
| 2680 int dstenc = $dst$$reg; | |
| 2681 if (dstenc >= 8) { | |
| 2682 emit_opcode(cbuf, Assembler::REX_B); | |
| 2683 dstenc -= 8; | |
| 2684 } | |
| 2685 $$$emit8$primary; | |
| 2686 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2687 $$$emit8$shift$$constant; | |
| 2688 %} | |
| 2689 | |
| 2690 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift) | |
| 2691 %{ | |
| 2692 // SAL, SAR, SHR | |
| 2693 int dstenc = $dst$$reg; | |
| 2694 if (dstenc < 8) { | |
| 2695 emit_opcode(cbuf, Assembler::REX_W); | |
| 2696 } else { | |
| 2697 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2698 dstenc -= 8; | |
| 2699 } | |
| 2700 $$$emit8$primary; | |
| 2701 emit_rm(cbuf, 0x3, $secondary, dstenc); | |
| 2702 $$$emit8$shift$$constant; | |
| 2703 %} | |
| 2704 | |
| 2705 enc_class load_immI(rRegI dst, immI src) | |
| 2706 %{ | |
| 2707 int dstenc = $dst$$reg; | |
| 2708 if (dstenc >= 8) { | |
| 2709 emit_opcode(cbuf, Assembler::REX_B); | |
| 2710 dstenc -= 8; | |
| 2711 } | |
| 2712 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2713 $$$emit32$src$$constant; | |
| 2714 %} | |
| 2715 | |
| 2716 enc_class load_immL(rRegL dst, immL src) | |
| 2717 %{ | |
| 2718 int dstenc = $dst$$reg; | |
| 2719 if (dstenc < 8) { | |
| 2720 emit_opcode(cbuf, Assembler::REX_W); | |
| 2721 } else { | |
| 2722 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2723 dstenc -= 8; | |
| 2724 } | |
| 2725 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2726 emit_d64(cbuf, $src$$constant); | |
| 2727 %} | |
| 2728 | |
| 2729 enc_class load_immUL32(rRegL dst, immUL32 src) | |
| 2730 %{ | |
| 2731 // same as load_immI, but this time we care about zeroes in the high word | |
| 2732 int dstenc = $dst$$reg; | |
| 2733 if (dstenc >= 8) { | |
| 2734 emit_opcode(cbuf, Assembler::REX_B); | |
| 2735 dstenc -= 8; | |
| 2736 } | |
| 2737 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2738 $$$emit32$src$$constant; | |
| 2739 %} | |
| 2740 | |
| 2741 enc_class load_immL32(rRegL dst, immL32 src) | |
| 2742 %{ | |
| 2743 int dstenc = $dst$$reg; | |
| 2744 if (dstenc < 8) { | |
| 2745 emit_opcode(cbuf, Assembler::REX_W); | |
| 2746 } else { | |
| 2747 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2748 dstenc -= 8; | |
| 2749 } | |
| 2750 emit_opcode(cbuf, 0xC7); | |
| 2751 emit_rm(cbuf, 0x03, 0x00, dstenc); | |
| 2752 $$$emit32$src$$constant; | |
| 2753 %} | |
| 2754 | |
| 2755 enc_class load_immP31(rRegP dst, immP32 src) | |
| 2756 %{ | |
| 2757 // same as load_immI, but this time we care about zeroes in the high word | |
| 2758 int dstenc = $dst$$reg; | |
| 2759 if (dstenc >= 8) { | |
| 2760 emit_opcode(cbuf, Assembler::REX_B); | |
| 2761 dstenc -= 8; | |
| 2762 } | |
| 2763 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2764 $$$emit32$src$$constant; | |
| 2765 %} | |
| 2766 | |
| 2767 enc_class load_immP(rRegP dst, immP src) | |
| 2768 %{ | |
| 2769 int dstenc = $dst$$reg; | |
| 2770 if (dstenc < 8) { | |
| 2771 emit_opcode(cbuf, Assembler::REX_W); | |
| 2772 } else { | |
| 2773 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2774 dstenc -= 8; | |
| 2775 } | |
| 2776 emit_opcode(cbuf, 0xB8 | dstenc); | |
| 2777 // This next line should be generated from ADLC | |
| 2778 if ($src->constant_is_oop()) { | |
| 2779 emit_d64_reloc(cbuf, $src$$constant, relocInfo::oop_type, RELOC_IMM64); | |
| 2780 } else { | |
| 2781 emit_d64(cbuf, $src$$constant); | |
| 2782 } | |
| 2783 %} | |
| 2784 | |
| 2785 enc_class load_immF(regF dst, immF con) | |
| 2786 %{ | |
| 2787 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 2788 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
| 2789 emit_float_constant(cbuf, $con$$constant); | |
| 2790 %} | |
| 2791 | |
| 2792 enc_class load_immD(regD dst, immD con) | |
| 2793 %{ | |
| 2794 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 2795 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
| 2796 emit_double_constant(cbuf, $con$$constant); | |
| 2797 %} | |
| 2798 | |
| 2799 enc_class load_conF (regF dst, immF con) %{ // Load float constant | |
| 2800 emit_opcode(cbuf, 0xF3); | |
| 2801 if ($dst$$reg >= 8) { | |
| 2802 emit_opcode(cbuf, Assembler::REX_R); | |
| 2803 } | |
| 2804 emit_opcode(cbuf, 0x0F); | |
| 2805 emit_opcode(cbuf, 0x10); | |
| 2806 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
| 2807 emit_float_constant(cbuf, $con$$constant); | |
| 2808 %} | |
| 2809 | |
| 2810 enc_class load_conD (regD dst, immD con) %{ // Load double constant | |
| 2811 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con) | |
| 2812 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 2813 if ($dst$$reg >= 8) { | |
| 2814 emit_opcode(cbuf, Assembler::REX_R); | |
| 2815 } | |
| 2816 emit_opcode(cbuf, 0x0F); | |
| 2817 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); | |
| 2818 emit_rm(cbuf, 0x0, $dst$$reg & 7, 0x5); // 00 reg 101 | |
| 2819 emit_double_constant(cbuf, $con$$constant); | |
| 2820 %} | |
| 2821 | |
| 2822 // Encode a reg-reg copy. If it is useless, then empty encoding. | |
| 2823 enc_class enc_copy(rRegI dst, rRegI src) | |
| 2824 %{ | |
| 2825 encode_copy(cbuf, $dst$$reg, $src$$reg); | |
| 2826 %} | |
| 2827 | |
| 2828 // Encode xmm reg-reg copy. If it is useless, then empty encoding. | |
| 2829 enc_class enc_CopyXD( RegD dst, RegD src ) %{ | |
| 2830 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); | |
| 2831 %} | |
| 2832 | |
| 2833 enc_class enc_copy_always(rRegI dst, rRegI src) | |
| 2834 %{ | |
| 2835 int srcenc = $src$$reg; | |
| 2836 int dstenc = $dst$$reg; | |
| 2837 | |
| 2838 if (dstenc < 8) { | |
| 2839 if (srcenc >= 8) { | |
| 2840 emit_opcode(cbuf, Assembler::REX_B); | |
| 2841 srcenc -= 8; | |
| 2842 } | |
| 2843 } else { | |
| 2844 if (srcenc < 8) { | |
| 2845 emit_opcode(cbuf, Assembler::REX_R); | |
| 2846 } else { | |
| 2847 emit_opcode(cbuf, Assembler::REX_RB); | |
| 2848 srcenc -= 8; | |
| 2849 } | |
| 2850 dstenc -= 8; | |
| 2851 } | |
| 2852 | |
| 2853 emit_opcode(cbuf, 0x8B); | |
| 2854 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
| 2855 %} | |
| 2856 | |
| 2857 enc_class enc_copy_wide(rRegL dst, rRegL src) | |
| 2858 %{ | |
| 2859 int srcenc = $src$$reg; | |
| 2860 int dstenc = $dst$$reg; | |
| 2861 | |
| 2862 if (dstenc != srcenc) { | |
| 2863 if (dstenc < 8) { | |
| 2864 if (srcenc < 8) { | |
| 2865 emit_opcode(cbuf, Assembler::REX_W); | |
| 2866 } else { | |
| 2867 emit_opcode(cbuf, Assembler::REX_WB); | |
| 2868 srcenc -= 8; | |
| 2869 } | |
| 2870 } else { | |
| 2871 if (srcenc < 8) { | |
| 2872 emit_opcode(cbuf, Assembler::REX_WR); | |
| 2873 } else { | |
| 2874 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 2875 srcenc -= 8; | |
| 2876 } | |
| 2877 dstenc -= 8; | |
| 2878 } | |
| 2879 emit_opcode(cbuf, 0x8B); | |
| 2880 emit_rm(cbuf, 0x3, dstenc, srcenc); | |
| 2881 } | |
| 2882 %} | |
| 2883 | |
| 2884 enc_class Con32(immI src) | |
| 2885 %{ | |
| 2886 // Output immediate | |
| 2887 $$$emit32$src$$constant; | |
| 2888 %} | |
| 2889 | |
| 2890 enc_class Con64(immL src) | |
| 2891 %{ | |
| 2892 // Output immediate | |
| 2893 emit_d64($src$$constant); | |
| 2894 %} | |
| 2895 | |
| 2896 enc_class Con32F_as_bits(immF src) | |
| 2897 %{ | |
| 2898 // Output Float immediate bits | |
| 2899 jfloat jf = $src$$constant; | |
| 2900 jint jf_as_bits = jint_cast(jf); | |
| 2901 emit_d32(cbuf, jf_as_bits); | |
| 2902 %} | |
| 2903 | |
| 2904 enc_class Con16(immI src) | |
| 2905 %{ | |
| 2906 // Output immediate | |
| 2907 $$$emit16$src$$constant; | |
| 2908 %} | |
| 2909 | |
| 2910 // How is this different from Con32??? XXX | |
| 2911 enc_class Con_d32(immI src) | |
| 2912 %{ | |
| 2913 emit_d32(cbuf,$src$$constant); | |
| 2914 %} | |
| 2915 | |
| 2916 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI) | |
| 2917 // Output immediate memory reference | |
| 2918 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); | |
| 2919 emit_d32(cbuf, 0x00); | |
| 2920 %} | |
| 2921 | |
| 2922 enc_class jump_enc(rRegL switch_val, rRegI dest) %{ | |
| 2923 MacroAssembler masm(&cbuf); | |
| 2924 | |
| 2925 Register switch_reg = as_Register($switch_val$$reg); | |
| 2926 Register dest_reg = as_Register($dest$$reg); | |
| 2927 address table_base = masm.address_table_constant(_index2label); | |
| 2928 | |
| 2929 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 2930 // to do that and the compiler is using that register as one it can allocate. | |
| 2931 // So we build it all by hand. | |
| 2932 // Address index(noreg, switch_reg, Address::times_1); | |
| 2933 // ArrayAddress dispatch(table, index); | |
| 2934 | |
| 2935 Address dispatch(dest_reg, switch_reg, Address::times_1); | |
| 2936 | |
| 2937 masm.lea(dest_reg, InternalAddress(table_base)); | |
| 2938 masm.jmp(dispatch); | |
| 2939 %} | |
| 2940 | |
| 2941 enc_class jump_enc_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 2942 MacroAssembler masm(&cbuf); | |
| 2943 | |
| 2944 Register switch_reg = as_Register($switch_val$$reg); | |
| 2945 Register dest_reg = as_Register($dest$$reg); | |
| 2946 address table_base = masm.address_table_constant(_index2label); | |
| 2947 | |
| 2948 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 2949 // to do that and the compiler is using that register as one it can allocate. | |
| 2950 // So we build it all by hand. | |
| 2951 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant); | |
| 2952 // ArrayAddress dispatch(table, index); | |
| 2953 | |
| 2954 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant, (int)$offset$$constant); | |
| 2955 | |
| 2956 masm.lea(dest_reg, InternalAddress(table_base)); | |
| 2957 masm.jmp(dispatch); | |
| 2958 %} | |
| 2959 | |
| 2960 enc_class jump_enc_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 2961 MacroAssembler masm(&cbuf); | |
| 2962 | |
| 2963 Register switch_reg = as_Register($switch_val$$reg); | |
| 2964 Register dest_reg = as_Register($dest$$reg); | |
| 2965 address table_base = masm.address_table_constant(_index2label); | |
| 2966 | |
| 2967 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10 | |
| 2968 // to do that and the compiler is using that register as one it can allocate. | |
| 2969 // So we build it all by hand. | |
| 2970 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 2971 // ArrayAddress dispatch(table, index); | |
| 2972 | |
| 2973 Address dispatch(dest_reg, switch_reg, (Address::ScaleFactor)$shift$$constant); | |
| 2974 masm.lea(dest_reg, InternalAddress(table_base)); | |
| 2975 masm.jmp(dispatch); | |
| 2976 | |
| 2977 %} | |
| 2978 | |
| 2979 enc_class lock_prefix() | |
| 2980 %{ | |
| 2981 if (os::is_MP()) { | |
| 2982 emit_opcode(cbuf, 0xF0); // lock | |
| 2983 } | |
| 2984 %} | |
| 2985 | |
| 2986 enc_class REX_mem(memory mem) | |
| 2987 %{ | |
| 2988 if ($mem$$base >= 8) { | |
| 2989 if ($mem$$index < 8) { | |
| 2990 emit_opcode(cbuf, Assembler::REX_B); | |
| 2991 } else { | |
| 2992 emit_opcode(cbuf, Assembler::REX_XB); | |
| 2993 } | |
| 2994 } else { | |
| 2995 if ($mem$$index >= 8) { | |
| 2996 emit_opcode(cbuf, Assembler::REX_X); | |
| 2997 } | |
| 2998 } | |
| 2999 %} | |
| 3000 | |
| 3001 enc_class REX_mem_wide(memory mem) | |
| 3002 %{ | |
| 3003 if ($mem$$base >= 8) { | |
| 3004 if ($mem$$index < 8) { | |
| 3005 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3006 } else { | |
| 3007 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 3008 } | |
| 3009 } else { | |
| 3010 if ($mem$$index < 8) { | |
| 3011 emit_opcode(cbuf, Assembler::REX_W); | |
| 3012 } else { | |
| 3013 emit_opcode(cbuf, Assembler::REX_WX); | |
| 3014 } | |
| 3015 } | |
| 3016 %} | |
| 3017 | |
| 3018 // for byte regs | |
| 3019 enc_class REX_breg(rRegI reg) | |
| 3020 %{ | |
| 3021 if ($reg$$reg >= 4) { | |
| 3022 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 3023 } | |
| 3024 %} | |
| 3025 | |
| 3026 // for byte regs | |
| 3027 enc_class REX_reg_breg(rRegI dst, rRegI src) | |
| 3028 %{ | |
| 3029 if ($dst$$reg < 8) { | |
| 3030 if ($src$$reg >= 4) { | |
| 3031 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B); | |
| 3032 } | |
| 3033 } else { | |
| 3034 if ($src$$reg < 8) { | |
| 3035 emit_opcode(cbuf, Assembler::REX_R); | |
| 3036 } else { | |
| 3037 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3038 } | |
| 3039 } | |
| 3040 %} | |
| 3041 | |
| 3042 // for byte regs | |
| 3043 enc_class REX_breg_mem(rRegI reg, memory mem) | |
| 3044 %{ | |
| 3045 if ($reg$$reg < 8) { | |
| 3046 if ($mem$$base < 8) { | |
| 3047 if ($mem$$index >= 8) { | |
| 3048 emit_opcode(cbuf, Assembler::REX_X); | |
| 3049 } else if ($reg$$reg >= 4) { | |
| 3050 emit_opcode(cbuf, Assembler::REX); | |
| 3051 } | |
| 3052 } else { | |
| 3053 if ($mem$$index < 8) { | |
| 3054 emit_opcode(cbuf, Assembler::REX_B); | |
| 3055 } else { | |
| 3056 emit_opcode(cbuf, Assembler::REX_XB); | |
| 3057 } | |
| 3058 } | |
| 3059 } else { | |
| 3060 if ($mem$$base < 8) { | |
| 3061 if ($mem$$index < 8) { | |
| 3062 emit_opcode(cbuf, Assembler::REX_R); | |
| 3063 } else { | |
| 3064 emit_opcode(cbuf, Assembler::REX_RX); | |
| 3065 } | |
| 3066 } else { | |
| 3067 if ($mem$$index < 8) { | |
| 3068 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3069 } else { | |
| 3070 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 3071 } | |
| 3072 } | |
| 3073 } | |
| 3074 %} | |
| 3075 | |
| 3076 enc_class REX_reg(rRegI reg) | |
| 3077 %{ | |
| 3078 if ($reg$$reg >= 8) { | |
| 3079 emit_opcode(cbuf, Assembler::REX_B); | |
| 3080 } | |
| 3081 %} | |
| 3082 | |
| 3083 enc_class REX_reg_wide(rRegI reg) | |
| 3084 %{ | |
| 3085 if ($reg$$reg < 8) { | |
| 3086 emit_opcode(cbuf, Assembler::REX_W); | |
| 3087 } else { | |
| 3088 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3089 } | |
| 3090 %} | |
| 3091 | |
| 3092 enc_class REX_reg_reg(rRegI dst, rRegI src) | |
| 3093 %{ | |
| 3094 if ($dst$$reg < 8) { | |
| 3095 if ($src$$reg >= 8) { | |
| 3096 emit_opcode(cbuf, Assembler::REX_B); | |
| 3097 } | |
| 3098 } else { | |
| 3099 if ($src$$reg < 8) { | |
| 3100 emit_opcode(cbuf, Assembler::REX_R); | |
| 3101 } else { | |
| 3102 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3103 } | |
| 3104 } | |
| 3105 %} | |
| 3106 | |
| 3107 enc_class REX_reg_reg_wide(rRegI dst, rRegI src) | |
| 3108 %{ | |
| 3109 if ($dst$$reg < 8) { | |
| 3110 if ($src$$reg < 8) { | |
| 3111 emit_opcode(cbuf, Assembler::REX_W); | |
| 3112 } else { | |
| 3113 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3114 } | |
| 3115 } else { | |
| 3116 if ($src$$reg < 8) { | |
| 3117 emit_opcode(cbuf, Assembler::REX_WR); | |
| 3118 } else { | |
| 3119 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 3120 } | |
| 3121 } | |
| 3122 %} | |
| 3123 | |
| 3124 enc_class REX_reg_mem(rRegI reg, memory mem) | |
| 3125 %{ | |
| 3126 if ($reg$$reg < 8) { | |
| 3127 if ($mem$$base < 8) { | |
| 3128 if ($mem$$index >= 8) { | |
| 3129 emit_opcode(cbuf, Assembler::REX_X); | |
| 3130 } | |
| 3131 } else { | |
| 3132 if ($mem$$index < 8) { | |
| 3133 emit_opcode(cbuf, Assembler::REX_B); | |
| 3134 } else { | |
| 3135 emit_opcode(cbuf, Assembler::REX_XB); | |
| 3136 } | |
| 3137 } | |
| 3138 } else { | |
| 3139 if ($mem$$base < 8) { | |
| 3140 if ($mem$$index < 8) { | |
| 3141 emit_opcode(cbuf, Assembler::REX_R); | |
| 3142 } else { | |
| 3143 emit_opcode(cbuf, Assembler::REX_RX); | |
| 3144 } | |
| 3145 } else { | |
| 3146 if ($mem$$index < 8) { | |
| 3147 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3148 } else { | |
| 3149 emit_opcode(cbuf, Assembler::REX_RXB); | |
| 3150 } | |
| 3151 } | |
| 3152 } | |
| 3153 %} | |
| 3154 | |
| 3155 enc_class REX_reg_mem_wide(rRegL reg, memory mem) | |
| 3156 %{ | |
| 3157 if ($reg$$reg < 8) { | |
| 3158 if ($mem$$base < 8) { | |
| 3159 if ($mem$$index < 8) { | |
| 3160 emit_opcode(cbuf, Assembler::REX_W); | |
| 3161 } else { | |
| 3162 emit_opcode(cbuf, Assembler::REX_WX); | |
| 3163 } | |
| 3164 } else { | |
| 3165 if ($mem$$index < 8) { | |
| 3166 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3167 } else { | |
| 3168 emit_opcode(cbuf, Assembler::REX_WXB); | |
| 3169 } | |
| 3170 } | |
| 3171 } else { | |
| 3172 if ($mem$$base < 8) { | |
| 3173 if ($mem$$index < 8) { | |
| 3174 emit_opcode(cbuf, Assembler::REX_WR); | |
| 3175 } else { | |
| 3176 emit_opcode(cbuf, Assembler::REX_WRX); | |
| 3177 } | |
| 3178 } else { | |
| 3179 if ($mem$$index < 8) { | |
| 3180 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 3181 } else { | |
| 3182 emit_opcode(cbuf, Assembler::REX_WRXB); | |
| 3183 } | |
| 3184 } | |
| 3185 } | |
| 3186 %} | |
| 3187 | |
| 3188 enc_class reg_mem(rRegI ereg, memory mem) | |
| 3189 %{ | |
| 3190 // High registers handle in encode_RegMem | |
| 3191 int reg = $ereg$$reg; | |
| 3192 int base = $mem$$base; | |
| 3193 int index = $mem$$index; | |
| 3194 int scale = $mem$$scale; | |
| 3195 int disp = $mem$$disp; | |
| 3196 bool disp_is_oop = $mem->disp_is_oop(); | |
| 3197 | |
| 3198 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_is_oop); | |
| 3199 %} | |
| 3200 | |
| 3201 enc_class RM_opc_mem(immI rm_opcode, memory mem) | |
| 3202 %{ | |
| 3203 int rm_byte_opcode = $rm_opcode$$constant; | |
| 3204 | |
| 3205 // High registers handle in encode_RegMem | |
| 3206 int base = $mem$$base; | |
| 3207 int index = $mem$$index; | |
| 3208 int scale = $mem$$scale; | |
| 3209 int displace = $mem$$disp; | |
| 3210 | |
| 3211 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when | |
| 3212 // working with static | |
| 3213 // globals | |
| 3214 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, | |
| 3215 disp_is_oop); | |
| 3216 %} | |
| 3217 | |
| 3218 enc_class reg_lea(rRegI dst, rRegI src0, immI src1) | |
| 3219 %{ | |
| 3220 int reg_encoding = $dst$$reg; | |
| 3221 int base = $src0$$reg; // 0xFFFFFFFF indicates no base | |
| 3222 int index = 0x04; // 0x04 indicates no index | |
| 3223 int scale = 0x00; // 0x00 indicates no scale | |
| 3224 int displace = $src1$$constant; // 0x00 indicates no displacement | |
| 3225 bool disp_is_oop = false; | |
| 3226 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, | |
| 3227 disp_is_oop); | |
| 3228 %} | |
| 3229 | |
| 3230 enc_class neg_reg(rRegI dst) | |
| 3231 %{ | |
| 3232 int dstenc = $dst$$reg; | |
| 3233 if (dstenc >= 8) { | |
| 3234 emit_opcode(cbuf, Assembler::REX_B); | |
| 3235 dstenc -= 8; | |
| 3236 } | |
| 3237 // NEG $dst | |
| 3238 emit_opcode(cbuf, 0xF7); | |
| 3239 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 3240 %} | |
| 3241 | |
| 3242 enc_class neg_reg_wide(rRegI dst) | |
| 3243 %{ | |
| 3244 int dstenc = $dst$$reg; | |
| 3245 if (dstenc < 8) { | |
| 3246 emit_opcode(cbuf, Assembler::REX_W); | |
| 3247 } else { | |
| 3248 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3249 dstenc -= 8; | |
| 3250 } | |
| 3251 // NEG $dst | |
| 3252 emit_opcode(cbuf, 0xF7); | |
| 3253 emit_rm(cbuf, 0x3, 0x03, dstenc); | |
| 3254 %} | |
| 3255 | |
| 3256 enc_class setLT_reg(rRegI dst) | |
| 3257 %{ | |
| 3258 int dstenc = $dst$$reg; | |
| 3259 if (dstenc >= 8) { | |
| 3260 emit_opcode(cbuf, Assembler::REX_B); | |
| 3261 dstenc -= 8; | |
| 3262 } else if (dstenc >= 4) { | |
| 3263 emit_opcode(cbuf, Assembler::REX); | |
| 3264 } | |
| 3265 // SETLT $dst | |
| 3266 emit_opcode(cbuf, 0x0F); | |
| 3267 emit_opcode(cbuf, 0x9C); | |
| 3268 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 3269 %} | |
| 3270 | |
| 3271 enc_class setNZ_reg(rRegI dst) | |
| 3272 %{ | |
| 3273 int dstenc = $dst$$reg; | |
| 3274 if (dstenc >= 8) { | |
| 3275 emit_opcode(cbuf, Assembler::REX_B); | |
| 3276 dstenc -= 8; | |
| 3277 } else if (dstenc >= 4) { | |
| 3278 emit_opcode(cbuf, Assembler::REX); | |
| 3279 } | |
| 3280 // SETNZ $dst | |
| 3281 emit_opcode(cbuf, 0x0F); | |
| 3282 emit_opcode(cbuf, 0x95); | |
| 3283 emit_rm(cbuf, 0x3, 0x0, dstenc); | |
| 3284 %} | |
| 3285 | |
| 3286 enc_class enc_cmpLTP(no_rcx_RegI p, no_rcx_RegI q, no_rcx_RegI y, | |
| 3287 rcx_RegI tmp) | |
| 3288 %{ | |
| 3289 // cadd_cmpLT | |
| 3290 | |
| 3291 int tmpReg = $tmp$$reg; | |
| 3292 | |
| 3293 int penc = $p$$reg; | |
| 3294 int qenc = $q$$reg; | |
| 3295 int yenc = $y$$reg; | |
| 3296 | |
| 3297 // subl $p,$q | |
| 3298 if (penc < 8) { | |
| 3299 if (qenc >= 8) { | |
| 3300 emit_opcode(cbuf, Assembler::REX_B); | |
| 3301 } | |
| 3302 } else { | |
| 3303 if (qenc < 8) { | |
| 3304 emit_opcode(cbuf, Assembler::REX_R); | |
| 3305 } else { | |
| 3306 emit_opcode(cbuf, Assembler::REX_RB); | |
| 3307 } | |
| 3308 } | |
| 3309 emit_opcode(cbuf, 0x2B); | |
| 3310 emit_rm(cbuf, 0x3, penc & 7, qenc & 7); | |
| 3311 | |
| 3312 // sbbl $tmp, $tmp | |
| 3313 emit_opcode(cbuf, 0x1B); | |
| 3314 emit_rm(cbuf, 0x3, tmpReg, tmpReg); | |
| 3315 | |
| 3316 // andl $tmp, $y | |
| 3317 if (yenc >= 8) { | |
| 3318 emit_opcode(cbuf, Assembler::REX_B); | |
| 3319 } | |
| 3320 emit_opcode(cbuf, 0x23); | |
| 3321 emit_rm(cbuf, 0x3, tmpReg, yenc & 7); | |
| 3322 | |
| 3323 // addl $p,$tmp | |
| 3324 if (penc >= 8) { | |
| 3325 emit_opcode(cbuf, Assembler::REX_R); | |
| 3326 } | |
| 3327 emit_opcode(cbuf, 0x03); | |
| 3328 emit_rm(cbuf, 0x3, penc & 7, tmpReg); | |
| 3329 %} | |
| 3330 | |
| 3331 // Compare the lonogs and set -1, 0, or 1 into dst | |
| 3332 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst) | |
| 3333 %{ | |
| 3334 int src1enc = $src1$$reg; | |
| 3335 int src2enc = $src2$$reg; | |
| 3336 int dstenc = $dst$$reg; | |
| 3337 | |
| 3338 // cmpq $src1, $src2 | |
| 3339 if (src1enc < 8) { | |
| 3340 if (src2enc < 8) { | |
| 3341 emit_opcode(cbuf, Assembler::REX_W); | |
| 3342 } else { | |
| 3343 emit_opcode(cbuf, Assembler::REX_WB); | |
| 3344 } | |
| 3345 } else { | |
| 3346 if (src2enc < 8) { | |
| 3347 emit_opcode(cbuf, Assembler::REX_WR); | |
| 3348 } else { | |
| 3349 emit_opcode(cbuf, Assembler::REX_WRB); | |
| 3350 } | |
| 3351 } | |
| 3352 emit_opcode(cbuf, 0x3B); | |
| 3353 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7); | |
| 3354 | |
| 3355 // movl $dst, -1 | |
| 3356 if (dstenc >= 8) { | |
| 3357 emit_opcode(cbuf, Assembler::REX_B); | |
| 3358 } | |
| 3359 emit_opcode(cbuf, 0xB8 | (dstenc & 7)); | |
| 3360 emit_d32(cbuf, -1); | |
| 3361 | |
| 3362 // jl,s done | |
| 3363 emit_opcode(cbuf, 0x7C); | |
| 3364 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08); | |
| 3365 | |
| 3366 // setne $dst | |
| 3367 if (dstenc >= 4) { | |
| 3368 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B); | |
| 3369 } | |
| 3370 emit_opcode(cbuf, 0x0F); | |
| 3371 emit_opcode(cbuf, 0x95); | |
| 3372 emit_opcode(cbuf, 0xC0 | (dstenc & 7)); | |
| 3373 | |
| 3374 // movzbl $dst, $dst | |
| 3375 if (dstenc >= 4) { | |
| 3376 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB); | |
| 3377 } | |
| 3378 emit_opcode(cbuf, 0x0F); | |
| 3379 emit_opcode(cbuf, 0xB6); | |
| 3380 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7); | |
| 3381 %} | |
| 3382 | |
| 3383 enc_class Push_ResultXD(regD dst) %{ | |
| 3384 int dstenc = $dst$$reg; | |
| 3385 | |
| 3386 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [RSP] | |
| 3387 | |
| 3388 // UseXmmLoadAndClearUpper ? movsd dst,[rsp] : movlpd dst,[rsp] | |
| 3389 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); | |
| 3390 if (dstenc >= 8) { | |
| 3391 emit_opcode(cbuf, Assembler::REX_R); | |
| 3392 } | |
| 3393 emit_opcode (cbuf, 0x0F ); | |
| 3394 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12 ); | |
| 3395 encode_RegMem(cbuf, dstenc, RSP_enc, 0x4, 0, 0, false); | |
| 3396 | |
| 3397 // add rsp,8 | |
| 3398 emit_opcode(cbuf, Assembler::REX_W); | |
| 3399 emit_opcode(cbuf,0x83); | |
| 3400 emit_rm(cbuf,0x3, 0x0, RSP_enc); | |
| 3401 emit_d8(cbuf,0x08); | |
| 3402 %} | |
| 3403 | |
| 3404 enc_class Push_SrcXD(regD src) %{ | |
| 3405 int srcenc = $src$$reg; | |
| 3406 | |
| 3407 // subq rsp,#8 | |
| 3408 emit_opcode(cbuf, Assembler::REX_W); | |
| 3409 emit_opcode(cbuf, 0x83); | |
| 3410 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3411 emit_d8(cbuf, 0x8); | |
| 3412 | |
| 3413 // movsd [rsp],src | |
| 3414 emit_opcode(cbuf, 0xF2); | |
| 3415 if (srcenc >= 8) { | |
| 3416 emit_opcode(cbuf, Assembler::REX_R); | |
| 3417 } | |
| 3418 emit_opcode(cbuf, 0x0F); | |
| 3419 emit_opcode(cbuf, 0x11); | |
| 3420 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); | |
| 3421 | |
| 3422 // fldd [rsp] | |
| 3423 emit_opcode(cbuf, 0x66); | |
| 3424 emit_opcode(cbuf, 0xDD); | |
| 3425 encode_RegMem(cbuf, 0x0, RSP_enc, 0x4, 0, 0, false); | |
| 3426 %} | |
| 3427 | |
| 3428 | |
| 3429 enc_class movq_ld(regD dst, memory mem) %{ | |
| 3430 MacroAssembler _masm(&cbuf); | |
| 624 | 3431 __ movq($dst$$XMMRegister, $mem$$Address); |
| 0 | 3432 %} |
| 3433 | |
| 3434 enc_class movq_st(memory mem, regD src) %{ | |
| 3435 MacroAssembler _masm(&cbuf); | |
| 624 | 3436 __ movq($mem$$Address, $src$$XMMRegister); |
| 0 | 3437 %} |
| 3438 | |
| 3439 enc_class pshufd_8x8(regF dst, regF src) %{ | |
| 3440 MacroAssembler _masm(&cbuf); | |
| 3441 | |
| 3442 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); | |
| 3443 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); | |
| 3444 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); | |
| 3445 %} | |
| 3446 | |
| 3447 enc_class pshufd_4x16(regF dst, regF src) %{ | |
| 3448 MacroAssembler _masm(&cbuf); | |
| 3449 | |
| 3450 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); | |
| 3451 %} | |
| 3452 | |
| 3453 enc_class pshufd(regD dst, regD src, int mode) %{ | |
| 3454 MacroAssembler _masm(&cbuf); | |
| 3455 | |
| 3456 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); | |
| 3457 %} | |
| 3458 | |
| 3459 enc_class pxor(regD dst, regD src) %{ | |
| 3460 MacroAssembler _masm(&cbuf); | |
| 3461 | |
| 3462 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); | |
| 3463 %} | |
| 3464 | |
| 3465 enc_class mov_i2x(regD dst, rRegI src) %{ | |
| 3466 MacroAssembler _masm(&cbuf); | |
| 3467 | |
| 3468 __ movdl(as_XMMRegister($dst$$reg), as_Register($src$$reg)); | |
| 3469 %} | |
| 3470 | |
| 3471 // obj: object to lock | |
| 3472 // box: box address (header location) -- killed | |
| 3473 // tmp: rax -- killed | |
| 3474 // scr: rbx -- killed | |
| 3475 // | |
| 3476 // What follows is a direct transliteration of fast_lock() and fast_unlock() | |
| 3477 // from i486.ad. See that file for comments. | |
| 3478 // TODO: where possible switch from movq (r, 0) to movl(r,0) and | |
| 3479 // use the shorter encoding. (Movl clears the high-order 32-bits). | |
| 3480 | |
| 3481 | |
| 3482 enc_class Fast_Lock(rRegP obj, rRegP box, rax_RegI tmp, rRegP scr) | |
| 3483 %{ | |
| 3484 Register objReg = as_Register((int)$obj$$reg); | |
| 3485 Register boxReg = as_Register((int)$box$$reg); | |
| 3486 Register tmpReg = as_Register($tmp$$reg); | |
| 3487 Register scrReg = as_Register($scr$$reg); | |
| 3488 MacroAssembler masm(&cbuf); | |
| 3489 | |
| 3490 // Verify uniqueness of register assignments -- necessary but not sufficient | |
| 3491 assert (objReg != boxReg && objReg != tmpReg && | |
| 3492 objReg != scrReg && tmpReg != scrReg, "invariant") ; | |
| 3493 | |
| 3494 if (_counters != NULL) { | |
| 3495 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); | |
| 3496 } | |
| 3497 if (EmitSync & 1) { | |
| 304 | 3498 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
| 3499 masm.movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; | |
| 3500 masm.cmpptr(rsp, (int32_t)NULL_WORD) ; | |
| 0 | 3501 } else |
| 3502 if (EmitSync & 2) { | |
| 3503 Label DONE_LABEL; | |
| 3504 if (UseBiasedLocking) { | |
| 3505 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. | |
| 3506 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); | |
| 3507 } | |
| 304 | 3508 // QQQ was movl... |
| 3509 masm.movptr(tmpReg, 0x1); | |
| 3510 masm.orptr(tmpReg, Address(objReg, 0)); | |
| 3511 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3512 if (os::is_MP()) { |
| 3513 masm.lock(); | |
| 3514 } | |
| 304 | 3515 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg |
| 0 | 3516 masm.jcc(Assembler::equal, DONE_LABEL); |
| 3517 | |
| 3518 // Recursive locking | |
| 304 | 3519 masm.subptr(tmpReg, rsp); |
| 3520 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 3521 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3522 |
| 3523 masm.bind(DONE_LABEL); | |
| 3524 masm.nop(); // avoid branch to branch | |
| 3525 } else { | |
| 3526 Label DONE_LABEL, IsInflated, Egress; | |
| 3527 | |
| 304 | 3528 masm.movptr(tmpReg, Address(objReg, 0)) ; |
| 3529 masm.testl (tmpReg, 0x02) ; // inflated vs stack-locked|neutral|biased | |
| 3530 masm.jcc (Assembler::notZero, IsInflated) ; | |
| 3531 | |
| 0 | 3532 // it's stack-locked, biased or neutral |
| 3533 // TODO: optimize markword triage order to reduce the number of | |
| 3534 // conditional branches in the most common cases. | |
| 3535 // Beware -- there's a subtle invariant that fetch of the markword | |
| 3536 // at [FETCH], below, will never observe a biased encoding (*101b). | |
| 3537 // If this invariant is not held we'll suffer exclusion (safety) failure. | |
| 3538 | |
|
420
a1980da045cc
6462850: generate biased locking code in C2 ideal graph
kvn
parents:
415
diff
changeset
|
3539 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3540 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, true, DONE_LABEL, NULL, _counters); |
| 304 | 3541 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] |
| 0 | 3542 } |
| 3543 | |
| 304 | 3544 // was q will it destroy high? |
| 3545 masm.orl (tmpReg, 1) ; | |
| 3546 masm.movptr(Address(boxReg, 0), tmpReg) ; | |
| 3547 if (os::is_MP()) { masm.lock(); } | |
| 3548 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg | |
| 0 | 3549 if (_counters != NULL) { |
| 3550 masm.cond_inc32(Assembler::equal, | |
| 3551 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 3552 } | |
| 3553 masm.jcc (Assembler::equal, DONE_LABEL); | |
| 3554 | |
| 3555 // Recursive locking | |
| 304 | 3556 masm.subptr(tmpReg, rsp); |
| 3557 masm.andptr(tmpReg, 7 - os::vm_page_size()); | |
| 3558 masm.movptr(Address(boxReg, 0), tmpReg); | |
| 0 | 3559 if (_counters != NULL) { |
| 3560 masm.cond_inc32(Assembler::equal, | |
| 3561 ExternalAddress((address) _counters->fast_path_entry_count_addr())); | |
| 3562 } | |
| 3563 masm.jmp (DONE_LABEL) ; | |
| 3564 | |
| 3565 masm.bind (IsInflated) ; | |
| 3566 // It's inflated | |
| 3567 | |
| 3568 // TODO: someday avoid the ST-before-CAS penalty by | |
| 3569 // relocating (deferring) the following ST. | |
| 3570 // We should also think about trying a CAS without having | |
| 3571 // fetched _owner. If the CAS is successful we may | |
| 3572 // avoid an RTO->RTS upgrade on the $line. | |
| 304 | 3573 // Without cast to int32_t a movptr will destroy r10 which is typically obj |
| 3574 masm.movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())) ; | |
| 3575 | |
| 3576 masm.mov (boxReg, tmpReg) ; | |
| 3577 masm.movptr (tmpReg, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 3578 masm.testptr(tmpReg, tmpReg) ; | |
| 3579 masm.jcc (Assembler::notZero, DONE_LABEL) ; | |
| 0 | 3580 |
| 3581 // It's inflated and appears unlocked | |
| 304 | 3582 if (os::is_MP()) { masm.lock(); } |
| 3583 masm.cmpxchgptr(r15_thread, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; | |
| 0 | 3584 // Intentional fall-through into DONE_LABEL ... |
| 3585 | |
| 3586 masm.bind (DONE_LABEL) ; | |
| 3587 masm.nop () ; // avoid jmp to jmp | |
| 3588 } | |
| 3589 %} | |
| 3590 | |
| 3591 // obj: object to unlock | |
| 3592 // box: box address (displaced header location), killed | |
| 3593 // RBX: killed tmp; cannot be obj nor box | |
| 3594 enc_class Fast_Unlock(rRegP obj, rax_RegP box, rRegP tmp) | |
| 3595 %{ | |
| 3596 | |
| 3597 Register objReg = as_Register($obj$$reg); | |
| 3598 Register boxReg = as_Register($box$$reg); | |
| 3599 Register tmpReg = as_Register($tmp$$reg); | |
| 3600 MacroAssembler masm(&cbuf); | |
| 3601 | |
| 304 | 3602 if (EmitSync & 4) { |
| 3603 masm.cmpptr(rsp, 0) ; | |
| 0 | 3604 } else |
| 3605 if (EmitSync & 8) { | |
| 3606 Label DONE_LABEL; | |
| 3607 if (UseBiasedLocking) { | |
| 3608 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); | |
| 3609 } | |
| 3610 | |
| 3611 // Check whether the displaced header is 0 | |
| 3612 //(=> recursive unlock) | |
| 304 | 3613 masm.movptr(tmpReg, Address(boxReg, 0)); |
| 3614 masm.testptr(tmpReg, tmpReg); | |
| 0 | 3615 masm.jcc(Assembler::zero, DONE_LABEL); |
| 3616 | |
| 3617 // If not recursive lock, reset the header to displaced header | |
| 3618 if (os::is_MP()) { | |
| 3619 masm.lock(); | |
| 3620 } | |
| 304 | 3621 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box |
| 0 | 3622 masm.bind(DONE_LABEL); |
| 3623 masm.nop(); // avoid branch to branch | |
| 3624 } else { | |
| 3625 Label DONE_LABEL, Stacked, CheckSucc ; | |
| 3626 | |
|
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diff
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|
3627 if (UseBiasedLocking && !UseOptoBiasInlining) { |
| 0 | 3628 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); |
| 3629 } | |
| 304 | 3630 |
| 3631 masm.movptr(tmpReg, Address(objReg, 0)) ; | |
| 3632 masm.cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD) ; | |
| 3633 masm.jcc (Assembler::zero, DONE_LABEL) ; | |
| 3634 masm.testl (tmpReg, 0x02) ; | |
| 3635 masm.jcc (Assembler::zero, Stacked) ; | |
| 3636 | |
| 0 | 3637 // It's inflated |
| 304 | 3638 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; |
| 3639 masm.xorptr(boxReg, r15_thread) ; | |
| 3640 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; | |
| 3641 masm.jcc (Assembler::notZero, DONE_LABEL) ; | |
| 3642 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; | |
| 3643 masm.orptr (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; | |
| 3644 masm.jcc (Assembler::notZero, CheckSucc) ; | |
| 3645 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; | |
| 3646 masm.jmp (DONE_LABEL) ; | |
| 3647 | |
| 3648 if ((EmitSync & 65536) == 0) { | |
| 0 | 3649 Label LSuccess, LGoSlowPath ; |
| 3650 masm.bind (CheckSucc) ; | |
| 304 | 3651 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3652 masm.jcc (Assembler::zero, LGoSlowPath) ; |
| 3653 | |
| 3654 // I'd much rather use lock:andl m->_owner, 0 as it's faster than the | |
| 3655 // the explicit ST;MEMBAR combination, but masm doesn't currently support | |
| 3656 // "ANDQ M,IMM". Don't use MFENCE here. lock:add to TOS, xchg, etc | |
| 3657 // are all faster when the write buffer is populated. | |
| 304 | 3658 masm.movptr (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3659 if (os::is_MP()) { |
| 304 | 3660 masm.lock () ; masm.addl (Address(rsp, 0), 0) ; |
| 0 | 3661 } |
| 304 | 3662 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), (int32_t)NULL_WORD) ; |
| 0 | 3663 masm.jcc (Assembler::notZero, LSuccess) ; |
| 3664 | |
| 304 | 3665 masm.movptr (boxReg, (int32_t)NULL_WORD) ; // box is really EAX |
| 0 | 3666 if (os::is_MP()) { masm.lock(); } |
| 304 | 3667 masm.cmpxchgptr(r15_thread, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); |
| 0 | 3668 masm.jcc (Assembler::notEqual, LSuccess) ; |
| 3669 // Intentional fall-through into slow-path | |
| 3670 | |
| 3671 masm.bind (LGoSlowPath) ; | |
| 3672 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure | |
| 3673 masm.jmp (DONE_LABEL) ; | |
| 3674 | |
| 3675 masm.bind (LSuccess) ; | |
| 3676 masm.testl (boxReg, 0) ; // set ICC.ZF=1 to indicate success | |
| 3677 masm.jmp (DONE_LABEL) ; | |
| 3678 } | |
| 3679 | |
| 304 | 3680 masm.bind (Stacked) ; |
| 3681 masm.movptr(tmpReg, Address (boxReg, 0)) ; // re-fetch | |
| 3682 if (os::is_MP()) { masm.lock(); } | |
| 3683 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box | |
| 0 | 3684 |
| 3685 if (EmitSync & 65536) { | |
| 3686 masm.bind (CheckSucc) ; | |
| 3687 } | |
| 3688 masm.bind(DONE_LABEL); | |
| 3689 if (EmitSync & 32768) { | |
| 3690 masm.nop(); // avoid branch to branch | |
| 3691 } | |
| 3692 } | |
| 3693 %} | |
| 3694 | |
|
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168
diff
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|
3695 |
| 0 | 3696 enc_class enc_rethrow() |
| 3697 %{ | |
| 1748 | 3698 cbuf.set_insts_mark(); |
| 0 | 3699 emit_opcode(cbuf, 0xE9); // jmp entry |
| 3700 emit_d32_reloc(cbuf, | |
| 1748 | 3701 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4), |
| 0 | 3702 runtime_call_Relocation::spec(), |
| 3703 RELOC_DISP32); | |
| 3704 %} | |
| 3705 | |
| 3706 enc_class absF_encoding(regF dst) | |
| 3707 %{ | |
| 3708 int dstenc = $dst$$reg; | |
| 304 | 3709 address signmask_address = (address) StubRoutines::x86::float_sign_mask(); |
| 0 | 3710 |
| 1748 | 3711 cbuf.set_insts_mark(); |
| 0 | 3712 if (dstenc >= 8) { |
| 3713 emit_opcode(cbuf, Assembler::REX_R); | |
| 3714 dstenc -= 8; | |
| 3715 } | |
| 3716 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3717 emit_opcode(cbuf, 0x0F); | |
| 3718 emit_opcode(cbuf, 0x54); | |
| 3719 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3720 emit_d32_reloc(cbuf, signmask_address); | |
| 3721 %} | |
| 3722 | |
| 3723 enc_class absD_encoding(regD dst) | |
| 3724 %{ | |
| 3725 int dstenc = $dst$$reg; | |
| 304 | 3726 address signmask_address = (address) StubRoutines::x86::double_sign_mask(); |
| 0 | 3727 |
| 1748 | 3728 cbuf.set_insts_mark(); |
| 0 | 3729 emit_opcode(cbuf, 0x66); |
| 3730 if (dstenc >= 8) { | |
| 3731 emit_opcode(cbuf, Assembler::REX_R); | |
| 3732 dstenc -= 8; | |
| 3733 } | |
| 3734 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3735 emit_opcode(cbuf, 0x0F); | |
| 3736 emit_opcode(cbuf, 0x54); | |
| 3737 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3738 emit_d32_reloc(cbuf, signmask_address); | |
| 3739 %} | |
| 3740 | |
| 3741 enc_class negF_encoding(regF dst) | |
| 3742 %{ | |
| 3743 int dstenc = $dst$$reg; | |
| 304 | 3744 address signflip_address = (address) StubRoutines::x86::float_sign_flip(); |
| 0 | 3745 |
| 1748 | 3746 cbuf.set_insts_mark(); |
| 0 | 3747 if (dstenc >= 8) { |
| 3748 emit_opcode(cbuf, Assembler::REX_R); | |
| 3749 dstenc -= 8; | |
| 3750 } | |
| 3751 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3752 emit_opcode(cbuf, 0x0F); | |
| 3753 emit_opcode(cbuf, 0x57); | |
| 3754 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3755 emit_d32_reloc(cbuf, signflip_address); | |
| 3756 %} | |
| 3757 | |
| 3758 enc_class negD_encoding(regD dst) | |
| 3759 %{ | |
| 3760 int dstenc = $dst$$reg; | |
| 304 | 3761 address signflip_address = (address) StubRoutines::x86::double_sign_flip(); |
| 0 | 3762 |
| 1748 | 3763 cbuf.set_insts_mark(); |
| 0 | 3764 emit_opcode(cbuf, 0x66); |
| 3765 if (dstenc >= 8) { | |
| 3766 emit_opcode(cbuf, Assembler::REX_R); | |
| 3767 dstenc -= 8; | |
| 3768 } | |
| 3769 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3770 emit_opcode(cbuf, 0x0F); | |
| 3771 emit_opcode(cbuf, 0x57); | |
| 3772 emit_rm(cbuf, 0x0, dstenc, 0x5); // 00 reg 101 | |
| 3773 emit_d32_reloc(cbuf, signflip_address); | |
| 3774 %} | |
| 3775 | |
| 3776 enc_class f2i_fixup(rRegI dst, regF src) | |
| 3777 %{ | |
| 3778 int dstenc = $dst$$reg; | |
| 3779 int srcenc = $src$$reg; | |
| 3780 | |
| 3781 // cmpl $dst, #0x80000000 | |
| 3782 if (dstenc >= 8) { | |
| 3783 emit_opcode(cbuf, Assembler::REX_B); | |
| 3784 } | |
| 3785 emit_opcode(cbuf, 0x81); | |
| 3786 emit_rm(cbuf, 0x3, 0x7, dstenc & 7); | |
| 3787 emit_d32(cbuf, 0x80000000); | |
| 3788 | |
| 3789 // jne,s done | |
| 3790 emit_opcode(cbuf, 0x75); | |
| 3791 if (srcenc < 8 && dstenc < 8) { | |
| 3792 emit_d8(cbuf, 0xF); | |
| 3793 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 3794 emit_d8(cbuf, 0x11); | |
| 3795 } else { | |
| 3796 emit_d8(cbuf, 0x10); | |
| 3797 } | |
| 3798 | |
| 3799 // subq rsp, #8 | |
| 3800 emit_opcode(cbuf, Assembler::REX_W); | |
| 3801 emit_opcode(cbuf, 0x83); | |
| 3802 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3803 emit_d8(cbuf, 8); | |
| 3804 | |
| 3805 // movss [rsp], $src | |
| 3806 emit_opcode(cbuf, 0xF3); | |
| 3807 if (srcenc >= 8) { | |
| 3808 emit_opcode(cbuf, Assembler::REX_R); | |
| 3809 } | |
| 3810 emit_opcode(cbuf, 0x0F); | |
| 3811 emit_opcode(cbuf, 0x11); | |
| 3812 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 3813 | |
| 3814 // call f2i_fixup | |
| 1748 | 3815 cbuf.set_insts_mark(); |
| 0 | 3816 emit_opcode(cbuf, 0xE8); |
| 3817 emit_d32_reloc(cbuf, | |
| 3818 (int) | |
| 1748 | 3819 (StubRoutines::x86::f2i_fixup() - cbuf.insts_end() - 4), |
| 0 | 3820 runtime_call_Relocation::spec(), |
| 3821 RELOC_DISP32); | |
| 3822 | |
| 3823 // popq $dst | |
| 3824 if (dstenc >= 8) { | |
| 3825 emit_opcode(cbuf, Assembler::REX_B); | |
| 3826 } | |
| 3827 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 3828 | |
| 3829 // done: | |
| 3830 %} | |
| 3831 | |
| 3832 enc_class f2l_fixup(rRegL dst, regF src) | |
| 3833 %{ | |
| 3834 int dstenc = $dst$$reg; | |
| 3835 int srcenc = $src$$reg; | |
| 304 | 3836 address const_address = (address) StubRoutines::x86::double_sign_flip(); |
| 0 | 3837 |
| 3838 // cmpq $dst, [0x8000000000000000] | |
| 1748 | 3839 cbuf.set_insts_mark(); |
| 0 | 3840 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR); |
| 3841 emit_opcode(cbuf, 0x39); | |
| 3842 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3843 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101 | |
| 3844 emit_d32_reloc(cbuf, const_address); | |
| 3845 | |
| 3846 | |
| 3847 // jne,s done | |
| 3848 emit_opcode(cbuf, 0x75); | |
| 3849 if (srcenc < 8 && dstenc < 8) { | |
| 3850 emit_d8(cbuf, 0xF); | |
| 3851 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 3852 emit_d8(cbuf, 0x11); | |
| 3853 } else { | |
| 3854 emit_d8(cbuf, 0x10); | |
| 3855 } | |
| 3856 | |
| 3857 // subq rsp, #8 | |
| 3858 emit_opcode(cbuf, Assembler::REX_W); | |
| 3859 emit_opcode(cbuf, 0x83); | |
| 3860 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3861 emit_d8(cbuf, 8); | |
| 3862 | |
| 3863 // movss [rsp], $src | |
| 3864 emit_opcode(cbuf, 0xF3); | |
| 3865 if (srcenc >= 8) { | |
| 3866 emit_opcode(cbuf, Assembler::REX_R); | |
| 3867 } | |
| 3868 emit_opcode(cbuf, 0x0F); | |
| 3869 emit_opcode(cbuf, 0x11); | |
| 3870 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 3871 | |
| 3872 // call f2l_fixup | |
| 1748 | 3873 cbuf.set_insts_mark(); |
| 0 | 3874 emit_opcode(cbuf, 0xE8); |
| 3875 emit_d32_reloc(cbuf, | |
| 3876 (int) | |
| 1748 | 3877 (StubRoutines::x86::f2l_fixup() - cbuf.insts_end() - 4), |
| 0 | 3878 runtime_call_Relocation::spec(), |
| 3879 RELOC_DISP32); | |
| 3880 | |
| 3881 // popq $dst | |
| 3882 if (dstenc >= 8) { | |
| 3883 emit_opcode(cbuf, Assembler::REX_B); | |
| 3884 } | |
| 3885 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 3886 | |
| 3887 // done: | |
| 3888 %} | |
| 3889 | |
| 3890 enc_class d2i_fixup(rRegI dst, regD src) | |
| 3891 %{ | |
| 3892 int dstenc = $dst$$reg; | |
| 3893 int srcenc = $src$$reg; | |
| 3894 | |
| 3895 // cmpl $dst, #0x80000000 | |
| 3896 if (dstenc >= 8) { | |
| 3897 emit_opcode(cbuf, Assembler::REX_B); | |
| 3898 } | |
| 3899 emit_opcode(cbuf, 0x81); | |
| 3900 emit_rm(cbuf, 0x3, 0x7, dstenc & 7); | |
| 3901 emit_d32(cbuf, 0x80000000); | |
| 3902 | |
| 3903 // jne,s done | |
| 3904 emit_opcode(cbuf, 0x75); | |
| 3905 if (srcenc < 8 && dstenc < 8) { | |
| 3906 emit_d8(cbuf, 0xF); | |
| 3907 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 3908 emit_d8(cbuf, 0x11); | |
| 3909 } else { | |
| 3910 emit_d8(cbuf, 0x10); | |
| 3911 } | |
| 3912 | |
| 3913 // subq rsp, #8 | |
| 3914 emit_opcode(cbuf, Assembler::REX_W); | |
| 3915 emit_opcode(cbuf, 0x83); | |
| 3916 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3917 emit_d8(cbuf, 8); | |
| 3918 | |
| 3919 // movsd [rsp], $src | |
| 3920 emit_opcode(cbuf, 0xF2); | |
| 3921 if (srcenc >= 8) { | |
| 3922 emit_opcode(cbuf, Assembler::REX_R); | |
| 3923 } | |
| 3924 emit_opcode(cbuf, 0x0F); | |
| 3925 emit_opcode(cbuf, 0x11); | |
| 3926 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 3927 | |
| 3928 // call d2i_fixup | |
| 1748 | 3929 cbuf.set_insts_mark(); |
| 0 | 3930 emit_opcode(cbuf, 0xE8); |
| 3931 emit_d32_reloc(cbuf, | |
| 3932 (int) | |
| 1748 | 3933 (StubRoutines::x86::d2i_fixup() - cbuf.insts_end() - 4), |
| 0 | 3934 runtime_call_Relocation::spec(), |
| 3935 RELOC_DISP32); | |
| 3936 | |
| 3937 // popq $dst | |
| 3938 if (dstenc >= 8) { | |
| 3939 emit_opcode(cbuf, Assembler::REX_B); | |
| 3940 } | |
| 3941 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 3942 | |
| 3943 // done: | |
| 3944 %} | |
| 3945 | |
| 3946 enc_class d2l_fixup(rRegL dst, regD src) | |
| 3947 %{ | |
| 3948 int dstenc = $dst$$reg; | |
| 3949 int srcenc = $src$$reg; | |
| 304 | 3950 address const_address = (address) StubRoutines::x86::double_sign_flip(); |
| 0 | 3951 |
| 3952 // cmpq $dst, [0x8000000000000000] | |
| 1748 | 3953 cbuf.set_insts_mark(); |
| 0 | 3954 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX_W : Assembler::REX_WR); |
| 3955 emit_opcode(cbuf, 0x39); | |
| 3956 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 3957 emit_rm(cbuf, 0x0, dstenc & 7, 0x5); // 00 reg 101 | |
| 3958 emit_d32_reloc(cbuf, const_address); | |
| 3959 | |
| 3960 | |
| 3961 // jne,s done | |
| 3962 emit_opcode(cbuf, 0x75); | |
| 3963 if (srcenc < 8 && dstenc < 8) { | |
| 3964 emit_d8(cbuf, 0xF); | |
| 3965 } else if (srcenc >= 8 && dstenc >= 8) { | |
| 3966 emit_d8(cbuf, 0x11); | |
| 3967 } else { | |
| 3968 emit_d8(cbuf, 0x10); | |
| 3969 } | |
| 3970 | |
| 3971 // subq rsp, #8 | |
| 3972 emit_opcode(cbuf, Assembler::REX_W); | |
| 3973 emit_opcode(cbuf, 0x83); | |
| 3974 emit_rm(cbuf, 0x3, 0x5, RSP_enc); | |
| 3975 emit_d8(cbuf, 8); | |
| 3976 | |
| 3977 // movsd [rsp], $src | |
| 3978 emit_opcode(cbuf, 0xF2); | |
| 3979 if (srcenc >= 8) { | |
| 3980 emit_opcode(cbuf, Assembler::REX_R); | |
| 3981 } | |
| 3982 emit_opcode(cbuf, 0x0F); | |
| 3983 emit_opcode(cbuf, 0x11); | |
| 3984 encode_RegMem(cbuf, srcenc, RSP_enc, 0x4, 0, 0, false); // 2 bytes | |
| 3985 | |
| 3986 // call d2l_fixup | |
| 1748 | 3987 cbuf.set_insts_mark(); |
| 0 | 3988 emit_opcode(cbuf, 0xE8); |
| 3989 emit_d32_reloc(cbuf, | |
| 3990 (int) | |
| 1748 | 3991 (StubRoutines::x86::d2l_fixup() - cbuf.insts_end() - 4), |
| 0 | 3992 runtime_call_Relocation::spec(), |
| 3993 RELOC_DISP32); | |
| 3994 | |
| 3995 // popq $dst | |
| 3996 if (dstenc >= 8) { | |
| 3997 emit_opcode(cbuf, Assembler::REX_B); | |
| 3998 } | |
| 3999 emit_opcode(cbuf, 0x58 | (dstenc & 7)); | |
| 4000 | |
| 4001 // done: | |
| 4002 %} | |
| 4003 | |
| 4004 // Safepoint Poll. This polls the safepoint page, and causes an | |
| 4005 // exception if it is not readable. Unfortunately, it kills | |
| 4006 // RFLAGS in the process. | |
| 4007 enc_class enc_safepoint_poll | |
| 4008 %{ | |
| 4009 // testl %rax, off(%rip) // Opcode + ModRM + Disp32 == 6 bytes | |
| 4010 // XXX reg_mem doesn't support RIP-relative addressing yet | |
| 1748 | 4011 cbuf.set_insts_mark(); |
| 4012 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); // XXX | |
| 0 | 4013 emit_opcode(cbuf, 0x85); // testl |
| 4014 emit_rm(cbuf, 0x0, RAX_enc, 0x5); // 00 rax 101 == 0x5 | |
| 1748 | 4015 // cbuf.insts_mark() is beginning of instruction |
| 0 | 4016 emit_d32_reloc(cbuf, os::get_polling_page()); |
| 4017 // relocInfo::poll_type, | |
| 4018 %} | |
| 4019 %} | |
| 4020 | |
| 4021 | |
|
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71
diff
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|
4022 |
| 0 | 4023 //----------FRAME-------------------------------------------------------------- |
| 4024 // Definition of frame structure and management information. | |
| 4025 // | |
| 4026 // S T A C K L A Y O U T Allocators stack-slot number | |
| 4027 // | (to get allocators register number | |
| 4028 // G Owned by | | v add OptoReg::stack0()) | |
| 4029 // r CALLER | | | |
| 4030 // o | +--------+ pad to even-align allocators stack-slot | |
| 4031 // w V | pad0 | numbers; owned by CALLER | |
| 4032 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned | |
| 4033 // h ^ | in | 5 | |
| 4034 // | | args | 4 Holes in incoming args owned by SELF | |
| 4035 // | | | | 3 | |
| 4036 // | | +--------+ | |
| 4037 // V | | old out| Empty on Intel, window on Sparc | |
| 4038 // | old |preserve| Must be even aligned. | |
| 4039 // | SP-+--------+----> Matcher::_old_SP, even aligned | |
| 4040 // | | in | 3 area for Intel ret address | |
| 4041 // Owned by |preserve| Empty on Sparc. | |
| 4042 // SELF +--------+ | |
| 4043 // | | pad2 | 2 pad to align old SP | |
| 4044 // | +--------+ 1 | |
| 4045 // | | locks | 0 | |
| 4046 // | +--------+----> OptoReg::stack0(), even aligned | |
| 4047 // | | pad1 | 11 pad to align new SP | |
| 4048 // | +--------+ | |
| 4049 // | | | 10 | |
| 4050 // | | spills | 9 spills | |
| 4051 // V | | 8 (pad0 slot for callee) | |
| 4052 // -----------+--------+----> Matcher::_out_arg_limit, unaligned | |
| 4053 // ^ | out | 7 | |
| 4054 // | | args | 6 Holes in outgoing args owned by CALLEE | |
| 4055 // Owned by +--------+ | |
| 4056 // CALLEE | new out| 6 Empty on Intel, window on Sparc | |
| 4057 // | new |preserve| Must be even-aligned. | |
| 4058 // | SP-+--------+----> Matcher::_new_SP, even aligned | |
| 4059 // | | | | |
| 4060 // | |
| 4061 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is | |
| 4062 // known from SELF's arguments and the Java calling convention. | |
| 4063 // Region 6-7 is determined per call site. | |
| 4064 // Note 2: If the calling convention leaves holes in the incoming argument | |
| 4065 // area, those holes are owned by SELF. Holes in the outgoing area | |
| 4066 // are owned by the CALLEE. Holes should not be nessecary in the | |
| 4067 // incoming area, as the Java calling convention is completely under | |
| 4068 // the control of the AD file. Doubles can be sorted and packed to | |
| 4069 // avoid holes. Holes in the outgoing arguments may be nessecary for | |
| 4070 // varargs C calling conventions. | |
| 4071 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is | |
| 4072 // even aligned with pad0 as needed. | |
| 4073 // Region 6 is even aligned. Region 6-7 is NOT even aligned; | |
| 4074 // region 6-11 is even aligned; it may be padded out more so that | |
| 4075 // the region from SP to FP meets the minimum stack alignment. | |
| 4076 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack | |
| 4077 // alignment. Region 11, pad1, may be dynamically extended so that | |
| 4078 // SP meets the minimum alignment. | |
| 4079 | |
| 4080 frame | |
| 4081 %{ | |
| 4082 // What direction does stack grow in (assumed to be same for C & Java) | |
| 4083 stack_direction(TOWARDS_LOW); | |
| 4084 | |
| 4085 // These three registers define part of the calling convention | |
| 4086 // between compiled code and the interpreter. | |
| 4087 inline_cache_reg(RAX); // Inline Cache Register | |
| 4088 interpreter_method_oop_reg(RBX); // Method Oop Register when | |
| 4089 // calling interpreter | |
| 4090 | |
| 4091 // Optional: name the operand used by cisc-spilling to access | |
| 4092 // [stack_pointer + offset] | |
| 4093 cisc_spilling_operand_name(indOffset32); | |
| 4094 | |
| 4095 // Number of stack slots consumed by locking an object | |
| 4096 sync_stack_slots(2); | |
| 4097 | |
| 4098 // Compiled code's Frame Pointer | |
| 4099 frame_pointer(RSP); | |
| 4100 | |
| 4101 // Interpreter stores its frame pointer in a register which is | |
| 4102 // stored to the stack by I2CAdaptors. | |
| 4103 // I2CAdaptors convert from interpreted java to compiled java. | |
| 4104 interpreter_frame_pointer(RBP); | |
| 4105 | |
| 4106 // Stack alignment requirement | |
| 4107 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes) | |
| 4108 | |
| 4109 // Number of stack slots between incoming argument block and the start of | |
| 4110 // a new frame. The PROLOG must add this many slots to the stack. The | |
| 4111 // EPILOG must remove this many slots. amd64 needs two slots for | |
| 4112 // return address. | |
| 4113 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls); | |
| 4114 | |
| 4115 // Number of outgoing stack slots killed above the out_preserve_stack_slots | |
| 4116 // for calls to C. Supports the var-args backing area for register parms. | |
| 4117 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt); | |
| 4118 | |
| 4119 // The after-PROLOG location of the return address. Location of | |
| 4120 // return address specifies a type (REG or STACK) and a number | |
| 4121 // representing the register number (i.e. - use a register name) or | |
| 4122 // stack slot. | |
| 4123 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. | |
| 4124 // Otherwise, it is above the locks and verification slot and alignment word | |
| 4125 return_addr(STACK - 2 + | |
| 4126 round_to(2 + 2 * VerifyStackAtCalls + | |
| 4127 Compile::current()->fixed_slots(), | |
| 4128 WordsPerLong * 2)); | |
| 4129 | |
| 4130 // Body of function which returns an integer array locating | |
| 4131 // arguments either in registers or in stack slots. Passed an array | |
| 4132 // of ideal registers called "sig" and a "length" count. Stack-slot | |
| 4133 // offsets are based on outgoing arguments, i.e. a CALLER setting up | |
| 4134 // arguments for a CALLEE. Incoming stack arguments are | |
| 4135 // automatically biased by the preserve_stack_slots field above. | |
| 4136 | |
| 4137 calling_convention | |
| 4138 %{ | |
| 4139 // No difference between ingoing/outgoing just pass false | |
| 4140 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); | |
| 4141 %} | |
| 4142 | |
| 4143 c_calling_convention | |
| 4144 %{ | |
| 4145 // This is obviously always outgoing | |
| 4146 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); | |
| 4147 %} | |
| 4148 | |
| 4149 // Location of compiled Java return values. Same as C for now. | |
| 4150 return_value | |
| 4151 %{ | |
| 4152 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, | |
| 4153 "only return normal values"); | |
| 4154 | |
| 4155 static const int lo[Op_RegL + 1] = { | |
| 4156 0, | |
| 4157 0, | |
|
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4158 RAX_num, // Op_RegN |
| 0 | 4159 RAX_num, // Op_RegI |
| 4160 RAX_num, // Op_RegP | |
| 4161 XMM0_num, // Op_RegF | |
| 4162 XMM0_num, // Op_RegD | |
| 4163 RAX_num // Op_RegL | |
| 4164 }; | |
| 4165 static const int hi[Op_RegL + 1] = { | |
| 4166 0, | |
| 4167 0, | |
|
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4168 OptoReg::Bad, // Op_RegN |
| 0 | 4169 OptoReg::Bad, // Op_RegI |
| 4170 RAX_H_num, // Op_RegP | |
| 4171 OptoReg::Bad, // Op_RegF | |
| 4172 XMM0_H_num, // Op_RegD | |
| 4173 RAX_H_num // Op_RegL | |
| 4174 }; | |
|
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4175 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 1, "missing type"); |
| 0 | 4176 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]); |
| 4177 %} | |
| 4178 %} | |
| 4179 | |
| 4180 //----------ATTRIBUTES--------------------------------------------------------- | |
| 4181 //----------Operand Attributes------------------------------------------------- | |
| 4182 op_attrib op_cost(0); // Required cost attribute | |
| 4183 | |
| 4184 //----------Instruction Attributes--------------------------------------------- | |
| 4185 ins_attrib ins_cost(100); // Required cost attribute | |
| 4186 ins_attrib ins_size(8); // Required size attribute (in bits) | |
| 4187 ins_attrib ins_pc_relative(0); // Required PC Relative flag | |
| 4188 ins_attrib ins_short_branch(0); // Required flag: is this instruction | |
| 4189 // a non-matching short branch variant | |
| 4190 // of some long branch? | |
| 4191 ins_attrib ins_alignment(1); // Required alignment attribute (must | |
| 4192 // be a power of 2) specifies the | |
| 4193 // alignment that some part of the | |
| 4194 // instruction (not necessarily the | |
| 4195 // start) requires. If > 1, a | |
| 4196 // compute_padding() function must be | |
| 4197 // provided for the instruction | |
| 4198 | |
| 4199 //----------OPERANDS----------------------------------------------------------- | |
| 4200 // Operand definitions must precede instruction definitions for correct parsing | |
| 4201 // in the ADLC because operands constitute user defined types which are used in | |
| 4202 // instruction definitions. | |
| 4203 | |
| 4204 //----------Simple Operands---------------------------------------------------- | |
| 4205 // Immediate Operands | |
| 4206 // Integer Immediate | |
| 4207 operand immI() | |
| 4208 %{ | |
| 4209 match(ConI); | |
| 4210 | |
| 4211 op_cost(10); | |
| 4212 format %{ %} | |
| 4213 interface(CONST_INTER); | |
| 4214 %} | |
| 4215 | |
| 4216 // Constant for test vs zero | |
| 4217 operand immI0() | |
| 4218 %{ | |
| 4219 predicate(n->get_int() == 0); | |
| 4220 match(ConI); | |
| 4221 | |
| 4222 op_cost(0); | |
| 4223 format %{ %} | |
| 4224 interface(CONST_INTER); | |
| 4225 %} | |
| 4226 | |
| 4227 // Constant for increment | |
| 4228 operand immI1() | |
| 4229 %{ | |
| 4230 predicate(n->get_int() == 1); | |
| 4231 match(ConI); | |
| 4232 | |
| 4233 op_cost(0); | |
| 4234 format %{ %} | |
| 4235 interface(CONST_INTER); | |
| 4236 %} | |
| 4237 | |
| 4238 // Constant for decrement | |
| 4239 operand immI_M1() | |
| 4240 %{ | |
| 4241 predicate(n->get_int() == -1); | |
| 4242 match(ConI); | |
| 4243 | |
| 4244 op_cost(0); | |
| 4245 format %{ %} | |
| 4246 interface(CONST_INTER); | |
| 4247 %} | |
| 4248 | |
| 4249 // Valid scale values for addressing modes | |
| 4250 operand immI2() | |
| 4251 %{ | |
| 4252 predicate(0 <= n->get_int() && (n->get_int() <= 3)); | |
| 4253 match(ConI); | |
| 4254 | |
| 4255 format %{ %} | |
| 4256 interface(CONST_INTER); | |
| 4257 %} | |
| 4258 | |
| 4259 operand immI8() | |
| 4260 %{ | |
| 4261 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80)); | |
| 4262 match(ConI); | |
| 4263 | |
| 4264 op_cost(5); | |
| 4265 format %{ %} | |
| 4266 interface(CONST_INTER); | |
| 4267 %} | |
| 4268 | |
| 4269 operand immI16() | |
| 4270 %{ | |
| 4271 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); | |
| 4272 match(ConI); | |
| 4273 | |
| 4274 op_cost(10); | |
| 4275 format %{ %} | |
| 4276 interface(CONST_INTER); | |
| 4277 %} | |
| 4278 | |
| 4279 // Constant for long shifts | |
| 4280 operand immI_32() | |
| 4281 %{ | |
| 4282 predicate( n->get_int() == 32 ); | |
| 4283 match(ConI); | |
| 4284 | |
| 4285 op_cost(0); | |
| 4286 format %{ %} | |
| 4287 interface(CONST_INTER); | |
| 4288 %} | |
| 4289 | |
| 4290 // Constant for long shifts | |
| 4291 operand immI_64() | |
| 4292 %{ | |
| 4293 predicate( n->get_int() == 64 ); | |
| 4294 match(ConI); | |
| 4295 | |
| 4296 op_cost(0); | |
| 4297 format %{ %} | |
| 4298 interface(CONST_INTER); | |
| 4299 %} | |
| 4300 | |
| 4301 // Pointer Immediate | |
| 4302 operand immP() | |
| 4303 %{ | |
| 4304 match(ConP); | |
| 4305 | |
| 4306 op_cost(10); | |
| 4307 format %{ %} | |
| 4308 interface(CONST_INTER); | |
| 4309 %} | |
| 4310 | |
| 4311 // NULL Pointer Immediate | |
| 4312 operand immP0() | |
| 4313 %{ | |
| 4314 predicate(n->get_ptr() == 0); | |
| 4315 match(ConP); | |
| 4316 | |
| 4317 op_cost(5); | |
| 4318 format %{ %} | |
| 4319 interface(CONST_INTER); | |
| 4320 %} | |
| 4321 | |
|
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4322 // Pointer Immediate |
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4323 operand immN() %{ |
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4324 match(ConN); |
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4325 |
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4326 op_cost(10); |
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4327 format %{ %} |
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4328 interface(CONST_INTER); |
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4329 %} |
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4330 |
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4331 // NULL Pointer Immediate |
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4332 operand immN0() %{ |
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4333 predicate(n->get_narrowcon() == 0); |
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4334 match(ConN); |
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4335 |
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4336 op_cost(5); |
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4337 format %{ %} |
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4338 interface(CONST_INTER); |
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4339 %} |
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4340 |
| 0 | 4341 operand immP31() |
| 4342 %{ | |
| 4343 predicate(!n->as_Type()->type()->isa_oopptr() | |
| 4344 && (n->get_ptr() >> 31) == 0); | |
| 4345 match(ConP); | |
| 4346 | |
| 4347 op_cost(5); | |
| 4348 format %{ %} | |
| 4349 interface(CONST_INTER); | |
| 4350 %} | |
| 4351 | |
|
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4352 |
| 0 | 4353 // Long Immediate |
| 4354 operand immL() | |
| 4355 %{ | |
| 4356 match(ConL); | |
| 4357 | |
| 4358 op_cost(20); | |
| 4359 format %{ %} | |
| 4360 interface(CONST_INTER); | |
| 4361 %} | |
| 4362 | |
| 4363 // Long Immediate 8-bit | |
| 4364 operand immL8() | |
| 4365 %{ | |
| 4366 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L); | |
| 4367 match(ConL); | |
| 4368 | |
| 4369 op_cost(5); | |
| 4370 format %{ %} | |
| 4371 interface(CONST_INTER); | |
| 4372 %} | |
| 4373 | |
| 4374 // Long Immediate 32-bit unsigned | |
| 4375 operand immUL32() | |
| 4376 %{ | |
| 4377 predicate(n->get_long() == (unsigned int) (n->get_long())); | |
| 4378 match(ConL); | |
| 4379 | |
| 4380 op_cost(10); | |
| 4381 format %{ %} | |
| 4382 interface(CONST_INTER); | |
| 4383 %} | |
| 4384 | |
| 4385 // Long Immediate 32-bit signed | |
| 4386 operand immL32() | |
| 4387 %{ | |
| 4388 predicate(n->get_long() == (int) (n->get_long())); | |
| 4389 match(ConL); | |
| 4390 | |
| 4391 op_cost(15); | |
| 4392 format %{ %} | |
| 4393 interface(CONST_INTER); | |
| 4394 %} | |
| 4395 | |
| 4396 // Long Immediate zero | |
| 4397 operand immL0() | |
| 4398 %{ | |
| 4399 predicate(n->get_long() == 0L); | |
| 4400 match(ConL); | |
| 4401 | |
| 4402 op_cost(10); | |
| 4403 format %{ %} | |
| 4404 interface(CONST_INTER); | |
| 4405 %} | |
| 4406 | |
| 4407 // Constant for increment | |
| 4408 operand immL1() | |
| 4409 %{ | |
| 4410 predicate(n->get_long() == 1); | |
| 4411 match(ConL); | |
| 4412 | |
| 4413 format %{ %} | |
| 4414 interface(CONST_INTER); | |
| 4415 %} | |
| 4416 | |
| 4417 // Constant for decrement | |
| 4418 operand immL_M1() | |
| 4419 %{ | |
| 4420 predicate(n->get_long() == -1); | |
| 4421 match(ConL); | |
| 4422 | |
| 4423 format %{ %} | |
| 4424 interface(CONST_INTER); | |
| 4425 %} | |
| 4426 | |
| 4427 // Long Immediate: the value 10 | |
| 4428 operand immL10() | |
| 4429 %{ | |
| 4430 predicate(n->get_long() == 10); | |
| 4431 match(ConL); | |
| 4432 | |
| 4433 format %{ %} | |
| 4434 interface(CONST_INTER); | |
| 4435 %} | |
| 4436 | |
| 4437 // Long immediate from 0 to 127. | |
| 4438 // Used for a shorter form of long mul by 10. | |
| 4439 operand immL_127() | |
| 4440 %{ | |
| 4441 predicate(0 <= n->get_long() && n->get_long() < 0x80); | |
| 4442 match(ConL); | |
| 4443 | |
| 4444 op_cost(10); | |
| 4445 format %{ %} | |
| 4446 interface(CONST_INTER); | |
| 4447 %} | |
| 4448 | |
| 4449 // Long Immediate: low 32-bit mask | |
| 4450 operand immL_32bits() | |
| 4451 %{ | |
| 4452 predicate(n->get_long() == 0xFFFFFFFFL); | |
| 4453 match(ConL); | |
| 4454 op_cost(20); | |
| 4455 | |
| 4456 format %{ %} | |
| 4457 interface(CONST_INTER); | |
| 4458 %} | |
| 4459 | |
| 4460 // Float Immediate zero | |
| 4461 operand immF0() | |
| 4462 %{ | |
| 4463 predicate(jint_cast(n->getf()) == 0); | |
| 4464 match(ConF); | |
| 4465 | |
| 4466 op_cost(5); | |
| 4467 format %{ %} | |
| 4468 interface(CONST_INTER); | |
| 4469 %} | |
| 4470 | |
| 4471 // Float Immediate | |
| 4472 operand immF() | |
| 4473 %{ | |
| 4474 match(ConF); | |
| 4475 | |
| 4476 op_cost(15); | |
| 4477 format %{ %} | |
| 4478 interface(CONST_INTER); | |
| 4479 %} | |
| 4480 | |
| 4481 // Double Immediate zero | |
| 4482 operand immD0() | |
| 4483 %{ | |
| 4484 predicate(jlong_cast(n->getd()) == 0); | |
| 4485 match(ConD); | |
| 4486 | |
| 4487 op_cost(5); | |
| 4488 format %{ %} | |
| 4489 interface(CONST_INTER); | |
| 4490 %} | |
| 4491 | |
| 4492 // Double Immediate | |
| 4493 operand immD() | |
| 4494 %{ | |
| 4495 match(ConD); | |
| 4496 | |
| 4497 op_cost(15); | |
| 4498 format %{ %} | |
| 4499 interface(CONST_INTER); | |
| 4500 %} | |
| 4501 | |
| 4502 // Immediates for special shifts (sign extend) | |
| 4503 | |
| 4504 // Constants for increment | |
| 4505 operand immI_16() | |
| 4506 %{ | |
| 4507 predicate(n->get_int() == 16); | |
| 4508 match(ConI); | |
| 4509 | |
| 4510 format %{ %} | |
| 4511 interface(CONST_INTER); | |
| 4512 %} | |
| 4513 | |
| 4514 operand immI_24() | |
| 4515 %{ | |
| 4516 predicate(n->get_int() == 24); | |
| 4517 match(ConI); | |
| 4518 | |
| 4519 format %{ %} | |
| 4520 interface(CONST_INTER); | |
| 4521 %} | |
| 4522 | |
| 4523 // Constant for byte-wide masking | |
| 4524 operand immI_255() | |
| 4525 %{ | |
| 4526 predicate(n->get_int() == 255); | |
| 4527 match(ConI); | |
| 4528 | |
| 4529 format %{ %} | |
| 4530 interface(CONST_INTER); | |
| 4531 %} | |
| 4532 | |
| 4533 // Constant for short-wide masking | |
| 4534 operand immI_65535() | |
| 4535 %{ | |
| 4536 predicate(n->get_int() == 65535); | |
| 4537 match(ConI); | |
| 4538 | |
| 4539 format %{ %} | |
| 4540 interface(CONST_INTER); | |
| 4541 %} | |
| 4542 | |
| 4543 // Constant for byte-wide masking | |
| 4544 operand immL_255() | |
| 4545 %{ | |
| 4546 predicate(n->get_long() == 255); | |
| 4547 match(ConL); | |
| 4548 | |
| 4549 format %{ %} | |
| 4550 interface(CONST_INTER); | |
| 4551 %} | |
| 4552 | |
| 4553 // Constant for short-wide masking | |
| 4554 operand immL_65535() | |
| 4555 %{ | |
| 4556 predicate(n->get_long() == 65535); | |
| 4557 match(ConL); | |
| 4558 | |
| 4559 format %{ %} | |
| 4560 interface(CONST_INTER); | |
| 4561 %} | |
| 4562 | |
| 4563 // Register Operands | |
| 4564 // Integer Register | |
| 4565 operand rRegI() | |
| 4566 %{ | |
| 4567 constraint(ALLOC_IN_RC(int_reg)); | |
| 4568 match(RegI); | |
| 4569 | |
| 4570 match(rax_RegI); | |
| 4571 match(rbx_RegI); | |
| 4572 match(rcx_RegI); | |
| 4573 match(rdx_RegI); | |
| 4574 match(rdi_RegI); | |
| 4575 | |
| 4576 format %{ %} | |
| 4577 interface(REG_INTER); | |
| 4578 %} | |
| 4579 | |
| 4580 // Special Registers | |
| 4581 operand rax_RegI() | |
| 4582 %{ | |
| 4583 constraint(ALLOC_IN_RC(int_rax_reg)); | |
| 4584 match(RegI); | |
| 4585 match(rRegI); | |
| 4586 | |
| 4587 format %{ "RAX" %} | |
| 4588 interface(REG_INTER); | |
| 4589 %} | |
| 4590 | |
| 4591 // Special Registers | |
| 4592 operand rbx_RegI() | |
| 4593 %{ | |
| 4594 constraint(ALLOC_IN_RC(int_rbx_reg)); | |
| 4595 match(RegI); | |
| 4596 match(rRegI); | |
| 4597 | |
| 4598 format %{ "RBX" %} | |
| 4599 interface(REG_INTER); | |
| 4600 %} | |
| 4601 | |
| 4602 operand rcx_RegI() | |
| 4603 %{ | |
| 4604 constraint(ALLOC_IN_RC(int_rcx_reg)); | |
| 4605 match(RegI); | |
| 4606 match(rRegI); | |
| 4607 | |
| 4608 format %{ "RCX" %} | |
| 4609 interface(REG_INTER); | |
| 4610 %} | |
| 4611 | |
| 4612 operand rdx_RegI() | |
| 4613 %{ | |
| 4614 constraint(ALLOC_IN_RC(int_rdx_reg)); | |
| 4615 match(RegI); | |
| 4616 match(rRegI); | |
| 4617 | |
| 4618 format %{ "RDX" %} | |
| 4619 interface(REG_INTER); | |
| 4620 %} | |
| 4621 | |
| 4622 operand rdi_RegI() | |
| 4623 %{ | |
| 4624 constraint(ALLOC_IN_RC(int_rdi_reg)); | |
| 4625 match(RegI); | |
| 4626 match(rRegI); | |
| 4627 | |
| 4628 format %{ "RDI" %} | |
| 4629 interface(REG_INTER); | |
| 4630 %} | |
| 4631 | |
| 4632 operand no_rcx_RegI() | |
| 4633 %{ | |
| 4634 constraint(ALLOC_IN_RC(int_no_rcx_reg)); | |
| 4635 match(RegI); | |
| 4636 match(rax_RegI); | |
| 4637 match(rbx_RegI); | |
| 4638 match(rdx_RegI); | |
| 4639 match(rdi_RegI); | |
| 4640 | |
| 4641 format %{ %} | |
| 4642 interface(REG_INTER); | |
| 4643 %} | |
| 4644 | |
| 4645 operand no_rax_rdx_RegI() | |
| 4646 %{ | |
| 4647 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg)); | |
| 4648 match(RegI); | |
| 4649 match(rbx_RegI); | |
| 4650 match(rcx_RegI); | |
| 4651 match(rdi_RegI); | |
| 4652 | |
| 4653 format %{ %} | |
| 4654 interface(REG_INTER); | |
| 4655 %} | |
| 4656 | |
| 4657 // Pointer Register | |
| 4658 operand any_RegP() | |
| 4659 %{ | |
| 4660 constraint(ALLOC_IN_RC(any_reg)); | |
| 4661 match(RegP); | |
| 4662 match(rax_RegP); | |
| 4663 match(rbx_RegP); | |
| 4664 match(rdi_RegP); | |
| 4665 match(rsi_RegP); | |
| 4666 match(rbp_RegP); | |
| 4667 match(r15_RegP); | |
| 4668 match(rRegP); | |
| 4669 | |
| 4670 format %{ %} | |
| 4671 interface(REG_INTER); | |
| 4672 %} | |
| 4673 | |
| 4674 operand rRegP() | |
| 4675 %{ | |
| 4676 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4677 match(RegP); | |
| 4678 match(rax_RegP); | |
| 4679 match(rbx_RegP); | |
| 4680 match(rdi_RegP); | |
| 4681 match(rsi_RegP); | |
| 4682 match(rbp_RegP); | |
| 4683 match(r15_RegP); // See Q&A below about r15_RegP. | |
| 4684 | |
| 4685 format %{ %} | |
| 4686 interface(REG_INTER); | |
| 4687 %} | |
| 4688 | |
|
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4689 operand rRegN() %{ |
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4690 constraint(ALLOC_IN_RC(int_reg)); |
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4691 match(RegN); |
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4692 |
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4693 format %{ %} |
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4694 interface(REG_INTER); |
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4695 %} |
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4696 |
| 0 | 4697 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP? |
| 4698 // Answer: Operand match rules govern the DFA as it processes instruction inputs. | |
| 4699 // It's fine for an instruction input which expects rRegP to match a r15_RegP. | |
| 4700 // The output of an instruction is controlled by the allocator, which respects | |
| 4701 // register class masks, not match rules. Unless an instruction mentions | |
| 4702 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered | |
| 4703 // by the allocator as an input. | |
| 4704 | |
| 4705 operand no_rax_RegP() | |
| 4706 %{ | |
| 4707 constraint(ALLOC_IN_RC(ptr_no_rax_reg)); | |
| 4708 match(RegP); | |
| 4709 match(rbx_RegP); | |
| 4710 match(rsi_RegP); | |
| 4711 match(rdi_RegP); | |
| 4712 | |
| 4713 format %{ %} | |
| 4714 interface(REG_INTER); | |
| 4715 %} | |
| 4716 | |
| 4717 operand no_rbp_RegP() | |
| 4718 %{ | |
| 4719 constraint(ALLOC_IN_RC(ptr_no_rbp_reg)); | |
| 4720 match(RegP); | |
| 4721 match(rbx_RegP); | |
| 4722 match(rsi_RegP); | |
| 4723 match(rdi_RegP); | |
| 4724 | |
| 4725 format %{ %} | |
| 4726 interface(REG_INTER); | |
| 4727 %} | |
| 4728 | |
| 4729 operand no_rax_rbx_RegP() | |
| 4730 %{ | |
| 4731 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg)); | |
| 4732 match(RegP); | |
| 4733 match(rsi_RegP); | |
| 4734 match(rdi_RegP); | |
| 4735 | |
| 4736 format %{ %} | |
| 4737 interface(REG_INTER); | |
| 4738 %} | |
| 4739 | |
| 4740 // Special Registers | |
| 4741 // Return a pointer value | |
| 4742 operand rax_RegP() | |
| 4743 %{ | |
| 4744 constraint(ALLOC_IN_RC(ptr_rax_reg)); | |
| 4745 match(RegP); | |
| 4746 match(rRegP); | |
| 4747 | |
| 4748 format %{ %} | |
| 4749 interface(REG_INTER); | |
| 4750 %} | |
| 4751 | |
|
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4752 // Special Registers |
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4753 // Return a compressed pointer value |
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4754 operand rax_RegN() |
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4755 %{ |
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4756 constraint(ALLOC_IN_RC(int_rax_reg)); |
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4757 match(RegN); |
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4758 match(rRegN); |
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|
4759 |
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|
4760 format %{ %} |
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4761 interface(REG_INTER); |
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4762 %} |
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|
4763 |
| 0 | 4764 // Used in AtomicAdd |
| 4765 operand rbx_RegP() | |
| 4766 %{ | |
| 4767 constraint(ALLOC_IN_RC(ptr_rbx_reg)); | |
| 4768 match(RegP); | |
| 4769 match(rRegP); | |
| 4770 | |
| 4771 format %{ %} | |
| 4772 interface(REG_INTER); | |
| 4773 %} | |
| 4774 | |
| 4775 operand rsi_RegP() | |
| 4776 %{ | |
| 4777 constraint(ALLOC_IN_RC(ptr_rsi_reg)); | |
| 4778 match(RegP); | |
| 4779 match(rRegP); | |
| 4780 | |
| 4781 format %{ %} | |
| 4782 interface(REG_INTER); | |
| 4783 %} | |
| 4784 | |
| 4785 // Used in rep stosq | |
| 4786 operand rdi_RegP() | |
| 4787 %{ | |
| 4788 constraint(ALLOC_IN_RC(ptr_rdi_reg)); | |
| 4789 match(RegP); | |
| 4790 match(rRegP); | |
| 4791 | |
| 4792 format %{ %} | |
| 4793 interface(REG_INTER); | |
| 4794 %} | |
| 4795 | |
| 4796 operand rbp_RegP() | |
| 4797 %{ | |
| 4798 constraint(ALLOC_IN_RC(ptr_rbp_reg)); | |
| 4799 match(RegP); | |
| 4800 match(rRegP); | |
| 4801 | |
| 4802 format %{ %} | |
| 4803 interface(REG_INTER); | |
| 4804 %} | |
| 4805 | |
| 4806 operand r15_RegP() | |
| 4807 %{ | |
| 4808 constraint(ALLOC_IN_RC(ptr_r15_reg)); | |
| 4809 match(RegP); | |
| 4810 match(rRegP); | |
| 4811 | |
| 4812 format %{ %} | |
| 4813 interface(REG_INTER); | |
| 4814 %} | |
| 4815 | |
| 4816 operand rRegL() | |
| 4817 %{ | |
| 4818 constraint(ALLOC_IN_RC(long_reg)); | |
| 4819 match(RegL); | |
| 4820 match(rax_RegL); | |
| 4821 match(rdx_RegL); | |
| 4822 | |
| 4823 format %{ %} | |
| 4824 interface(REG_INTER); | |
| 4825 %} | |
| 4826 | |
| 4827 // Special Registers | |
| 4828 operand no_rax_rdx_RegL() | |
| 4829 %{ | |
| 4830 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 4831 match(RegL); | |
| 4832 match(rRegL); | |
| 4833 | |
| 4834 format %{ %} | |
| 4835 interface(REG_INTER); | |
| 4836 %} | |
| 4837 | |
| 4838 operand no_rax_RegL() | |
| 4839 %{ | |
| 4840 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg)); | |
| 4841 match(RegL); | |
| 4842 match(rRegL); | |
| 4843 match(rdx_RegL); | |
| 4844 | |
| 4845 format %{ %} | |
| 4846 interface(REG_INTER); | |
| 4847 %} | |
| 4848 | |
| 4849 operand no_rcx_RegL() | |
| 4850 %{ | |
| 4851 constraint(ALLOC_IN_RC(long_no_rcx_reg)); | |
| 4852 match(RegL); | |
| 4853 match(rRegL); | |
| 4854 | |
| 4855 format %{ %} | |
| 4856 interface(REG_INTER); | |
| 4857 %} | |
| 4858 | |
| 4859 operand rax_RegL() | |
| 4860 %{ | |
| 4861 constraint(ALLOC_IN_RC(long_rax_reg)); | |
| 4862 match(RegL); | |
| 4863 match(rRegL); | |
| 4864 | |
| 4865 format %{ "RAX" %} | |
| 4866 interface(REG_INTER); | |
| 4867 %} | |
| 4868 | |
| 4869 operand rcx_RegL() | |
| 4870 %{ | |
| 4871 constraint(ALLOC_IN_RC(long_rcx_reg)); | |
| 4872 match(RegL); | |
| 4873 match(rRegL); | |
| 4874 | |
| 4875 format %{ %} | |
| 4876 interface(REG_INTER); | |
| 4877 %} | |
| 4878 | |
| 4879 operand rdx_RegL() | |
| 4880 %{ | |
| 4881 constraint(ALLOC_IN_RC(long_rdx_reg)); | |
| 4882 match(RegL); | |
| 4883 match(rRegL); | |
| 4884 | |
| 4885 format %{ %} | |
| 4886 interface(REG_INTER); | |
| 4887 %} | |
| 4888 | |
| 4889 // Flags register, used as output of compare instructions | |
| 4890 operand rFlagsReg() | |
| 4891 %{ | |
| 4892 constraint(ALLOC_IN_RC(int_flags)); | |
| 4893 match(RegFlags); | |
| 4894 | |
| 4895 format %{ "RFLAGS" %} | |
| 4896 interface(REG_INTER); | |
| 4897 %} | |
| 4898 | |
| 4899 // Flags register, used as output of FLOATING POINT compare instructions | |
| 4900 operand rFlagsRegU() | |
| 4901 %{ | |
| 4902 constraint(ALLOC_IN_RC(int_flags)); | |
| 4903 match(RegFlags); | |
| 4904 | |
| 4905 format %{ "RFLAGS_U" %} | |
| 4906 interface(REG_INTER); | |
| 4907 %} | |
| 4908 | |
|
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4909 operand rFlagsRegUCF() %{ |
|
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4910 constraint(ALLOC_IN_RC(int_flags)); |
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4911 match(RegFlags); |
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|
4912 predicate(false); |
|
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|
4913 |
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|
4914 format %{ "RFLAGS_U_CF" %} |
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4915 interface(REG_INTER); |
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|
4916 %} |
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|
4917 |
| 0 | 4918 // Float register operands |
| 4919 operand regF() | |
| 4920 %{ | |
| 4921 constraint(ALLOC_IN_RC(float_reg)); | |
| 4922 match(RegF); | |
| 4923 | |
| 4924 format %{ %} | |
| 4925 interface(REG_INTER); | |
| 4926 %} | |
| 4927 | |
| 4928 // Double register operands | |
| 681 | 4929 operand regD() |
| 0 | 4930 %{ |
| 4931 constraint(ALLOC_IN_RC(double_reg)); | |
| 4932 match(RegD); | |
| 4933 | |
| 4934 format %{ %} | |
| 4935 interface(REG_INTER); | |
| 4936 %} | |
| 4937 | |
| 4938 | |
| 4939 //----------Memory Operands---------------------------------------------------- | |
| 4940 // Direct Memory Operand | |
| 4941 // operand direct(immP addr) | |
| 4942 // %{ | |
| 4943 // match(addr); | |
| 4944 | |
| 4945 // format %{ "[$addr]" %} | |
| 4946 // interface(MEMORY_INTER) %{ | |
| 4947 // base(0xFFFFFFFF); | |
| 4948 // index(0x4); | |
| 4949 // scale(0x0); | |
| 4950 // disp($addr); | |
| 4951 // %} | |
| 4952 // %} | |
| 4953 | |
| 4954 // Indirect Memory Operand | |
| 4955 operand indirect(any_RegP reg) | |
| 4956 %{ | |
| 4957 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4958 match(reg); | |
| 4959 | |
| 4960 format %{ "[$reg]" %} | |
| 4961 interface(MEMORY_INTER) %{ | |
| 4962 base($reg); | |
| 4963 index(0x4); | |
| 4964 scale(0x0); | |
| 4965 disp(0x0); | |
| 4966 %} | |
| 4967 %} | |
| 4968 | |
| 4969 // Indirect Memory Plus Short Offset Operand | |
| 4970 operand indOffset8(any_RegP reg, immL8 off) | |
| 4971 %{ | |
| 4972 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4973 match(AddP reg off); | |
| 4974 | |
| 4975 format %{ "[$reg + $off (8-bit)]" %} | |
| 4976 interface(MEMORY_INTER) %{ | |
| 4977 base($reg); | |
| 4978 index(0x4); | |
| 4979 scale(0x0); | |
| 4980 disp($off); | |
| 4981 %} | |
| 4982 %} | |
| 4983 | |
| 4984 // Indirect Memory Plus Long Offset Operand | |
| 4985 operand indOffset32(any_RegP reg, immL32 off) | |
| 4986 %{ | |
| 4987 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 4988 match(AddP reg off); | |
| 4989 | |
| 4990 format %{ "[$reg + $off (32-bit)]" %} | |
| 4991 interface(MEMORY_INTER) %{ | |
| 4992 base($reg); | |
| 4993 index(0x4); | |
| 4994 scale(0x0); | |
| 4995 disp($off); | |
| 4996 %} | |
| 4997 %} | |
| 4998 | |
| 4999 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5000 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off) | |
| 5001 %{ | |
| 5002 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5003 match(AddP (AddP reg lreg) off); | |
| 5004 | |
| 5005 op_cost(10); | |
| 5006 format %{"[$reg + $off + $lreg]" %} | |
| 5007 interface(MEMORY_INTER) %{ | |
| 5008 base($reg); | |
| 5009 index($lreg); | |
| 5010 scale(0x0); | |
| 5011 disp($off); | |
| 5012 %} | |
| 5013 %} | |
| 5014 | |
| 5015 // Indirect Memory Plus Index Register Plus Offset Operand | |
| 5016 operand indIndex(any_RegP reg, rRegL lreg) | |
| 5017 %{ | |
| 5018 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5019 match(AddP reg lreg); | |
| 5020 | |
| 5021 op_cost(10); | |
| 5022 format %{"[$reg + $lreg]" %} | |
| 5023 interface(MEMORY_INTER) %{ | |
| 5024 base($reg); | |
| 5025 index($lreg); | |
| 5026 scale(0x0); | |
| 5027 disp(0x0); | |
| 5028 %} | |
| 5029 %} | |
| 5030 | |
| 5031 // Indirect Memory Times Scale Plus Index Register | |
| 5032 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale) | |
| 5033 %{ | |
| 5034 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5035 match(AddP reg (LShiftL lreg scale)); | |
| 5036 | |
| 5037 op_cost(10); | |
| 5038 format %{"[$reg + $lreg << $scale]" %} | |
| 5039 interface(MEMORY_INTER) %{ | |
| 5040 base($reg); | |
| 5041 index($lreg); | |
| 5042 scale($scale); | |
| 5043 disp(0x0); | |
| 5044 %} | |
| 5045 %} | |
| 5046 | |
| 5047 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand | |
| 5048 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale) | |
| 5049 %{ | |
| 5050 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5051 match(AddP (AddP reg (LShiftL lreg scale)) off); | |
| 5052 | |
| 5053 op_cost(10); | |
| 5054 format %{"[$reg + $off + $lreg << $scale]" %} | |
| 5055 interface(MEMORY_INTER) %{ | |
| 5056 base($reg); | |
| 5057 index($lreg); | |
| 5058 scale($scale); | |
| 5059 disp($off); | |
| 5060 %} | |
| 5061 %} | |
| 5062 | |
| 5063 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand | |
| 5064 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale) | |
| 5065 %{ | |
| 5066 constraint(ALLOC_IN_RC(ptr_reg)); | |
| 5067 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); | |
| 5068 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off); | |
| 5069 | |
| 5070 op_cost(10); | |
| 5071 format %{"[$reg + $off + $idx << $scale]" %} | |
| 5072 interface(MEMORY_INTER) %{ | |
| 5073 base($reg); | |
| 5074 index($idx); | |
| 5075 scale($scale); | |
| 5076 disp($off); | |
| 5077 %} | |
| 5078 %} | |
| 5079 | |
|
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5080 // Indirect Narrow Oop Plus Offset Operand |
|
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5081 // Note: x86 architecture doesn't support "scale * index + offset" without a base |
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5082 // we can't free r12 even with Universe::narrow_oop_base() == NULL. |
|
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5083 operand indCompressedOopOffset(rRegN reg, immL32 off) %{ |
|
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5084 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8)); |
|
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5085 constraint(ALLOC_IN_RC(ptr_reg)); |
|
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5086 match(AddP (DecodeN reg) off); |
|
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|
5087 |
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changeset
|
5088 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5089 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5090 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5091 base(0xc); // R12 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5092 index($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5093 scale(0x3); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5094 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5095 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5096 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5097 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5098 // Indirect Memory Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5099 operand indirectNarrow(rRegN reg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5100 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5101 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5102 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5103 match(DecodeN reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5104 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5105 format %{ "[$reg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5106 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5107 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5108 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5109 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5110 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5111 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5112 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5113 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5114 // Indirect Memory Plus Short Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5115 operand indOffset8Narrow(rRegN reg, immL8 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5116 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5117 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5118 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5119 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5120 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5121 format %{ "[$reg + $off (8-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5122 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5123 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5124 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5125 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5126 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5127 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5128 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5129 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5130 // Indirect Memory Plus Long Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5131 operand indOffset32Narrow(rRegN reg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5132 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5133 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5134 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5135 match(AddP (DecodeN reg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5136 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5137 format %{ "[$reg + $off (32-bit)]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5138 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5139 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5140 index(0x4); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5141 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5142 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5143 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5144 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5145 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5146 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5147 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5148 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5149 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5150 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5151 match(AddP (AddP (DecodeN reg) lreg) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5152 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5153 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5154 format %{"[$reg + $off + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5155 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5156 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5157 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5158 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5159 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5160 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5161 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5162 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5163 // Indirect Memory Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5164 operand indIndexNarrow(rRegN reg, rRegL lreg) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5165 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5166 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5167 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5168 match(AddP (DecodeN reg) lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5169 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5170 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5171 format %{"[$reg + $lreg]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5172 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5173 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5174 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5175 scale(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5176 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5177 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5178 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5179 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5180 // Indirect Memory Times Scale Plus Index Register |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5181 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5182 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5183 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5184 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5185 match(AddP (DecodeN reg) (LShiftL lreg scale)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5186 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5187 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5188 format %{"[$reg + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5189 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5190 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5191 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5192 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5193 disp(0x0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5194 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5195 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5196 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5197 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5198 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5199 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5200 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5201 constraint(ALLOC_IN_RC(ptr_reg)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5202 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5203 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5204 op_cost(10); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5205 format %{"[$reg + $off + $lreg << $scale]" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5206 interface(MEMORY_INTER) %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5207 base($reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5208 index($lreg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5209 scale($scale); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5210 disp($off); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5211 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5212 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5213 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5214 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
5215 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale) |
|
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5216 %{ |
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5217 constraint(ALLOC_IN_RC(ptr_reg)); |
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5218 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0); |
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5219 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off); |
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5220 |
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|
5221 op_cost(10); |
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|
5222 format %{"[$reg + $off + $idx << $scale]" %} |
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5223 interface(MEMORY_INTER) %{ |
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5224 base($reg); |
|
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5225 index($idx); |
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|
5226 scale($scale); |
|
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|
5227 disp($off); |
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5228 %} |
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|
5229 %} |
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|
5230 |
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5231 |
| 0 | 5232 //----------Special Memory Operands-------------------------------------------- |
| 5233 // Stack Slot Operand - This operand is used for loading and storing temporary | |
| 5234 // values on the stack where a match requires a value to | |
| 5235 // flow through memory. | |
| 5236 operand stackSlotP(sRegP reg) | |
| 5237 %{ | |
| 5238 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5239 // No match rule because this operand is only generated in matching | |
| 5240 | |
| 5241 format %{ "[$reg]" %} | |
| 5242 interface(MEMORY_INTER) %{ | |
| 5243 base(0x4); // RSP | |
| 5244 index(0x4); // No Index | |
| 5245 scale(0x0); // No Scale | |
| 5246 disp($reg); // Stack Offset | |
| 5247 %} | |
| 5248 %} | |
| 5249 | |
| 5250 operand stackSlotI(sRegI reg) | |
| 5251 %{ | |
| 5252 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5253 // No match rule because this operand is only generated in matching | |
| 5254 | |
| 5255 format %{ "[$reg]" %} | |
| 5256 interface(MEMORY_INTER) %{ | |
| 5257 base(0x4); // RSP | |
| 5258 index(0x4); // No Index | |
| 5259 scale(0x0); // No Scale | |
| 5260 disp($reg); // Stack Offset | |
| 5261 %} | |
| 5262 %} | |
| 5263 | |
| 5264 operand stackSlotF(sRegF reg) | |
| 5265 %{ | |
| 5266 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5267 // No match rule because this operand is only generated in matching | |
| 5268 | |
| 5269 format %{ "[$reg]" %} | |
| 5270 interface(MEMORY_INTER) %{ | |
| 5271 base(0x4); // RSP | |
| 5272 index(0x4); // No Index | |
| 5273 scale(0x0); // No Scale | |
| 5274 disp($reg); // Stack Offset | |
| 5275 %} | |
| 5276 %} | |
| 5277 | |
| 5278 operand stackSlotD(sRegD reg) | |
| 5279 %{ | |
| 5280 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5281 // No match rule because this operand is only generated in matching | |
| 5282 | |
| 5283 format %{ "[$reg]" %} | |
| 5284 interface(MEMORY_INTER) %{ | |
| 5285 base(0x4); // RSP | |
| 5286 index(0x4); // No Index | |
| 5287 scale(0x0); // No Scale | |
| 5288 disp($reg); // Stack Offset | |
| 5289 %} | |
| 5290 %} | |
| 5291 operand stackSlotL(sRegL reg) | |
| 5292 %{ | |
| 5293 constraint(ALLOC_IN_RC(stack_slots)); | |
| 5294 // No match rule because this operand is only generated in matching | |
| 5295 | |
| 5296 format %{ "[$reg]" %} | |
| 5297 interface(MEMORY_INTER) %{ | |
| 5298 base(0x4); // RSP | |
| 5299 index(0x4); // No Index | |
| 5300 scale(0x0); // No Scale | |
| 5301 disp($reg); // Stack Offset | |
| 5302 %} | |
| 5303 %} | |
| 5304 | |
| 5305 //----------Conditional Branch Operands---------------------------------------- | |
| 5306 // Comparison Op - This is the operation of the comparison, and is limited to | |
| 5307 // the following set of codes: | |
| 5308 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) | |
| 5309 // | |
| 5310 // Other attributes of the comparison, such as unsignedness, are specified | |
| 5311 // by the comparison instruction that sets a condition code flags register. | |
| 5312 // That result is represented by a flags operand whose subtype is appropriate | |
| 5313 // to the unsignedness (etc.) of the comparison. | |
| 5314 // | |
| 5315 // Later, the instruction which matches both the Comparison Op (a Bool) and | |
| 5316 // the flags (produced by the Cmp) specifies the coding of the comparison op | |
| 5317 // by matching a specific subtype of Bool operand below, such as cmpOpU. | |
| 5318 | |
| 5319 // Comparision Code | |
| 5320 operand cmpOp() | |
| 5321 %{ | |
| 5322 match(Bool); | |
| 5323 | |
| 5324 format %{ "" %} | |
| 5325 interface(COND_INTER) %{ | |
|
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5326 equal(0x4, "e"); |
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5327 not_equal(0x5, "ne"); |
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5328 less(0xC, "l"); |
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5329 greater_equal(0xD, "ge"); |
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5330 less_equal(0xE, "le"); |
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5331 greater(0xF, "g"); |
| 0 | 5332 %} |
| 5333 %} | |
| 5334 | |
| 5335 // Comparison Code, unsigned compare. Used by FP also, with | |
| 5336 // C2 (unordered) turned into GT or LT already. The other bits | |
| 5337 // C0 and C3 are turned into Carry & Zero flags. | |
| 5338 operand cmpOpU() | |
| 5339 %{ | |
| 5340 match(Bool); | |
| 5341 | |
| 5342 format %{ "" %} | |
| 5343 interface(COND_INTER) %{ | |
|
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5344 equal(0x4, "e"); |
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|
5345 not_equal(0x5, "ne"); |
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|
5346 less(0x2, "b"); |
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|
5347 greater_equal(0x3, "nb"); |
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|
5348 less_equal(0x6, "be"); |
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|
5349 greater(0x7, "nbe"); |
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|
5350 %} |
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|
5351 %} |
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|
5352 |
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|
5353 |
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|
5354 // Floating comparisons that don't require any fixup for the unordered case |
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5355 operand cmpOpUCF() %{ |
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5356 match(Bool); |
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|
5357 predicate(n->as_Bool()->_test._test == BoolTest::lt || |
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|
5358 n->as_Bool()->_test._test == BoolTest::ge || |
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5359 n->as_Bool()->_test._test == BoolTest::le || |
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|
5360 n->as_Bool()->_test._test == BoolTest::gt); |
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|
5361 format %{ "" %} |
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|
5362 interface(COND_INTER) %{ |
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|
5363 equal(0x4, "e"); |
|
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|
5364 not_equal(0x5, "ne"); |
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|
5365 less(0x2, "b"); |
|
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|
5366 greater_equal(0x3, "nb"); |
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|
5367 less_equal(0x6, "be"); |
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|
5368 greater(0x7, "nbe"); |
|
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|
5369 %} |
|
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|
5370 %} |
|
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|
5371 |
|
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|
5372 |
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|
5373 // Floating comparisons that can be fixed up with extra conditional jumps |
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|
5374 operand cmpOpUCF2() %{ |
|
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|
5375 match(Bool); |
|
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|
5376 predicate(n->as_Bool()->_test._test == BoolTest::ne || |
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|
5377 n->as_Bool()->_test._test == BoolTest::eq); |
|
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|
5378 format %{ "" %} |
|
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|
5379 interface(COND_INTER) %{ |
|
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|
5380 equal(0x4, "e"); |
|
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|
5381 not_equal(0x5, "ne"); |
|
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|
5382 less(0x2, "b"); |
|
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|
5383 greater_equal(0x3, "nb"); |
|
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|
5384 less_equal(0x6, "be"); |
|
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|
5385 greater(0x7, "nbe"); |
| 0 | 5386 %} |
| 5387 %} | |
| 5388 | |
| 5389 | |
| 5390 //----------OPERAND CLASSES---------------------------------------------------- | |
| 5391 // Operand Classes are groups of operands that are used as to simplify | |
| 605 | 5392 // instruction definitions by not requiring the AD writer to specify separate |
| 0 | 5393 // instructions for every form of operand when the instruction accepts |
| 5394 // multiple operand types with the same basic encoding and format. The classic | |
| 5395 // case of this is memory operands. | |
| 5396 | |
| 5397 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex, | |
|
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|
5398 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset, |
|
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5399 indCompressedOopOffset, |
|
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|
5400 indirectNarrow, indOffset8Narrow, indOffset32Narrow, |
|
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5401 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow, |
|
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|
5402 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow); |
| 0 | 5403 |
| 5404 //----------PIPELINE----------------------------------------------------------- | |
| 5405 // Rules which define the behavior of the target architectures pipeline. | |
| 5406 pipeline %{ | |
| 5407 | |
| 5408 //----------ATTRIBUTES--------------------------------------------------------- | |
| 5409 attributes %{ | |
| 5410 variable_size_instructions; // Fixed size instructions | |
| 5411 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle | |
| 5412 instruction_unit_size = 1; // An instruction is 1 bytes long | |
| 5413 instruction_fetch_unit_size = 16; // The processor fetches one line | |
| 5414 instruction_fetch_units = 1; // of 16 bytes | |
| 5415 | |
| 5416 // List of nop instructions | |
| 5417 nops( MachNop ); | |
| 5418 %} | |
| 5419 | |
| 5420 //----------RESOURCES---------------------------------------------------------- | |
| 5421 // Resources are the functional units available to the machine | |
| 5422 | |
| 5423 // Generic P2/P3 pipeline | |
| 5424 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of | |
| 5425 // 3 instructions decoded per cycle. | |
| 5426 // 2 load/store ops per cycle, 1 branch, 1 FPU, | |
| 5427 // 3 ALU op, only ALU0 handles mul instructions. | |
| 5428 resources( D0, D1, D2, DECODE = D0 | D1 | D2, | |
| 5429 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2, | |
| 5430 BR, FPU, | |
| 5431 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2); | |
| 5432 | |
| 5433 //----------PIPELINE DESCRIPTION----------------------------------------------- | |
| 5434 // Pipeline Description specifies the stages in the machine's pipeline | |
| 5435 | |
| 5436 // Generic P2/P3 pipeline | |
| 5437 pipe_desc(S0, S1, S2, S3, S4, S5); | |
| 5438 | |
| 5439 //----------PIPELINE CLASSES--------------------------------------------------- | |
| 5440 // Pipeline Classes describe the stages in which input and output are | |
| 5441 // referenced by the hardware pipeline. | |
| 5442 | |
| 5443 // Naming convention: ialu or fpu | |
| 5444 // Then: _reg | |
| 5445 // Then: _reg if there is a 2nd register | |
| 5446 // Then: _long if it's a pair of instructions implementing a long | |
| 5447 // Then: _fat if it requires the big decoder | |
| 5448 // Or: _mem if it requires the big decoder and a memory unit. | |
| 5449 | |
| 5450 // Integer ALU reg operation | |
| 5451 pipe_class ialu_reg(rRegI dst) | |
| 5452 %{ | |
| 5453 single_instruction; | |
| 5454 dst : S4(write); | |
| 5455 dst : S3(read); | |
| 5456 DECODE : S0; // any decoder | |
| 5457 ALU : S3; // any alu | |
| 5458 %} | |
| 5459 | |
| 5460 // Long ALU reg operation | |
| 5461 pipe_class ialu_reg_long(rRegL dst) | |
| 5462 %{ | |
| 5463 instruction_count(2); | |
| 5464 dst : S4(write); | |
| 5465 dst : S3(read); | |
| 5466 DECODE : S0(2); // any 2 decoders | |
| 5467 ALU : S3(2); // both alus | |
| 5468 %} | |
| 5469 | |
| 5470 // Integer ALU reg operation using big decoder | |
| 5471 pipe_class ialu_reg_fat(rRegI dst) | |
| 5472 %{ | |
| 5473 single_instruction; | |
| 5474 dst : S4(write); | |
| 5475 dst : S3(read); | |
| 5476 D0 : S0; // big decoder only | |
| 5477 ALU : S3; // any alu | |
| 5478 %} | |
| 5479 | |
| 5480 // Long ALU reg operation using big decoder | |
| 5481 pipe_class ialu_reg_long_fat(rRegL dst) | |
| 5482 %{ | |
| 5483 instruction_count(2); | |
| 5484 dst : S4(write); | |
| 5485 dst : S3(read); | |
| 5486 D0 : S0(2); // big decoder only; twice | |
| 5487 ALU : S3(2); // any 2 alus | |
| 5488 %} | |
| 5489 | |
| 5490 // Integer ALU reg-reg operation | |
| 5491 pipe_class ialu_reg_reg(rRegI dst, rRegI src) | |
| 5492 %{ | |
| 5493 single_instruction; | |
| 5494 dst : S4(write); | |
| 5495 src : S3(read); | |
| 5496 DECODE : S0; // any decoder | |
| 5497 ALU : S3; // any alu | |
| 5498 %} | |
| 5499 | |
| 5500 // Long ALU reg-reg operation | |
| 5501 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src) | |
| 5502 %{ | |
| 5503 instruction_count(2); | |
| 5504 dst : S4(write); | |
| 5505 src : S3(read); | |
| 5506 DECODE : S0(2); // any 2 decoders | |
| 5507 ALU : S3(2); // both alus | |
| 5508 %} | |
| 5509 | |
| 5510 // Integer ALU reg-reg operation | |
| 5511 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) | |
| 5512 %{ | |
| 5513 single_instruction; | |
| 5514 dst : S4(write); | |
| 5515 src : S3(read); | |
| 5516 D0 : S0; // big decoder only | |
| 5517 ALU : S3; // any alu | |
| 5518 %} | |
| 5519 | |
| 5520 // Long ALU reg-reg operation | |
| 5521 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src) | |
| 5522 %{ | |
| 5523 instruction_count(2); | |
| 5524 dst : S4(write); | |
| 5525 src : S3(read); | |
| 5526 D0 : S0(2); // big decoder only; twice | |
| 5527 ALU : S3(2); // both alus | |
| 5528 %} | |
| 5529 | |
| 5530 // Integer ALU reg-mem operation | |
| 5531 pipe_class ialu_reg_mem(rRegI dst, memory mem) | |
| 5532 %{ | |
| 5533 single_instruction; | |
| 5534 dst : S5(write); | |
| 5535 mem : S3(read); | |
| 5536 D0 : S0; // big decoder only | |
| 5537 ALU : S4; // any alu | |
| 5538 MEM : S3; // any mem | |
| 5539 %} | |
| 5540 | |
| 5541 // Integer mem operation (prefetch) | |
| 5542 pipe_class ialu_mem(memory mem) | |
| 5543 %{ | |
| 5544 single_instruction; | |
| 5545 mem : S3(read); | |
| 5546 D0 : S0; // big decoder only | |
| 5547 MEM : S3; // any mem | |
| 5548 %} | |
| 5549 | |
| 5550 // Integer Store to Memory | |
| 5551 pipe_class ialu_mem_reg(memory mem, rRegI src) | |
| 5552 %{ | |
| 5553 single_instruction; | |
| 5554 mem : S3(read); | |
| 5555 src : S5(read); | |
| 5556 D0 : S0; // big decoder only | |
| 5557 ALU : S4; // any alu | |
| 5558 MEM : S3; | |
| 5559 %} | |
| 5560 | |
| 5561 // // Long Store to Memory | |
| 5562 // pipe_class ialu_mem_long_reg(memory mem, rRegL src) | |
| 5563 // %{ | |
| 5564 // instruction_count(2); | |
| 5565 // mem : S3(read); | |
| 5566 // src : S5(read); | |
| 5567 // D0 : S0(2); // big decoder only; twice | |
| 5568 // ALU : S4(2); // any 2 alus | |
| 5569 // MEM : S3(2); // Both mems | |
| 5570 // %} | |
| 5571 | |
| 5572 // Integer Store to Memory | |
| 5573 pipe_class ialu_mem_imm(memory mem) | |
| 5574 %{ | |
| 5575 single_instruction; | |
| 5576 mem : S3(read); | |
| 5577 D0 : S0; // big decoder only | |
| 5578 ALU : S4; // any alu | |
| 5579 MEM : S3; | |
| 5580 %} | |
| 5581 | |
| 5582 // Integer ALU0 reg-reg operation | |
| 5583 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) | |
| 5584 %{ | |
| 5585 single_instruction; | |
| 5586 dst : S4(write); | |
| 5587 src : S3(read); | |
| 5588 D0 : S0; // Big decoder only | |
| 5589 ALU0 : S3; // only alu0 | |
| 5590 %} | |
| 5591 | |
| 5592 // Integer ALU0 reg-mem operation | |
| 5593 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) | |
| 5594 %{ | |
| 5595 single_instruction; | |
| 5596 dst : S5(write); | |
| 5597 mem : S3(read); | |
| 5598 D0 : S0; // big decoder only | |
| 5599 ALU0 : S4; // ALU0 only | |
| 5600 MEM : S3; // any mem | |
| 5601 %} | |
| 5602 | |
| 5603 // Integer ALU reg-reg operation | |
| 5604 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2) | |
| 5605 %{ | |
| 5606 single_instruction; | |
| 5607 cr : S4(write); | |
| 5608 src1 : S3(read); | |
| 5609 src2 : S3(read); | |
| 5610 DECODE : S0; // any decoder | |
| 5611 ALU : S3; // any alu | |
| 5612 %} | |
| 5613 | |
| 5614 // Integer ALU reg-imm operation | |
| 5615 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1) | |
| 5616 %{ | |
| 5617 single_instruction; | |
| 5618 cr : S4(write); | |
| 5619 src1 : S3(read); | |
| 5620 DECODE : S0; // any decoder | |
| 5621 ALU : S3; // any alu | |
| 5622 %} | |
| 5623 | |
| 5624 // Integer ALU reg-mem operation | |
| 5625 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2) | |
| 5626 %{ | |
| 5627 single_instruction; | |
| 5628 cr : S4(write); | |
| 5629 src1 : S3(read); | |
| 5630 src2 : S3(read); | |
| 5631 D0 : S0; // big decoder only | |
| 5632 ALU : S4; // any alu | |
| 5633 MEM : S3; | |
| 5634 %} | |
| 5635 | |
| 5636 // Conditional move reg-reg | |
| 5637 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y) | |
| 5638 %{ | |
| 5639 instruction_count(4); | |
| 5640 y : S4(read); | |
| 5641 q : S3(read); | |
| 5642 p : S3(read); | |
| 5643 DECODE : S0(4); // any decoder | |
| 5644 %} | |
| 5645 | |
| 5646 // Conditional move reg-reg | |
| 5647 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr) | |
| 5648 %{ | |
| 5649 single_instruction; | |
| 5650 dst : S4(write); | |
| 5651 src : S3(read); | |
| 5652 cr : S3(read); | |
| 5653 DECODE : S0; // any decoder | |
| 5654 %} | |
| 5655 | |
| 5656 // Conditional move reg-mem | |
| 5657 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src) | |
| 5658 %{ | |
| 5659 single_instruction; | |
| 5660 dst : S4(write); | |
| 5661 src : S3(read); | |
| 5662 cr : S3(read); | |
| 5663 DECODE : S0; // any decoder | |
| 5664 MEM : S3; | |
| 5665 %} | |
| 5666 | |
| 5667 // Conditional move reg-reg long | |
| 5668 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src) | |
| 5669 %{ | |
| 5670 single_instruction; | |
| 5671 dst : S4(write); | |
| 5672 src : S3(read); | |
| 5673 cr : S3(read); | |
| 5674 DECODE : S0(2); // any 2 decoders | |
| 5675 %} | |
| 5676 | |
| 5677 // XXX | |
| 5678 // // Conditional move double reg-reg | |
| 5679 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src) | |
| 5680 // %{ | |
| 5681 // single_instruction; | |
| 5682 // dst : S4(write); | |
| 5683 // src : S3(read); | |
| 5684 // cr : S3(read); | |
| 5685 // DECODE : S0; // any decoder | |
| 5686 // %} | |
| 5687 | |
| 5688 // Float reg-reg operation | |
| 5689 pipe_class fpu_reg(regD dst) | |
| 5690 %{ | |
| 5691 instruction_count(2); | |
| 5692 dst : S3(read); | |
| 5693 DECODE : S0(2); // any 2 decoders | |
| 5694 FPU : S3; | |
| 5695 %} | |
| 5696 | |
| 5697 // Float reg-reg operation | |
| 5698 pipe_class fpu_reg_reg(regD dst, regD src) | |
| 5699 %{ | |
| 5700 instruction_count(2); | |
| 5701 dst : S4(write); | |
| 5702 src : S3(read); | |
| 5703 DECODE : S0(2); // any 2 decoders | |
| 5704 FPU : S3; | |
| 5705 %} | |
| 5706 | |
| 5707 // Float reg-reg operation | |
| 5708 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) | |
| 5709 %{ | |
| 5710 instruction_count(3); | |
| 5711 dst : S4(write); | |
| 5712 src1 : S3(read); | |
| 5713 src2 : S3(read); | |
| 5714 DECODE : S0(3); // any 3 decoders | |
| 5715 FPU : S3(2); | |
| 5716 %} | |
| 5717 | |
| 5718 // Float reg-reg operation | |
| 5719 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) | |
| 5720 %{ | |
| 5721 instruction_count(4); | |
| 5722 dst : S4(write); | |
| 5723 src1 : S3(read); | |
| 5724 src2 : S3(read); | |
| 5725 src3 : S3(read); | |
| 5726 DECODE : S0(4); // any 3 decoders | |
| 5727 FPU : S3(2); | |
| 5728 %} | |
| 5729 | |
| 5730 // Float reg-reg operation | |
| 5731 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) | |
| 5732 %{ | |
| 5733 instruction_count(4); | |
| 5734 dst : S4(write); | |
| 5735 src1 : S3(read); | |
| 5736 src2 : S3(read); | |
| 5737 src3 : S3(read); | |
| 5738 DECODE : S1(3); // any 3 decoders | |
| 5739 D0 : S0; // Big decoder only | |
| 5740 FPU : S3(2); | |
| 5741 MEM : S3; | |
| 5742 %} | |
| 5743 | |
| 5744 // Float reg-mem operation | |
| 5745 pipe_class fpu_reg_mem(regD dst, memory mem) | |
| 5746 %{ | |
| 5747 instruction_count(2); | |
| 5748 dst : S5(write); | |
| 5749 mem : S3(read); | |
| 5750 D0 : S0; // big decoder only | |
| 5751 DECODE : S1; // any decoder for FPU POP | |
| 5752 FPU : S4; | |
| 5753 MEM : S3; // any mem | |
| 5754 %} | |
| 5755 | |
| 5756 // Float reg-mem operation | |
| 5757 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) | |
| 5758 %{ | |
| 5759 instruction_count(3); | |
| 5760 dst : S5(write); | |
| 5761 src1 : S3(read); | |
| 5762 mem : S3(read); | |
| 5763 D0 : S0; // big decoder only | |
| 5764 DECODE : S1(2); // any decoder for FPU POP | |
| 5765 FPU : S4; | |
| 5766 MEM : S3; // any mem | |
| 5767 %} | |
| 5768 | |
| 5769 // Float mem-reg operation | |
| 5770 pipe_class fpu_mem_reg(memory mem, regD src) | |
| 5771 %{ | |
| 5772 instruction_count(2); | |
| 5773 src : S5(read); | |
| 5774 mem : S3(read); | |
| 5775 DECODE : S0; // any decoder for FPU PUSH | |
| 5776 D0 : S1; // big decoder only | |
| 5777 FPU : S4; | |
| 5778 MEM : S3; // any mem | |
| 5779 %} | |
| 5780 | |
| 5781 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) | |
| 5782 %{ | |
| 5783 instruction_count(3); | |
| 5784 src1 : S3(read); | |
| 5785 src2 : S3(read); | |
| 5786 mem : S3(read); | |
| 5787 DECODE : S0(2); // any decoder for FPU PUSH | |
| 5788 D0 : S1; // big decoder only | |
| 5789 FPU : S4; | |
| 5790 MEM : S3; // any mem | |
| 5791 %} | |
| 5792 | |
| 5793 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) | |
| 5794 %{ | |
| 5795 instruction_count(3); | |
| 5796 src1 : S3(read); | |
| 5797 src2 : S3(read); | |
| 5798 mem : S4(read); | |
| 5799 DECODE : S0; // any decoder for FPU PUSH | |
| 5800 D0 : S0(2); // big decoder only | |
| 5801 FPU : S4; | |
| 5802 MEM : S3(2); // any mem | |
| 5803 %} | |
| 5804 | |
| 5805 pipe_class fpu_mem_mem(memory dst, memory src1) | |
| 5806 %{ | |
| 5807 instruction_count(2); | |
| 5808 src1 : S3(read); | |
| 5809 dst : S4(read); | |
| 5810 D0 : S0(2); // big decoder only | |
| 5811 MEM : S3(2); // any mem | |
| 5812 %} | |
| 5813 | |
| 5814 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) | |
| 5815 %{ | |
| 5816 instruction_count(3); | |
| 5817 src1 : S3(read); | |
| 5818 src2 : S3(read); | |
| 5819 dst : S4(read); | |
| 5820 D0 : S0(3); // big decoder only | |
| 5821 FPU : S4; | |
| 5822 MEM : S3(3); // any mem | |
| 5823 %} | |
| 5824 | |
| 5825 pipe_class fpu_mem_reg_con(memory mem, regD src1) | |
| 5826 %{ | |
| 5827 instruction_count(3); | |
| 5828 src1 : S4(read); | |
| 5829 mem : S4(read); | |
| 5830 DECODE : S0; // any decoder for FPU PUSH | |
| 5831 D0 : S0(2); // big decoder only | |
| 5832 FPU : S4; | |
| 5833 MEM : S3(2); // any mem | |
| 5834 %} | |
| 5835 | |
| 5836 // Float load constant | |
| 5837 pipe_class fpu_reg_con(regD dst) | |
| 5838 %{ | |
| 5839 instruction_count(2); | |
| 5840 dst : S5(write); | |
| 5841 D0 : S0; // big decoder only for the load | |
| 5842 DECODE : S1; // any decoder for FPU POP | |
| 5843 FPU : S4; | |
| 5844 MEM : S3; // any mem | |
| 5845 %} | |
| 5846 | |
| 5847 // Float load constant | |
| 5848 pipe_class fpu_reg_reg_con(regD dst, regD src) | |
| 5849 %{ | |
| 5850 instruction_count(3); | |
| 5851 dst : S5(write); | |
| 5852 src : S3(read); | |
| 5853 D0 : S0; // big decoder only for the load | |
| 5854 DECODE : S1(2); // any decoder for FPU POP | |
| 5855 FPU : S4; | |
| 5856 MEM : S3; // any mem | |
| 5857 %} | |
| 5858 | |
| 5859 // UnConditional branch | |
| 5860 pipe_class pipe_jmp(label labl) | |
| 5861 %{ | |
| 5862 single_instruction; | |
| 5863 BR : S3; | |
| 5864 %} | |
| 5865 | |
| 5866 // Conditional branch | |
| 5867 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl) | |
| 5868 %{ | |
| 5869 single_instruction; | |
| 5870 cr : S1(read); | |
| 5871 BR : S3; | |
| 5872 %} | |
| 5873 | |
| 5874 // Allocation idiom | |
| 5875 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr) | |
| 5876 %{ | |
| 5877 instruction_count(1); force_serialization; | |
| 5878 fixed_latency(6); | |
| 5879 heap_ptr : S3(read); | |
| 5880 DECODE : S0(3); | |
| 5881 D0 : S2; | |
| 5882 MEM : S3; | |
| 5883 ALU : S3(2); | |
| 5884 dst : S5(write); | |
| 5885 BR : S5; | |
| 5886 %} | |
| 5887 | |
| 5888 // Generic big/slow expanded idiom | |
| 5889 pipe_class pipe_slow() | |
| 5890 %{ | |
| 5891 instruction_count(10); multiple_bundles; force_serialization; | |
| 5892 fixed_latency(100); | |
| 5893 D0 : S0(2); | |
| 5894 MEM : S3(2); | |
| 5895 %} | |
| 5896 | |
| 5897 // The real do-nothing guy | |
| 5898 pipe_class empty() | |
| 5899 %{ | |
| 5900 instruction_count(0); | |
| 5901 %} | |
| 5902 | |
| 5903 // Define the class for the Nop node | |
| 5904 define | |
| 5905 %{ | |
| 5906 MachNop = empty; | |
| 5907 %} | |
| 5908 | |
| 5909 %} | |
| 5910 | |
| 5911 //----------INSTRUCTIONS------------------------------------------------------- | |
| 5912 // | |
| 5913 // match -- States which machine-independent subtree may be replaced | |
| 5914 // by this instruction. | |
| 5915 // ins_cost -- The estimated cost of this instruction is used by instruction | |
| 5916 // selection to identify a minimum cost tree of machine | |
| 5917 // instructions that matches a tree of machine-independent | |
| 5918 // instructions. | |
| 5919 // format -- A string providing the disassembly for this instruction. | |
| 5920 // The value of an instruction's operand may be inserted | |
| 5921 // by referring to it with a '$' prefix. | |
| 5922 // opcode -- Three instruction opcodes may be provided. These are referred | |
| 5923 // to within an encode class as $primary, $secondary, and $tertiary | |
| 5924 // rrspectively. The primary opcode is commonly used to | |
| 5925 // indicate the type of machine instruction, while secondary | |
| 5926 // and tertiary are often used for prefix options or addressing | |
| 5927 // modes. | |
| 5928 // ins_encode -- A list of encode classes with parameters. The encode class | |
| 5929 // name must have been defined in an 'enc_class' specification | |
| 5930 // in the encode section of the architecture description. | |
| 5931 | |
| 5932 | |
| 5933 //----------Load/Store/Move Instructions--------------------------------------- | |
| 5934 //----------Load Instructions-------------------------------------------------- | |
| 5935 | |
| 5936 // Load Byte (8 bit signed) | |
| 5937 instruct loadB(rRegI dst, memory mem) | |
| 5938 %{ | |
| 5939 match(Set dst (LoadB mem)); | |
| 5940 | |
| 5941 ins_cost(125); | |
| 5942 format %{ "movsbl $dst, $mem\t# byte" %} | |
| 624 | 5943 |
| 5944 ins_encode %{ | |
| 5945 __ movsbl($dst$$Register, $mem$$Address); | |
| 5946 %} | |
| 5947 | |
| 0 | 5948 ins_pipe(ialu_reg_mem); |
| 5949 %} | |
| 5950 | |
| 624 | 5951 // Load Byte (8 bit signed) into Long Register |
| 5952 instruct loadB2L(rRegL dst, memory mem) | |
| 5953 %{ | |
| 5954 match(Set dst (ConvI2L (LoadB mem))); | |
| 5955 | |
| 5956 ins_cost(125); | |
| 5957 format %{ "movsbq $dst, $mem\t# byte -> long" %} | |
| 5958 | |
| 5959 ins_encode %{ | |
| 5960 __ movsbq($dst$$Register, $mem$$Address); | |
| 5961 %} | |
| 5962 | |
| 5963 ins_pipe(ialu_reg_mem); | |
| 5964 %} | |
| 5965 | |
| 5966 // Load Unsigned Byte (8 bit UNsigned) | |
| 5967 instruct loadUB(rRegI dst, memory mem) | |
| 5968 %{ | |
| 5969 match(Set dst (LoadUB mem)); | |
| 0 | 5970 |
| 5971 ins_cost(125); | |
| 5972 format %{ "movzbl $dst, $mem\t# ubyte" %} | |
| 624 | 5973 |
| 5974 ins_encode %{ | |
| 5975 __ movzbl($dst$$Register, $mem$$Address); | |
| 5976 %} | |
| 5977 | |
| 0 | 5978 ins_pipe(ialu_reg_mem); |
| 5979 %} | |
| 5980 | |
| 624 | 5981 // Load Unsigned Byte (8 bit UNsigned) into Long Register |
| 5982 instruct loadUB2L(rRegL dst, memory mem) | |
| 5983 %{ | |
| 5984 match(Set dst (ConvI2L (LoadUB mem))); | |
| 5985 | |
| 5986 ins_cost(125); | |
| 5987 format %{ "movzbq $dst, $mem\t# ubyte -> long" %} | |
| 5988 | |
| 5989 ins_encode %{ | |
| 5990 __ movzbq($dst$$Register, $mem$$Address); | |
| 5991 %} | |
| 5992 | |
| 5993 ins_pipe(ialu_reg_mem); | |
| 5994 %} | |
| 0 | 5995 |
| 824 | 5996 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register |
| 5997 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{ | |
| 5998 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); | |
| 5999 effect(KILL cr); | |
| 6000 | |
| 6001 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t" | |
| 6002 "andl $dst, $mask" %} | |
| 6003 ins_encode %{ | |
| 6004 Register Rdst = $dst$$Register; | |
| 6005 __ movzbq(Rdst, $mem$$Address); | |
| 6006 __ andl(Rdst, $mask$$constant); | |
| 6007 %} | |
| 6008 ins_pipe(ialu_reg_mem); | |
| 6009 %} | |
| 6010 | |
| 0 | 6011 // Load Short (16 bit signed) |
| 6012 instruct loadS(rRegI dst, memory mem) | |
| 6013 %{ | |
| 6014 match(Set dst (LoadS mem)); | |
| 6015 | |
| 624 | 6016 ins_cost(125); |
| 0 | 6017 format %{ "movswl $dst, $mem\t# short" %} |
| 624 | 6018 |
| 6019 ins_encode %{ | |
| 6020 __ movswl($dst$$Register, $mem$$Address); | |
| 6021 %} | |
| 6022 | |
| 0 | 6023 ins_pipe(ialu_reg_mem); |
| 6024 %} | |
| 6025 | |
| 785 | 6026 // Load Short (16 bit signed) to Byte (8 bit signed) |
| 6027 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6028 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); | |
| 6029 | |
| 6030 ins_cost(125); | |
| 6031 format %{ "movsbl $dst, $mem\t# short -> byte" %} | |
| 6032 ins_encode %{ | |
| 6033 __ movsbl($dst$$Register, $mem$$Address); | |
| 6034 %} | |
| 6035 ins_pipe(ialu_reg_mem); | |
| 6036 %} | |
| 6037 | |
| 624 | 6038 // Load Short (16 bit signed) into Long Register |
| 6039 instruct loadS2L(rRegL dst, memory mem) | |
| 6040 %{ | |
| 6041 match(Set dst (ConvI2L (LoadS mem))); | |
| 6042 | |
| 6043 ins_cost(125); | |
| 6044 format %{ "movswq $dst, $mem\t# short -> long" %} | |
| 6045 | |
| 6046 ins_encode %{ | |
| 6047 __ movswq($dst$$Register, $mem$$Address); | |
| 6048 %} | |
| 6049 | |
| 6050 ins_pipe(ialu_reg_mem); | |
| 6051 %} | |
| 0 | 6052 |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
6053 // Load Unsigned Short/Char (16 bit UNsigned) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
6054 instruct loadUS(rRegI dst, memory mem) |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
6055 %{ |
|
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
6056 match(Set dst (LoadUS mem)); |
| 0 | 6057 |
| 6058 ins_cost(125); | |
|
558
3b5ac9e7e6ea
6796746: rename LoadC (char) opcode class to LoadUS (unsigned short)
twisti
parents:
420
diff
changeset
|
6059 format %{ "movzwl $dst, $mem\t# ushort/char" %} |
| 624 | 6060 |
| 6061 ins_encode %{ | |
| 6062 __ movzwl($dst$$Register, $mem$$Address); | |
| 6063 %} | |
| 6064 | |
| 0 | 6065 ins_pipe(ialu_reg_mem); |
| 6066 %} | |
| 6067 | |
| 785 | 6068 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) |
| 6069 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6070 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); | |
| 6071 | |
| 6072 ins_cost(125); | |
| 6073 format %{ "movsbl $dst, $mem\t# ushort -> byte" %} | |
| 6074 ins_encode %{ | |
| 6075 __ movsbl($dst$$Register, $mem$$Address); | |
| 6076 %} | |
| 6077 ins_pipe(ialu_reg_mem); | |
| 6078 %} | |
| 6079 | |
| 624 | 6080 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register |
| 6081 instruct loadUS2L(rRegL dst, memory mem) | |
| 6082 %{ | |
| 6083 match(Set dst (ConvI2L (LoadUS mem))); | |
| 6084 | |
| 6085 ins_cost(125); | |
| 6086 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %} | |
| 6087 | |
| 6088 ins_encode %{ | |
| 6089 __ movzwq($dst$$Register, $mem$$Address); | |
| 6090 %} | |
| 6091 | |
| 6092 ins_pipe(ialu_reg_mem); | |
| 6093 %} | |
| 0 | 6094 |
| 824 | 6095 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register |
| 6096 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 6097 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 6098 | |
| 6099 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %} | |
| 6100 ins_encode %{ | |
| 6101 __ movzbq($dst$$Register, $mem$$Address); | |
| 6102 %} | |
| 6103 ins_pipe(ialu_reg_mem); | |
| 6104 %} | |
| 6105 | |
| 6106 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register | |
| 6107 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{ | |
| 6108 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); | |
| 6109 effect(KILL cr); | |
| 6110 | |
| 6111 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t" | |
| 6112 "andl $dst, $mask" %} | |
| 6113 ins_encode %{ | |
| 6114 Register Rdst = $dst$$Register; | |
| 6115 __ movzwq(Rdst, $mem$$Address); | |
| 6116 __ andl(Rdst, $mask$$constant); | |
| 6117 %} | |
| 6118 ins_pipe(ialu_reg_mem); | |
| 6119 %} | |
| 6120 | |
| 0 | 6121 // Load Integer |
| 6122 instruct loadI(rRegI dst, memory mem) | |
| 6123 %{ | |
| 6124 match(Set dst (LoadI mem)); | |
| 6125 | |
| 624 | 6126 ins_cost(125); |
| 0 | 6127 format %{ "movl $dst, $mem\t# int" %} |
| 624 | 6128 |
| 6129 ins_encode %{ | |
| 6130 __ movl($dst$$Register, $mem$$Address); | |
| 6131 %} | |
| 6132 | |
| 6133 ins_pipe(ialu_reg_mem); | |
| 6134 %} | |
| 6135 | |
| 785 | 6136 // Load Integer (32 bit signed) to Byte (8 bit signed) |
| 6137 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ | |
| 6138 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); | |
| 6139 | |
| 6140 ins_cost(125); | |
| 6141 format %{ "movsbl $dst, $mem\t# int -> byte" %} | |
| 6142 ins_encode %{ | |
| 6143 __ movsbl($dst$$Register, $mem$$Address); | |
| 6144 %} | |
| 6145 ins_pipe(ialu_reg_mem); | |
| 6146 %} | |
| 6147 | |
| 6148 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) | |
| 6149 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ | |
| 6150 match(Set dst (AndI (LoadI mem) mask)); | |
| 6151 | |
| 6152 ins_cost(125); | |
| 6153 format %{ "movzbl $dst, $mem\t# int -> ubyte" %} | |
| 6154 ins_encode %{ | |
| 6155 __ movzbl($dst$$Register, $mem$$Address); | |
| 6156 %} | |
| 6157 ins_pipe(ialu_reg_mem); | |
| 6158 %} | |
| 6159 | |
| 6160 // Load Integer (32 bit signed) to Short (16 bit signed) | |
| 6161 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ | |
| 6162 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); | |
| 6163 | |
| 6164 ins_cost(125); | |
| 6165 format %{ "movswl $dst, $mem\t# int -> short" %} | |
| 6166 ins_encode %{ | |
| 6167 __ movswl($dst$$Register, $mem$$Address); | |
| 6168 %} | |
| 6169 ins_pipe(ialu_reg_mem); | |
| 6170 %} | |
| 6171 | |
| 6172 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) | |
| 6173 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ | |
| 6174 match(Set dst (AndI (LoadI mem) mask)); | |
| 6175 | |
| 6176 ins_cost(125); | |
| 6177 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %} | |
| 6178 ins_encode %{ | |
| 6179 __ movzwl($dst$$Register, $mem$$Address); | |
| 6180 %} | |
| 6181 ins_pipe(ialu_reg_mem); | |
| 6182 %} | |
| 6183 | |
| 624 | 6184 // Load Integer into Long Register |
| 6185 instruct loadI2L(rRegL dst, memory mem) | |
| 6186 %{ | |
| 6187 match(Set dst (ConvI2L (LoadI mem))); | |
| 6188 | |
| 6189 ins_cost(125); | |
| 6190 format %{ "movslq $dst, $mem\t# int -> long" %} | |
| 6191 | |
| 6192 ins_encode %{ | |
| 6193 __ movslq($dst$$Register, $mem$$Address); | |
| 6194 %} | |
| 6195 | |
| 6196 ins_pipe(ialu_reg_mem); | |
| 6197 %} | |
| 6198 | |
| 824 | 6199 // Load Integer with mask 0xFF into Long Register |
| 6200 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ | |
| 6201 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6202 | |
| 6203 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %} | |
| 6204 ins_encode %{ | |
| 6205 __ movzbq($dst$$Register, $mem$$Address); | |
| 6206 %} | |
| 6207 ins_pipe(ialu_reg_mem); | |
| 6208 %} | |
| 6209 | |
| 6210 // Load Integer with mask 0xFFFF into Long Register | |
| 6211 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{ | |
| 6212 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6213 | |
| 6214 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %} | |
| 6215 ins_encode %{ | |
| 6216 __ movzwq($dst$$Register, $mem$$Address); | |
| 6217 %} | |
| 6218 ins_pipe(ialu_reg_mem); | |
| 6219 %} | |
| 6220 | |
| 6221 // Load Integer with a 32-bit mask into Long Register | |
| 6222 instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{ | |
| 6223 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); | |
| 6224 effect(KILL cr); | |
| 6225 | |
| 6226 format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t" | |
| 6227 "andl $dst, $mask" %} | |
| 6228 ins_encode %{ | |
| 6229 Register Rdst = $dst$$Register; | |
| 6230 __ movl(Rdst, $mem$$Address); | |
| 6231 __ andl(Rdst, $mask$$constant); | |
| 6232 %} | |
| 6233 ins_pipe(ialu_reg_mem); | |
| 6234 %} | |
| 6235 | |
| 624 | 6236 // Load Unsigned Integer into Long Register |
| 6237 instruct loadUI2L(rRegL dst, memory mem) | |
| 6238 %{ | |
| 6239 match(Set dst (LoadUI2L mem)); | |
| 6240 | |
| 6241 ins_cost(125); | |
| 6242 format %{ "movl $dst, $mem\t# uint -> long" %} | |
| 6243 | |
| 6244 ins_encode %{ | |
| 6245 __ movl($dst$$Register, $mem$$Address); | |
| 6246 %} | |
| 6247 | |
| 0 | 6248 ins_pipe(ialu_reg_mem); |
| 6249 %} | |
| 6250 | |
| 6251 // Load Long | |
| 6252 instruct loadL(rRegL dst, memory mem) | |
| 6253 %{ | |
| 6254 match(Set dst (LoadL mem)); | |
| 6255 | |
| 624 | 6256 ins_cost(125); |
| 0 | 6257 format %{ "movq $dst, $mem\t# long" %} |
| 624 | 6258 |
| 6259 ins_encode %{ | |
| 6260 __ movq($dst$$Register, $mem$$Address); | |
| 6261 %} | |
| 6262 | |
| 0 | 6263 ins_pipe(ialu_reg_mem); // XXX |
| 6264 %} | |
| 6265 | |
| 6266 // Load Range | |
| 6267 instruct loadRange(rRegI dst, memory mem) | |
| 6268 %{ | |
| 6269 match(Set dst (LoadRange mem)); | |
| 6270 | |
| 6271 ins_cost(125); // XXX | |
| 6272 format %{ "movl $dst, $mem\t# range" %} | |
| 6273 opcode(0x8B); | |
| 6274 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6275 ins_pipe(ialu_reg_mem); | |
| 6276 %} | |
| 6277 | |
| 6278 // Load Pointer | |
| 6279 instruct loadP(rRegP dst, memory mem) | |
| 6280 %{ | |
| 6281 match(Set dst (LoadP mem)); | |
| 6282 | |
| 6283 ins_cost(125); // XXX | |
| 6284 format %{ "movq $dst, $mem\t# ptr" %} | |
| 6285 opcode(0x8B); | |
| 6286 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6287 ins_pipe(ialu_reg_mem); // XXX | |
| 6288 %} | |
| 6289 | |
|
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6290 // Load Compressed Pointer |
| 163 | 6291 instruct loadN(rRegN dst, memory mem) |
|
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6292 %{ |
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6293 match(Set dst (LoadN mem)); |
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6294 |
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6295 ins_cost(125); // XXX |
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6296 format %{ "movl $dst, $mem\t# compressed ptr" %} |
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6297 ins_encode %{ |
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6298 __ movl($dst$$Register, $mem$$Address); |
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6299 %} |
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6300 ins_pipe(ialu_reg_mem); // XXX |
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6301 %} |
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6302 |
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6303 |
| 0 | 6304 // Load Klass Pointer |
| 6305 instruct loadKlass(rRegP dst, memory mem) | |
| 6306 %{ | |
| 6307 match(Set dst (LoadKlass mem)); | |
| 6308 | |
| 6309 ins_cost(125); // XXX | |
| 6310 format %{ "movq $dst, $mem\t# class" %} | |
| 6311 opcode(0x8B); | |
| 6312 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6313 ins_pipe(ialu_reg_mem); // XXX | |
| 6314 %} | |
| 6315 | |
|
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6316 // Load narrow Klass Pointer |
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6317 instruct loadNKlass(rRegN dst, memory mem) |
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6318 %{ |
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6319 match(Set dst (LoadNKlass mem)); |
|
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6320 |
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6321 ins_cost(125); // XXX |
|
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6322 format %{ "movl $dst, $mem\t# compressed klass ptr" %} |
|
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6323 ins_encode %{ |
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6324 __ movl($dst$$Register, $mem$$Address); |
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6325 %} |
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6326 ins_pipe(ialu_reg_mem); // XXX |
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6327 %} |
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6328 |
| 0 | 6329 // Load Float |
| 6330 instruct loadF(regF dst, memory mem) | |
| 6331 %{ | |
| 6332 match(Set dst (LoadF mem)); | |
| 6333 | |
| 6334 ins_cost(145); // XXX | |
| 6335 format %{ "movss $dst, $mem\t# float" %} | |
| 6336 opcode(0xF3, 0x0F, 0x10); | |
| 6337 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
| 6338 ins_pipe(pipe_slow); // XXX | |
| 6339 %} | |
| 6340 | |
| 6341 // Load Double | |
| 6342 instruct loadD_partial(regD dst, memory mem) | |
| 6343 %{ | |
| 6344 predicate(!UseXmmLoadAndClearUpper); | |
| 6345 match(Set dst (LoadD mem)); | |
| 6346 | |
| 6347 ins_cost(145); // XXX | |
| 6348 format %{ "movlpd $dst, $mem\t# double" %} | |
| 6349 opcode(0x66, 0x0F, 0x12); | |
| 6350 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
| 6351 ins_pipe(pipe_slow); // XXX | |
| 6352 %} | |
| 6353 | |
| 6354 instruct loadD(regD dst, memory mem) | |
| 6355 %{ | |
| 6356 predicate(UseXmmLoadAndClearUpper); | |
| 6357 match(Set dst (LoadD mem)); | |
| 6358 | |
| 6359 ins_cost(145); // XXX | |
| 6360 format %{ "movsd $dst, $mem\t# double" %} | |
| 6361 opcode(0xF2, 0x0F, 0x10); | |
| 6362 ins_encode(OpcP, REX_reg_mem(dst, mem), OpcS, OpcT, reg_mem(dst, mem)); | |
| 6363 ins_pipe(pipe_slow); // XXX | |
| 6364 %} | |
| 6365 | |
| 6366 // Load Aligned Packed Byte to XMM register | |
| 6367 instruct loadA8B(regD dst, memory mem) %{ | |
| 6368 match(Set dst (Load8B mem)); | |
| 6369 ins_cost(125); | |
| 6370 format %{ "MOVQ $dst,$mem\t! packed8B" %} | |
| 6371 ins_encode( movq_ld(dst, mem)); | |
| 6372 ins_pipe( pipe_slow ); | |
| 6373 %} | |
| 6374 | |
| 6375 // Load Aligned Packed Short to XMM register | |
| 6376 instruct loadA4S(regD dst, memory mem) %{ | |
| 6377 match(Set dst (Load4S mem)); | |
| 6378 ins_cost(125); | |
| 6379 format %{ "MOVQ $dst,$mem\t! packed4S" %} | |
| 6380 ins_encode( movq_ld(dst, mem)); | |
| 6381 ins_pipe( pipe_slow ); | |
| 6382 %} | |
| 6383 | |
| 6384 // Load Aligned Packed Char to XMM register | |
| 6385 instruct loadA4C(regD dst, memory mem) %{ | |
| 6386 match(Set dst (Load4C mem)); | |
| 6387 ins_cost(125); | |
| 6388 format %{ "MOVQ $dst,$mem\t! packed4C" %} | |
| 6389 ins_encode( movq_ld(dst, mem)); | |
| 6390 ins_pipe( pipe_slow ); | |
| 6391 %} | |
| 6392 | |
| 6393 // Load Aligned Packed Integer to XMM register | |
| 6394 instruct load2IU(regD dst, memory mem) %{ | |
| 6395 match(Set dst (Load2I mem)); | |
| 6396 ins_cost(125); | |
| 6397 format %{ "MOVQ $dst,$mem\t! packed2I" %} | |
| 6398 ins_encode( movq_ld(dst, mem)); | |
| 6399 ins_pipe( pipe_slow ); | |
| 6400 %} | |
| 6401 | |
| 6402 // Load Aligned Packed Single to XMM | |
| 6403 instruct loadA2F(regD dst, memory mem) %{ | |
| 6404 match(Set dst (Load2F mem)); | |
| 6405 ins_cost(145); | |
| 6406 format %{ "MOVQ $dst,$mem\t! packed2F" %} | |
| 6407 ins_encode( movq_ld(dst, mem)); | |
| 6408 ins_pipe( pipe_slow ); | |
| 6409 %} | |
| 6410 | |
| 6411 // Load Effective Address | |
| 6412 instruct leaP8(rRegP dst, indOffset8 mem) | |
| 6413 %{ | |
| 6414 match(Set dst mem); | |
| 6415 | |
| 6416 ins_cost(110); // XXX | |
| 6417 format %{ "leaq $dst, $mem\t# ptr 8" %} | |
| 6418 opcode(0x8D); | |
| 6419 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6420 ins_pipe(ialu_reg_reg_fat); | |
| 6421 %} | |
| 6422 | |
| 6423 instruct leaP32(rRegP dst, indOffset32 mem) | |
| 6424 %{ | |
| 6425 match(Set dst mem); | |
| 6426 | |
| 6427 ins_cost(110); | |
| 6428 format %{ "leaq $dst, $mem\t# ptr 32" %} | |
| 6429 opcode(0x8D); | |
| 6430 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6431 ins_pipe(ialu_reg_reg_fat); | |
| 6432 %} | |
| 6433 | |
| 6434 // instruct leaPIdx(rRegP dst, indIndex mem) | |
| 6435 // %{ | |
| 6436 // match(Set dst mem); | |
| 6437 | |
| 6438 // ins_cost(110); | |
| 6439 // format %{ "leaq $dst, $mem\t# ptr idx" %} | |
| 6440 // opcode(0x8D); | |
| 6441 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6442 // ins_pipe(ialu_reg_reg_fat); | |
| 6443 // %} | |
| 6444 | |
| 6445 instruct leaPIdxOff(rRegP dst, indIndexOffset mem) | |
| 6446 %{ | |
| 6447 match(Set dst mem); | |
| 6448 | |
| 6449 ins_cost(110); | |
| 6450 format %{ "leaq $dst, $mem\t# ptr idxoff" %} | |
| 6451 opcode(0x8D); | |
| 6452 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6453 ins_pipe(ialu_reg_reg_fat); | |
| 6454 %} | |
| 6455 | |
| 6456 instruct leaPIdxScale(rRegP dst, indIndexScale mem) | |
| 6457 %{ | |
| 6458 match(Set dst mem); | |
| 6459 | |
| 6460 ins_cost(110); | |
| 6461 format %{ "leaq $dst, $mem\t# ptr idxscale" %} | |
| 6462 opcode(0x8D); | |
| 6463 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6464 ins_pipe(ialu_reg_reg_fat); | |
| 6465 %} | |
| 6466 | |
| 6467 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem) | |
| 6468 %{ | |
| 6469 match(Set dst mem); | |
| 6470 | |
| 6471 ins_cost(110); | |
| 6472 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %} | |
| 6473 opcode(0x8D); | |
| 6474 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 6475 ins_pipe(ialu_reg_reg_fat); | |
| 6476 %} | |
| 6477 | |
|
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6478 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem) |
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6479 %{ |
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6480 match(Set dst mem); |
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6481 |
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6482 ins_cost(110); |
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changeset
|
6483 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6484 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6485 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6486 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6487 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6488 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6489 // Load Effective Address which uses Narrow (32-bits) oop |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6490 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6491 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6492 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6493 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6494 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6495 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6496 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6497 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6498 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6499 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6500 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6501 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6502 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6503 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6504 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6505 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6506 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6507 ins_cost(110); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6508 format %{ "leaq $dst, $mem\t# ptr off8narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6509 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6510 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6511 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6512 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6513 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6514 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6515 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6516 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6517 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6518 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6519 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6520 format %{ "leaq $dst, $mem\t# ptr off32narrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6521 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6522 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6523 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6524 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6525 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6526 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6527 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6528 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6529 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6530 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6531 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6532 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6533 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6534 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6535 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6536 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6537 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6538 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6539 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6540 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6541 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6542 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6543 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6544 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6545 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6546 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6547 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6548 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6549 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6550 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6551 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6552 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6553 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6554 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6555 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6556 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6557 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6558 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6559 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6560 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6561 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6562 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6563 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6564 predicate(Universe::narrow_oop_shift() == 0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6565 match(Set dst mem); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6566 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6567 ins_cost(110); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6568 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6569 opcode(0x8D); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6570 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6571 ins_pipe(ialu_reg_reg_fat); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6572 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6573 |
| 0 | 6574 instruct loadConI(rRegI dst, immI src) |
| 6575 %{ | |
| 6576 match(Set dst src); | |
| 6577 | |
| 6578 format %{ "movl $dst, $src\t# int" %} | |
| 6579 ins_encode(load_immI(dst, src)); | |
| 6580 ins_pipe(ialu_reg_fat); // XXX | |
| 6581 %} | |
| 6582 | |
| 6583 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr) | |
| 6584 %{ | |
| 6585 match(Set dst src); | |
| 6586 effect(KILL cr); | |
| 6587 | |
| 6588 ins_cost(50); | |
| 6589 format %{ "xorl $dst, $dst\t# int" %} | |
| 6590 opcode(0x33); /* + rd */ | |
| 6591 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 6592 ins_pipe(ialu_reg); | |
| 6593 %} | |
| 6594 | |
| 6595 instruct loadConL(rRegL dst, immL src) | |
| 6596 %{ | |
| 6597 match(Set dst src); | |
| 6598 | |
| 6599 ins_cost(150); | |
| 6600 format %{ "movq $dst, $src\t# long" %} | |
| 6601 ins_encode(load_immL(dst, src)); | |
| 6602 ins_pipe(ialu_reg); | |
| 6603 %} | |
| 6604 | |
| 6605 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr) | |
| 6606 %{ | |
| 6607 match(Set dst src); | |
| 6608 effect(KILL cr); | |
| 6609 | |
| 6610 ins_cost(50); | |
| 6611 format %{ "xorl $dst, $dst\t# long" %} | |
| 6612 opcode(0x33); /* + rd */ | |
| 6613 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 6614 ins_pipe(ialu_reg); // XXX | |
| 6615 %} | |
| 6616 | |
| 6617 instruct loadConUL32(rRegL dst, immUL32 src) | |
| 6618 %{ | |
| 6619 match(Set dst src); | |
| 6620 | |
| 6621 ins_cost(60); | |
| 6622 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %} | |
| 6623 ins_encode(load_immUL32(dst, src)); | |
| 6624 ins_pipe(ialu_reg); | |
| 6625 %} | |
| 6626 | |
| 6627 instruct loadConL32(rRegL dst, immL32 src) | |
| 6628 %{ | |
| 6629 match(Set dst src); | |
| 6630 | |
| 6631 ins_cost(70); | |
| 6632 format %{ "movq $dst, $src\t# long (32-bit)" %} | |
| 6633 ins_encode(load_immL32(dst, src)); | |
| 6634 ins_pipe(ialu_reg); | |
| 6635 %} | |
| 6636 | |
| 6637 instruct loadConP(rRegP dst, immP src) | |
| 6638 %{ | |
| 6639 match(Set dst src); | |
| 6640 | |
| 6641 format %{ "movq $dst, $src\t# ptr" %} | |
| 6642 ins_encode(load_immP(dst, src)); | |
| 6643 ins_pipe(ialu_reg_fat); // XXX | |
| 6644 %} | |
| 6645 | |
| 6646 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr) | |
| 6647 %{ | |
| 6648 match(Set dst src); | |
| 6649 effect(KILL cr); | |
| 6650 | |
| 6651 ins_cost(50); | |
| 6652 format %{ "xorl $dst, $dst\t# ptr" %} | |
| 6653 opcode(0x33); /* + rd */ | |
| 6654 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst)); | |
| 6655 ins_pipe(ialu_reg); | |
| 6656 %} | |
| 6657 | |
| 6658 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr) | |
| 6659 %{ | |
| 6660 match(Set dst src); | |
| 6661 effect(KILL cr); | |
| 6662 | |
| 6663 ins_cost(60); | |
| 6664 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %} | |
| 6665 ins_encode(load_immP31(dst, src)); | |
| 6666 ins_pipe(ialu_reg); | |
| 6667 %} | |
| 6668 | |
| 6669 instruct loadConF(regF dst, immF src) | |
| 6670 %{ | |
| 6671 match(Set dst src); | |
| 6672 ins_cost(125); | |
| 6673 | |
| 6674 format %{ "movss $dst, [$src]" %} | |
| 6675 ins_encode(load_conF(dst, src)); | |
| 6676 ins_pipe(pipe_slow); | |
| 6677 %} | |
| 6678 | |
|
113
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6679 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{ |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6680 match(Set dst src); |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6681 effect(KILL cr); |
|
124
b130b98db9cf
6689060: Escape Analysis does not work with Compressed Oops
kvn
parents:
113
diff
changeset
|
6682 format %{ "xorq $dst, $src\t# compressed NULL ptr" %} |
|
113
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6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
parents:
71
diff
changeset
|
6683 ins_encode %{ |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
6684 __ xorq($dst$$Register, $dst$$Register); |
|
113
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coleenp
parents:
71
diff
changeset
|
6685 %} |
|
ba764ed4b6f2
6420645: Create a vm that uses compressed oops for up to 32gb heapsizes
coleenp
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6686 ins_pipe(ialu_reg); |
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6687 %} |
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6688 |
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6689 instruct loadConN(rRegN dst, immN src) %{ |
|
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6690 match(Set dst src); |
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6691 |
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6692 ins_cost(125); |
|
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6693 format %{ "movl $dst, $src\t# compressed ptr" %} |
|
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6694 ins_encode %{ |
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6695 address con = (address)$src$$constant; |
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6696 if (con == NULL) { |
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6697 ShouldNotReachHere(); |
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6698 } else { |
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6699 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant); |
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6700 } |
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6701 %} |
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6702 ins_pipe(ialu_reg_fat); // XXX |
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6703 %} |
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6704 |
| 0 | 6705 instruct loadConF0(regF dst, immF0 src) |
| 6706 %{ | |
| 6707 match(Set dst src); | |
| 6708 ins_cost(100); | |
| 6709 | |
| 6710 format %{ "xorps $dst, $dst\t# float 0.0" %} | |
| 6711 opcode(0x0F, 0x57); | |
| 6712 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 6713 ins_pipe(pipe_slow); | |
| 6714 %} | |
| 6715 | |
| 6716 // Use the same format since predicate() can not be used here. | |
| 6717 instruct loadConD(regD dst, immD src) | |
| 6718 %{ | |
| 6719 match(Set dst src); | |
| 6720 ins_cost(125); | |
| 6721 | |
| 6722 format %{ "movsd $dst, [$src]" %} | |
| 6723 ins_encode(load_conD(dst, src)); | |
| 6724 ins_pipe(pipe_slow); | |
| 6725 %} | |
| 6726 | |
| 6727 instruct loadConD0(regD dst, immD0 src) | |
| 6728 %{ | |
| 6729 match(Set dst src); | |
| 6730 ins_cost(100); | |
| 6731 | |
| 6732 format %{ "xorpd $dst, $dst\t# double 0.0" %} | |
| 6733 opcode(0x66, 0x0F, 0x57); | |
| 6734 ins_encode(OpcP, REX_reg_reg(dst, dst), OpcS, OpcT, reg_reg(dst, dst)); | |
| 6735 ins_pipe(pipe_slow); | |
| 6736 %} | |
| 6737 | |
| 6738 instruct loadSSI(rRegI dst, stackSlotI src) | |
| 6739 %{ | |
| 6740 match(Set dst src); | |
| 6741 | |
| 6742 ins_cost(125); | |
| 6743 format %{ "movl $dst, $src\t# int stk" %} | |
| 6744 opcode(0x8B); | |
| 6745 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 6746 ins_pipe(ialu_reg_mem); | |
| 6747 %} | |
| 6748 | |
| 6749 instruct loadSSL(rRegL dst, stackSlotL src) | |
| 6750 %{ | |
| 6751 match(Set dst src); | |
| 6752 | |
| 6753 ins_cost(125); | |
| 6754 format %{ "movq $dst, $src\t# long stk" %} | |
| 6755 opcode(0x8B); | |
| 6756 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 6757 ins_pipe(ialu_reg_mem); | |
| 6758 %} | |
| 6759 | |
| 6760 instruct loadSSP(rRegP dst, stackSlotP src) | |
| 6761 %{ | |
| 6762 match(Set dst src); | |
| 6763 | |
| 6764 ins_cost(125); | |
| 6765 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 6766 opcode(0x8B); | |
| 6767 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 6768 ins_pipe(ialu_reg_mem); | |
| 6769 %} | |
| 6770 | |
| 6771 instruct loadSSF(regF dst, stackSlotF src) | |
| 6772 %{ | |
| 6773 match(Set dst src); | |
| 6774 | |
| 6775 ins_cost(125); | |
| 6776 format %{ "movss $dst, $src\t# float stk" %} | |
| 6777 opcode(0xF3, 0x0F, 0x10); | |
| 6778 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 6779 ins_pipe(pipe_slow); // XXX | |
| 6780 %} | |
| 6781 | |
| 6782 // Use the same format since predicate() can not be used here. | |
| 6783 instruct loadSSD(regD dst, stackSlotD src) | |
| 6784 %{ | |
| 6785 match(Set dst src); | |
| 6786 | |
| 6787 ins_cost(125); | |
| 6788 format %{ "movsd $dst, $src\t# double stk" %} | |
| 6789 ins_encode %{ | |
| 6790 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); | |
| 6791 %} | |
| 6792 ins_pipe(pipe_slow); // XXX | |
| 6793 %} | |
| 6794 | |
| 6795 // Prefetch instructions. | |
| 6796 // Must be safe to execute with invalid address (cannot fault). | |
| 6797 | |
| 6798 instruct prefetchr( memory mem ) %{ | |
| 6799 predicate(ReadPrefetchInstr==3); | |
| 6800 match(PrefetchRead mem); | |
| 6801 ins_cost(125); | |
| 6802 | |
| 6803 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} | |
| 6804 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */ | |
| 6805 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
| 6806 ins_pipe(ialu_mem); | |
| 6807 %} | |
| 6808 | |
| 6809 instruct prefetchrNTA( memory mem ) %{ | |
| 6810 predicate(ReadPrefetchInstr==0); | |
| 6811 match(PrefetchRead mem); | |
| 6812 ins_cost(125); | |
| 6813 | |
| 6814 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} | |
| 6815 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 6816 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
| 6817 ins_pipe(ialu_mem); | |
| 6818 %} | |
| 6819 | |
| 6820 instruct prefetchrT0( memory mem ) %{ | |
| 6821 predicate(ReadPrefetchInstr==1); | |
| 6822 match(PrefetchRead mem); | |
| 6823 ins_cost(125); | |
| 6824 | |
| 6825 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} | |
| 6826 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 6827 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
| 6828 ins_pipe(ialu_mem); | |
| 6829 %} | |
| 6830 | |
| 6831 instruct prefetchrT2( memory mem ) %{ | |
| 6832 predicate(ReadPrefetchInstr==2); | |
| 6833 match(PrefetchRead mem); | |
| 6834 ins_cost(125); | |
| 6835 | |
| 6836 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} | |
| 6837 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 6838 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); | |
| 6839 ins_pipe(ialu_mem); | |
| 6840 %} | |
| 6841 | |
| 6842 instruct prefetchw( memory mem ) %{ | |
| 6843 predicate(AllocatePrefetchInstr==3); | |
| 6844 match(PrefetchWrite mem); | |
| 6845 ins_cost(125); | |
| 6846 | |
| 6847 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %} | |
| 6848 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ | |
| 6849 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
| 6850 ins_pipe(ialu_mem); | |
| 6851 %} | |
| 6852 | |
| 6853 instruct prefetchwNTA( memory mem ) %{ | |
| 6854 predicate(AllocatePrefetchInstr==0); | |
| 6855 match(PrefetchWrite mem); | |
| 6856 ins_cost(125); | |
| 6857 | |
| 6858 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} | |
| 6859 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ | |
| 6860 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); | |
| 6861 ins_pipe(ialu_mem); | |
| 6862 %} | |
| 6863 | |
| 6864 instruct prefetchwT0( memory mem ) %{ | |
| 6865 predicate(AllocatePrefetchInstr==1); | |
| 6866 match(PrefetchWrite mem); | |
| 6867 ins_cost(125); | |
| 6868 | |
| 6869 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %} | |
| 6870 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ | |
| 6871 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); | |
| 6872 ins_pipe(ialu_mem); | |
| 6873 %} | |
| 6874 | |
| 6875 instruct prefetchwT2( memory mem ) %{ | |
| 6876 predicate(AllocatePrefetchInstr==2); | |
| 6877 match(PrefetchWrite mem); | |
| 6878 ins_cost(125); | |
| 6879 | |
| 6880 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %} | |
| 6881 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ | |
| 6882 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); | |
| 6883 ins_pipe(ialu_mem); | |
| 6884 %} | |
| 6885 | |
| 6886 //----------Store Instructions------------------------------------------------- | |
| 6887 | |
| 6888 // Store Byte | |
| 6889 instruct storeB(memory mem, rRegI src) | |
| 6890 %{ | |
| 6891 match(Set mem (StoreB mem src)); | |
| 6892 | |
| 6893 ins_cost(125); // XXX | |
| 6894 format %{ "movb $mem, $src\t# byte" %} | |
| 6895 opcode(0x88); | |
| 6896 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6897 ins_pipe(ialu_mem_reg); | |
| 6898 %} | |
| 6899 | |
| 6900 // Store Char/Short | |
| 6901 instruct storeC(memory mem, rRegI src) | |
| 6902 %{ | |
| 6903 match(Set mem (StoreC mem src)); | |
| 6904 | |
| 6905 ins_cost(125); // XXX | |
| 6906 format %{ "movw $mem, $src\t# char/short" %} | |
| 6907 opcode(0x89); | |
| 6908 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6909 ins_pipe(ialu_mem_reg); | |
| 6910 %} | |
| 6911 | |
| 6912 // Store Integer | |
| 6913 instruct storeI(memory mem, rRegI src) | |
| 6914 %{ | |
| 6915 match(Set mem (StoreI mem src)); | |
| 6916 | |
| 6917 ins_cost(125); // XXX | |
| 6918 format %{ "movl $mem, $src\t# int" %} | |
| 6919 opcode(0x89); | |
| 6920 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 6921 ins_pipe(ialu_mem_reg); | |
| 6922 %} | |
| 6923 | |
| 6924 // Store Long | |
| 6925 instruct storeL(memory mem, rRegL src) | |
| 6926 %{ | |
| 6927 match(Set mem (StoreL mem src)); | |
| 6928 | |
| 6929 ins_cost(125); // XXX | |
| 6930 format %{ "movq $mem, $src\t# long" %} | |
| 6931 opcode(0x89); | |
| 6932 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 6933 ins_pipe(ialu_mem_reg); // XXX | |
| 6934 %} | |
| 6935 | |
| 6936 // Store Pointer | |
| 6937 instruct storeP(memory mem, any_RegP src) | |
| 6938 %{ | |
| 6939 match(Set mem (StoreP mem src)); | |
| 6940 | |
| 6941 ins_cost(125); // XXX | |
| 6942 format %{ "movq $mem, $src\t# ptr" %} | |
| 6943 opcode(0x89); | |
| 6944 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 6945 ins_pipe(ialu_mem_reg); | |
| 6946 %} | |
| 6947 | |
|
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6948 instruct storeImmP0(memory mem, immP0 zero) |
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6949 %{ |
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6950 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
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6951 match(Set mem (StoreP mem zero)); |
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6952 |
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6953 ins_cost(125); // XXX |
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6954 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %} |
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6955 ins_encode %{ |
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6956 __ movq($mem$$Address, r12); |
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6957 %} |
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6958 ins_pipe(ialu_mem_reg); |
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6959 %} |
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6960 |
| 0 | 6961 // Store NULL Pointer, mark word, or other simple pointer constant. |
| 6962 instruct storeImmP(memory mem, immP31 src) | |
| 6963 %{ | |
| 6964 match(Set mem (StoreP mem src)); | |
| 6965 | |
|
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6966 ins_cost(150); // XXX |
| 0 | 6967 format %{ "movq $mem, $src\t# ptr" %} |
| 6968 opcode(0xC7); /* C7 /0 */ | |
| 6969 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 6970 ins_pipe(ialu_mem_imm); | |
| 6971 %} | |
| 6972 | |
|
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6973 // Store Compressed Pointer |
| 163 | 6974 instruct storeN(memory mem, rRegN src) |
|
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6975 %{ |
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6976 match(Set mem (StoreN mem src)); |
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6977 |
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6978 ins_cost(125); // XXX |
|
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6979 format %{ "movl $mem, $src\t# compressed ptr" %} |
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6980 ins_encode %{ |
|
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6981 __ movl($mem$$Address, $src$$Register); |
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6982 %} |
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6983 ins_pipe(ialu_mem_reg); |
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6984 %} |
|
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6985 |
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6986 instruct storeImmN0(memory mem, immN0 zero) |
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6987 %{ |
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6988 predicate(Universe::narrow_oop_base() == NULL); |
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6989 match(Set mem (StoreN mem zero)); |
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6990 |
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6991 ins_cost(125); // XXX |
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6992 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %} |
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6993 ins_encode %{ |
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6994 __ movl($mem$$Address, r12); |
|
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6995 %} |
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6996 ins_pipe(ialu_mem_reg); |
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6997 %} |
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6998 |
|
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6999 instruct storeImmN(memory mem, immN src) |
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kvn
parents:
624
diff
changeset
|
7000 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7001 match(Set mem (StoreN mem src)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7002 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7003 ins_cost(150); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7004 format %{ "movl $mem, $src\t# compressed ptr" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7005 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7006 address con = (address)$src$$constant; |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7007 if (con == NULL) { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7008 __ movl($mem$$Address, (int32_t)0); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7009 } else { |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7010 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7011 } |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7012 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7013 ins_pipe(ialu_mem_imm); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7014 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7015 |
| 0 | 7016 // Store Integer Immediate |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7017 instruct storeImmI0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7018 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7019 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7020 match(Set mem (StoreI mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7021 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7022 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7023 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7024 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7025 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7026 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7027 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7028 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7029 |
| 0 | 7030 instruct storeImmI(memory mem, immI src) |
| 7031 %{ | |
| 7032 match(Set mem (StoreI mem src)); | |
| 7033 | |
| 7034 ins_cost(150); | |
| 7035 format %{ "movl $mem, $src\t# int" %} | |
| 7036 opcode(0xC7); /* C7 /0 */ | |
| 7037 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 7038 ins_pipe(ialu_mem_imm); | |
| 7039 %} | |
| 7040 | |
| 7041 // Store Long Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7042 instruct storeImmL0(memory mem, immL0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7043 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7044 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7045 match(Set mem (StoreL mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7046 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7047 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7048 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7049 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7050 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7051 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7052 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7053 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7054 |
| 0 | 7055 instruct storeImmL(memory mem, immL32 src) |
| 7056 %{ | |
| 7057 match(Set mem (StoreL mem src)); | |
| 7058 | |
| 7059 ins_cost(150); | |
| 7060 format %{ "movq $mem, $src\t# long" %} | |
| 7061 opcode(0xC7); /* C7 /0 */ | |
| 7062 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src)); | |
| 7063 ins_pipe(ialu_mem_imm); | |
| 7064 %} | |
| 7065 | |
| 7066 // Store Short/Char Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7067 instruct storeImmC0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7068 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7069 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7070 match(Set mem (StoreC mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7071 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7072 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7073 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7074 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7075 __ movw($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7076 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7077 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7078 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7079 |
| 0 | 7080 instruct storeImmI16(memory mem, immI16 src) |
| 7081 %{ | |
| 7082 predicate(UseStoreImmI16); | |
| 7083 match(Set mem (StoreC mem src)); | |
| 7084 | |
| 7085 ins_cost(150); | |
| 7086 format %{ "movw $mem, $src\t# short/char" %} | |
| 7087 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ | |
| 7088 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src)); | |
| 7089 ins_pipe(ialu_mem_imm); | |
| 7090 %} | |
| 7091 | |
| 7092 // Store Byte Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7093 instruct storeImmB0(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7094 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7095 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7096 match(Set mem (StoreB mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7097 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7098 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7099 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7100 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7101 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7102 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7103 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7104 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7105 |
| 0 | 7106 instruct storeImmB(memory mem, immI8 src) |
| 7107 %{ | |
| 7108 match(Set mem (StoreB mem src)); | |
| 7109 | |
| 7110 ins_cost(150); // XXX | |
| 7111 format %{ "movb $mem, $src\t# byte" %} | |
| 7112 opcode(0xC6); /* C6 /0 */ | |
| 7113 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 7114 ins_pipe(ialu_mem_imm); | |
| 7115 %} | |
| 7116 | |
| 7117 // Store Aligned Packed Byte XMM register to memory | |
| 7118 instruct storeA8B(memory mem, regD src) %{ | |
| 7119 match(Set mem (Store8B mem src)); | |
| 7120 ins_cost(145); | |
| 7121 format %{ "MOVQ $mem,$src\t! packed8B" %} | |
| 7122 ins_encode( movq_st(mem, src)); | |
| 7123 ins_pipe( pipe_slow ); | |
| 7124 %} | |
| 7125 | |
| 7126 // Store Aligned Packed Char/Short XMM register to memory | |
| 7127 instruct storeA4C(memory mem, regD src) %{ | |
| 7128 match(Set mem (Store4C mem src)); | |
| 7129 ins_cost(145); | |
| 7130 format %{ "MOVQ $mem,$src\t! packed4C" %} | |
| 7131 ins_encode( movq_st(mem, src)); | |
| 7132 ins_pipe( pipe_slow ); | |
| 7133 %} | |
| 7134 | |
| 7135 // Store Aligned Packed Integer XMM register to memory | |
| 7136 instruct storeA2I(memory mem, regD src) %{ | |
| 7137 match(Set mem (Store2I mem src)); | |
| 7138 ins_cost(145); | |
| 7139 format %{ "MOVQ $mem,$src\t! packed2I" %} | |
| 7140 ins_encode( movq_st(mem, src)); | |
| 7141 ins_pipe( pipe_slow ); | |
| 7142 %} | |
| 7143 | |
| 7144 // Store CMS card-mark Immediate | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7145 instruct storeImmCM0_reg(memory mem, immI0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7146 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7147 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7148 match(Set mem (StoreCM mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7149 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7150 ins_cost(125); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7151 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7152 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7153 __ movb($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7154 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7155 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7156 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7157 |
| 0 | 7158 instruct storeImmCM0(memory mem, immI0 src) |
| 7159 %{ | |
| 7160 match(Set mem (StoreCM mem src)); | |
| 7161 | |
| 7162 ins_cost(150); // XXX | |
| 7163 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %} | |
| 7164 opcode(0xC6); /* C6 /0 */ | |
| 7165 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src)); | |
| 7166 ins_pipe(ialu_mem_imm); | |
| 7167 %} | |
| 7168 | |
| 7169 // Store Aligned Packed Single Float XMM register to memory | |
| 7170 instruct storeA2F(memory mem, regD src) %{ | |
| 7171 match(Set mem (Store2F mem src)); | |
| 7172 ins_cost(145); | |
| 7173 format %{ "MOVQ $mem,$src\t! packed2F" %} | |
| 7174 ins_encode( movq_st(mem, src)); | |
| 7175 ins_pipe( pipe_slow ); | |
| 7176 %} | |
| 7177 | |
| 7178 // Store Float | |
| 7179 instruct storeF(memory mem, regF src) | |
| 7180 %{ | |
| 7181 match(Set mem (StoreF mem src)); | |
| 7182 | |
| 7183 ins_cost(95); // XXX | |
| 7184 format %{ "movss $mem, $src\t# float" %} | |
| 7185 opcode(0xF3, 0x0F, 0x11); | |
| 7186 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | |
| 7187 ins_pipe(pipe_slow); // XXX | |
| 7188 %} | |
| 7189 | |
| 7190 // Store immediate Float value (it is faster than store from XMM register) | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7191 instruct storeF0(memory mem, immF0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7192 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7193 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7194 match(Set mem (StoreF mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7195 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7196 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7197 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7198 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7199 __ movl($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7200 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7201 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7202 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7203 |
| 0 | 7204 instruct storeF_imm(memory mem, immF src) |
| 7205 %{ | |
| 7206 match(Set mem (StoreF mem src)); | |
| 7207 | |
| 7208 ins_cost(50); | |
| 7209 format %{ "movl $mem, $src\t# float" %} | |
| 7210 opcode(0xC7); /* C7 /0 */ | |
| 7211 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 7212 ins_pipe(ialu_mem_imm); | |
| 7213 %} | |
| 7214 | |
| 7215 // Store Double | |
| 7216 instruct storeD(memory mem, regD src) | |
| 7217 %{ | |
| 7218 match(Set mem (StoreD mem src)); | |
| 7219 | |
| 7220 ins_cost(95); // XXX | |
| 7221 format %{ "movsd $mem, $src\t# double" %} | |
| 7222 opcode(0xF2, 0x0F, 0x11); | |
| 7223 ins_encode(OpcP, REX_reg_mem(src, mem), OpcS, OpcT, reg_mem(src, mem)); | |
| 7224 ins_pipe(pipe_slow); // XXX | |
| 7225 %} | |
| 7226 | |
| 7227 // Store immediate double 0.0 (it is faster than store from XMM register) | |
| 7228 instruct storeD0_imm(memory mem, immD0 src) | |
| 7229 %{ | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7230 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 7231 match(Set mem (StoreD mem src)); |
| 7232 | |
| 7233 ins_cost(50); | |
| 7234 format %{ "movq $mem, $src\t# double 0." %} | |
| 7235 opcode(0xC7); /* C7 /0 */ | |
| 7236 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src)); | |
| 7237 ins_pipe(ialu_mem_imm); | |
| 7238 %} | |
| 7239 | |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7240 instruct storeD0(memory mem, immD0 zero) |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7241 %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7242 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7243 match(Set mem (StoreD mem zero)); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7244 |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7245 ins_cost(25); // XXX |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7246 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7247 ins_encode %{ |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7248 __ movq($mem$$Address, r12); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7249 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7250 ins_pipe(ialu_mem_reg); |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7251 %} |
|
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7252 |
| 0 | 7253 instruct storeSSI(stackSlotI dst, rRegI src) |
| 7254 %{ | |
| 7255 match(Set dst src); | |
| 7256 | |
| 7257 ins_cost(100); | |
| 7258 format %{ "movl $dst, $src\t# int stk" %} | |
| 7259 opcode(0x89); | |
| 7260 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 7261 ins_pipe( ialu_mem_reg ); | |
| 7262 %} | |
| 7263 | |
| 7264 instruct storeSSL(stackSlotL dst, rRegL src) | |
| 7265 %{ | |
| 7266 match(Set dst src); | |
| 7267 | |
| 7268 ins_cost(100); | |
| 7269 format %{ "movq $dst, $src\t# long stk" %} | |
| 7270 opcode(0x89); | |
| 7271 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7272 ins_pipe(ialu_mem_reg); | |
| 7273 %} | |
| 7274 | |
| 7275 instruct storeSSP(stackSlotP dst, rRegP src) | |
| 7276 %{ | |
| 7277 match(Set dst src); | |
| 7278 | |
| 7279 ins_cost(100); | |
| 7280 format %{ "movq $dst, $src\t# ptr stk" %} | |
| 7281 opcode(0x89); | |
| 7282 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 7283 ins_pipe(ialu_mem_reg); | |
| 7284 %} | |
| 7285 | |
| 7286 instruct storeSSF(stackSlotF dst, regF src) | |
| 7287 %{ | |
| 7288 match(Set dst src); | |
| 7289 | |
| 7290 ins_cost(95); // XXX | |
| 7291 format %{ "movss $dst, $src\t# float stk" %} | |
| 7292 opcode(0xF3, 0x0F, 0x11); | |
| 7293 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 7294 ins_pipe(pipe_slow); // XXX | |
| 7295 %} | |
| 7296 | |
| 7297 instruct storeSSD(stackSlotD dst, regD src) | |
| 7298 %{ | |
| 7299 match(Set dst src); | |
| 7300 | |
| 7301 ins_cost(95); // XXX | |
| 7302 format %{ "movsd $dst, $src\t# double stk" %} | |
| 7303 opcode(0xF2, 0x0F, 0x11); | |
| 7304 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 7305 ins_pipe(pipe_slow); // XXX | |
| 7306 %} | |
| 7307 | |
| 7308 //----------BSWAP Instructions------------------------------------------------- | |
| 7309 instruct bytes_reverse_int(rRegI dst) %{ | |
| 7310 match(Set dst (ReverseBytesI dst)); | |
| 7311 | |
| 7312 format %{ "bswapl $dst" %} | |
| 7313 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */ | |
| 7314 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) ); | |
| 7315 ins_pipe( ialu_reg ); | |
| 7316 %} | |
| 7317 | |
| 7318 instruct bytes_reverse_long(rRegL dst) %{ | |
| 7319 match(Set dst (ReverseBytesL dst)); | |
| 7320 | |
| 7321 format %{ "bswapq $dst" %} | |
| 7322 | |
| 7323 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */ | |
| 7324 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) ); | |
| 7325 ins_pipe( ialu_reg); | |
| 7326 %} | |
| 7327 | |
|
1396
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7328 instruct bytes_reverse_unsigned_short(rRegI dst) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7329 match(Set dst (ReverseBytesUS dst)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7330 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7331 format %{ "bswapl $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7332 "shrl $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7333 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7334 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7335 __ shrl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7336 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7337 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7338 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7339 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7340 instruct bytes_reverse_short(rRegI dst) %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7341 match(Set dst (ReverseBytesS dst)); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7342 |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7343 format %{ "bswapl $dst\n\t" |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7344 "sar $dst,16\n\t" %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7345 ins_encode %{ |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7346 __ bswapl($dst$$Register); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7347 __ sarl($dst$$Register, 16); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7348 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7349 ins_pipe( ialu_reg ); |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7350 %} |
|
d7f654633cfe
6946040: add intrinsic for short and char reverseBytes
never
parents:
1274
diff
changeset
|
7351 |
| 0 | 7352 instruct loadI_reversed(rRegI dst, memory src) %{ |
| 7353 match(Set dst (ReverseBytesI (LoadI src))); | |
| 7354 | |
| 7355 format %{ "bswap_movl $dst, $src" %} | |
| 7356 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */ | |
| 7357 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src), REX_reg(dst), OpcS, opc3_reg(dst)); | |
| 7358 ins_pipe( ialu_reg_mem ); | |
| 7359 %} | |
| 7360 | |
| 7361 instruct loadL_reversed(rRegL dst, memory src) %{ | |
| 7362 match(Set dst (ReverseBytesL (LoadL src))); | |
| 7363 | |
| 7364 format %{ "bswap_movq $dst, $src" %} | |
| 7365 opcode(0x8B, 0x0F, 0xC8); /* Opcode 8B 0F C8 */ | |
| 7366 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src), REX_reg_wide(dst), OpcS, opc3_reg(dst)); | |
| 7367 ins_pipe( ialu_reg_mem ); | |
| 7368 %} | |
| 7369 | |
| 7370 instruct storeI_reversed(memory dst, rRegI src) %{ | |
| 7371 match(Set dst (StoreI dst (ReverseBytesI src))); | |
| 7372 | |
| 7373 format %{ "movl_bswap $dst, $src" %} | |
| 7374 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */ | |
| 7375 ins_encode( REX_reg(src), OpcP, opc2_reg(src), REX_reg_mem(src, dst), OpcT, reg_mem(src, dst) ); | |
| 7376 ins_pipe( ialu_mem_reg ); | |
| 7377 %} | |
| 7378 | |
| 7379 instruct storeL_reversed(memory dst, rRegL src) %{ | |
| 7380 match(Set dst (StoreL dst (ReverseBytesL src))); | |
| 7381 | |
| 7382 format %{ "movq_bswap $dst, $src" %} | |
| 7383 opcode(0x0F, 0xC8, 0x89); /* Opcode 0F C8 89 */ | |
| 7384 ins_encode( REX_reg_wide(src), OpcP, opc2_reg(src), REX_reg_mem_wide(src, dst), OpcT, reg_mem(src, dst) ); | |
| 7385 ins_pipe( ialu_mem_reg ); | |
| 7386 %} | |
| 7387 | |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7388 |
|
775
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7389 //---------- Zeros Count Instructions ------------------------------------------ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7390 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7391 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7392 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7393 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7394 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7395 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7396 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7397 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7398 __ lzcntl($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7399 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7400 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7401 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7402 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7403 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7404 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7405 match(Set dst (CountLeadingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7406 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7407 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7408 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7409 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7410 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7411 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7412 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7413 "addl $dst, 31" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7414 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7415 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7416 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7417 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7418 __ bsrl(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7419 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7420 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7421 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7422 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7423 __ addl(Rdst, BitsPerInt - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7424 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7425 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7426 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7427 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7428 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7429 predicate(UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7430 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7431 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7432 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7433 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7434 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7435 __ lzcntq($dst$$Register, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7436 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7437 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7438 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7439 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7440 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7441 predicate(!UseCountLeadingZerosInstruction); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7442 match(Set dst (CountLeadingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7443 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7444 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7445 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7446 "jnz skip\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7447 "movl $dst, -1\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7448 "skip:\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7449 "negl $dst\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7450 "addl $dst, 63" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7451 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7452 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7453 Register Rsrc = $src$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7454 Label skip; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7455 __ bsrq(Rdst, Rsrc); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7456 __ jccb(Assembler::notZero, skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7457 __ movl(Rdst, -1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7458 __ bind(skip); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7459 __ negl(Rdst); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7460 __ addl(Rdst, BitsPerLong - 1); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7461 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7462 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7463 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7464 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7465 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7466 match(Set dst (CountTrailingZerosI src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7467 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7468 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7469 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7470 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7471 "movl $dst, 32\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7472 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7473 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7474 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7475 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7476 __ bsfl(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7477 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7478 __ movl(Rdst, BitsPerInt); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7479 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7480 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7481 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7482 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7483 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7484 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7485 match(Set dst (CountTrailingZerosL src)); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7486 effect(KILL cr); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7487 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7488 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7489 "jnz done\n\t" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7490 "movl $dst, 64\n" |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7491 "done:" %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7492 ins_encode %{ |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7493 Register Rdst = $dst$$Register; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7494 Label done; |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7495 __ bsfq(Rdst, $src$$Register); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7496 __ jccb(Assembler::notZero, done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7497 __ movl(Rdst, BitsPerLong); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7498 __ bind(done); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7499 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7500 ins_pipe(ialu_reg); |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7501 %} |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7502 |
|
93c14e5562c4
6823354: Add intrinsics for {Integer,Long}.{numberOfLeadingZeros,numberOfTrailingZeros}()
twisti
parents:
681
diff
changeset
|
7503 |
|
643
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7504 //---------- Population Count Instructions ------------------------------------- |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7505 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7506 instruct popCountI(rRegI dst, rRegI src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7507 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7508 match(Set dst (PopCountI src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7509 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7510 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7511 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7512 __ popcntl($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7513 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7514 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7515 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7516 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7517 instruct popCountI_mem(rRegI dst, memory mem) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7518 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7519 match(Set dst (PopCountI (LoadI mem))); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7520 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7521 format %{ "popcnt $dst, $mem" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7522 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7523 __ popcntl($dst$$Register, $mem$$Address); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7524 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7525 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7526 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7527 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7528 // Note: Long.bitCount(long) returns an int. |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7529 instruct popCountL(rRegI dst, rRegL src) %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7530 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7531 match(Set dst (PopCountL src)); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7532 |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7533 format %{ "popcnt $dst, $src" %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7534 ins_encode %{ |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7535 __ popcntq($dst$$Register, $src$$Register); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7536 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7537 ins_pipe(ialu_reg); |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7538 %} |
|
c771b7f43bbf
6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7539 |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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diff
changeset
|
7540 // Note: Long.bitCount(long) returns an int. |
|
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diff
changeset
|
7541 instruct popCountL_mem(rRegI dst, memory mem) %{ |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
twisti
parents:
642
diff
changeset
|
7542 predicate(UsePopCountInstruction); |
|
c771b7f43bbf
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642
diff
changeset
|
7543 match(Set dst (PopCountL (LoadL mem))); |
|
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diff
changeset
|
7544 |
|
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parents:
642
diff
changeset
|
7545 format %{ "popcnt $dst, $mem" %} |
|
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6378821: bitCount() should use POPC on SPARC processors and AMD+10h
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642
diff
changeset
|
7546 ins_encode %{ |
|
c771b7f43bbf
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twisti
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diff
changeset
|
7547 __ popcntq($dst$$Register, $mem$$Address); |
|
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642
diff
changeset
|
7548 %} |
|
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diff
changeset
|
7549 ins_pipe(ialu_reg); |
|
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642
diff
changeset
|
7550 %} |
|
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642
diff
changeset
|
7551 |
|
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diff
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|
7552 |
| 0 | 7553 //----------MemBar Instructions----------------------------------------------- |
| 7554 // Memory barrier flavors | |
| 7555 | |
| 7556 instruct membar_acquire() | |
| 7557 %{ | |
| 7558 match(MemBarAcquire); | |
| 7559 ins_cost(0); | |
| 7560 | |
| 7561 size(0); | |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7562 format %{ "MEMBAR-acquire ! (empty encoding)" %} |
| 0 | 7563 ins_encode(); |
| 7564 ins_pipe(empty); | |
| 7565 %} | |
| 7566 | |
| 7567 instruct membar_acquire_lock() | |
| 7568 %{ | |
| 7569 match(MemBarAcquire); | |
| 7570 predicate(Matcher::prior_fast_lock(n)); | |
| 7571 ins_cost(0); | |
| 7572 | |
| 7573 size(0); | |
| 7574 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} | |
| 7575 ins_encode(); | |
| 7576 ins_pipe(empty); | |
| 7577 %} | |
| 7578 | |
| 7579 instruct membar_release() | |
| 7580 %{ | |
| 7581 match(MemBarRelease); | |
| 7582 ins_cost(0); | |
| 7583 | |
| 7584 size(0); | |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7585 format %{ "MEMBAR-release ! (empty encoding)" %} |
| 0 | 7586 ins_encode(); |
| 7587 ins_pipe(empty); | |
| 7588 %} | |
| 7589 | |
| 7590 instruct membar_release_lock() | |
| 7591 %{ | |
| 7592 match(MemBarRelease); | |
| 7593 predicate(Matcher::post_fast_unlock(n)); | |
| 7594 ins_cost(0); | |
| 7595 | |
| 7596 size(0); | |
| 7597 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} | |
| 7598 ins_encode(); | |
| 7599 ins_pipe(empty); | |
| 7600 %} | |
| 7601 | |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7602 instruct membar_volatile(rFlagsReg cr) %{ |
| 0 | 7603 match(MemBarVolatile); |
|
671
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diff
changeset
|
7604 effect(KILL cr); |
| 0 | 7605 ins_cost(400); |
| 7606 | |
|
671
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7607 format %{ |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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diff
changeset
|
7608 $$template |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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parents:
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diff
changeset
|
7609 if (os::is_MP()) { |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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changeset
|
7610 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile" |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
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diff
changeset
|
7611 } else { |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
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diff
changeset
|
7612 $$emit$$"MEMBAR-volatile ! (empty encoding)" |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
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parents:
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diff
changeset
|
7613 } |
|
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6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7614 %} |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7615 ins_encode %{ |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
never
parents:
647
diff
changeset
|
7616 __ membar(Assembler::StoreLoad); |
|
d0994e5bebce
6822204: volatile fences should prefer lock:addl to actual mfence instructions
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647
diff
changeset
|
7617 %} |
| 0 | 7618 ins_pipe(pipe_slow); |
| 7619 %} | |
| 7620 | |
| 7621 instruct unnecessary_membar_volatile() | |
| 7622 %{ | |
| 7623 match(MemBarVolatile); | |
| 7624 predicate(Matcher::post_store_load_barrier(n)); | |
| 7625 ins_cost(0); | |
| 7626 | |
| 7627 size(0); | |
| 7628 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} | |
| 7629 ins_encode(); | |
| 7630 ins_pipe(empty); | |
| 7631 %} | |
| 7632 | |
| 7633 //----------Move Instructions-------------------------------------------------- | |
| 7634 | |
| 7635 instruct castX2P(rRegP dst, rRegL src) | |
| 7636 %{ | |
| 7637 match(Set dst (CastX2P src)); | |
| 7638 | |
| 7639 format %{ "movq $dst, $src\t# long->ptr" %} | |
| 7640 ins_encode(enc_copy_wide(dst, src)); | |
| 7641 ins_pipe(ialu_reg_reg); // XXX | |
| 7642 %} | |
| 7643 | |
| 7644 instruct castP2X(rRegL dst, rRegP src) | |
| 7645 %{ | |
| 7646 match(Set dst (CastP2X src)); | |
| 7647 | |
| 7648 format %{ "movq $dst, $src\t# ptr -> long" %} | |
| 7649 ins_encode(enc_copy_wide(dst, src)); | |
| 7650 ins_pipe(ialu_reg_reg); // XXX | |
| 7651 %} | |
| 7652 | |
|
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|
7653 |
|
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|
7654 // Convert oop pointer into compressed form |
|
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|
7655 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
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|
7656 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); |
|
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|
7657 match(Set dst (EncodeP src)); |
|
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|
7658 effect(KILL cr); |
|
ba764ed4b6f2
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|
7659 format %{ "encode_heap_oop $dst,$src" %} |
|
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|
7660 ins_encode %{ |
|
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|
7661 Register s = $src$$Register; |
|
ba764ed4b6f2
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|
7662 Register d = $dst$$Register; |
|
ba764ed4b6f2
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|
7663 if (s != d) { |
|
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|
7664 __ movq(d, s); |
|
ba764ed4b6f2
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|
7665 } |
|
ba764ed4b6f2
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changeset
|
7666 __ encode_heap_oop(d); |
|
ba764ed4b6f2
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|
7667 %} |
|
ba764ed4b6f2
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changeset
|
7668 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
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|
7669 %} |
|
ba764ed4b6f2
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diff
changeset
|
7670 |
|
124
b130b98db9cf
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diff
changeset
|
7671 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{ |
|
221
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|
7672 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); |
|
124
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changeset
|
7673 match(Set dst (EncodeP src)); |
|
b130b98db9cf
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113
diff
changeset
|
7674 effect(KILL cr); |
|
b130b98db9cf
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parents:
113
diff
changeset
|
7675 format %{ "encode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
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diff
changeset
|
7676 ins_encode %{ |
|
642
660978a2a31a
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changeset
|
7677 __ encode_heap_oop_not_null($dst$$Register, $src$$Register); |
|
124
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|
7678 %} |
|
b130b98db9cf
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113
diff
changeset
|
7679 ins_pipe(ialu_reg_long); |
|
b130b98db9cf
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kvn
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diff
changeset
|
7680 %} |
|
b130b98db9cf
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113
diff
changeset
|
7681 |
|
113
ba764ed4b6f2
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coleenp
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diff
changeset
|
7682 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
182
44abbb0d4c18
6709093: Compressed Oops: reduce size of compiled methods
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169
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changeset
|
7683 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && |
|
44abbb0d4c18
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diff
changeset
|
7684 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); |
|
113
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diff
changeset
|
7685 match(Set dst (DecodeN src)); |
|
ba764ed4b6f2
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71
diff
changeset
|
7686 effect(KILL cr); |
|
ba764ed4b6f2
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71
diff
changeset
|
7687 format %{ "decode_heap_oop $dst,$src" %} |
|
ba764ed4b6f2
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diff
changeset
|
7688 ins_encode %{ |
|
ba764ed4b6f2
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diff
changeset
|
7689 Register s = $src$$Register; |
|
ba764ed4b6f2
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diff
changeset
|
7690 Register d = $dst$$Register; |
|
ba764ed4b6f2
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diff
changeset
|
7691 if (s != d) { |
|
ba764ed4b6f2
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71
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changeset
|
7692 __ movq(d, s); |
|
ba764ed4b6f2
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diff
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|
7693 } |
|
ba764ed4b6f2
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changeset
|
7694 __ decode_heap_oop(d); |
|
ba764ed4b6f2
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|
7695 %} |
|
ba764ed4b6f2
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changeset
|
7696 ins_pipe(ialu_reg_long); |
|
ba764ed4b6f2
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|
7697 %} |
|
ba764ed4b6f2
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diff
changeset
|
7698 |
|
1571
2d127394260e
6916623: Align object to 16 bytes to use Compressed Oops with java heap up to 64Gb
kvn
parents:
1567
diff
changeset
|
7699 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{ |
|
182
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|
7700 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || |
|
44abbb0d4c18
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changeset
|
7701 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); |
|
124
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changeset
|
7702 match(Set dst (DecodeN src)); |
|
1571
2d127394260e
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diff
changeset
|
7703 effect(KILL cr); |
|
124
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changeset
|
7704 format %{ "decode_heap_oop_not_null $dst,$src" %} |
|
b130b98db9cf
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113
diff
changeset
|
7705 ins_encode %{ |
|
b130b98db9cf
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113
diff
changeset
|
7706 Register s = $src$$Register; |
|
b130b98db9cf
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113
diff
changeset
|
7707 Register d = $dst$$Register; |
|
642
660978a2a31a
6791178: Specialize for zero as the compressed oop vm heap base
kvn
parents:
624
diff
changeset
|
7708 if (s != d) { |
|
660978a2a31a
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kvn
parents:
624
diff
changeset
|
7709 __ decode_heap_oop_not_null(d, s); |
|
660978a2a31a
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kvn
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624
diff
changeset
|
7710 } else { |
|
660978a2a31a
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624
diff
changeset
|
7711 __ decode_heap_oop_not_null(d); |
|
660978a2a31a
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624
diff
changeset
|
7712 } |
|
124
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|
7713 %} |
|
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changeset
|
7714 ins_pipe(ialu_reg_long); |
|
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diff
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|
7715 %} |
|
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|
7716 |
|
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|
7717 |
| 0 | 7718 //----------Conditional Move--------------------------------------------------- |
| 7719 // Jump | |
| 7720 // dummy instruction for generating temp registers | |
| 7721 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{ | |
| 7722 match(Jump (LShiftL switch_val shift)); | |
| 7723 ins_cost(350); | |
| 7724 predicate(false); | |
| 7725 effect(TEMP dest); | |
| 7726 | |
| 7727 format %{ "leaq $dest, table_base\n\t" | |
| 7728 "jmp [$dest + $switch_val << $shift]\n\t" %} | |
| 7729 ins_encode(jump_enc_offset(switch_val, shift, dest)); | |
| 7730 ins_pipe(pipe_jmp); | |
| 7731 ins_pc_relative(1); | |
| 7732 %} | |
| 7733 | |
| 7734 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{ | |
| 7735 match(Jump (AddL (LShiftL switch_val shift) offset)); | |
| 7736 ins_cost(350); | |
| 7737 effect(TEMP dest); | |
| 7738 | |
| 7739 format %{ "leaq $dest, table_base\n\t" | |
| 7740 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %} | |
| 7741 ins_encode(jump_enc_addr(switch_val, shift, offset, dest)); | |
| 7742 ins_pipe(pipe_jmp); | |
| 7743 ins_pc_relative(1); | |
| 7744 %} | |
| 7745 | |
| 7746 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{ | |
| 7747 match(Jump switch_val); | |
| 7748 ins_cost(350); | |
| 7749 effect(TEMP dest); | |
| 7750 | |
| 7751 format %{ "leaq $dest, table_base\n\t" | |
| 7752 "jmp [$dest + $switch_val]\n\t" %} | |
| 7753 ins_encode(jump_enc(switch_val, dest)); | |
| 7754 ins_pipe(pipe_jmp); | |
| 7755 ins_pc_relative(1); | |
| 7756 %} | |
| 7757 | |
| 7758 // Conditional move | |
| 7759 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop) | |
| 7760 %{ | |
| 7761 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); | |
| 7762 | |
| 7763 ins_cost(200); // XXX | |
| 7764 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 7765 opcode(0x0F, 0x40); | |
| 7766 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7767 ins_pipe(pipe_cmov_reg); | |
| 7768 %} | |
| 7769 | |
|
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never
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diff
changeset
|
7770 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{ |
| 0 | 7771 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
| 7772 | |
| 7773 ins_cost(200); // XXX | |
| 7774 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 7775 opcode(0x0F, 0x40); | |
| 7776 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7777 ins_pipe(pipe_cmov_reg); | |
| 7778 %} | |
| 7779 | |
|
415
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never
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403
diff
changeset
|
7780 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{ |
|
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diff
changeset
|
7781 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
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403
diff
changeset
|
7782 ins_cost(200); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7783 expand %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7784 cmovI_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7785 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7786 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7787 |
| 0 | 7788 // Conditional move |
|
415
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never
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diff
changeset
|
7789 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{ |
| 0 | 7790 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
| 7791 | |
| 7792 ins_cost(250); // XXX | |
| 7793 format %{ "cmovl$cop $dst, $src\t# signed, int" %} | |
| 7794 opcode(0x0F, 0x40); | |
| 7795 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7796 ins_pipe(pipe_cmov_mem); | |
| 7797 %} | |
| 7798 | |
| 7799 // Conditional move | |
| 7800 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src) | |
| 7801 %{ | |
| 7802 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); | |
| 7803 | |
| 7804 ins_cost(250); // XXX | |
| 7805 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} | |
| 7806 opcode(0x0F, 0x40); | |
| 7807 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7808 ins_pipe(pipe_cmov_mem); | |
| 7809 %} | |
| 7810 | |
|
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|
7811 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{ |
|
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diff
changeset
|
7812 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); |
|
4d9884b01ba6
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never
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diff
changeset
|
7813 ins_cost(250); |
|
4d9884b01ba6
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never
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403
diff
changeset
|
7814 expand %{ |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7815 cmovI_memU(cop, cr, dst, src); |
|
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diff
changeset
|
7816 %} |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7817 %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
7818 |
| 0 | 7819 // Conditional move |
|
164
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diff
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|
7820 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop) |
|
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changeset
|
7821 %{ |
|
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diff
changeset
|
7822 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
c436414a719e
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parents:
163
diff
changeset
|
7823 |
|
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kvn
parents:
163
diff
changeset
|
7824 ins_cost(200); // XXX |
|
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parents:
163
diff
changeset
|
7825 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %} |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
7826 opcode(0x0F, 0x40); |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
7827 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
7828 ins_pipe(pipe_cmov_reg); |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
7829 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
7830 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
7831 // Conditional move |
|
415
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diff
changeset
|
7832 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src) |
|
164
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diff
changeset
|
7833 %{ |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
7834 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
7835 |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
7836 ins_cost(200); // XXX |
|
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kvn
parents:
163
diff
changeset
|
7837 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %} |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
7838 opcode(0x0F, 0x40); |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
7839 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src)); |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
7840 ins_pipe(pipe_cmov_reg); |
|
c436414a719e
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kvn
parents:
163
diff
changeset
|
7841 %} |
|
c436414a719e
6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions
kvn
parents:
163
diff
changeset
|
7842 |
|
415
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7843 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7844 match(Set dst (CMoveN (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7845 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7846 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7847 cmovN_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7848 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7849 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7850 |
|
164
c436414a719e
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kvn
parents:
163
diff
changeset
|
7851 // Conditional move |
| 0 | 7852 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) |
| 7853 %{ | |
| 7854 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7855 | |
| 7856 ins_cost(200); // XXX | |
| 7857 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %} | |
| 7858 opcode(0x0F, 0x40); | |
| 7859 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7860 ins_pipe(pipe_cmov_reg); // XXX | |
| 7861 %} | |
| 7862 | |
| 7863 // Conditional move | |
|
415
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parents:
403
diff
changeset
|
7864 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src) |
| 0 | 7865 %{ |
| 7866 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); | |
| 7867 | |
| 7868 ins_cost(200); // XXX | |
| 7869 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %} | |
| 7870 opcode(0x0F, 0x40); | |
| 7871 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7872 ins_pipe(pipe_cmov_reg); // XXX | |
| 7873 %} | |
| 7874 | |
|
415
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7875 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7876 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7877 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7878 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7879 cmovP_regU(cop, cr, dst, src); |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7880 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7881 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7882 |
| 0 | 7883 // DISABLED: Requires the ADLC to emit a bottom_type call that |
| 7884 // correctly meets the two pointer arguments; one is an incoming | |
| 7885 // register but the other is a memory operand. ALSO appears to | |
| 7886 // be buggy with implicit null checks. | |
| 7887 // | |
| 7888 //// Conditional move | |
| 7889 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src) | |
| 7890 //%{ | |
| 7891 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7892 // ins_cost(250); | |
| 7893 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7894 // opcode(0x0F,0x40); | |
| 7895 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 7896 // ins_pipe( pipe_cmov_mem ); | |
| 7897 //%} | |
| 7898 // | |
| 7899 //// Conditional move | |
| 7900 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src) | |
| 7901 //%{ | |
| 7902 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); | |
| 7903 // ins_cost(250); | |
| 7904 // format %{ "CMOV$cop $dst,$src\t# ptr" %} | |
| 7905 // opcode(0x0F,0x40); | |
| 7906 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) ); | |
| 7907 // ins_pipe( pipe_cmov_mem ); | |
| 7908 //%} | |
| 7909 | |
| 7910 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src) | |
| 7911 %{ | |
| 7912 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7913 | |
| 7914 ins_cost(200); // XXX | |
| 7915 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 7916 opcode(0x0F, 0x40); | |
| 7917 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7918 ins_pipe(pipe_cmov_reg); // XXX | |
| 7919 %} | |
| 7920 | |
| 7921 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src) | |
| 7922 %{ | |
| 7923 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7924 | |
| 7925 ins_cost(200); // XXX | |
| 7926 format %{ "cmovq$cop $dst, $src\t# signed, long" %} | |
| 7927 opcode(0x0F, 0x40); | |
| 7928 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7929 ins_pipe(pipe_cmov_mem); // XXX | |
| 7930 %} | |
| 7931 | |
| 7932 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src) | |
| 7933 %{ | |
| 7934 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); | |
| 7935 | |
| 7936 ins_cost(200); // XXX | |
| 7937 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7938 opcode(0x0F, 0x40); | |
| 7939 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src)); | |
| 7940 ins_pipe(pipe_cmov_reg); // XXX | |
| 7941 %} | |
| 7942 | |
|
415
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7943 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7944 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7945 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7946 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7947 cmovL_regU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7948 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7949 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7950 |
| 0 | 7951 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src) |
| 7952 %{ | |
| 7953 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7954 | |
| 7955 ins_cost(200); // XXX | |
| 7956 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %} | |
| 7957 opcode(0x0F, 0x40); | |
| 7958 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src)); | |
| 7959 ins_pipe(pipe_cmov_mem); // XXX | |
| 7960 %} | |
| 7961 | |
|
415
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7962 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{ |
|
4d9884b01ba6
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never
parents:
403
diff
changeset
|
7963 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src)))); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7964 ins_cost(200); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7965 expand %{ |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7966 cmovL_memU(cop, cr, dst, src); |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7967 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7968 %} |
|
4d9884b01ba6
6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
7969 |
| 0 | 7970 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src) |
| 7971 %{ | |
| 7972 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7973 | |
| 7974 ins_cost(200); // XXX | |
| 7975 format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7976 "movss $dst, $src\n" | |
| 7977 "skip:" %} | |
| 7978 ins_encode(enc_cmovf_branch(cop, dst, src)); | |
| 7979 ins_pipe(pipe_slow); | |
| 7980 %} | |
| 7981 | |
| 7982 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src) | |
| 7983 // %{ | |
| 7984 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src)))); | |
| 7985 | |
| 7986 // ins_cost(200); // XXX | |
| 7987 // format %{ "jn$cop skip\t# signed cmove float\n\t" | |
| 7988 // "movss $dst, $src\n" | |
| 7989 // "skip:" %} | |
| 7990 // ins_encode(enc_cmovf_mem_branch(cop, dst, src)); | |
| 7991 // ins_pipe(pipe_slow); | |
| 7992 // %} | |
| 7993 | |
| 7994 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src) | |
| 7995 %{ | |
| 7996 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); | |
| 7997 | |
| 7998 ins_cost(200); // XXX | |
| 7999 format %{ "jn$cop skip\t# unsigned cmove float\n\t" | |
| 8000 "movss $dst, $src\n" | |
| 8001 "skip:" %} | |
| 8002 ins_encode(enc_cmovf_branch(cop, dst, src)); | |
| 8003 ins_pipe(pipe_slow); | |
| 8004 %} | |
| 8005 | |
|
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8006 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{ |
|
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|
8007 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); |
|
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|
8008 ins_cost(200); |
|
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|
8009 expand %{ |
|
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|
8010 cmovF_regU(cop, cr, dst, src); |
|
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|
8011 %} |
|
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|
8012 %} |
|
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|
8013 |
| 0 | 8014 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src) |
| 8015 %{ | |
| 8016 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8017 | |
| 8018 ins_cost(200); // XXX | |
| 8019 format %{ "jn$cop skip\t# signed cmove double\n\t" | |
| 8020 "movsd $dst, $src\n" | |
| 8021 "skip:" %} | |
| 8022 ins_encode(enc_cmovd_branch(cop, dst, src)); | |
| 8023 ins_pipe(pipe_slow); | |
| 8024 %} | |
| 8025 | |
| 8026 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src) | |
| 8027 %{ | |
| 8028 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); | |
| 8029 | |
| 8030 ins_cost(200); // XXX | |
| 8031 format %{ "jn$cop skip\t# unsigned cmove double\n\t" | |
| 8032 "movsd $dst, $src\n" | |
| 8033 "skip:" %} | |
| 8034 ins_encode(enc_cmovd_branch(cop, dst, src)); | |
| 8035 ins_pipe(pipe_slow); | |
| 8036 %} | |
| 8037 | |
|
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|
8038 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{ |
|
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diff
changeset
|
8039 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); |
|
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diff
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|
8040 ins_cost(200); |
|
4d9884b01ba6
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never
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diff
changeset
|
8041 expand %{ |
|
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diff
changeset
|
8042 cmovD_regU(cop, cr, dst, src); |
|
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diff
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|
8043 %} |
|
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diff
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|
8044 %} |
|
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|
8045 |
| 0 | 8046 //----------Arithmetic Instructions-------------------------------------------- |
| 8047 //----------Addition Instructions---------------------------------------------- | |
| 8048 | |
| 8049 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8050 %{ | |
| 8051 match(Set dst (AddI dst src)); | |
| 8052 effect(KILL cr); | |
| 8053 | |
| 8054 format %{ "addl $dst, $src\t# int" %} | |
| 8055 opcode(0x03); | |
| 8056 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8057 ins_pipe(ialu_reg_reg); | |
| 8058 %} | |
| 8059 | |
| 8060 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8061 %{ | |
| 8062 match(Set dst (AddI dst src)); | |
| 8063 effect(KILL cr); | |
| 8064 | |
| 8065 format %{ "addl $dst, $src\t# int" %} | |
| 8066 opcode(0x81, 0x00); /* /0 id */ | |
| 8067 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8068 ins_pipe( ialu_reg ); | |
| 8069 %} | |
| 8070 | |
| 8071 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8072 %{ | |
| 8073 match(Set dst (AddI dst (LoadI src))); | |
| 8074 effect(KILL cr); | |
| 8075 | |
| 8076 ins_cost(125); // XXX | |
| 8077 format %{ "addl $dst, $src\t# int" %} | |
| 8078 opcode(0x03); | |
| 8079 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8080 ins_pipe(ialu_reg_mem); | |
| 8081 %} | |
| 8082 | |
| 8083 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8084 %{ | |
| 8085 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8086 effect(KILL cr); | |
| 8087 | |
| 8088 ins_cost(150); // XXX | |
| 8089 format %{ "addl $dst, $src\t# int" %} | |
| 8090 opcode(0x01); /* Opcode 01 /r */ | |
| 8091 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8092 ins_pipe(ialu_mem_reg); | |
| 8093 %} | |
| 8094 | |
| 8095 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8096 %{ | |
| 8097 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8098 effect(KILL cr); | |
| 8099 | |
| 8100 ins_cost(125); // XXX | |
| 8101 format %{ "addl $dst, $src\t# int" %} | |
| 8102 opcode(0x81); /* Opcode 81 /0 id */ | |
| 8103 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 8104 ins_pipe(ialu_mem_imm); | |
| 8105 %} | |
| 8106 | |
| 8107 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 8108 %{ | |
| 8109 predicate(UseIncDec); | |
| 8110 match(Set dst (AddI dst src)); | |
| 8111 effect(KILL cr); | |
| 8112 | |
| 8113 format %{ "incl $dst\t# int" %} | |
| 8114 opcode(0xFF, 0x00); // FF /0 | |
| 8115 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8116 ins_pipe(ialu_reg); | |
| 8117 %} | |
| 8118 | |
| 8119 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr) | |
| 8120 %{ | |
| 8121 predicate(UseIncDec); | |
| 8122 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8123 effect(KILL cr); | |
| 8124 | |
| 8125 ins_cost(125); // XXX | |
| 8126 format %{ "incl $dst\t# int" %} | |
| 8127 opcode(0xFF); /* Opcode FF /0 */ | |
| 8128 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 8129 ins_pipe(ialu_mem_imm); | |
| 8130 %} | |
| 8131 | |
| 8132 // XXX why does that use AddI | |
| 8133 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr) | |
| 8134 %{ | |
| 8135 predicate(UseIncDec); | |
| 8136 match(Set dst (AddI dst src)); | |
| 8137 effect(KILL cr); | |
| 8138 | |
| 8139 format %{ "decl $dst\t# int" %} | |
| 8140 opcode(0xFF, 0x01); // FF /1 | |
| 8141 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8142 ins_pipe(ialu_reg); | |
| 8143 %} | |
| 8144 | |
| 8145 // XXX why does that use AddI | |
| 8146 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr) | |
| 8147 %{ | |
| 8148 predicate(UseIncDec); | |
| 8149 match(Set dst (StoreI dst (AddI (LoadI dst) src))); | |
| 8150 effect(KILL cr); | |
| 8151 | |
| 8152 ins_cost(125); // XXX | |
| 8153 format %{ "decl $dst\t# int" %} | |
| 8154 opcode(0xFF); /* Opcode FF /1 */ | |
| 8155 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 8156 ins_pipe(ialu_mem_imm); | |
| 8157 %} | |
| 8158 | |
| 8159 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1) | |
| 8160 %{ | |
| 8161 match(Set dst (AddI src0 src1)); | |
| 8162 | |
| 8163 ins_cost(110); | |
| 8164 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %} | |
| 8165 opcode(0x8D); /* 0x8D /r */ | |
| 8166 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 8167 ins_pipe(ialu_reg_reg); | |
| 8168 %} | |
| 8169 | |
| 8170 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8171 %{ | |
| 8172 match(Set dst (AddL dst src)); | |
| 8173 effect(KILL cr); | |
| 8174 | |
| 8175 format %{ "addq $dst, $src\t# long" %} | |
| 8176 opcode(0x03); | |
| 8177 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8178 ins_pipe(ialu_reg_reg); | |
| 8179 %} | |
| 8180 | |
| 8181 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 8182 %{ | |
| 8183 match(Set dst (AddL dst src)); | |
| 8184 effect(KILL cr); | |
| 8185 | |
| 8186 format %{ "addq $dst, $src\t# long" %} | |
| 8187 opcode(0x81, 0x00); /* /0 id */ | |
| 8188 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8189 ins_pipe( ialu_reg ); | |
| 8190 %} | |
| 8191 | |
| 8192 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8193 %{ | |
| 8194 match(Set dst (AddL dst (LoadL src))); | |
| 8195 effect(KILL cr); | |
| 8196 | |
| 8197 ins_cost(125); // XXX | |
| 8198 format %{ "addq $dst, $src\t# long" %} | |
| 8199 opcode(0x03); | |
| 8200 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 8201 ins_pipe(ialu_reg_mem); | |
| 8202 %} | |
| 8203 | |
| 8204 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 8205 %{ | |
| 8206 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 8207 effect(KILL cr); | |
| 8208 | |
| 8209 ins_cost(150); // XXX | |
| 8210 format %{ "addq $dst, $src\t# long" %} | |
| 8211 opcode(0x01); /* Opcode 01 /r */ | |
| 8212 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 8213 ins_pipe(ialu_mem_reg); | |
| 8214 %} | |
| 8215 | |
| 8216 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 8217 %{ | |
| 8218 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 8219 effect(KILL cr); | |
| 8220 | |
| 8221 ins_cost(125); // XXX | |
| 8222 format %{ "addq $dst, $src\t# long" %} | |
| 8223 opcode(0x81); /* Opcode 81 /0 id */ | |
| 8224 ins_encode(REX_mem_wide(dst), | |
| 8225 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src)); | |
| 8226 ins_pipe(ialu_mem_imm); | |
| 8227 %} | |
| 8228 | |
| 8229 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr) | |
| 8230 %{ | |
| 8231 predicate(UseIncDec); | |
| 8232 match(Set dst (AddL dst src)); | |
| 8233 effect(KILL cr); | |
| 8234 | |
| 8235 format %{ "incq $dst\t# long" %} | |
| 8236 opcode(0xFF, 0x00); // FF /0 | |
| 8237 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8238 ins_pipe(ialu_reg); | |
| 8239 %} | |
| 8240 | |
| 8241 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr) | |
| 8242 %{ | |
| 8243 predicate(UseIncDec); | |
| 8244 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 8245 effect(KILL cr); | |
| 8246 | |
| 8247 ins_cost(125); // XXX | |
| 8248 format %{ "incq $dst\t# long" %} | |
| 8249 opcode(0xFF); /* Opcode FF /0 */ | |
| 8250 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst)); | |
| 8251 ins_pipe(ialu_mem_imm); | |
| 8252 %} | |
| 8253 | |
| 8254 // XXX why does that use AddL | |
| 8255 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr) | |
| 8256 %{ | |
| 8257 predicate(UseIncDec); | |
| 8258 match(Set dst (AddL dst src)); | |
| 8259 effect(KILL cr); | |
| 8260 | |
| 8261 format %{ "decq $dst\t# long" %} | |
| 8262 opcode(0xFF, 0x01); // FF /1 | |
| 8263 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8264 ins_pipe(ialu_reg); | |
| 8265 %} | |
| 8266 | |
| 8267 // XXX why does that use AddL | |
| 8268 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr) | |
| 8269 %{ | |
| 8270 predicate(UseIncDec); | |
| 8271 match(Set dst (StoreL dst (AddL (LoadL dst) src))); | |
| 8272 effect(KILL cr); | |
| 8273 | |
| 8274 ins_cost(125); // XXX | |
| 8275 format %{ "decq $dst\t# long" %} | |
| 8276 opcode(0xFF); /* Opcode FF /1 */ | |
| 8277 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst)); | |
| 8278 ins_pipe(ialu_mem_imm); | |
| 8279 %} | |
| 8280 | |
| 8281 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1) | |
| 8282 %{ | |
| 8283 match(Set dst (AddL src0 src1)); | |
| 8284 | |
| 8285 ins_cost(110); | |
| 8286 format %{ "leaq $dst, [$src0 + $src1]\t# long" %} | |
| 8287 opcode(0x8D); /* 0x8D /r */ | |
| 8288 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX | |
| 8289 ins_pipe(ialu_reg_reg); | |
| 8290 %} | |
| 8291 | |
| 8292 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr) | |
| 8293 %{ | |
| 8294 match(Set dst (AddP dst src)); | |
| 8295 effect(KILL cr); | |
| 8296 | |
| 8297 format %{ "addq $dst, $src\t# ptr" %} | |
| 8298 opcode(0x03); | |
| 8299 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8300 ins_pipe(ialu_reg_reg); | |
| 8301 %} | |
| 8302 | |
| 8303 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr) | |
| 8304 %{ | |
| 8305 match(Set dst (AddP dst src)); | |
| 8306 effect(KILL cr); | |
| 8307 | |
| 8308 format %{ "addq $dst, $src\t# ptr" %} | |
| 8309 opcode(0x81, 0x00); /* /0 id */ | |
| 8310 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8311 ins_pipe( ialu_reg ); | |
| 8312 %} | |
| 8313 | |
| 8314 // XXX addP mem ops ???? | |
| 8315 | |
| 8316 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1) | |
| 8317 %{ | |
| 8318 match(Set dst (AddP src0 src1)); | |
| 8319 | |
| 8320 ins_cost(110); | |
| 8321 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %} | |
| 8322 opcode(0x8D); /* 0x8D /r */ | |
| 8323 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX | |
| 8324 ins_pipe(ialu_reg_reg); | |
| 8325 %} | |
| 8326 | |
| 8327 instruct checkCastPP(rRegP dst) | |
| 8328 %{ | |
| 8329 match(Set dst (CheckCastPP dst)); | |
| 8330 | |
| 8331 size(0); | |
| 8332 format %{ "# checkcastPP of $dst" %} | |
| 8333 ins_encode(/* empty encoding */); | |
| 8334 ins_pipe(empty); | |
| 8335 %} | |
| 8336 | |
| 8337 instruct castPP(rRegP dst) | |
| 8338 %{ | |
| 8339 match(Set dst (CastPP dst)); | |
| 8340 | |
| 8341 size(0); | |
| 8342 format %{ "# castPP of $dst" %} | |
| 8343 ins_encode(/* empty encoding */); | |
| 8344 ins_pipe(empty); | |
| 8345 %} | |
| 8346 | |
| 8347 instruct castII(rRegI dst) | |
| 8348 %{ | |
| 8349 match(Set dst (CastII dst)); | |
| 8350 | |
| 8351 size(0); | |
| 8352 format %{ "# castII of $dst" %} | |
| 8353 ins_encode(/* empty encoding */); | |
| 8354 ins_cost(0); | |
| 8355 ins_pipe(empty); | |
| 8356 %} | |
| 8357 | |
| 8358 // LoadP-locked same as a regular LoadP when used with compare-swap | |
| 8359 instruct loadPLocked(rRegP dst, memory mem) | |
| 8360 %{ | |
| 8361 match(Set dst (LoadPLocked mem)); | |
| 8362 | |
| 8363 ins_cost(125); // XXX | |
| 8364 format %{ "movq $dst, $mem\t# ptr locked" %} | |
| 8365 opcode(0x8B); | |
| 8366 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 8367 ins_pipe(ialu_reg_mem); // XXX | |
| 8368 %} | |
| 8369 | |
| 8370 // LoadL-locked - same as a regular LoadL when used with compare-swap | |
| 8371 instruct loadLLocked(rRegL dst, memory mem) | |
| 8372 %{ | |
| 8373 match(Set dst (LoadLLocked mem)); | |
| 8374 | |
| 8375 ins_cost(125); // XXX | |
| 8376 format %{ "movq $dst, $mem\t# long locked" %} | |
| 8377 opcode(0x8B); | |
| 8378 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); | |
| 8379 ins_pipe(ialu_reg_mem); // XXX | |
| 8380 %} | |
| 8381 | |
| 8382 // Conditional-store of the updated heap-top. | |
| 8383 // Used during allocation of the shared heap. | |
| 8384 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. | |
| 8385 | |
| 8386 instruct storePConditional(memory heap_top_ptr, | |
| 8387 rax_RegP oldval, rRegP newval, | |
| 8388 rFlagsReg cr) | |
| 8389 %{ | |
| 8390 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); | |
|
420
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changeset
|
8391 |
| 0 | 8392 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) " |
| 8393 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %} | |
| 8394 opcode(0x0F, 0xB1); | |
| 8395 ins_encode(lock_prefix, | |
| 8396 REX_reg_mem_wide(newval, heap_top_ptr), | |
| 8397 OpcP, OpcS, | |
| 8398 reg_mem(newval, heap_top_ptr)); | |
| 8399 ins_pipe(pipe_cmpxchg); | |
| 8400 %} | |
| 8401 | |
|
420
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|
8402 // Conditional-store of an int value. |
|
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|
8403 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
|
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|
8404 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr) |
|
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8405 %{ |
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8406 match(Set cr (StoreIConditional mem (Binary oldval newval))); |
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8407 effect(KILL oldval); |
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8408 |
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8409 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 8410 opcode(0x0F, 0xB1); |
| 8411 ins_encode(lock_prefix, | |
|
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8412 REX_reg_mem(newval, mem), |
| 0 | 8413 OpcP, OpcS, |
|
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8414 reg_mem(newval, mem)); |
| 0 | 8415 ins_pipe(pipe_cmpxchg); |
| 8416 %} | |
| 8417 | |
|
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8418 // Conditional-store of a long value. |
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8419 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG. |
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8420 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr) |
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8421 %{ |
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8422 match(Set cr (StoreLConditional mem (Binary oldval newval))); |
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8423 effect(KILL oldval); |
|
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8424 |
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8425 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %} |
| 0 | 8426 opcode(0x0F, 0xB1); |
| 8427 ins_encode(lock_prefix, | |
|
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8428 REX_reg_mem_wide(newval, mem), |
| 0 | 8429 OpcP, OpcS, |
|
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8430 reg_mem(newval, mem)); |
| 0 | 8431 ins_pipe(pipe_cmpxchg); |
| 8432 %} | |
| 8433 | |
|
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8434 |
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8435 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them |
| 0 | 8436 instruct compareAndSwapP(rRegI res, |
| 8437 memory mem_ptr, | |
| 8438 rax_RegP oldval, rRegP newval, | |
| 8439 rFlagsReg cr) | |
| 8440 %{ | |
| 8441 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); | |
| 8442 effect(KILL cr, KILL oldval); | |
| 8443 | |
| 8444 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 8445 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 8446 "sete $res\n\t" | |
| 8447 "movzbl $res, $res" %} | |
| 8448 opcode(0x0F, 0xB1); | |
| 8449 ins_encode(lock_prefix, | |
| 8450 REX_reg_mem_wide(newval, mem_ptr), | |
| 8451 OpcP, OpcS, | |
| 8452 reg_mem(newval, mem_ptr), | |
| 8453 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 8454 REX_reg_breg(res, res), // movzbl | |
| 8455 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 8456 ins_pipe( pipe_cmpxchg ); | |
| 8457 %} | |
| 8458 | |
| 8459 instruct compareAndSwapL(rRegI res, | |
| 8460 memory mem_ptr, | |
| 8461 rax_RegL oldval, rRegL newval, | |
| 8462 rFlagsReg cr) | |
| 8463 %{ | |
| 8464 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); | |
| 8465 effect(KILL cr, KILL oldval); | |
| 8466 | |
| 8467 format %{ "cmpxchgq $mem_ptr,$newval\t# " | |
| 8468 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 8469 "sete $res\n\t" | |
| 8470 "movzbl $res, $res" %} | |
| 8471 opcode(0x0F, 0xB1); | |
| 8472 ins_encode(lock_prefix, | |
| 8473 REX_reg_mem_wide(newval, mem_ptr), | |
| 8474 OpcP, OpcS, | |
| 8475 reg_mem(newval, mem_ptr), | |
| 8476 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 8477 REX_reg_breg(res, res), // movzbl | |
| 8478 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 8479 ins_pipe( pipe_cmpxchg ); | |
| 8480 %} | |
| 8481 | |
| 8482 instruct compareAndSwapI(rRegI res, | |
| 8483 memory mem_ptr, | |
| 8484 rax_RegI oldval, rRegI newval, | |
| 8485 rFlagsReg cr) | |
| 8486 %{ | |
| 8487 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); | |
| 8488 effect(KILL cr, KILL oldval); | |
| 8489 | |
| 8490 format %{ "cmpxchgl $mem_ptr,$newval\t# " | |
| 8491 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" | |
| 8492 "sete $res\n\t" | |
| 8493 "movzbl $res, $res" %} | |
| 8494 opcode(0x0F, 0xB1); | |
| 8495 ins_encode(lock_prefix, | |
| 8496 REX_reg_mem(newval, mem_ptr), | |
| 8497 OpcP, OpcS, | |
| 8498 reg_mem(newval, mem_ptr), | |
| 8499 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete | |
| 8500 REX_reg_breg(res, res), // movzbl | |
| 8501 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); | |
| 8502 ins_pipe( pipe_cmpxchg ); | |
| 8503 %} | |
| 8504 | |
| 8505 | |
|
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8506 instruct compareAndSwapN(rRegI res, |
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8507 memory mem_ptr, |
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8508 rax_RegN oldval, rRegN newval, |
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8509 rFlagsReg cr) %{ |
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8510 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); |
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8511 effect(KILL cr, KILL oldval); |
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8512 |
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8513 format %{ "cmpxchgl $mem_ptr,$newval\t# " |
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8514 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" |
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8515 "sete $res\n\t" |
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8516 "movzbl $res, $res" %} |
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8517 opcode(0x0F, 0xB1); |
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8518 ins_encode(lock_prefix, |
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8519 REX_reg_mem(newval, mem_ptr), |
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8520 OpcP, OpcS, |
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8521 reg_mem(newval, mem_ptr), |
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8522 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete |
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8523 REX_reg_breg(res, res), // movzbl |
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8524 Opcode(0xF), Opcode(0xB6), reg_reg(res, res)); |
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8525 ins_pipe( pipe_cmpxchg ); |
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8526 %} |
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8527 |
| 0 | 8528 //----------Subtraction Instructions------------------------------------------- |
| 8529 | |
| 8530 // Integer Subtraction Instructions | |
| 8531 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8532 %{ | |
| 8533 match(Set dst (SubI dst src)); | |
| 8534 effect(KILL cr); | |
| 8535 | |
| 8536 format %{ "subl $dst, $src\t# int" %} | |
| 8537 opcode(0x2B); | |
| 8538 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 8539 ins_pipe(ialu_reg_reg); | |
| 8540 %} | |
| 8541 | |
| 8542 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 8543 %{ | |
| 8544 match(Set dst (SubI dst src)); | |
| 8545 effect(KILL cr); | |
| 8546 | |
| 8547 format %{ "subl $dst, $src\t# int" %} | |
| 8548 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 8549 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 8550 ins_pipe(ialu_reg); | |
| 8551 %} | |
| 8552 | |
| 8553 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8554 %{ | |
| 8555 match(Set dst (SubI dst (LoadI src))); | |
| 8556 effect(KILL cr); | |
| 8557 | |
| 8558 ins_cost(125); | |
| 8559 format %{ "subl $dst, $src\t# int" %} | |
| 8560 opcode(0x2B); | |
| 8561 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 8562 ins_pipe(ialu_reg_mem); | |
| 8563 %} | |
| 8564 | |
| 8565 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 8566 %{ | |
| 8567 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 8568 effect(KILL cr); | |
| 8569 | |
| 8570 ins_cost(150); | |
| 8571 format %{ "subl $dst, $src\t# int" %} | |
| 8572 opcode(0x29); /* Opcode 29 /r */ | |
| 8573 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 8574 ins_pipe(ialu_mem_reg); | |
| 8575 %} | |
| 8576 | |
| 8577 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 8578 %{ | |
| 8579 match(Set dst (StoreI dst (SubI (LoadI dst) src))); | |
| 8580 effect(KILL cr); | |
| 8581 | |
| 8582 ins_cost(125); // XXX | |
| 8583 format %{ "subl $dst, $src\t# int" %} | |
| 8584 opcode(0x81); /* Opcode 81 /5 id */ | |
| 8585 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 8586 ins_pipe(ialu_mem_imm); | |
| 8587 %} | |
| 8588 | |
| 8589 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8590 %{ | |
| 8591 match(Set dst (SubL dst src)); | |
| 8592 effect(KILL cr); | |
| 8593 | |
| 8594 format %{ "subq $dst, $src\t# long" %} | |
| 8595 opcode(0x2B); | |
| 8596 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8597 ins_pipe(ialu_reg_reg); | |
| 8598 %} | |
| 8599 | |
| 8600 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr) | |
| 8601 %{ | |
| 8602 match(Set dst (SubL dst src)); | |
| 8603 effect(KILL cr); | |
| 8604 | |
| 8605 format %{ "subq $dst, $src\t# long" %} | |
| 8606 opcode(0x81, 0x05); /* Opcode 81 /5 */ | |
| 8607 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 8608 ins_pipe(ialu_reg); | |
| 8609 %} | |
| 8610 | |
| 8611 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8612 %{ | |
| 8613 match(Set dst (SubL dst (LoadL src))); | |
| 8614 effect(KILL cr); | |
| 8615 | |
| 8616 ins_cost(125); | |
| 8617 format %{ "subq $dst, $src\t# long" %} | |
| 8618 opcode(0x2B); | |
| 8619 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 8620 ins_pipe(ialu_reg_mem); | |
| 8621 %} | |
| 8622 | |
| 8623 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 8624 %{ | |
| 8625 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 8626 effect(KILL cr); | |
| 8627 | |
| 8628 ins_cost(150); | |
| 8629 format %{ "subq $dst, $src\t# long" %} | |
| 8630 opcode(0x29); /* Opcode 29 /r */ | |
| 8631 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 8632 ins_pipe(ialu_mem_reg); | |
| 8633 %} | |
| 8634 | |
| 8635 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 8636 %{ | |
| 8637 match(Set dst (StoreL dst (SubL (LoadL dst) src))); | |
| 8638 effect(KILL cr); | |
| 8639 | |
| 8640 ins_cost(125); // XXX | |
| 8641 format %{ "subq $dst, $src\t# long" %} | |
| 8642 opcode(0x81); /* Opcode 81 /5 id */ | |
| 8643 ins_encode(REX_mem_wide(dst), | |
| 8644 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src)); | |
| 8645 ins_pipe(ialu_mem_imm); | |
| 8646 %} | |
| 8647 | |
| 8648 // Subtract from a pointer | |
| 8649 // XXX hmpf??? | |
| 8650 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr) | |
| 8651 %{ | |
| 8652 match(Set dst (AddP dst (SubI zero src))); | |
| 8653 effect(KILL cr); | |
| 8654 | |
| 8655 format %{ "subq $dst, $src\t# ptr - int" %} | |
| 8656 opcode(0x2B); | |
| 8657 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 8658 ins_pipe(ialu_reg_reg); | |
| 8659 %} | |
| 8660 | |
| 8661 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 8662 %{ | |
| 8663 match(Set dst (SubI zero dst)); | |
| 8664 effect(KILL cr); | |
| 8665 | |
| 8666 format %{ "negl $dst\t# int" %} | |
| 8667 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8668 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 8669 ins_pipe(ialu_reg); | |
| 8670 %} | |
| 8671 | |
| 8672 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr) | |
| 8673 %{ | |
| 8674 match(Set dst (StoreI dst (SubI zero (LoadI dst)))); | |
| 8675 effect(KILL cr); | |
| 8676 | |
| 8677 format %{ "negl $dst\t# int" %} | |
| 8678 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8679 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8680 ins_pipe(ialu_reg); | |
| 8681 %} | |
| 8682 | |
| 8683 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr) | |
| 8684 %{ | |
| 8685 match(Set dst (SubL zero dst)); | |
| 8686 effect(KILL cr); | |
| 8687 | |
| 8688 format %{ "negq $dst\t# long" %} | |
| 8689 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8690 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 8691 ins_pipe(ialu_reg); | |
| 8692 %} | |
| 8693 | |
| 8694 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr) | |
| 8695 %{ | |
| 8696 match(Set dst (StoreL dst (SubL zero (LoadL dst)))); | |
| 8697 effect(KILL cr); | |
| 8698 | |
| 8699 format %{ "negq $dst\t# long" %} | |
| 8700 opcode(0xF7, 0x03); // Opcode F7 /3 | |
| 8701 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 8702 ins_pipe(ialu_reg); | |
| 8703 %} | |
| 8704 | |
| 8705 | |
| 8706 //----------Multiplication/Division Instructions------------------------------- | |
| 8707 // Integer Multiplication Instructions | |
| 8708 // Multiply Register | |
| 8709 | |
| 8710 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 8711 %{ | |
| 8712 match(Set dst (MulI dst src)); | |
| 8713 effect(KILL cr); | |
| 8714 | |
| 8715 ins_cost(300); | |
| 8716 format %{ "imull $dst, $src\t# int" %} | |
| 8717 opcode(0x0F, 0xAF); | |
| 8718 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8719 ins_pipe(ialu_reg_reg_alu0); | |
| 8720 %} | |
| 8721 | |
| 8722 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr) | |
| 8723 %{ | |
| 8724 match(Set dst (MulI src imm)); | |
| 8725 effect(KILL cr); | |
| 8726 | |
| 8727 ins_cost(300); | |
| 8728 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 8729 opcode(0x69); /* 69 /r id */ | |
| 8730 ins_encode(REX_reg_reg(dst, src), | |
| 8731 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 8732 ins_pipe(ialu_reg_reg_alu0); | |
| 8733 %} | |
| 8734 | |
| 8735 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 8736 %{ | |
| 8737 match(Set dst (MulI dst (LoadI src))); | |
| 8738 effect(KILL cr); | |
| 8739 | |
| 8740 ins_cost(350); | |
| 8741 format %{ "imull $dst, $src\t# int" %} | |
| 8742 opcode(0x0F, 0xAF); | |
| 8743 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 8744 ins_pipe(ialu_reg_mem_alu0); | |
| 8745 %} | |
| 8746 | |
| 8747 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr) | |
| 8748 %{ | |
| 8749 match(Set dst (MulI (LoadI src) imm)); | |
| 8750 effect(KILL cr); | |
| 8751 | |
| 8752 ins_cost(300); | |
| 8753 format %{ "imull $dst, $src, $imm\t# int" %} | |
| 8754 opcode(0x69); /* 69 /r id */ | |
| 8755 ins_encode(REX_reg_mem(dst, src), | |
| 8756 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 8757 ins_pipe(ialu_reg_mem_alu0); | |
| 8758 %} | |
| 8759 | |
| 8760 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 8761 %{ | |
| 8762 match(Set dst (MulL dst src)); | |
| 8763 effect(KILL cr); | |
| 8764 | |
| 8765 ins_cost(300); | |
| 8766 format %{ "imulq $dst, $src\t# long" %} | |
| 8767 opcode(0x0F, 0xAF); | |
| 8768 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 8769 ins_pipe(ialu_reg_reg_alu0); | |
| 8770 %} | |
| 8771 | |
| 8772 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr) | |
| 8773 %{ | |
| 8774 match(Set dst (MulL src imm)); | |
| 8775 effect(KILL cr); | |
| 8776 | |
| 8777 ins_cost(300); | |
| 8778 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 8779 opcode(0x69); /* 69 /r id */ | |
| 8780 ins_encode(REX_reg_reg_wide(dst, src), | |
| 8781 OpcSE(imm), reg_reg(dst, src), Con8or32(imm)); | |
| 8782 ins_pipe(ialu_reg_reg_alu0); | |
| 8783 %} | |
| 8784 | |
| 8785 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 8786 %{ | |
| 8787 match(Set dst (MulL dst (LoadL src))); | |
| 8788 effect(KILL cr); | |
| 8789 | |
| 8790 ins_cost(350); | |
| 8791 format %{ "imulq $dst, $src\t# long" %} | |
| 8792 opcode(0x0F, 0xAF); | |
| 8793 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src)); | |
| 8794 ins_pipe(ialu_reg_mem_alu0); | |
| 8795 %} | |
| 8796 | |
| 8797 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr) | |
| 8798 %{ | |
| 8799 match(Set dst (MulL (LoadL src) imm)); | |
| 8800 effect(KILL cr); | |
| 8801 | |
| 8802 ins_cost(300); | |
| 8803 format %{ "imulq $dst, $src, $imm\t# long" %} | |
| 8804 opcode(0x69); /* 69 /r id */ | |
| 8805 ins_encode(REX_reg_mem_wide(dst, src), | |
| 8806 OpcSE(imm), reg_mem(dst, src), Con8or32(imm)); | |
| 8807 ins_pipe(ialu_reg_mem_alu0); | |
| 8808 %} | |
| 8809 | |
| 145 | 8810 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) |
| 8811 %{ | |
| 8812 match(Set dst (MulHiL src rax)); | |
| 8813 effect(USE_KILL rax, KILL cr); | |
| 8814 | |
| 8815 ins_cost(300); | |
| 8816 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %} | |
| 8817 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8818 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8819 ins_pipe(ialu_reg_reg_alu0); | |
| 8820 %} | |
| 8821 | |
| 0 | 8822 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, |
| 8823 rFlagsReg cr) | |
| 8824 %{ | |
| 8825 match(Set rax (DivI rax div)); | |
| 8826 effect(KILL rdx, KILL cr); | |
| 8827 | |
| 8828 ins_cost(30*100+10*100); // XXX | |
| 8829 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8830 "jne,s normal\n\t" | |
| 8831 "xorl rdx, rdx\n\t" | |
| 8832 "cmpl $div, -1\n\t" | |
| 8833 "je,s done\n" | |
| 8834 "normal: cdql\n\t" | |
| 8835 "idivl $div\n" | |
| 8836 "done:" %} | |
| 8837 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8838 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8839 ins_pipe(ialu_reg_reg_alu0); | |
| 8840 %} | |
| 8841 | |
| 8842 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8843 rFlagsReg cr) | |
| 8844 %{ | |
| 8845 match(Set rax (DivL rax div)); | |
| 8846 effect(KILL rdx, KILL cr); | |
| 8847 | |
| 8848 ins_cost(30*100+10*100); // XXX | |
| 8849 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8850 "cmpq rax, rdx\n\t" | |
| 8851 "jne,s normal\n\t" | |
| 8852 "xorl rdx, rdx\n\t" | |
| 8853 "cmpq $div, -1\n\t" | |
| 8854 "je,s done\n" | |
| 8855 "normal: cdqq\n\t" | |
| 8856 "idivq $div\n" | |
| 8857 "done:" %} | |
| 8858 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8859 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8860 ins_pipe(ialu_reg_reg_alu0); | |
| 8861 %} | |
| 8862 | |
| 8863 // Integer DIVMOD with Register, both quotient and mod results | |
| 8864 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, | |
| 8865 rFlagsReg cr) | |
| 8866 %{ | |
| 8867 match(DivModI rax div); | |
| 8868 effect(KILL cr); | |
| 8869 | |
| 8870 ins_cost(30*100+10*100); // XXX | |
| 8871 format %{ "cmpl rax, 0x80000000\t# idiv\n\t" | |
| 8872 "jne,s normal\n\t" | |
| 8873 "xorl rdx, rdx\n\t" | |
| 8874 "cmpl $div, -1\n\t" | |
| 8875 "je,s done\n" | |
| 8876 "normal: cdql\n\t" | |
| 8877 "idivl $div\n" | |
| 8878 "done:" %} | |
| 8879 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8880 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8881 ins_pipe(pipe_slow); | |
| 8882 %} | |
| 8883 | |
| 8884 // Long DIVMOD with Register, both quotient and mod results | |
| 8885 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, | |
| 8886 rFlagsReg cr) | |
| 8887 %{ | |
| 8888 match(DivModL rax div); | |
| 8889 effect(KILL cr); | |
| 8890 | |
| 8891 ins_cost(30*100+10*100); // XXX | |
| 8892 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t" | |
| 8893 "cmpq rax, rdx\n\t" | |
| 8894 "jne,s normal\n\t" | |
| 8895 "xorl rdx, rdx\n\t" | |
| 8896 "cmpq $div, -1\n\t" | |
| 8897 "je,s done\n" | |
| 8898 "normal: cdqq\n\t" | |
| 8899 "idivq $div\n" | |
| 8900 "done:" %} | |
| 8901 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8902 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 8903 ins_pipe(pipe_slow); | |
| 8904 %} | |
| 8905 | |
| 8906 //----------- DivL-By-Constant-Expansions-------------------------------------- | |
| 8907 // DivI cases are handled by the compiler | |
| 8908 | |
| 605 | 8909 // Magic constant, reciprocal of 10 |
| 0 | 8910 instruct loadConL_0x6666666666666667(rRegL dst) |
| 8911 %{ | |
| 8912 effect(DEF dst); | |
| 8913 | |
| 8914 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %} | |
| 8915 ins_encode(load_immL(dst, 0x6666666666666667)); | |
| 8916 ins_pipe(ialu_reg); | |
| 8917 %} | |
| 8918 | |
| 8919 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr) | |
| 8920 %{ | |
| 8921 effect(DEF dst, USE src, USE_KILL rax, KILL cr); | |
| 8922 | |
| 8923 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %} | |
| 8924 opcode(0xF7, 0x5); /* Opcode F7 /5 */ | |
| 8925 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src)); | |
| 8926 ins_pipe(ialu_reg_reg_alu0); | |
| 8927 %} | |
| 8928 | |
| 8929 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr) | |
| 8930 %{ | |
| 8931 effect(USE_DEF dst, KILL cr); | |
| 8932 | |
| 8933 format %{ "sarq $dst, #63\t# Used in div-by-10" %} | |
| 8934 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8935 ins_encode(reg_opc_imm_wide(dst, 0x3F)); | |
| 8936 ins_pipe(ialu_reg); | |
| 8937 %} | |
| 8938 | |
| 8939 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr) | |
| 8940 %{ | |
| 8941 effect(USE_DEF dst, KILL cr); | |
| 8942 | |
| 8943 format %{ "sarq $dst, #2\t# Used in div-by-10" %} | |
| 8944 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 8945 ins_encode(reg_opc_imm_wide(dst, 0x2)); | |
| 8946 ins_pipe(ialu_reg); | |
| 8947 %} | |
| 8948 | |
| 8949 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div) | |
| 8950 %{ | |
| 8951 match(Set dst (DivL src div)); | |
| 8952 | |
| 8953 ins_cost((5+8)*100); | |
| 8954 expand %{ | |
| 8955 rax_RegL rax; // Killed temp | |
| 8956 rFlagsReg cr; // Killed | |
| 8957 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667 | |
| 8958 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src | |
| 8959 sarL_rReg_63(src, cr); // sarq src, 63 | |
| 8960 sarL_rReg_2(dst, cr); // sarq rdx, 2 | |
| 8961 subL_rReg(dst, src, cr); // subl rdx, src | |
| 8962 %} | |
| 8963 %} | |
| 8964 | |
| 8965 //----------------------------------------------------------------------------- | |
| 8966 | |
| 8967 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, | |
| 8968 rFlagsReg cr) | |
| 8969 %{ | |
| 8970 match(Set rdx (ModI rax div)); | |
| 8971 effect(KILL rax, KILL cr); | |
| 8972 | |
| 8973 ins_cost(300); // XXX | |
| 8974 format %{ "cmpl rax, 0x80000000\t# irem\n\t" | |
| 8975 "jne,s normal\n\t" | |
| 8976 "xorl rdx, rdx\n\t" | |
| 8977 "cmpl $div, -1\n\t" | |
| 8978 "je,s done\n" | |
| 8979 "normal: cdql\n\t" | |
| 8980 "idivl $div\n" | |
| 8981 "done:" %} | |
| 8982 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 8983 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div)); | |
| 8984 ins_pipe(ialu_reg_reg_alu0); | |
| 8985 %} | |
| 8986 | |
| 8987 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, | |
| 8988 rFlagsReg cr) | |
| 8989 %{ | |
| 8990 match(Set rdx (ModL rax div)); | |
| 8991 effect(KILL rax, KILL cr); | |
| 8992 | |
| 8993 ins_cost(300); // XXX | |
| 8994 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t" | |
| 8995 "cmpq rax, rdx\n\t" | |
| 8996 "jne,s normal\n\t" | |
| 8997 "xorl rdx, rdx\n\t" | |
| 8998 "cmpq $div, -1\n\t" | |
| 8999 "je,s done\n" | |
| 9000 "normal: cdqq\n\t" | |
| 9001 "idivq $div\n" | |
| 9002 "done:" %} | |
| 9003 opcode(0xF7, 0x7); /* Opcode F7 /7 */ | |
| 9004 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div)); | |
| 9005 ins_pipe(ialu_reg_reg_alu0); | |
| 9006 %} | |
| 9007 | |
| 9008 // Integer Shift Instructions | |
| 9009 // Shift Left by one | |
| 9010 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 9011 %{ | |
| 9012 match(Set dst (LShiftI dst shift)); | |
| 9013 effect(KILL cr); | |
| 9014 | |
| 9015 format %{ "sall $dst, $shift" %} | |
| 9016 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 9017 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9018 ins_pipe(ialu_reg); | |
| 9019 %} | |
| 9020 | |
| 9021 // Shift Left by one | |
| 9022 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9023 %{ | |
| 9024 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 9025 effect(KILL cr); | |
| 9026 | |
| 9027 format %{ "sall $dst, $shift\t" %} | |
| 9028 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 9029 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9030 ins_pipe(ialu_mem_imm); | |
| 9031 %} | |
| 9032 | |
| 9033 // Shift Left by 8-bit immediate | |
| 9034 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 9035 %{ | |
| 9036 match(Set dst (LShiftI dst shift)); | |
| 9037 effect(KILL cr); | |
| 9038 | |
| 9039 format %{ "sall $dst, $shift" %} | |
| 9040 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9041 ins_encode(reg_opc_imm(dst, shift)); | |
| 9042 ins_pipe(ialu_reg); | |
| 9043 %} | |
| 9044 | |
| 9045 // Shift Left by 8-bit immediate | |
| 9046 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9047 %{ | |
| 9048 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 9049 effect(KILL cr); | |
| 9050 | |
| 9051 format %{ "sall $dst, $shift" %} | |
| 9052 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9053 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9054 ins_pipe(ialu_mem_imm); | |
| 9055 %} | |
| 9056 | |
| 9057 // Shift Left by variable | |
| 9058 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9059 %{ | |
| 9060 match(Set dst (LShiftI dst shift)); | |
| 9061 effect(KILL cr); | |
| 9062 | |
| 9063 format %{ "sall $dst, $shift" %} | |
| 9064 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 9065 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9066 ins_pipe(ialu_reg_reg); | |
| 9067 %} | |
| 9068 | |
| 9069 // Shift Left by variable | |
| 9070 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9071 %{ | |
| 9072 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift))); | |
| 9073 effect(KILL cr); | |
| 9074 | |
| 9075 format %{ "sall $dst, $shift" %} | |
| 9076 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 9077 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9078 ins_pipe(ialu_mem_reg); | |
| 9079 %} | |
| 9080 | |
| 9081 // Arithmetic shift right by one | |
| 9082 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 9083 %{ | |
| 9084 match(Set dst (RShiftI dst shift)); | |
| 9085 effect(KILL cr); | |
| 9086 | |
| 9087 format %{ "sarl $dst, $shift" %} | |
| 9088 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9089 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9090 ins_pipe(ialu_reg); | |
| 9091 %} | |
| 9092 | |
| 9093 // Arithmetic shift right by one | |
| 9094 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9095 %{ | |
| 9096 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 9097 effect(KILL cr); | |
| 9098 | |
| 9099 format %{ "sarl $dst, $shift" %} | |
| 9100 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9101 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9102 ins_pipe(ialu_mem_imm); | |
| 9103 %} | |
| 9104 | |
| 9105 // Arithmetic Shift Right by 8-bit immediate | |
| 9106 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 9107 %{ | |
| 9108 match(Set dst (RShiftI dst shift)); | |
| 9109 effect(KILL cr); | |
| 9110 | |
| 9111 format %{ "sarl $dst, $shift" %} | |
| 9112 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9113 ins_encode(reg_opc_imm(dst, shift)); | |
| 9114 ins_pipe(ialu_mem_imm); | |
| 9115 %} | |
| 9116 | |
| 9117 // Arithmetic Shift Right by 8-bit immediate | |
| 9118 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9119 %{ | |
| 9120 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 9121 effect(KILL cr); | |
| 9122 | |
| 9123 format %{ "sarl $dst, $shift" %} | |
| 9124 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9125 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9126 ins_pipe(ialu_mem_imm); | |
| 9127 %} | |
| 9128 | |
| 9129 // Arithmetic Shift Right by variable | |
| 9130 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9131 %{ | |
| 9132 match(Set dst (RShiftI dst shift)); | |
| 9133 effect(KILL cr); | |
| 9134 | |
| 9135 format %{ "sarl $dst, $shift" %} | |
| 9136 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9137 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9138 ins_pipe(ialu_reg_reg); | |
| 9139 %} | |
| 9140 | |
| 9141 // Arithmetic Shift Right by variable | |
| 9142 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9143 %{ | |
| 9144 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); | |
| 9145 effect(KILL cr); | |
| 9146 | |
| 9147 format %{ "sarl $dst, $shift" %} | |
| 9148 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9149 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9150 ins_pipe(ialu_mem_reg); | |
| 9151 %} | |
| 9152 | |
| 9153 // Logical shift right by one | |
| 9154 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr) | |
| 9155 %{ | |
| 9156 match(Set dst (URShiftI dst shift)); | |
| 9157 effect(KILL cr); | |
| 9158 | |
| 9159 format %{ "shrl $dst, $shift" %} | |
| 9160 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9161 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9162 ins_pipe(ialu_reg); | |
| 9163 %} | |
| 9164 | |
| 9165 // Logical shift right by one | |
| 9166 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9167 %{ | |
| 9168 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 9169 effect(KILL cr); | |
| 9170 | |
| 9171 format %{ "shrl $dst, $shift" %} | |
| 9172 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9173 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9174 ins_pipe(ialu_mem_imm); | |
| 9175 %} | |
| 9176 | |
| 9177 // Logical Shift Right by 8-bit immediate | |
| 9178 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 9179 %{ | |
| 9180 match(Set dst (URShiftI dst shift)); | |
| 9181 effect(KILL cr); | |
| 9182 | |
| 9183 format %{ "shrl $dst, $shift" %} | |
| 9184 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9185 ins_encode(reg_opc_imm(dst, shift)); | |
| 9186 ins_pipe(ialu_reg); | |
| 9187 %} | |
| 9188 | |
| 9189 // Logical Shift Right by 8-bit immediate | |
| 9190 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9191 %{ | |
| 9192 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 9193 effect(KILL cr); | |
| 9194 | |
| 9195 format %{ "shrl $dst, $shift" %} | |
| 9196 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9197 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9198 ins_pipe(ialu_mem_imm); | |
| 9199 %} | |
| 9200 | |
| 9201 // Logical Shift Right by variable | |
| 9202 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9203 %{ | |
| 9204 match(Set dst (URShiftI dst shift)); | |
| 9205 effect(KILL cr); | |
| 9206 | |
| 9207 format %{ "shrl $dst, $shift" %} | |
| 9208 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9209 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9210 ins_pipe(ialu_reg_reg); | |
| 9211 %} | |
| 9212 | |
| 9213 // Logical Shift Right by variable | |
| 9214 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9215 %{ | |
| 9216 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift))); | |
| 9217 effect(KILL cr); | |
| 9218 | |
| 9219 format %{ "shrl $dst, $shift" %} | |
| 9220 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9221 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9222 ins_pipe(ialu_mem_reg); | |
| 9223 %} | |
| 9224 | |
| 9225 // Long Shift Instructions | |
| 9226 // Shift Left by one | |
| 9227 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 9228 %{ | |
| 9229 match(Set dst (LShiftL dst shift)); | |
| 9230 effect(KILL cr); | |
| 9231 | |
| 9232 format %{ "salq $dst, $shift" %} | |
| 9233 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 9234 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9235 ins_pipe(ialu_reg); | |
| 9236 %} | |
| 9237 | |
| 9238 // Shift Left by one | |
| 9239 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9240 %{ | |
| 9241 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 9242 effect(KILL cr); | |
| 9243 | |
| 9244 format %{ "salq $dst, $shift" %} | |
| 9245 opcode(0xD1, 0x4); /* D1 /4 */ | |
| 9246 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9247 ins_pipe(ialu_mem_imm); | |
| 9248 %} | |
| 9249 | |
| 9250 // Shift Left by 8-bit immediate | |
| 9251 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9252 %{ | |
| 9253 match(Set dst (LShiftL dst shift)); | |
| 9254 effect(KILL cr); | |
| 9255 | |
| 9256 format %{ "salq $dst, $shift" %} | |
| 9257 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9258 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9259 ins_pipe(ialu_reg); | |
| 9260 %} | |
| 9261 | |
| 9262 // Shift Left by 8-bit immediate | |
| 9263 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9264 %{ | |
| 9265 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 9266 effect(KILL cr); | |
| 9267 | |
| 9268 format %{ "salq $dst, $shift" %} | |
| 9269 opcode(0xC1, 0x4); /* C1 /4 ib */ | |
| 9270 ins_encode(REX_mem_wide(dst), OpcP, | |
| 9271 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9272 ins_pipe(ialu_mem_imm); | |
| 9273 %} | |
| 9274 | |
| 9275 // Shift Left by variable | |
| 9276 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9277 %{ | |
| 9278 match(Set dst (LShiftL dst shift)); | |
| 9279 effect(KILL cr); | |
| 9280 | |
| 9281 format %{ "salq $dst, $shift" %} | |
| 9282 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 9283 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9284 ins_pipe(ialu_reg_reg); | |
| 9285 %} | |
| 9286 | |
| 9287 // Shift Left by variable | |
| 9288 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9289 %{ | |
| 9290 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift))); | |
| 9291 effect(KILL cr); | |
| 9292 | |
| 9293 format %{ "salq $dst, $shift" %} | |
| 9294 opcode(0xD3, 0x4); /* D3 /4 */ | |
| 9295 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9296 ins_pipe(ialu_mem_reg); | |
| 9297 %} | |
| 9298 | |
| 9299 // Arithmetic shift right by one | |
| 9300 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 9301 %{ | |
| 9302 match(Set dst (RShiftL dst shift)); | |
| 9303 effect(KILL cr); | |
| 9304 | |
| 9305 format %{ "sarq $dst, $shift" %} | |
| 9306 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9307 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9308 ins_pipe(ialu_reg); | |
| 9309 %} | |
| 9310 | |
| 9311 // Arithmetic shift right by one | |
| 9312 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9313 %{ | |
| 9314 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 9315 effect(KILL cr); | |
| 9316 | |
| 9317 format %{ "sarq $dst, $shift" %} | |
| 9318 opcode(0xD1, 0x7); /* D1 /7 */ | |
| 9319 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9320 ins_pipe(ialu_mem_imm); | |
| 9321 %} | |
| 9322 | |
| 9323 // Arithmetic Shift Right by 8-bit immediate | |
| 9324 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9325 %{ | |
| 9326 match(Set dst (RShiftL dst shift)); | |
| 9327 effect(KILL cr); | |
| 9328 | |
| 9329 format %{ "sarq $dst, $shift" %} | |
| 9330 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9331 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9332 ins_pipe(ialu_mem_imm); | |
| 9333 %} | |
| 9334 | |
| 9335 // Arithmetic Shift Right by 8-bit immediate | |
| 9336 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9337 %{ | |
| 9338 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 9339 effect(KILL cr); | |
| 9340 | |
| 9341 format %{ "sarq $dst, $shift" %} | |
| 9342 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 9343 ins_encode(REX_mem_wide(dst), OpcP, | |
| 9344 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9345 ins_pipe(ialu_mem_imm); | |
| 9346 %} | |
| 9347 | |
| 9348 // Arithmetic Shift Right by variable | |
| 9349 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9350 %{ | |
| 9351 match(Set dst (RShiftL dst shift)); | |
| 9352 effect(KILL cr); | |
| 9353 | |
| 9354 format %{ "sarq $dst, $shift" %} | |
| 9355 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9356 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9357 ins_pipe(ialu_reg_reg); | |
| 9358 %} | |
| 9359 | |
| 9360 // Arithmetic Shift Right by variable | |
| 9361 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9362 %{ | |
| 9363 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift))); | |
| 9364 effect(KILL cr); | |
| 9365 | |
| 9366 format %{ "sarq $dst, $shift" %} | |
| 9367 opcode(0xD3, 0x7); /* D3 /7 */ | |
| 9368 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9369 ins_pipe(ialu_mem_reg); | |
| 9370 %} | |
| 9371 | |
| 9372 // Logical shift right by one | |
| 9373 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr) | |
| 9374 %{ | |
| 9375 match(Set dst (URShiftL dst shift)); | |
| 9376 effect(KILL cr); | |
| 9377 | |
| 9378 format %{ "shrq $dst, $shift" %} | |
| 9379 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9380 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst )); | |
| 9381 ins_pipe(ialu_reg); | |
| 9382 %} | |
| 9383 | |
| 9384 // Logical shift right by one | |
| 9385 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr) | |
| 9386 %{ | |
| 9387 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 9388 effect(KILL cr); | |
| 9389 | |
| 9390 format %{ "shrq $dst, $shift" %} | |
| 9391 opcode(0xD1, 0x5); /* D1 /5 */ | |
| 9392 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9393 ins_pipe(ialu_mem_imm); | |
| 9394 %} | |
| 9395 | |
| 9396 // Logical Shift Right by 8-bit immediate | |
| 9397 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9398 %{ | |
| 9399 match(Set dst (URShiftL dst shift)); | |
| 9400 effect(KILL cr); | |
| 9401 | |
| 9402 format %{ "shrq $dst, $shift" %} | |
| 9403 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9404 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9405 ins_pipe(ialu_reg); | |
| 9406 %} | |
| 9407 | |
|
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|
9408 |
| 0 | 9409 // Logical Shift Right by 8-bit immediate |
| 9410 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr) | |
| 9411 %{ | |
| 9412 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 9413 effect(KILL cr); | |
| 9414 | |
| 9415 format %{ "shrq $dst, $shift" %} | |
| 9416 opcode(0xC1, 0x5); /* C1 /5 ib */ | |
| 9417 ins_encode(REX_mem_wide(dst), OpcP, | |
| 9418 RM_opc_mem(secondary, dst), Con8or32(shift)); | |
| 9419 ins_pipe(ialu_mem_imm); | |
| 9420 %} | |
| 9421 | |
| 9422 // Logical Shift Right by variable | |
| 9423 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9424 %{ | |
| 9425 match(Set dst (URShiftL dst shift)); | |
| 9426 effect(KILL cr); | |
| 9427 | |
| 9428 format %{ "shrq $dst, $shift" %} | |
| 9429 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9430 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9431 ins_pipe(ialu_reg_reg); | |
| 9432 %} | |
| 9433 | |
| 9434 // Logical Shift Right by variable | |
| 9435 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr) | |
| 9436 %{ | |
| 9437 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift))); | |
| 9438 effect(KILL cr); | |
| 9439 | |
| 9440 format %{ "shrq $dst, $shift" %} | |
| 9441 opcode(0xD3, 0x5); /* D3 /5 */ | |
| 9442 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst)); | |
| 9443 ins_pipe(ialu_mem_reg); | |
| 9444 %} | |
| 9445 | |
| 9446 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. | |
| 9447 // This idiom is used by the compiler for the i2b bytecode. | |
| 9448 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour) | |
| 9449 %{ | |
| 9450 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); | |
| 9451 | |
| 9452 format %{ "movsbl $dst, $src\t# i2b" %} | |
| 9453 opcode(0x0F, 0xBE); | |
| 9454 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9455 ins_pipe(ialu_reg_reg); | |
| 9456 %} | |
| 9457 | |
| 9458 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. | |
| 9459 // This idiom is used by the compiler the i2s bytecode. | |
| 9460 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen) | |
| 9461 %{ | |
| 9462 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); | |
| 9463 | |
| 9464 format %{ "movswl $dst, $src\t# i2s" %} | |
| 9465 opcode(0x0F, 0xBF); | |
| 9466 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9467 ins_pipe(ialu_reg_reg); | |
| 9468 %} | |
| 9469 | |
| 9470 // ROL/ROR instructions | |
| 9471 | |
| 9472 // ROL expand | |
| 9473 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{ | |
| 9474 effect(KILL cr, USE_DEF dst); | |
| 9475 | |
| 9476 format %{ "roll $dst" %} | |
| 9477 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 9478 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9479 ins_pipe(ialu_reg); | |
| 9480 %} | |
| 9481 | |
| 9482 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{ | |
| 9483 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9484 | |
| 9485 format %{ "roll $dst, $shift" %} | |
| 9486 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 9487 ins_encode( reg_opc_imm(dst, shift) ); | |
| 9488 ins_pipe(ialu_reg); | |
| 9489 %} | |
| 9490 | |
| 9491 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9492 %{ | |
| 9493 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9494 | |
| 9495 format %{ "roll $dst, $shift" %} | |
| 9496 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 9497 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9498 ins_pipe(ialu_reg_reg); | |
| 9499 %} | |
| 9500 // end of ROL expand | |
| 9501 | |
| 9502 // Rotate Left by one | |
| 9503 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 9504 %{ | |
| 9505 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9506 | |
| 9507 expand %{ | |
| 9508 rolI_rReg_imm1(dst, cr); | |
| 9509 %} | |
| 9510 %} | |
| 9511 | |
| 9512 // Rotate Left by 8-bit immediate | |
| 9513 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 9514 %{ | |
| 9515 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9516 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift))); | |
| 9517 | |
| 9518 expand %{ | |
| 9519 rolI_rReg_imm8(dst, lshift, cr); | |
| 9520 %} | |
| 9521 %} | |
| 9522 | |
| 9523 // Rotate Left by variable | |
| 9524 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9525 %{ | |
| 9526 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); | |
| 9527 | |
| 9528 expand %{ | |
| 9529 rolI_rReg_CL(dst, shift, cr); | |
| 9530 %} | |
| 9531 %} | |
| 9532 | |
| 9533 // Rotate Left by variable | |
| 9534 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 9535 %{ | |
| 9536 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); | |
| 9537 | |
| 9538 expand %{ | |
| 9539 rolI_rReg_CL(dst, shift, cr); | |
| 9540 %} | |
| 9541 %} | |
| 9542 | |
| 9543 // ROR expand | |
| 9544 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr) | |
| 9545 %{ | |
| 9546 effect(USE_DEF dst, KILL cr); | |
| 9547 | |
| 9548 format %{ "rorl $dst" %} | |
| 9549 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 9550 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9551 ins_pipe(ialu_reg); | |
| 9552 %} | |
| 9553 | |
| 9554 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) | |
| 9555 %{ | |
| 9556 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9557 | |
| 9558 format %{ "rorl $dst, $shift" %} | |
| 9559 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 9560 ins_encode(reg_opc_imm(dst, shift)); | |
| 9561 ins_pipe(ialu_reg); | |
| 9562 %} | |
| 9563 | |
| 9564 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr) | |
| 9565 %{ | |
| 9566 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9567 | |
| 9568 format %{ "rorl $dst, $shift" %} | |
| 9569 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 9570 ins_encode(REX_reg(dst), OpcP, reg_opc(dst)); | |
| 9571 ins_pipe(ialu_reg_reg); | |
| 9572 %} | |
| 9573 // end of ROR expand | |
| 9574 | |
| 9575 // Rotate Right by one | |
| 9576 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 9577 %{ | |
| 9578 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9579 | |
| 9580 expand %{ | |
| 9581 rorI_rReg_imm1(dst, cr); | |
| 9582 %} | |
| 9583 %} | |
| 9584 | |
| 9585 // Rotate Right by 8-bit immediate | |
| 9586 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 9587 %{ | |
| 9588 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); | |
| 9589 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift))); | |
| 9590 | |
| 9591 expand %{ | |
| 9592 rorI_rReg_imm8(dst, rshift, cr); | |
| 9593 %} | |
| 9594 %} | |
| 9595 | |
| 9596 // Rotate Right by variable | |
| 9597 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9598 %{ | |
| 9599 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); | |
| 9600 | |
| 9601 expand %{ | |
| 9602 rorI_rReg_CL(dst, shift, cr); | |
| 9603 %} | |
| 9604 %} | |
| 9605 | |
| 9606 // Rotate Right by variable | |
| 9607 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr) | |
| 9608 %{ | |
| 9609 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); | |
| 9610 | |
| 9611 expand %{ | |
| 9612 rorI_rReg_CL(dst, shift, cr); | |
| 9613 %} | |
| 9614 %} | |
| 9615 | |
| 9616 // for long rotate | |
| 9617 // ROL expand | |
| 9618 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{ | |
| 9619 effect(USE_DEF dst, KILL cr); | |
| 9620 | |
| 9621 format %{ "rolq $dst" %} | |
| 9622 opcode(0xD1, 0x0); /* Opcode D1 /0 */ | |
| 9623 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9624 ins_pipe(ialu_reg); | |
| 9625 %} | |
| 9626 | |
| 9627 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{ | |
| 9628 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9629 | |
| 9630 format %{ "rolq $dst, $shift" %} | |
| 9631 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */ | |
| 9632 ins_encode( reg_opc_imm_wide(dst, shift) ); | |
| 9633 ins_pipe(ialu_reg); | |
| 9634 %} | |
| 9635 | |
| 9636 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9637 %{ | |
| 9638 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9639 | |
| 9640 format %{ "rolq $dst, $shift" %} | |
| 9641 opcode(0xD3, 0x0); /* Opcode D3 /0 */ | |
| 9642 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9643 ins_pipe(ialu_reg_reg); | |
| 9644 %} | |
| 9645 // end of ROL expand | |
| 9646 | |
| 9647 // Rotate Left by one | |
| 9648 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr) | |
| 9649 %{ | |
| 9650 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 9651 | |
| 9652 expand %{ | |
| 9653 rolL_rReg_imm1(dst, cr); | |
| 9654 %} | |
| 9655 %} | |
| 9656 | |
| 9657 // Rotate Left by 8-bit immediate | |
| 9658 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr) | |
| 9659 %{ | |
| 9660 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 9661 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift))); | |
| 9662 | |
| 9663 expand %{ | |
| 9664 rolL_rReg_imm8(dst, lshift, cr); | |
| 9665 %} | |
| 9666 %} | |
| 9667 | |
| 9668 // Rotate Left by variable | |
| 9669 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9670 %{ | |
| 9671 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift)))); | |
| 9672 | |
| 9673 expand %{ | |
| 9674 rolL_rReg_CL(dst, shift, cr); | |
| 9675 %} | |
| 9676 %} | |
| 9677 | |
| 9678 // Rotate Left by variable | |
| 9679 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 9680 %{ | |
| 9681 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift)))); | |
| 9682 | |
| 9683 expand %{ | |
| 9684 rolL_rReg_CL(dst, shift, cr); | |
| 9685 %} | |
| 9686 %} | |
| 9687 | |
| 9688 // ROR expand | |
| 9689 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr) | |
| 9690 %{ | |
| 9691 effect(USE_DEF dst, KILL cr); | |
| 9692 | |
| 9693 format %{ "rorq $dst" %} | |
| 9694 opcode(0xD1, 0x1); /* D1 /1 */ | |
| 9695 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9696 ins_pipe(ialu_reg); | |
| 9697 %} | |
| 9698 | |
| 9699 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) | |
| 9700 %{ | |
| 9701 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9702 | |
| 9703 format %{ "rorq $dst, $shift" %} | |
| 9704 opcode(0xC1, 0x1); /* C1 /1 ib */ | |
| 9705 ins_encode(reg_opc_imm_wide(dst, shift)); | |
| 9706 ins_pipe(ialu_reg); | |
| 9707 %} | |
| 9708 | |
| 9709 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr) | |
| 9710 %{ | |
| 9711 effect(USE_DEF dst, USE shift, KILL cr); | |
| 9712 | |
| 9713 format %{ "rorq $dst, $shift" %} | |
| 9714 opcode(0xD3, 0x1); /* D3 /1 */ | |
| 9715 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst)); | |
| 9716 ins_pipe(ialu_reg_reg); | |
| 9717 %} | |
| 9718 // end of ROR expand | |
| 9719 | |
| 9720 // Rotate Right by one | |
| 9721 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr) | |
| 9722 %{ | |
| 9723 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 9724 | |
| 9725 expand %{ | |
| 9726 rorL_rReg_imm1(dst, cr); | |
| 9727 %} | |
| 9728 %} | |
| 9729 | |
| 9730 // Rotate Right by 8-bit immediate | |
| 9731 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr) | |
| 9732 %{ | |
| 9733 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f)); | |
| 9734 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift))); | |
| 9735 | |
| 9736 expand %{ | |
| 9737 rorL_rReg_imm8(dst, rshift, cr); | |
| 9738 %} | |
| 9739 %} | |
| 9740 | |
| 9741 // Rotate Right by variable | |
| 9742 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr) | |
| 9743 %{ | |
| 9744 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift)))); | |
| 9745 | |
| 9746 expand %{ | |
| 9747 rorL_rReg_CL(dst, shift, cr); | |
| 9748 %} | |
| 9749 %} | |
| 9750 | |
| 9751 // Rotate Right by variable | |
| 9752 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr) | |
| 9753 %{ | |
| 9754 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift)))); | |
| 9755 | |
| 9756 expand %{ | |
| 9757 rorL_rReg_CL(dst, shift, cr); | |
| 9758 %} | |
| 9759 %} | |
| 9760 | |
| 9761 // Logical Instructions | |
| 9762 | |
| 9763 // Integer Logical Instructions | |
| 9764 | |
| 9765 // And Instructions | |
| 9766 // And Register with Register | |
| 9767 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9768 %{ | |
| 9769 match(Set dst (AndI dst src)); | |
| 9770 effect(KILL cr); | |
| 9771 | |
| 9772 format %{ "andl $dst, $src\t# int" %} | |
| 9773 opcode(0x23); | |
| 9774 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9775 ins_pipe(ialu_reg_reg); | |
| 9776 %} | |
| 9777 | |
| 9778 // And Register with Immediate 255 | |
| 9779 instruct andI_rReg_imm255(rRegI dst, immI_255 src) | |
| 9780 %{ | |
| 9781 match(Set dst (AndI dst src)); | |
| 9782 | |
| 9783 format %{ "movzbl $dst, $dst\t# int & 0xFF" %} | |
| 9784 opcode(0x0F, 0xB6); | |
| 9785 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9786 ins_pipe(ialu_reg); | |
| 9787 %} | |
| 9788 | |
| 9789 // And Register with Immediate 255 and promote to long | |
| 9790 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask) | |
| 9791 %{ | |
| 9792 match(Set dst (ConvI2L (AndI src mask))); | |
| 9793 | |
| 9794 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %} | |
| 9795 opcode(0x0F, 0xB6); | |
| 9796 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9797 ins_pipe(ialu_reg); | |
| 9798 %} | |
| 9799 | |
| 9800 // And Register with Immediate 65535 | |
| 9801 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src) | |
| 9802 %{ | |
| 9803 match(Set dst (AndI dst src)); | |
| 9804 | |
| 9805 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %} | |
| 9806 opcode(0x0F, 0xB7); | |
| 9807 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 9808 ins_pipe(ialu_reg); | |
| 9809 %} | |
| 9810 | |
| 9811 // And Register with Immediate 65535 and promote to long | |
| 9812 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask) | |
| 9813 %{ | |
| 9814 match(Set dst (ConvI2L (AndI src mask))); | |
| 9815 | |
| 9816 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %} | |
| 9817 opcode(0x0F, 0xB7); | |
| 9818 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 9819 ins_pipe(ialu_reg); | |
| 9820 %} | |
| 9821 | |
| 9822 // And Register with Immediate | |
| 9823 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9824 %{ | |
| 9825 match(Set dst (AndI dst src)); | |
| 9826 effect(KILL cr); | |
| 9827 | |
| 9828 format %{ "andl $dst, $src\t# int" %} | |
| 9829 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 9830 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9831 ins_pipe(ialu_reg); | |
| 9832 %} | |
| 9833 | |
| 9834 // And Register with Memory | |
| 9835 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9836 %{ | |
| 9837 match(Set dst (AndI dst (LoadI src))); | |
| 9838 effect(KILL cr); | |
| 9839 | |
| 9840 ins_cost(125); | |
| 9841 format %{ "andl $dst, $src\t# int" %} | |
| 9842 opcode(0x23); | |
| 9843 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9844 ins_pipe(ialu_reg_mem); | |
| 9845 %} | |
| 9846 | |
| 9847 // And Memory with Register | |
| 9848 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9849 %{ | |
| 9850 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9851 effect(KILL cr); | |
| 9852 | |
| 9853 ins_cost(150); | |
| 9854 format %{ "andl $dst, $src\t# int" %} | |
| 9855 opcode(0x21); /* Opcode 21 /r */ | |
| 9856 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9857 ins_pipe(ialu_mem_reg); | |
| 9858 %} | |
| 9859 | |
| 9860 // And Memory with Immediate | |
| 9861 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9862 %{ | |
| 9863 match(Set dst (StoreI dst (AndI (LoadI dst) src))); | |
| 9864 effect(KILL cr); | |
| 9865 | |
| 9866 ins_cost(125); | |
| 9867 format %{ "andl $dst, $src\t# int" %} | |
| 9868 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 9869 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9870 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9871 ins_pipe(ialu_mem_imm); | |
| 9872 %} | |
| 9873 | |
| 9874 // Or Instructions | |
| 9875 // Or Register with Register | |
| 9876 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9877 %{ | |
| 9878 match(Set dst (OrI dst src)); | |
| 9879 effect(KILL cr); | |
| 9880 | |
| 9881 format %{ "orl $dst, $src\t# int" %} | |
| 9882 opcode(0x0B); | |
| 9883 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9884 ins_pipe(ialu_reg_reg); | |
| 9885 %} | |
| 9886 | |
| 9887 // Or Register with Immediate | |
| 9888 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9889 %{ | |
| 9890 match(Set dst (OrI dst src)); | |
| 9891 effect(KILL cr); | |
| 9892 | |
| 9893 format %{ "orl $dst, $src\t# int" %} | |
| 9894 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 9895 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9896 ins_pipe(ialu_reg); | |
| 9897 %} | |
| 9898 | |
| 9899 // Or Register with Memory | |
| 9900 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9901 %{ | |
| 9902 match(Set dst (OrI dst (LoadI src))); | |
| 9903 effect(KILL cr); | |
| 9904 | |
| 9905 ins_cost(125); | |
| 9906 format %{ "orl $dst, $src\t# int" %} | |
| 9907 opcode(0x0B); | |
| 9908 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9909 ins_pipe(ialu_reg_mem); | |
| 9910 %} | |
| 9911 | |
| 9912 // Or Memory with Register | |
| 9913 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9914 %{ | |
| 9915 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9916 effect(KILL cr); | |
| 9917 | |
| 9918 ins_cost(150); | |
| 9919 format %{ "orl $dst, $src\t# int" %} | |
| 9920 opcode(0x09); /* Opcode 09 /r */ | |
| 9921 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9922 ins_pipe(ialu_mem_reg); | |
| 9923 %} | |
| 9924 | |
| 9925 // Or Memory with Immediate | |
| 9926 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 9927 %{ | |
| 9928 match(Set dst (StoreI dst (OrI (LoadI dst) src))); | |
| 9929 effect(KILL cr); | |
| 9930 | |
| 9931 ins_cost(125); | |
| 9932 format %{ "orl $dst, $src\t# int" %} | |
| 9933 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 9934 ins_encode(REX_mem(dst), OpcSE(src), | |
| 9935 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 9936 ins_pipe(ialu_mem_imm); | |
| 9937 %} | |
| 9938 | |
| 9939 // Xor Instructions | |
| 9940 // Xor Register with Register | |
| 9941 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr) | |
| 9942 %{ | |
| 9943 match(Set dst (XorI dst src)); | |
| 9944 effect(KILL cr); | |
| 9945 | |
| 9946 format %{ "xorl $dst, $src\t# int" %} | |
| 9947 opcode(0x33); | |
| 9948 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src)); | |
| 9949 ins_pipe(ialu_reg_reg); | |
| 9950 %} | |
| 9951 | |
| 403 | 9952 // Xor Register with Immediate -1 |
| 9953 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{ | |
| 9954 match(Set dst (XorI dst imm)); | |
| 9955 | |
| 9956 format %{ "not $dst" %} | |
| 9957 ins_encode %{ | |
| 9958 __ notl($dst$$Register); | |
| 9959 %} | |
| 9960 ins_pipe(ialu_reg); | |
| 9961 %} | |
| 9962 | |
| 0 | 9963 // Xor Register with Immediate |
| 9964 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr) | |
| 9965 %{ | |
| 9966 match(Set dst (XorI dst src)); | |
| 9967 effect(KILL cr); | |
| 9968 | |
| 9969 format %{ "xorl $dst, $src\t# int" %} | |
| 9970 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 9971 ins_encode(OpcSErm(dst, src), Con8or32(src)); | |
| 9972 ins_pipe(ialu_reg); | |
| 9973 %} | |
| 9974 | |
| 9975 // Xor Register with Memory | |
| 9976 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr) | |
| 9977 %{ | |
| 9978 match(Set dst (XorI dst (LoadI src))); | |
| 9979 effect(KILL cr); | |
| 9980 | |
| 9981 ins_cost(125); | |
| 9982 format %{ "xorl $dst, $src\t# int" %} | |
| 9983 opcode(0x33); | |
| 9984 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 9985 ins_pipe(ialu_reg_mem); | |
| 9986 %} | |
| 9987 | |
| 9988 // Xor Memory with Register | |
| 9989 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr) | |
| 9990 %{ | |
| 9991 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 9992 effect(KILL cr); | |
| 9993 | |
| 9994 ins_cost(150); | |
| 9995 format %{ "xorl $dst, $src\t# int" %} | |
| 9996 opcode(0x31); /* Opcode 31 /r */ | |
| 9997 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 9998 ins_pipe(ialu_mem_reg); | |
| 9999 %} | |
| 10000 | |
| 10001 // Xor Memory with Immediate | |
| 10002 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr) | |
| 10003 %{ | |
| 10004 match(Set dst (StoreI dst (XorI (LoadI dst) src))); | |
| 10005 effect(KILL cr); | |
| 10006 | |
| 10007 ins_cost(125); | |
| 10008 format %{ "xorl $dst, $src\t# int" %} | |
| 10009 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 10010 ins_encode(REX_mem(dst), OpcSE(src), | |
| 10011 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 10012 ins_pipe(ialu_mem_imm); | |
| 10013 %} | |
| 10014 | |
| 10015 | |
| 10016 // Long Logical Instructions | |
| 10017 | |
| 10018 // And Instructions | |
| 10019 // And Register with Register | |
| 10020 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 10021 %{ | |
| 10022 match(Set dst (AndL dst src)); | |
| 10023 effect(KILL cr); | |
| 10024 | |
| 10025 format %{ "andq $dst, $src\t# long" %} | |
| 10026 opcode(0x23); | |
| 10027 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 10028 ins_pipe(ialu_reg_reg); | |
| 10029 %} | |
| 10030 | |
| 10031 // And Register with Immediate 255 | |
| 10032 instruct andL_rReg_imm255(rRegL dst, immL_255 src) | |
| 10033 %{ | |
| 10034 match(Set dst (AndL dst src)); | |
| 10035 | |
|
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10036 format %{ "movzbq $dst, $dst\t# long & 0xFF" %} |
| 0 | 10037 opcode(0x0F, 0xB6); |
| 10038 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 10039 ins_pipe(ialu_reg); | |
| 10040 %} | |
| 10041 | |
| 10042 // And Register with Immediate 65535 | |
|
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10043 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src) |
| 0 | 10044 %{ |
| 10045 match(Set dst (AndL dst src)); | |
| 10046 | |
| 10047 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %} | |
| 10048 opcode(0x0F, 0xB7); | |
| 10049 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst)); | |
| 10050 ins_pipe(ialu_reg); | |
| 10051 %} | |
| 10052 | |
| 10053 // And Register with Immediate | |
| 10054 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 10055 %{ | |
| 10056 match(Set dst (AndL dst src)); | |
| 10057 effect(KILL cr); | |
| 10058 | |
| 10059 format %{ "andq $dst, $src\t# long" %} | |
| 10060 opcode(0x81, 0x04); /* Opcode 81 /4 */ | |
| 10061 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 10062 ins_pipe(ialu_reg); | |
| 10063 %} | |
| 10064 | |
| 10065 // And Register with Memory | |
| 10066 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 10067 %{ | |
| 10068 match(Set dst (AndL dst (LoadL src))); | |
| 10069 effect(KILL cr); | |
| 10070 | |
| 10071 ins_cost(125); | |
| 10072 format %{ "andq $dst, $src\t# long" %} | |
| 10073 opcode(0x23); | |
| 10074 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 10075 ins_pipe(ialu_reg_mem); | |
| 10076 %} | |
| 10077 | |
| 10078 // And Memory with Register | |
| 10079 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 10080 %{ | |
| 10081 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 10082 effect(KILL cr); | |
| 10083 | |
| 10084 ins_cost(150); | |
| 10085 format %{ "andq $dst, $src\t# long" %} | |
| 10086 opcode(0x21); /* Opcode 21 /r */ | |
| 10087 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 10088 ins_pipe(ialu_mem_reg); | |
| 10089 %} | |
| 10090 | |
| 10091 // And Memory with Immediate | |
| 10092 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 10093 %{ | |
| 10094 match(Set dst (StoreL dst (AndL (LoadL dst) src))); | |
| 10095 effect(KILL cr); | |
| 10096 | |
| 10097 ins_cost(125); | |
| 10098 format %{ "andq $dst, $src\t# long" %} | |
| 10099 opcode(0x81, 0x4); /* Opcode 81 /4 id */ | |
| 10100 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 10101 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 10102 ins_pipe(ialu_mem_imm); | |
| 10103 %} | |
| 10104 | |
| 10105 // Or Instructions | |
| 10106 // Or Register with Register | |
| 10107 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 10108 %{ | |
| 10109 match(Set dst (OrL dst src)); | |
| 10110 effect(KILL cr); | |
| 10111 | |
| 10112 format %{ "orq $dst, $src\t# long" %} | |
| 10113 opcode(0x0B); | |
| 10114 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 10115 ins_pipe(ialu_reg_reg); | |
| 10116 %} | |
| 10117 | |
|
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10118 // Use any_RegP to match R15 (TLS register) without spilling. |
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10119 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{ |
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10120 match(Set dst (OrL dst (CastP2X src))); |
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10121 effect(KILL cr); |
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10122 |
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10123 format %{ "orq $dst, $src\t# long" %} |
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10124 opcode(0x0B); |
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10125 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); |
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10126 ins_pipe(ialu_reg_reg); |
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10127 %} |
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10128 |
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10129 |
| 0 | 10130 // Or Register with Immediate |
| 10131 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 10132 %{ | |
| 10133 match(Set dst (OrL dst src)); | |
| 10134 effect(KILL cr); | |
| 10135 | |
| 10136 format %{ "orq $dst, $src\t# long" %} | |
| 10137 opcode(0x81, 0x01); /* Opcode 81 /1 id */ | |
| 10138 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 10139 ins_pipe(ialu_reg); | |
| 10140 %} | |
| 10141 | |
| 10142 // Or Register with Memory | |
| 10143 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 10144 %{ | |
| 10145 match(Set dst (OrL dst (LoadL src))); | |
| 10146 effect(KILL cr); | |
| 10147 | |
| 10148 ins_cost(125); | |
| 10149 format %{ "orq $dst, $src\t# long" %} | |
| 10150 opcode(0x0B); | |
| 10151 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 10152 ins_pipe(ialu_reg_mem); | |
| 10153 %} | |
| 10154 | |
| 10155 // Or Memory with Register | |
| 10156 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 10157 %{ | |
| 10158 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 10159 effect(KILL cr); | |
| 10160 | |
| 10161 ins_cost(150); | |
| 10162 format %{ "orq $dst, $src\t# long" %} | |
| 10163 opcode(0x09); /* Opcode 09 /r */ | |
| 10164 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 10165 ins_pipe(ialu_mem_reg); | |
| 10166 %} | |
| 10167 | |
| 10168 // Or Memory with Immediate | |
| 10169 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 10170 %{ | |
| 10171 match(Set dst (StoreL dst (OrL (LoadL dst) src))); | |
| 10172 effect(KILL cr); | |
| 10173 | |
| 10174 ins_cost(125); | |
| 10175 format %{ "orq $dst, $src\t# long" %} | |
| 10176 opcode(0x81, 0x1); /* Opcode 81 /1 id */ | |
| 10177 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 10178 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 10179 ins_pipe(ialu_mem_imm); | |
| 10180 %} | |
| 10181 | |
| 10182 // Xor Instructions | |
| 10183 // Xor Register with Register | |
| 10184 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr) | |
| 10185 %{ | |
| 10186 match(Set dst (XorL dst src)); | |
| 10187 effect(KILL cr); | |
| 10188 | |
| 10189 format %{ "xorq $dst, $src\t# long" %} | |
| 10190 opcode(0x33); | |
| 10191 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src)); | |
| 10192 ins_pipe(ialu_reg_reg); | |
| 10193 %} | |
| 10194 | |
| 403 | 10195 // Xor Register with Immediate -1 |
| 10196 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{ | |
| 10197 match(Set dst (XorL dst imm)); | |
| 10198 | |
| 10199 format %{ "notq $dst" %} | |
| 10200 ins_encode %{ | |
| 10201 __ notq($dst$$Register); | |
| 10202 %} | |
| 10203 ins_pipe(ialu_reg); | |
| 10204 %} | |
| 10205 | |
| 0 | 10206 // Xor Register with Immediate |
| 10207 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr) | |
| 10208 %{ | |
| 10209 match(Set dst (XorL dst src)); | |
| 10210 effect(KILL cr); | |
| 10211 | |
| 10212 format %{ "xorq $dst, $src\t# long" %} | |
| 10213 opcode(0x81, 0x06); /* Opcode 81 /6 id */ | |
| 10214 ins_encode(OpcSErm_wide(dst, src), Con8or32(src)); | |
| 10215 ins_pipe(ialu_reg); | |
| 10216 %} | |
| 10217 | |
| 10218 // Xor Register with Memory | |
| 10219 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr) | |
| 10220 %{ | |
| 10221 match(Set dst (XorL dst (LoadL src))); | |
| 10222 effect(KILL cr); | |
| 10223 | |
| 10224 ins_cost(125); | |
| 10225 format %{ "xorq $dst, $src\t# long" %} | |
| 10226 opcode(0x33); | |
| 10227 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 10228 ins_pipe(ialu_reg_mem); | |
| 10229 %} | |
| 10230 | |
| 10231 // Xor Memory with Register | |
| 10232 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr) | |
| 10233 %{ | |
| 10234 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 10235 effect(KILL cr); | |
| 10236 | |
| 10237 ins_cost(150); | |
| 10238 format %{ "xorq $dst, $src\t# long" %} | |
| 10239 opcode(0x31); /* Opcode 31 /r */ | |
| 10240 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 10241 ins_pipe(ialu_mem_reg); | |
| 10242 %} | |
| 10243 | |
| 10244 // Xor Memory with Immediate | |
| 10245 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr) | |
| 10246 %{ | |
| 10247 match(Set dst (StoreL dst (XorL (LoadL dst) src))); | |
| 10248 effect(KILL cr); | |
| 10249 | |
| 10250 ins_cost(125); | |
| 10251 format %{ "xorq $dst, $src\t# long" %} | |
| 10252 opcode(0x81, 0x6); /* Opcode 81 /6 id */ | |
| 10253 ins_encode(REX_mem_wide(dst), OpcSE(src), | |
| 10254 RM_opc_mem(secondary, dst), Con8or32(src)); | |
| 10255 ins_pipe(ialu_mem_imm); | |
| 10256 %} | |
| 10257 | |
| 10258 // Convert Int to Boolean | |
| 10259 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr) | |
| 10260 %{ | |
| 10261 match(Set dst (Conv2B src)); | |
| 10262 effect(KILL cr); | |
| 10263 | |
| 10264 format %{ "testl $src, $src\t# ci2b\n\t" | |
| 10265 "setnz $dst\n\t" | |
| 10266 "movzbl $dst, $dst" %} | |
| 10267 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl | |
| 10268 setNZ_reg(dst), | |
| 10269 REX_reg_breg(dst, dst), // movzbl | |
| 10270 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 10271 ins_pipe(pipe_slow); // XXX | |
| 10272 %} | |
| 10273 | |
| 10274 // Convert Pointer to Boolean | |
| 10275 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr) | |
| 10276 %{ | |
| 10277 match(Set dst (Conv2B src)); | |
| 10278 effect(KILL cr); | |
| 10279 | |
| 10280 format %{ "testq $src, $src\t# cp2b\n\t" | |
| 10281 "setnz $dst\n\t" | |
| 10282 "movzbl $dst, $dst" %} | |
| 10283 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq | |
| 10284 setNZ_reg(dst), | |
| 10285 REX_reg_breg(dst, dst), // movzbl | |
| 10286 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst)); | |
| 10287 ins_pipe(pipe_slow); // XXX | |
| 10288 %} | |
| 10289 | |
| 10290 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr) | |
| 10291 %{ | |
| 10292 match(Set dst (CmpLTMask p q)); | |
| 10293 effect(KILL cr); | |
| 10294 | |
| 10295 ins_cost(400); // XXX | |
| 10296 format %{ "cmpl $p, $q\t# cmpLTMask\n\t" | |
| 10297 "setlt $dst\n\t" | |
| 10298 "movzbl $dst, $dst\n\t" | |
| 10299 "negl $dst" %} | |
| 10300 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl | |
| 10301 setLT_reg(dst), | |
| 10302 REX_reg_breg(dst, dst), // movzbl | |
| 10303 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst), | |
| 10304 neg_reg(dst)); | |
| 10305 ins_pipe(pipe_slow); | |
| 10306 %} | |
| 10307 | |
| 10308 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr) | |
| 10309 %{ | |
| 10310 match(Set dst (CmpLTMask dst zero)); | |
| 10311 effect(KILL cr); | |
| 10312 | |
| 10313 ins_cost(100); // XXX | |
| 10314 format %{ "sarl $dst, #31\t# cmpLTMask0" %} | |
| 10315 opcode(0xC1, 0x7); /* C1 /7 ib */ | |
| 10316 ins_encode(reg_opc_imm(dst, 0x1F)); | |
| 10317 ins_pipe(ialu_reg); | |
| 10318 %} | |
| 10319 | |
| 10320 | |
| 10321 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, | |
| 10322 rRegI tmp, | |
| 10323 rFlagsReg cr) | |
| 10324 %{ | |
| 10325 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); | |
| 10326 effect(TEMP tmp, KILL cr); | |
| 10327 | |
| 10328 ins_cost(400); // XXX | |
| 10329 format %{ "subl $p, $q\t# cadd_cmpLTMask1\n\t" | |
| 10330 "sbbl $tmp, $tmp\n\t" | |
| 10331 "andl $tmp, $y\n\t" | |
| 10332 "addl $p, $tmp" %} | |
| 10333 ins_encode(enc_cmpLTP(p, q, y, tmp)); | |
| 10334 ins_pipe(pipe_cmplt); | |
| 10335 %} | |
| 10336 | |
| 10337 /* If I enable this, I encourage spilling in the inner loop of compress. | |
| 10338 instruct cadd_cmpLTMask_mem( rRegI p, rRegI q, memory y, rRegI tmp, rFlagsReg cr ) | |
| 10339 %{ | |
| 10340 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); | |
| 10341 effect( TEMP tmp, KILL cr ); | |
| 10342 ins_cost(400); | |
| 10343 | |
| 10344 format %{ "SUB $p,$q\n\t" | |
| 10345 "SBB RCX,RCX\n\t" | |
| 10346 "AND RCX,$y\n\t" | |
| 10347 "ADD $p,RCX" %} | |
| 10348 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); | |
| 10349 %} | |
| 10350 */ | |
| 10351 | |
| 10352 //---------- FP Instructions------------------------------------------------ | |
| 10353 | |
| 10354 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2) | |
| 10355 %{ | |
| 10356 match(Set cr (CmpF src1 src2)); | |
| 10357 | |
| 10358 ins_cost(145); | |
| 10359 format %{ "ucomiss $src1, $src2\n\t" | |
| 10360 "jnp,s exit\n\t" | |
| 10361 "pushfq\t# saw NaN, set CF\n\t" | |
| 10362 "andq [rsp], #0xffffff2b\n\t" | |
| 10363 "popfq\n" | |
| 10364 "exit: nop\t# avoid branch to branch" %} | |
| 10365 opcode(0x0F, 0x2E); | |
| 10366 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2), | |
| 10367 cmpfp_fixup); | |
| 10368 ins_pipe(pipe_slow); | |
| 10369 %} | |
| 10370 | |
|
415
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|
10371 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{ |
|
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|
10372 match(Set cr (CmpF src1 src2)); |
|
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|
10373 |
|
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|
10374 ins_cost(145); |
|
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|
10375 format %{ "ucomiss $src1, $src2" %} |
|
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|
10376 ins_encode %{ |
|
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|
10377 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); |
|
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|
10378 %} |
|
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|
10379 ins_pipe(pipe_slow); |
|
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|
10380 %} |
|
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|
10381 |
| 0 | 10382 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2) |
| 10383 %{ | |
| 10384 match(Set cr (CmpF src1 (LoadF src2))); | |
| 10385 | |
| 10386 ins_cost(145); | |
| 10387 format %{ "ucomiss $src1, $src2\n\t" | |
| 10388 "jnp,s exit\n\t" | |
| 10389 "pushfq\t# saw NaN, set CF\n\t" | |
| 10390 "andq [rsp], #0xffffff2b\n\t" | |
| 10391 "popfq\n" | |
| 10392 "exit: nop\t# avoid branch to branch" %} | |
| 10393 opcode(0x0F, 0x2E); | |
| 10394 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2), | |
| 10395 cmpfp_fixup); | |
| 10396 ins_pipe(pipe_slow); | |
| 10397 %} | |
| 10398 | |
|
415
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|
10399 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{ |
|
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|
10400 match(Set cr (CmpF src1 (LoadF src2))); |
|
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|
10401 |
|
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|
10402 ins_cost(100); |
|
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|
10403 format %{ "ucomiss $src1, $src2" %} |
|
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|
10404 opcode(0x0F, 0x2E); |
|
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|
10405 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2)); |
|
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|
10406 ins_pipe(pipe_slow); |
|
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diff
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|
10407 %} |
|
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|
10408 |
| 0 | 10409 instruct cmpF_cc_imm(rFlagsRegU cr, regF src1, immF src2) |
| 10410 %{ | |
| 10411 match(Set cr (CmpF src1 src2)); | |
| 10412 | |
| 10413 ins_cost(145); | |
| 10414 format %{ "ucomiss $src1, $src2\n\t" | |
| 10415 "jnp,s exit\n\t" | |
| 10416 "pushfq\t# saw NaN, set CF\n\t" | |
| 10417 "andq [rsp], #0xffffff2b\n\t" | |
| 10418 "popfq\n" | |
| 10419 "exit: nop\t# avoid branch to branch" %} | |
| 10420 opcode(0x0F, 0x2E); | |
| 10421 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2), | |
| 10422 cmpfp_fixup); | |
| 10423 ins_pipe(pipe_slow); | |
| 10424 %} | |
| 10425 | |
|
415
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|
10426 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src1, immF src2) %{ |
|
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|
10427 match(Set cr (CmpF src1 src2)); |
|
4d9884b01ba6
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diff
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|
10428 |
|
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|
10429 ins_cost(100); |
|
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|
10430 format %{ "ucomiss $src1, $src2" %} |
|
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|
10431 opcode(0x0F, 0x2E); |
|
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|
10432 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2)); |
|
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|
10433 ins_pipe(pipe_slow); |
|
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|
10434 %} |
|
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|
10435 |
| 0 | 10436 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2) |
| 10437 %{ | |
| 10438 match(Set cr (CmpD src1 src2)); | |
| 10439 | |
| 10440 ins_cost(145); | |
| 10441 format %{ "ucomisd $src1, $src2\n\t" | |
| 10442 "jnp,s exit\n\t" | |
| 10443 "pushfq\t# saw NaN, set CF\n\t" | |
| 10444 "andq [rsp], #0xffffff2b\n\t" | |
| 10445 "popfq\n" | |
| 10446 "exit: nop\t# avoid branch to branch" %} | |
| 10447 opcode(0x66, 0x0F, 0x2E); | |
| 10448 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2), | |
| 10449 cmpfp_fixup); | |
| 10450 ins_pipe(pipe_slow); | |
| 10451 %} | |
| 10452 | |
|
415
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|
10453 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{ |
|
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|
10454 match(Set cr (CmpD src1 src2)); |
|
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diff
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|
10455 |
|
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diff
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|
10456 ins_cost(100); |
|
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diff
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|
10457 format %{ "ucomisd $src1, $src2 test" %} |
|
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|
10458 ins_encode %{ |
|
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|
10459 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); |
|
4d9884b01ba6
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diff
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|
10460 %} |
|
4d9884b01ba6
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diff
changeset
|
10461 ins_pipe(pipe_slow); |
|
4d9884b01ba6
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diff
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|
10462 %} |
|
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|
10463 |
| 0 | 10464 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2) |
| 10465 %{ | |
| 10466 match(Set cr (CmpD src1 (LoadD src2))); | |
| 10467 | |
| 10468 ins_cost(145); | |
| 10469 format %{ "ucomisd $src1, $src2\n\t" | |
| 10470 "jnp,s exit\n\t" | |
| 10471 "pushfq\t# saw NaN, set CF\n\t" | |
| 10472 "andq [rsp], #0xffffff2b\n\t" | |
| 10473 "popfq\n" | |
| 10474 "exit: nop\t# avoid branch to branch" %} | |
| 10475 opcode(0x66, 0x0F, 0x2E); | |
| 10476 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2), | |
| 10477 cmpfp_fixup); | |
| 10478 ins_pipe(pipe_slow); | |
| 10479 %} | |
| 10480 | |
|
415
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|
10481 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{ |
|
4d9884b01ba6
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diff
changeset
|
10482 match(Set cr (CmpD src1 (LoadD src2))); |
|
4d9884b01ba6
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|
10483 |
|
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|
10484 ins_cost(100); |
|
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|
10485 format %{ "ucomisd $src1, $src2" %} |
|
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|
10486 opcode(0x66, 0x0F, 0x2E); |
|
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|
10487 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2)); |
|
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|
10488 ins_pipe(pipe_slow); |
|
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|
10489 %} |
|
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diff
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|
10490 |
| 0 | 10491 instruct cmpD_cc_imm(rFlagsRegU cr, regD src1, immD src2) |
| 10492 %{ | |
| 10493 match(Set cr (CmpD src1 src2)); | |
| 10494 | |
| 10495 ins_cost(145); | |
| 10496 format %{ "ucomisd $src1, [$src2]\n\t" | |
| 10497 "jnp,s exit\n\t" | |
| 10498 "pushfq\t# saw NaN, set CF\n\t" | |
| 10499 "andq [rsp], #0xffffff2b\n\t" | |
| 10500 "popfq\n" | |
| 10501 "exit: nop\t# avoid branch to branch" %} | |
| 10502 opcode(0x66, 0x0F, 0x2E); | |
| 10503 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2), | |
| 10504 cmpfp_fixup); | |
| 10505 ins_pipe(pipe_slow); | |
| 10506 %} | |
| 10507 | |
|
415
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|
10508 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src1, immD src2) %{ |
|
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|
10509 match(Set cr (CmpD src1 src2)); |
|
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diff
changeset
|
10510 |
|
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6754519: don't emit flag fixup for NaN when condition being tested doesn't need it
never
parents:
403
diff
changeset
|
10511 ins_cost(100); |
|
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parents:
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diff
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|
10512 format %{ "ucomisd $src1, [$src2]" %} |
|
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diff
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|
10513 opcode(0x66, 0x0F, 0x2E); |
|
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|
10514 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2)); |
|
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|
10515 ins_pipe(pipe_slow); |
|
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diff
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|
10516 %} |
|
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|
10517 |
| 0 | 10518 // Compare into -1,0,1 |
| 10519 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr) | |
| 10520 %{ | |
| 10521 match(Set dst (CmpF3 src1 src2)); | |
| 10522 effect(KILL cr); | |
| 10523 | |
| 10524 ins_cost(275); | |
| 10525 format %{ "ucomiss $src1, $src2\n\t" | |
| 10526 "movl $dst, #-1\n\t" | |
| 10527 "jp,s done\n\t" | |
| 10528 "jb,s done\n\t" | |
| 10529 "setne $dst\n\t" | |
| 10530 "movzbl $dst, $dst\n" | |
| 10531 "done:" %} | |
| 10532 | |
| 10533 opcode(0x0F, 0x2E); | |
| 10534 ins_encode(REX_reg_reg(src1, src2), OpcP, OpcS, reg_reg(src1, src2), | |
| 10535 cmpfp3(dst)); | |
| 10536 ins_pipe(pipe_slow); | |
| 10537 %} | |
| 10538 | |
| 10539 // Compare into -1,0,1 | |
| 10540 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr) | |
| 10541 %{ | |
| 10542 match(Set dst (CmpF3 src1 (LoadF src2))); | |
| 10543 effect(KILL cr); | |
| 10544 | |
| 10545 ins_cost(275); | |
| 10546 format %{ "ucomiss $src1, $src2\n\t" | |
| 10547 "movl $dst, #-1\n\t" | |
| 10548 "jp,s done\n\t" | |
| 10549 "jb,s done\n\t" | |
| 10550 "setne $dst\n\t" | |
| 10551 "movzbl $dst, $dst\n" | |
| 10552 "done:" %} | |
| 10553 | |
| 10554 opcode(0x0F, 0x2E); | |
| 10555 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, reg_mem(src1, src2), | |
| 10556 cmpfp3(dst)); | |
| 10557 ins_pipe(pipe_slow); | |
| 10558 %} | |
| 10559 | |
| 10560 // Compare into -1,0,1 | |
| 10561 instruct cmpF_imm(rRegI dst, regF src1, immF src2, rFlagsReg cr) | |
| 10562 %{ | |
| 10563 match(Set dst (CmpF3 src1 src2)); | |
| 10564 effect(KILL cr); | |
| 10565 | |
| 10566 ins_cost(275); | |
| 10567 format %{ "ucomiss $src1, [$src2]\n\t" | |
| 10568 "movl $dst, #-1\n\t" | |
| 10569 "jp,s done\n\t" | |
| 10570 "jb,s done\n\t" | |
| 10571 "setne $dst\n\t" | |
| 10572 "movzbl $dst, $dst\n" | |
| 10573 "done:" %} | |
| 10574 | |
| 10575 opcode(0x0F, 0x2E); | |
| 10576 ins_encode(REX_reg_mem(src1, src2), OpcP, OpcS, load_immF(src1, src2), | |
| 10577 cmpfp3(dst)); | |
| 10578 ins_pipe(pipe_slow); | |
| 10579 %} | |
| 10580 | |
| 10581 // Compare into -1,0,1 | |
| 10582 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr) | |
| 10583 %{ | |
| 10584 match(Set dst (CmpD3 src1 src2)); | |
| 10585 effect(KILL cr); | |
| 10586 | |
| 10587 ins_cost(275); | |
| 10588 format %{ "ucomisd $src1, $src2\n\t" | |
| 10589 "movl $dst, #-1\n\t" | |
| 10590 "jp,s done\n\t" | |
| 10591 "jb,s done\n\t" | |
| 10592 "setne $dst\n\t" | |
| 10593 "movzbl $dst, $dst\n" | |
| 10594 "done:" %} | |
| 10595 | |
| 10596 opcode(0x66, 0x0F, 0x2E); | |
| 10597 ins_encode(OpcP, REX_reg_reg(src1, src2), OpcS, OpcT, reg_reg(src1, src2), | |
| 10598 cmpfp3(dst)); | |
| 10599 ins_pipe(pipe_slow); | |
| 10600 %} | |
| 10601 | |
| 10602 // Compare into -1,0,1 | |
| 10603 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr) | |
| 10604 %{ | |
| 10605 match(Set dst (CmpD3 src1 (LoadD src2))); | |
| 10606 effect(KILL cr); | |
| 10607 | |
| 10608 ins_cost(275); | |
| 10609 format %{ "ucomisd $src1, $src2\n\t" | |
| 10610 "movl $dst, #-1\n\t" | |
| 10611 "jp,s done\n\t" | |
| 10612 "jb,s done\n\t" | |
| 10613 "setne $dst\n\t" | |
| 10614 "movzbl $dst, $dst\n" | |
| 10615 "done:" %} | |
| 10616 | |
| 10617 opcode(0x66, 0x0F, 0x2E); | |
| 10618 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, reg_mem(src1, src2), | |
| 10619 cmpfp3(dst)); | |
| 10620 ins_pipe(pipe_slow); | |
| 10621 %} | |
| 10622 | |
| 10623 // Compare into -1,0,1 | |
| 10624 instruct cmpD_imm(rRegI dst, regD src1, immD src2, rFlagsReg cr) | |
| 10625 %{ | |
| 10626 match(Set dst (CmpD3 src1 src2)); | |
| 10627 effect(KILL cr); | |
| 10628 | |
| 10629 ins_cost(275); | |
| 10630 format %{ "ucomisd $src1, [$src2]\n\t" | |
| 10631 "movl $dst, #-1\n\t" | |
| 10632 "jp,s done\n\t" | |
| 10633 "jb,s done\n\t" | |
| 10634 "setne $dst\n\t" | |
| 10635 "movzbl $dst, $dst\n" | |
| 10636 "done:" %} | |
| 10637 | |
| 10638 opcode(0x66, 0x0F, 0x2E); | |
| 10639 ins_encode(OpcP, REX_reg_mem(src1, src2), OpcS, OpcT, load_immD(src1, src2), | |
| 10640 cmpfp3(dst)); | |
| 10641 ins_pipe(pipe_slow); | |
| 10642 %} | |
| 10643 | |
| 10644 instruct addF_reg(regF dst, regF src) | |
| 10645 %{ | |
| 10646 match(Set dst (AddF dst src)); | |
| 10647 | |
| 10648 format %{ "addss $dst, $src" %} | |
| 10649 ins_cost(150); // XXX | |
| 10650 opcode(0xF3, 0x0F, 0x58); | |
| 10651 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10652 ins_pipe(pipe_slow); | |
| 10653 %} | |
| 10654 | |
| 10655 instruct addF_mem(regF dst, memory src) | |
| 10656 %{ | |
| 10657 match(Set dst (AddF dst (LoadF src))); | |
| 10658 | |
| 10659 format %{ "addss $dst, $src" %} | |
| 10660 ins_cost(150); // XXX | |
| 10661 opcode(0xF3, 0x0F, 0x58); | |
| 10662 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10663 ins_pipe(pipe_slow); | |
| 10664 %} | |
| 10665 | |
| 10666 instruct addF_imm(regF dst, immF src) | |
| 10667 %{ | |
| 10668 match(Set dst (AddF dst src)); | |
| 10669 | |
| 10670 format %{ "addss $dst, [$src]" %} | |
| 10671 ins_cost(150); // XXX | |
| 10672 opcode(0xF3, 0x0F, 0x58); | |
| 10673 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10674 ins_pipe(pipe_slow); | |
| 10675 %} | |
| 10676 | |
| 10677 instruct addD_reg(regD dst, regD src) | |
| 10678 %{ | |
| 10679 match(Set dst (AddD dst src)); | |
| 10680 | |
| 10681 format %{ "addsd $dst, $src" %} | |
| 10682 ins_cost(150); // XXX | |
| 10683 opcode(0xF2, 0x0F, 0x58); | |
| 10684 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10685 ins_pipe(pipe_slow); | |
| 10686 %} | |
| 10687 | |
| 10688 instruct addD_mem(regD dst, memory src) | |
| 10689 %{ | |
| 10690 match(Set dst (AddD dst (LoadD src))); | |
| 10691 | |
| 10692 format %{ "addsd $dst, $src" %} | |
| 10693 ins_cost(150); // XXX | |
| 10694 opcode(0xF2, 0x0F, 0x58); | |
| 10695 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10696 ins_pipe(pipe_slow); | |
| 10697 %} | |
| 10698 | |
| 10699 instruct addD_imm(regD dst, immD src) | |
| 10700 %{ | |
| 10701 match(Set dst (AddD dst src)); | |
| 10702 | |
| 10703 format %{ "addsd $dst, [$src]" %} | |
| 10704 ins_cost(150); // XXX | |
| 10705 opcode(0xF2, 0x0F, 0x58); | |
| 10706 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10707 ins_pipe(pipe_slow); | |
| 10708 %} | |
| 10709 | |
| 10710 instruct subF_reg(regF dst, regF src) | |
| 10711 %{ | |
| 10712 match(Set dst (SubF dst src)); | |
| 10713 | |
| 10714 format %{ "subss $dst, $src" %} | |
| 10715 ins_cost(150); // XXX | |
| 10716 opcode(0xF3, 0x0F, 0x5C); | |
| 10717 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10718 ins_pipe(pipe_slow); | |
| 10719 %} | |
| 10720 | |
| 10721 instruct subF_mem(regF dst, memory src) | |
| 10722 %{ | |
| 10723 match(Set dst (SubF dst (LoadF src))); | |
| 10724 | |
| 10725 format %{ "subss $dst, $src" %} | |
| 10726 ins_cost(150); // XXX | |
| 10727 opcode(0xF3, 0x0F, 0x5C); | |
| 10728 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10729 ins_pipe(pipe_slow); | |
| 10730 %} | |
| 10731 | |
| 10732 instruct subF_imm(regF dst, immF src) | |
| 10733 %{ | |
| 10734 match(Set dst (SubF dst src)); | |
| 10735 | |
| 10736 format %{ "subss $dst, [$src]" %} | |
| 10737 ins_cost(150); // XXX | |
| 10738 opcode(0xF3, 0x0F, 0x5C); | |
| 10739 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10740 ins_pipe(pipe_slow); | |
| 10741 %} | |
| 10742 | |
| 10743 instruct subD_reg(regD dst, regD src) | |
| 10744 %{ | |
| 10745 match(Set dst (SubD dst src)); | |
| 10746 | |
| 10747 format %{ "subsd $dst, $src" %} | |
| 10748 ins_cost(150); // XXX | |
| 10749 opcode(0xF2, 0x0F, 0x5C); | |
| 10750 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10751 ins_pipe(pipe_slow); | |
| 10752 %} | |
| 10753 | |
| 10754 instruct subD_mem(regD dst, memory src) | |
| 10755 %{ | |
| 10756 match(Set dst (SubD dst (LoadD src))); | |
| 10757 | |
| 10758 format %{ "subsd $dst, $src" %} | |
| 10759 ins_cost(150); // XXX | |
| 10760 opcode(0xF2, 0x0F, 0x5C); | |
| 10761 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10762 ins_pipe(pipe_slow); | |
| 10763 %} | |
| 10764 | |
| 10765 instruct subD_imm(regD dst, immD src) | |
| 10766 %{ | |
| 10767 match(Set dst (SubD dst src)); | |
| 10768 | |
| 10769 format %{ "subsd $dst, [$src]" %} | |
| 10770 ins_cost(150); // XXX | |
| 10771 opcode(0xF2, 0x0F, 0x5C); | |
| 10772 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10773 ins_pipe(pipe_slow); | |
| 10774 %} | |
| 10775 | |
| 10776 instruct mulF_reg(regF dst, regF src) | |
| 10777 %{ | |
| 10778 match(Set dst (MulF dst src)); | |
| 10779 | |
| 10780 format %{ "mulss $dst, $src" %} | |
| 10781 ins_cost(150); // XXX | |
| 10782 opcode(0xF3, 0x0F, 0x59); | |
| 10783 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10784 ins_pipe(pipe_slow); | |
| 10785 %} | |
| 10786 | |
| 10787 instruct mulF_mem(regF dst, memory src) | |
| 10788 %{ | |
| 10789 match(Set dst (MulF dst (LoadF src))); | |
| 10790 | |
| 10791 format %{ "mulss $dst, $src" %} | |
| 10792 ins_cost(150); // XXX | |
| 10793 opcode(0xF3, 0x0F, 0x59); | |
| 10794 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10795 ins_pipe(pipe_slow); | |
| 10796 %} | |
| 10797 | |
| 10798 instruct mulF_imm(regF dst, immF src) | |
| 10799 %{ | |
| 10800 match(Set dst (MulF dst src)); | |
| 10801 | |
| 10802 format %{ "mulss $dst, [$src]" %} | |
| 10803 ins_cost(150); // XXX | |
| 10804 opcode(0xF3, 0x0F, 0x59); | |
| 10805 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10806 ins_pipe(pipe_slow); | |
| 10807 %} | |
| 10808 | |
| 10809 instruct mulD_reg(regD dst, regD src) | |
| 10810 %{ | |
| 10811 match(Set dst (MulD dst src)); | |
| 10812 | |
| 10813 format %{ "mulsd $dst, $src" %} | |
| 10814 ins_cost(150); // XXX | |
| 10815 opcode(0xF2, 0x0F, 0x59); | |
| 10816 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10817 ins_pipe(pipe_slow); | |
| 10818 %} | |
| 10819 | |
| 10820 instruct mulD_mem(regD dst, memory src) | |
| 10821 %{ | |
| 10822 match(Set dst (MulD dst (LoadD src))); | |
| 10823 | |
| 10824 format %{ "mulsd $dst, $src" %} | |
| 10825 ins_cost(150); // XXX | |
| 10826 opcode(0xF2, 0x0F, 0x59); | |
| 10827 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10828 ins_pipe(pipe_slow); | |
| 10829 %} | |
| 10830 | |
| 10831 instruct mulD_imm(regD dst, immD src) | |
| 10832 %{ | |
| 10833 match(Set dst (MulD dst src)); | |
| 10834 | |
| 10835 format %{ "mulsd $dst, [$src]" %} | |
| 10836 ins_cost(150); // XXX | |
| 10837 opcode(0xF2, 0x0F, 0x59); | |
| 10838 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10839 ins_pipe(pipe_slow); | |
| 10840 %} | |
| 10841 | |
| 10842 instruct divF_reg(regF dst, regF src) | |
| 10843 %{ | |
| 10844 match(Set dst (DivF dst src)); | |
| 10845 | |
| 10846 format %{ "divss $dst, $src" %} | |
| 10847 ins_cost(150); // XXX | |
| 10848 opcode(0xF3, 0x0F, 0x5E); | |
| 10849 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10850 ins_pipe(pipe_slow); | |
| 10851 %} | |
| 10852 | |
| 10853 instruct divF_mem(regF dst, memory src) | |
| 10854 %{ | |
| 10855 match(Set dst (DivF dst (LoadF src))); | |
| 10856 | |
| 10857 format %{ "divss $dst, $src" %} | |
| 10858 ins_cost(150); // XXX | |
| 10859 opcode(0xF3, 0x0F, 0x5E); | |
| 10860 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10861 ins_pipe(pipe_slow); | |
| 10862 %} | |
| 10863 | |
| 10864 instruct divF_imm(regF dst, immF src) | |
| 10865 %{ | |
| 10866 match(Set dst (DivF dst src)); | |
| 10867 | |
| 10868 format %{ "divss $dst, [$src]" %} | |
| 10869 ins_cost(150); // XXX | |
| 10870 opcode(0xF3, 0x0F, 0x5E); | |
| 10871 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10872 ins_pipe(pipe_slow); | |
| 10873 %} | |
| 10874 | |
| 10875 instruct divD_reg(regD dst, regD src) | |
| 10876 %{ | |
| 10877 match(Set dst (DivD dst src)); | |
| 10878 | |
| 10879 format %{ "divsd $dst, $src" %} | |
| 10880 ins_cost(150); // XXX | |
| 10881 opcode(0xF2, 0x0F, 0x5E); | |
| 10882 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10883 ins_pipe(pipe_slow); | |
| 10884 %} | |
| 10885 | |
| 10886 instruct divD_mem(regD dst, memory src) | |
| 10887 %{ | |
| 10888 match(Set dst (DivD dst (LoadD src))); | |
| 10889 | |
| 10890 format %{ "divsd $dst, $src" %} | |
| 10891 ins_cost(150); // XXX | |
| 10892 opcode(0xF2, 0x0F, 0x5E); | |
| 10893 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10894 ins_pipe(pipe_slow); | |
| 10895 %} | |
| 10896 | |
| 10897 instruct divD_imm(regD dst, immD src) | |
| 10898 %{ | |
| 10899 match(Set dst (DivD dst src)); | |
| 10900 | |
| 10901 format %{ "divsd $dst, [$src]" %} | |
| 10902 ins_cost(150); // XXX | |
| 10903 opcode(0xF2, 0x0F, 0x5E); | |
| 10904 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10905 ins_pipe(pipe_slow); | |
| 10906 %} | |
| 10907 | |
| 10908 instruct sqrtF_reg(regF dst, regF src) | |
| 10909 %{ | |
| 10910 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 10911 | |
| 10912 format %{ "sqrtss $dst, $src" %} | |
| 10913 ins_cost(150); // XXX | |
| 10914 opcode(0xF3, 0x0F, 0x51); | |
| 10915 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10916 ins_pipe(pipe_slow); | |
| 10917 %} | |
| 10918 | |
| 10919 instruct sqrtF_mem(regF dst, memory src) | |
| 10920 %{ | |
| 10921 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src))))); | |
| 10922 | |
| 10923 format %{ "sqrtss $dst, $src" %} | |
| 10924 ins_cost(150); // XXX | |
| 10925 opcode(0xF3, 0x0F, 0x51); | |
| 10926 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10927 ins_pipe(pipe_slow); | |
| 10928 %} | |
| 10929 | |
| 10930 instruct sqrtF_imm(regF dst, immF src) | |
| 10931 %{ | |
| 10932 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); | |
| 10933 | |
| 10934 format %{ "sqrtss $dst, [$src]" %} | |
| 10935 ins_cost(150); // XXX | |
| 10936 opcode(0xF3, 0x0F, 0x51); | |
| 10937 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immF(dst, src)); | |
| 10938 ins_pipe(pipe_slow); | |
| 10939 %} | |
| 10940 | |
| 10941 instruct sqrtD_reg(regD dst, regD src) | |
| 10942 %{ | |
| 10943 match(Set dst (SqrtD src)); | |
| 10944 | |
| 10945 format %{ "sqrtsd $dst, $src" %} | |
| 10946 ins_cost(150); // XXX | |
| 10947 opcode(0xF2, 0x0F, 0x51); | |
| 10948 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 10949 ins_pipe(pipe_slow); | |
| 10950 %} | |
| 10951 | |
| 10952 instruct sqrtD_mem(regD dst, memory src) | |
| 10953 %{ | |
| 10954 match(Set dst (SqrtD (LoadD src))); | |
| 10955 | |
| 10956 format %{ "sqrtsd $dst, $src" %} | |
| 10957 ins_cost(150); // XXX | |
| 10958 opcode(0xF2, 0x0F, 0x51); | |
| 10959 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 10960 ins_pipe(pipe_slow); | |
| 10961 %} | |
| 10962 | |
| 10963 instruct sqrtD_imm(regD dst, immD src) | |
| 10964 %{ | |
| 10965 match(Set dst (SqrtD src)); | |
| 10966 | |
| 10967 format %{ "sqrtsd $dst, [$src]" %} | |
| 10968 ins_cost(150); // XXX | |
| 10969 opcode(0xF2, 0x0F, 0x51); | |
| 10970 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, load_immD(dst, src)); | |
| 10971 ins_pipe(pipe_slow); | |
| 10972 %} | |
| 10973 | |
| 10974 instruct absF_reg(regF dst) | |
| 10975 %{ | |
| 10976 match(Set dst (AbsF dst)); | |
| 10977 | |
| 10978 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %} | |
| 10979 ins_encode(absF_encoding(dst)); | |
| 10980 ins_pipe(pipe_slow); | |
| 10981 %} | |
| 10982 | |
| 10983 instruct absD_reg(regD dst) | |
| 10984 %{ | |
| 10985 match(Set dst (AbsD dst)); | |
| 10986 | |
| 10987 format %{ "andpd $dst, [0x7fffffffffffffff]\t" | |
| 10988 "# abs double by sign masking" %} | |
| 10989 ins_encode(absD_encoding(dst)); | |
| 10990 ins_pipe(pipe_slow); | |
| 10991 %} | |
| 10992 | |
| 10993 instruct negF_reg(regF dst) | |
| 10994 %{ | |
| 10995 match(Set dst (NegF dst)); | |
| 10996 | |
| 10997 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %} | |
| 10998 ins_encode(negF_encoding(dst)); | |
| 10999 ins_pipe(pipe_slow); | |
| 11000 %} | |
| 11001 | |
| 11002 instruct negD_reg(regD dst) | |
| 11003 %{ | |
| 11004 match(Set dst (NegD dst)); | |
| 11005 | |
| 11006 format %{ "xorpd $dst, [0x8000000000000000]\t" | |
| 11007 "# neg double by sign flipping" %} | |
| 11008 ins_encode(negD_encoding(dst)); | |
| 11009 ins_pipe(pipe_slow); | |
| 11010 %} | |
| 11011 | |
| 11012 // -----------Trig and Trancendental Instructions------------------------------ | |
| 11013 instruct cosD_reg(regD dst) %{ | |
| 11014 match(Set dst (CosD dst)); | |
| 11015 | |
| 11016 format %{ "dcos $dst\n\t" %} | |
| 11017 opcode(0xD9, 0xFF); | |
| 11018 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 11019 ins_pipe( pipe_slow ); | |
| 11020 %} | |
| 11021 | |
| 11022 instruct sinD_reg(regD dst) %{ | |
| 11023 match(Set dst (SinD dst)); | |
| 11024 | |
| 11025 format %{ "dsin $dst\n\t" %} | |
| 11026 opcode(0xD9, 0xFE); | |
| 11027 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); | |
| 11028 ins_pipe( pipe_slow ); | |
| 11029 %} | |
| 11030 | |
| 11031 instruct tanD_reg(regD dst) %{ | |
| 11032 match(Set dst (TanD dst)); | |
| 11033 | |
| 11034 format %{ "dtan $dst\n\t" %} | |
| 11035 ins_encode( Push_SrcXD(dst), | |
| 11036 Opcode(0xD9), Opcode(0xF2), //fptan | |
| 11037 Opcode(0xDD), Opcode(0xD8), //fstp st | |
| 11038 Push_ResultXD(dst) ); | |
| 11039 ins_pipe( pipe_slow ); | |
| 11040 %} | |
| 11041 | |
| 11042 instruct log10D_reg(regD dst) %{ | |
| 11043 // The source and result Double operands in XMM registers | |
| 11044 match(Set dst (Log10D dst)); | |
| 11045 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number | |
| 11046 // fyl2x ; compute log_10(2) * log_2(x) | |
| 11047 format %{ "fldlg2\t\t\t#Log10\n\t" | |
| 11048 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t" | |
| 11049 %} | |
| 11050 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2 | |
| 11051 Push_SrcXD(dst), | |
| 11052 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 11053 Push_ResultXD(dst)); | |
| 11054 | |
| 11055 ins_pipe( pipe_slow ); | |
| 11056 %} | |
| 11057 | |
| 11058 instruct logD_reg(regD dst) %{ | |
| 11059 // The source and result Double operands in XMM registers | |
| 11060 match(Set dst (LogD dst)); | |
| 11061 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number | |
| 11062 // fyl2x ; compute log_e(2) * log_2(x) | |
| 11063 format %{ "fldln2\t\t\t#Log_e\n\t" | |
| 11064 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t" | |
| 11065 %} | |
| 11066 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 | |
| 11067 Push_SrcXD(dst), | |
| 11068 Opcode(0xD9), Opcode(0xF1), // fyl2x | |
| 11069 Push_ResultXD(dst)); | |
| 11070 ins_pipe( pipe_slow ); | |
| 11071 %} | |
| 11072 | |
| 11073 | |
| 11074 | |
| 11075 //----------Arithmetic Conversion Instructions--------------------------------- | |
| 11076 | |
| 11077 instruct roundFloat_nop(regF dst) | |
| 11078 %{ | |
| 11079 match(Set dst (RoundFloat dst)); | |
| 11080 | |
| 11081 ins_cost(0); | |
| 11082 ins_encode(); | |
| 11083 ins_pipe(empty); | |
| 11084 %} | |
| 11085 | |
| 11086 instruct roundDouble_nop(regD dst) | |
| 11087 %{ | |
| 11088 match(Set dst (RoundDouble dst)); | |
| 11089 | |
| 11090 ins_cost(0); | |
| 11091 ins_encode(); | |
| 11092 ins_pipe(empty); | |
| 11093 %} | |
| 11094 | |
| 11095 instruct convF2D_reg_reg(regD dst, regF src) | |
| 11096 %{ | |
| 11097 match(Set dst (ConvF2D src)); | |
| 11098 | |
| 11099 format %{ "cvtss2sd $dst, $src" %} | |
| 11100 opcode(0xF3, 0x0F, 0x5A); | |
| 11101 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11102 ins_pipe(pipe_slow); // XXX | |
| 11103 %} | |
| 11104 | |
| 11105 instruct convF2D_reg_mem(regD dst, memory src) | |
| 11106 %{ | |
| 11107 match(Set dst (ConvF2D (LoadF src))); | |
| 11108 | |
| 11109 format %{ "cvtss2sd $dst, $src" %} | |
| 11110 opcode(0xF3, 0x0F, 0x5A); | |
| 11111 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11112 ins_pipe(pipe_slow); // XXX | |
| 11113 %} | |
| 11114 | |
| 11115 instruct convD2F_reg_reg(regF dst, regD src) | |
| 11116 %{ | |
| 11117 match(Set dst (ConvD2F src)); | |
| 11118 | |
| 11119 format %{ "cvtsd2ss $dst, $src" %} | |
| 11120 opcode(0xF2, 0x0F, 0x5A); | |
| 11121 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11122 ins_pipe(pipe_slow); // XXX | |
| 11123 %} | |
| 11124 | |
| 11125 instruct convD2F_reg_mem(regF dst, memory src) | |
| 11126 %{ | |
| 11127 match(Set dst (ConvD2F (LoadD src))); | |
| 11128 | |
| 11129 format %{ "cvtsd2ss $dst, $src" %} | |
| 11130 opcode(0xF2, 0x0F, 0x5A); | |
| 11131 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11132 ins_pipe(pipe_slow); // XXX | |
| 11133 %} | |
| 11134 | |
| 11135 // XXX do mem variants | |
| 11136 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr) | |
| 11137 %{ | |
| 11138 match(Set dst (ConvF2I src)); | |
| 11139 effect(KILL cr); | |
| 11140 | |
| 11141 format %{ "cvttss2sil $dst, $src\t# f2i\n\t" | |
| 11142 "cmpl $dst, #0x80000000\n\t" | |
| 11143 "jne,s done\n\t" | |
| 11144 "subq rsp, #8\n\t" | |
| 11145 "movss [rsp], $src\n\t" | |
| 11146 "call f2i_fixup\n\t" | |
| 11147 "popq $dst\n" | |
| 11148 "done: "%} | |
| 11149 opcode(0xF3, 0x0F, 0x2C); | |
| 11150 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 11151 f2i_fixup(dst, src)); | |
| 11152 ins_pipe(pipe_slow); | |
| 11153 %} | |
| 11154 | |
| 11155 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr) | |
| 11156 %{ | |
| 11157 match(Set dst (ConvF2L src)); | |
| 11158 effect(KILL cr); | |
| 11159 | |
| 11160 format %{ "cvttss2siq $dst, $src\t# f2l\n\t" | |
| 11161 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 11162 "jne,s done\n\t" | |
| 11163 "subq rsp, #8\n\t" | |
| 11164 "movss [rsp], $src\n\t" | |
| 11165 "call f2l_fixup\n\t" | |
| 11166 "popq $dst\n" | |
| 11167 "done: "%} | |
| 11168 opcode(0xF3, 0x0F, 0x2C); | |
| 11169 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 11170 f2l_fixup(dst, src)); | |
| 11171 ins_pipe(pipe_slow); | |
| 11172 %} | |
| 11173 | |
| 11174 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr) | |
| 11175 %{ | |
| 11176 match(Set dst (ConvD2I src)); | |
| 11177 effect(KILL cr); | |
| 11178 | |
| 11179 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t" | |
| 11180 "cmpl $dst, #0x80000000\n\t" | |
| 11181 "jne,s done\n\t" | |
| 11182 "subq rsp, #8\n\t" | |
| 11183 "movsd [rsp], $src\n\t" | |
| 11184 "call d2i_fixup\n\t" | |
| 11185 "popq $dst\n" | |
| 11186 "done: "%} | |
| 11187 opcode(0xF2, 0x0F, 0x2C); | |
| 11188 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 11189 d2i_fixup(dst, src)); | |
| 11190 ins_pipe(pipe_slow); | |
| 11191 %} | |
| 11192 | |
| 11193 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr) | |
| 11194 %{ | |
| 11195 match(Set dst (ConvD2L src)); | |
| 11196 effect(KILL cr); | |
| 11197 | |
| 11198 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t" | |
| 11199 "cmpq $dst, [0x8000000000000000]\n\t" | |
| 11200 "jne,s done\n\t" | |
| 11201 "subq rsp, #8\n\t" | |
| 11202 "movsd [rsp], $src\n\t" | |
| 11203 "call d2l_fixup\n\t" | |
| 11204 "popq $dst\n" | |
| 11205 "done: "%} | |
| 11206 opcode(0xF2, 0x0F, 0x2C); | |
| 11207 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src), | |
| 11208 d2l_fixup(dst, src)); | |
| 11209 ins_pipe(pipe_slow); | |
| 11210 %} | |
| 11211 | |
| 11212 instruct convI2F_reg_reg(regF dst, rRegI src) | |
| 11213 %{ | |
| 71 | 11214 predicate(!UseXmmI2F); |
| 0 | 11215 match(Set dst (ConvI2F src)); |
| 11216 | |
| 11217 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 11218 opcode(0xF3, 0x0F, 0x2A); | |
| 11219 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11220 ins_pipe(pipe_slow); // XXX | |
| 11221 %} | |
| 11222 | |
| 11223 instruct convI2F_reg_mem(regF dst, memory src) | |
| 11224 %{ | |
| 11225 match(Set dst (ConvI2F (LoadI src))); | |
| 11226 | |
| 11227 format %{ "cvtsi2ssl $dst, $src\t# i2f" %} | |
| 11228 opcode(0xF3, 0x0F, 0x2A); | |
| 11229 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11230 ins_pipe(pipe_slow); // XXX | |
| 11231 %} | |
| 11232 | |
| 11233 instruct convI2D_reg_reg(regD dst, rRegI src) | |
| 11234 %{ | |
| 71 | 11235 predicate(!UseXmmI2D); |
| 0 | 11236 match(Set dst (ConvI2D src)); |
| 11237 | |
| 11238 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 11239 opcode(0xF2, 0x0F, 0x2A); | |
| 11240 ins_encode(OpcP, REX_reg_reg(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11241 ins_pipe(pipe_slow); // XXX | |
| 11242 %} | |
| 11243 | |
| 11244 instruct convI2D_reg_mem(regD dst, memory src) | |
| 11245 %{ | |
| 11246 match(Set dst (ConvI2D (LoadI src))); | |
| 11247 | |
| 11248 format %{ "cvtsi2sdl $dst, $src\t# i2d" %} | |
| 11249 opcode(0xF2, 0x0F, 0x2A); | |
| 11250 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11251 ins_pipe(pipe_slow); // XXX | |
| 11252 %} | |
| 11253 | |
| 71 | 11254 instruct convXI2F_reg(regF dst, rRegI src) |
| 11255 %{ | |
| 11256 predicate(UseXmmI2F); | |
| 11257 match(Set dst (ConvI2F src)); | |
| 11258 | |
| 11259 format %{ "movdl $dst, $src\n\t" | |
| 11260 "cvtdq2psl $dst, $dst\t# i2f" %} | |
| 11261 ins_encode %{ | |
| 11262 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11263 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11264 %} | |
| 11265 ins_pipe(pipe_slow); // XXX | |
| 11266 %} | |
| 11267 | |
| 11268 instruct convXI2D_reg(regD dst, rRegI src) | |
| 11269 %{ | |
| 11270 predicate(UseXmmI2D); | |
| 11271 match(Set dst (ConvI2D src)); | |
| 11272 | |
| 11273 format %{ "movdl $dst, $src\n\t" | |
| 11274 "cvtdq2pdl $dst, $dst\t# i2d" %} | |
| 11275 ins_encode %{ | |
| 11276 __ movdl($dst$$XMMRegister, $src$$Register); | |
| 11277 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); | |
| 11278 %} | |
| 11279 ins_pipe(pipe_slow); // XXX | |
| 11280 %} | |
| 11281 | |
| 0 | 11282 instruct convL2F_reg_reg(regF dst, rRegL src) |
| 11283 %{ | |
| 11284 match(Set dst (ConvL2F src)); | |
| 11285 | |
| 11286 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 11287 opcode(0xF3, 0x0F, 0x2A); | |
| 11288 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11289 ins_pipe(pipe_slow); // XXX | |
| 11290 %} | |
| 11291 | |
| 11292 instruct convL2F_reg_mem(regF dst, memory src) | |
| 11293 %{ | |
| 11294 match(Set dst (ConvL2F (LoadL src))); | |
| 11295 | |
| 11296 format %{ "cvtsi2ssq $dst, $src\t# l2f" %} | |
| 11297 opcode(0xF3, 0x0F, 0x2A); | |
| 11298 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11299 ins_pipe(pipe_slow); // XXX | |
| 11300 %} | |
| 11301 | |
| 11302 instruct convL2D_reg_reg(regD dst, rRegL src) | |
| 11303 %{ | |
| 11304 match(Set dst (ConvL2D src)); | |
| 11305 | |
| 11306 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 11307 opcode(0xF2, 0x0F, 0x2A); | |
| 11308 ins_encode(OpcP, REX_reg_reg_wide(dst, src), OpcS, OpcT, reg_reg(dst, src)); | |
| 11309 ins_pipe(pipe_slow); // XXX | |
| 11310 %} | |
| 11311 | |
| 11312 instruct convL2D_reg_mem(regD dst, memory src) | |
| 11313 %{ | |
| 11314 match(Set dst (ConvL2D (LoadL src))); | |
| 11315 | |
| 11316 format %{ "cvtsi2sdq $dst, $src\t# l2d" %} | |
| 11317 opcode(0xF2, 0x0F, 0x2A); | |
| 11318 ins_encode(OpcP, REX_reg_mem_wide(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11319 ins_pipe(pipe_slow); // XXX | |
| 11320 %} | |
| 11321 | |
| 11322 instruct convI2L_reg_reg(rRegL dst, rRegI src) | |
| 11323 %{ | |
| 11324 match(Set dst (ConvI2L src)); | |
| 11325 | |
| 11326 ins_cost(125); | |
| 11327 format %{ "movslq $dst, $src\t# i2l" %} | |
| 824 | 11328 ins_encode %{ |
| 11329 __ movslq($dst$$Register, $src$$Register); | |
| 11330 %} | |
| 0 | 11331 ins_pipe(ialu_reg_reg); |
| 11332 %} | |
| 11333 | |
| 11334 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src) | |
| 11335 // %{ | |
| 11336 // match(Set dst (ConvI2L src)); | |
| 11337 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 && | |
| 11338 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0); | |
| 11339 // predicate(((const TypeNode*) n)->type()->is_long()->_hi == | |
| 11340 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi && | |
| 11341 // ((const TypeNode*) n)->type()->is_long()->_lo == | |
| 11342 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo); | |
| 11343 | |
| 11344 // format %{ "movl $dst, $src\t# unsigned i2l" %} | |
| 11345 // ins_encode(enc_copy(dst, src)); | |
| 11346 // // opcode(0x63); // needs REX.W | |
| 11347 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); | |
| 11348 // ins_pipe(ialu_reg_reg); | |
| 11349 // %} | |
| 11350 | |
| 11351 // Zero-extend convert int to long | |
| 11352 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask) | |
| 11353 %{ | |
| 11354 match(Set dst (AndL (ConvI2L src) mask)); | |
| 11355 | |
| 11356 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 11357 ins_encode(enc_copy(dst, src)); | |
| 11358 ins_pipe(ialu_reg_reg); | |
| 11359 %} | |
| 11360 | |
| 11361 // Zero-extend convert int to long | |
| 11362 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask) | |
| 11363 %{ | |
| 11364 match(Set dst (AndL (ConvI2L (LoadI src)) mask)); | |
| 11365 | |
| 11366 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %} | |
| 11367 opcode(0x8B); | |
| 11368 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 11369 ins_pipe(ialu_reg_mem); | |
| 11370 %} | |
| 11371 | |
| 11372 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask) | |
| 11373 %{ | |
| 11374 match(Set dst (AndL src mask)); | |
| 11375 | |
| 11376 format %{ "movl $dst, $src\t# zero-extend long" %} | |
| 11377 ins_encode(enc_copy_always(dst, src)); | |
| 11378 ins_pipe(ialu_reg_reg); | |
| 11379 %} | |
| 11380 | |
| 11381 instruct convL2I_reg_reg(rRegI dst, rRegL src) | |
| 11382 %{ | |
| 11383 match(Set dst (ConvL2I src)); | |
| 11384 | |
| 11385 format %{ "movl $dst, $src\t# l2i" %} | |
| 11386 ins_encode(enc_copy_always(dst, src)); | |
| 11387 ins_pipe(ialu_reg_reg); | |
| 11388 %} | |
| 11389 | |
| 11390 | |
| 11391 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ | |
| 11392 match(Set dst (MoveF2I src)); | |
| 11393 effect(DEF dst, USE src); | |
| 11394 | |
| 11395 ins_cost(125); | |
| 11396 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %} | |
| 11397 opcode(0x8B); | |
| 11398 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src)); | |
| 11399 ins_pipe(ialu_reg_mem); | |
| 11400 %} | |
| 11401 | |
| 11402 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ | |
| 11403 match(Set dst (MoveI2F src)); | |
| 11404 effect(DEF dst, USE src); | |
| 11405 | |
| 11406 ins_cost(125); | |
| 11407 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %} | |
| 11408 opcode(0xF3, 0x0F, 0x10); | |
| 11409 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11410 ins_pipe(pipe_slow); | |
| 11411 %} | |
| 11412 | |
| 11413 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{ | |
| 11414 match(Set dst (MoveD2L src)); | |
| 11415 effect(DEF dst, USE src); | |
| 11416 | |
| 11417 ins_cost(125); | |
| 11418 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %} | |
| 11419 opcode(0x8B); | |
| 11420 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src)); | |
| 11421 ins_pipe(ialu_reg_mem); | |
| 11422 %} | |
| 11423 | |
| 11424 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{ | |
| 11425 predicate(!UseXmmLoadAndClearUpper); | |
| 11426 match(Set dst (MoveL2D src)); | |
| 11427 effect(DEF dst, USE src); | |
| 11428 | |
| 11429 ins_cost(125); | |
| 11430 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 11431 opcode(0x66, 0x0F, 0x12); | |
| 11432 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11433 ins_pipe(pipe_slow); | |
| 11434 %} | |
| 11435 | |
| 11436 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ | |
| 11437 predicate(UseXmmLoadAndClearUpper); | |
| 11438 match(Set dst (MoveL2D src)); | |
| 11439 effect(DEF dst, USE src); | |
| 11440 | |
| 11441 ins_cost(125); | |
| 11442 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %} | |
| 11443 opcode(0xF2, 0x0F, 0x10); | |
| 11444 ins_encode(OpcP, REX_reg_mem(dst, src), OpcS, OpcT, reg_mem(dst, src)); | |
| 11445 ins_pipe(pipe_slow); | |
| 11446 %} | |
| 11447 | |
| 11448 | |
| 11449 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ | |
| 11450 match(Set dst (MoveF2I src)); | |
| 11451 effect(DEF dst, USE src); | |
| 11452 | |
| 11453 ins_cost(95); // XXX | |
| 11454 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %} | |
| 11455 opcode(0xF3, 0x0F, 0x11); | |
| 11456 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 11457 ins_pipe(pipe_slow); | |
| 11458 %} | |
| 11459 | |
| 11460 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ | |
| 11461 match(Set dst (MoveI2F src)); | |
| 11462 effect(DEF dst, USE src); | |
| 11463 | |
| 11464 ins_cost(100); | |
| 11465 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %} | |
| 11466 opcode(0x89); | |
| 11467 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst)); | |
| 11468 ins_pipe( ialu_mem_reg ); | |
| 11469 %} | |
| 11470 | |
| 11471 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ | |
| 11472 match(Set dst (MoveD2L src)); | |
| 11473 effect(DEF dst, USE src); | |
| 11474 | |
| 11475 ins_cost(95); // XXX | |
| 11476 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %} | |
| 11477 opcode(0xF2, 0x0F, 0x11); | |
| 11478 ins_encode(OpcP, REX_reg_mem(src, dst), OpcS, OpcT, reg_mem(src, dst)); | |
| 11479 ins_pipe(pipe_slow); | |
| 11480 %} | |
| 11481 | |
| 11482 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{ | |
| 11483 match(Set dst (MoveL2D src)); | |
| 11484 effect(DEF dst, USE src); | |
| 11485 | |
| 11486 ins_cost(100); | |
| 11487 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %} | |
| 11488 opcode(0x89); | |
| 11489 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst)); | |
| 11490 ins_pipe(ialu_mem_reg); | |
| 11491 %} | |
| 11492 | |
| 11493 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{ | |
| 11494 match(Set dst (MoveF2I src)); | |
| 11495 effect(DEF dst, USE src); | |
| 11496 ins_cost(85); | |
| 11497 format %{ "movd $dst,$src\t# MoveF2I" %} | |
| 11498 ins_encode %{ __ movdl($dst$$Register, $src$$XMMRegister); %} | |
| 11499 ins_pipe( pipe_slow ); | |
| 11500 %} | |
| 11501 | |
| 11502 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{ | |
| 11503 match(Set dst (MoveD2L src)); | |
| 11504 effect(DEF dst, USE src); | |
| 11505 ins_cost(85); | |
| 11506 format %{ "movd $dst,$src\t# MoveD2L" %} | |
| 11507 ins_encode %{ __ movdq($dst$$Register, $src$$XMMRegister); %} | |
| 11508 ins_pipe( pipe_slow ); | |
| 11509 %} | |
| 11510 | |
| 11511 // The next instructions have long latency and use Int unit. Set high cost. | |
| 11512 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{ | |
| 11513 match(Set dst (MoveI2F src)); | |
| 11514 effect(DEF dst, USE src); | |
| 11515 ins_cost(300); | |
| 11516 format %{ "movd $dst,$src\t# MoveI2F" %} | |
| 11517 ins_encode %{ __ movdl($dst$$XMMRegister, $src$$Register); %} | |
| 11518 ins_pipe( pipe_slow ); | |
| 11519 %} | |
| 11520 | |
| 11521 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{ | |
| 11522 match(Set dst (MoveL2D src)); | |
| 11523 effect(DEF dst, USE src); | |
| 11524 ins_cost(300); | |
| 11525 format %{ "movd $dst,$src\t# MoveL2D" %} | |
| 11526 ins_encode %{ __ movdq($dst$$XMMRegister, $src$$Register); %} | |
| 11527 ins_pipe( pipe_slow ); | |
| 11528 %} | |
| 11529 | |
| 11530 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 11531 instruct Repl8B_reg(regD dst, regD src) %{ | |
| 11532 match(Set dst (Replicate8B src)); | |
| 11533 format %{ "MOVDQA $dst,$src\n\t" | |
| 11534 "PUNPCKLBW $dst,$dst\n\t" | |
| 11535 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 11536 ins_encode( pshufd_8x8(dst, src)); | |
| 11537 ins_pipe( pipe_slow ); | |
| 11538 %} | |
| 11539 | |
| 11540 // Replicate scalar to packed byte (1 byte) values in xmm | |
| 11541 instruct Repl8B_rRegI(regD dst, rRegI src) %{ | |
| 11542 match(Set dst (Replicate8B src)); | |
| 11543 format %{ "MOVD $dst,$src\n\t" | |
| 11544 "PUNPCKLBW $dst,$dst\n\t" | |
| 11545 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} | |
| 11546 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); | |
| 11547 ins_pipe( pipe_slow ); | |
| 11548 %} | |
| 11549 | |
| 11550 // Replicate scalar zero to packed byte (1 byte) values in xmm | |
| 11551 instruct Repl8B_immI0(regD dst, immI0 zero) %{ | |
| 11552 match(Set dst (Replicate8B zero)); | |
| 11553 format %{ "PXOR $dst,$dst\t! replicate8B" %} | |
| 11554 ins_encode( pxor(dst, dst)); | |
| 11555 ins_pipe( fpu_reg_reg ); | |
| 11556 %} | |
| 11557 | |
| 11558 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 11559 instruct Repl4S_reg(regD dst, regD src) %{ | |
| 11560 match(Set dst (Replicate4S src)); | |
| 11561 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} | |
| 11562 ins_encode( pshufd_4x16(dst, src)); | |
| 11563 ins_pipe( fpu_reg_reg ); | |
| 11564 %} | |
| 11565 | |
| 11566 // Replicate scalar to packed shore (2 byte) values in xmm | |
| 11567 instruct Repl4S_rRegI(regD dst, rRegI src) %{ | |
| 11568 match(Set dst (Replicate4S src)); | |
| 11569 format %{ "MOVD $dst,$src\n\t" | |
| 11570 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} | |
| 11571 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 11572 ins_pipe( fpu_reg_reg ); | |
| 11573 %} | |
| 11574 | |
| 11575 // Replicate scalar zero to packed short (2 byte) values in xmm | |
| 11576 instruct Repl4S_immI0(regD dst, immI0 zero) %{ | |
| 11577 match(Set dst (Replicate4S zero)); | |
| 11578 format %{ "PXOR $dst,$dst\t! replicate4S" %} | |
| 11579 ins_encode( pxor(dst, dst)); | |
| 11580 ins_pipe( fpu_reg_reg ); | |
| 11581 %} | |
| 11582 | |
| 11583 // Replicate scalar to packed char (2 byte) values in xmm | |
| 11584 instruct Repl4C_reg(regD dst, regD src) %{ | |
| 11585 match(Set dst (Replicate4C src)); | |
| 11586 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} | |
| 11587 ins_encode( pshufd_4x16(dst, src)); | |
| 11588 ins_pipe( fpu_reg_reg ); | |
| 11589 %} | |
| 11590 | |
| 11591 // Replicate scalar to packed char (2 byte) values in xmm | |
| 11592 instruct Repl4C_rRegI(regD dst, rRegI src) %{ | |
| 11593 match(Set dst (Replicate4C src)); | |
| 11594 format %{ "MOVD $dst,$src\n\t" | |
| 11595 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} | |
| 11596 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); | |
| 11597 ins_pipe( fpu_reg_reg ); | |
| 11598 %} | |
| 11599 | |
| 11600 // Replicate scalar zero to packed char (2 byte) values in xmm | |
| 11601 instruct Repl4C_immI0(regD dst, immI0 zero) %{ | |
| 11602 match(Set dst (Replicate4C zero)); | |
| 11603 format %{ "PXOR $dst,$dst\t! replicate4C" %} | |
| 11604 ins_encode( pxor(dst, dst)); | |
| 11605 ins_pipe( fpu_reg_reg ); | |
| 11606 %} | |
| 11607 | |
| 11608 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 11609 instruct Repl2I_reg(regD dst, regD src) %{ | |
| 11610 match(Set dst (Replicate2I src)); | |
| 11611 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} | |
| 11612 ins_encode( pshufd(dst, src, 0x00)); | |
| 11613 ins_pipe( fpu_reg_reg ); | |
| 11614 %} | |
| 11615 | |
| 11616 // Replicate scalar to packed integer (4 byte) values in xmm | |
| 11617 instruct Repl2I_rRegI(regD dst, rRegI src) %{ | |
| 11618 match(Set dst (Replicate2I src)); | |
| 11619 format %{ "MOVD $dst,$src\n\t" | |
| 11620 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} | |
| 11621 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); | |
| 11622 ins_pipe( fpu_reg_reg ); | |
| 11623 %} | |
| 11624 | |
| 11625 // Replicate scalar zero to packed integer (2 byte) values in xmm | |
| 11626 instruct Repl2I_immI0(regD dst, immI0 zero) %{ | |
| 11627 match(Set dst (Replicate2I zero)); | |
| 11628 format %{ "PXOR $dst,$dst\t! replicate2I" %} | |
| 11629 ins_encode( pxor(dst, dst)); | |
| 11630 ins_pipe( fpu_reg_reg ); | |
| 11631 %} | |
| 11632 | |
| 11633 // Replicate scalar to packed single precision floating point values in xmm | |
| 11634 instruct Repl2F_reg(regD dst, regD src) %{ | |
| 11635 match(Set dst (Replicate2F src)); | |
| 11636 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 11637 ins_encode( pshufd(dst, src, 0xe0)); | |
| 11638 ins_pipe( fpu_reg_reg ); | |
| 11639 %} | |
| 11640 | |
| 11641 // Replicate scalar to packed single precision floating point values in xmm | |
| 11642 instruct Repl2F_regF(regD dst, regF src) %{ | |
| 11643 match(Set dst (Replicate2F src)); | |
| 11644 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} | |
| 11645 ins_encode( pshufd(dst, src, 0xe0)); | |
| 11646 ins_pipe( fpu_reg_reg ); | |
| 11647 %} | |
| 11648 | |
| 11649 // Replicate scalar to packed single precision floating point values in xmm | |
| 11650 instruct Repl2F_immF0(regD dst, immF0 zero) %{ | |
| 11651 match(Set dst (Replicate2F zero)); | |
| 11652 format %{ "PXOR $dst,$dst\t! replicate2F" %} | |
| 11653 ins_encode( pxor(dst, dst)); | |
| 11654 ins_pipe( fpu_reg_reg ); | |
| 11655 %} | |
| 11656 | |
| 11657 | |
| 11658 // ======================================================================= | |
| 11659 // fast clearing of an array | |
| 11660 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy, | |
| 11661 rFlagsReg cr) | |
| 11662 %{ | |
| 11663 match(Set dummy (ClearArray cnt base)); | |
| 11664 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); | |
| 11665 | |
| 11666 format %{ "xorl rax, rax\t# ClearArray:\n\t" | |
| 11667 "rep stosq\t# Store rax to *rdi++ while rcx--" %} | |
| 11668 ins_encode(opc_reg_reg(0x33, RAX, RAX), // xorl %eax, %eax | |
| 11669 Opcode(0xF3), Opcode(0x48), Opcode(0xAB)); // rep REX_W stos | |
| 11670 ins_pipe(pipe_slow); | |
| 11671 %} | |
| 11672 | |
|
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11673 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rbx_RegI cnt2, |
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11674 rax_RegI result, regD tmp1, regD tmp2, rFlagsReg cr) |
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11675 %{ |
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11676 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); |
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11677 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); |
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11678 |
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11679 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1, $tmp2" %} |
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11680 ins_encode %{ |
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11681 __ string_compare($str1$$Register, $str2$$Register, |
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11682 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
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11683 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
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11684 %} |
| 681 | 11685 ins_pipe( pipe_slow ); |
| 11686 %} | |
| 11687 | |
|
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11688 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2, |
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11689 rbx_RegI result, regD tmp1, rcx_RegI tmp2, rFlagsReg cr) |
| 681 | 11690 %{ |
| 11691 predicate(UseSSE42Intrinsics); | |
|
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11692 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); |
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11693 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp2, KILL cr); |
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11694 |
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11695 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1, $tmp2" %} |
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11696 ins_encode %{ |
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11697 __ string_indexof($str1$$Register, $str2$$Register, |
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11698 $cnt1$$Register, $cnt2$$Register, $result$$Register, |
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11699 $tmp1$$XMMRegister, $tmp2$$Register); |
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11700 %} |
| 681 | 11701 ins_pipe( pipe_slow ); |
| 11702 %} | |
| 11703 | |
| 11704 // fast string equals | |
|
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11705 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result, |
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11706 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr) |
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11707 %{ |
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11708 match(Set result (StrEquals (Binary str1 str2) cnt)); |
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11709 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); |
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11710 |
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11711 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} |
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11712 ins_encode %{ |
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11713 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, |
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11714 $cnt$$Register, $result$$Register, $tmp3$$Register, |
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11715 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
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11716 %} |
| 0 | 11717 ins_pipe( pipe_slow ); |
| 11718 %} | |
| 11719 | |
|
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11720 // fast array equals |
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11721 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result, |
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11722 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr) |
| 681 | 11723 %{ |
|
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11724 match(Set result (AryEq ary1 ary2)); |
| 681 | 11725 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); |
|
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11726 //ins_cost(300); |
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11727 |
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11728 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} |
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11729 ins_encode %{ |
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11730 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, |
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11731 $tmp3$$Register, $result$$Register, $tmp4$$Register, |
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11732 $tmp1$$XMMRegister, $tmp2$$XMMRegister); |
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11733 %} |
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11734 ins_pipe( pipe_slow ); |
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11735 %} |
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11736 |
| 0 | 11737 //----------Control Flow Instructions------------------------------------------ |
| 11738 // Signed compare Instructions | |
| 11739 | |
| 11740 // XXX more variants!! | |
| 11741 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2) | |
| 11742 %{ | |
| 11743 match(Set cr (CmpI op1 op2)); | |
| 11744 effect(DEF cr, USE op1, USE op2); | |
| 11745 | |
| 11746 format %{ "cmpl $op1, $op2" %} | |
| 11747 opcode(0x3B); /* Opcode 3B /r */ | |
| 11748 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11749 ins_pipe(ialu_cr_reg_reg); | |
| 11750 %} | |
| 11751 | |
| 11752 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2) | |
| 11753 %{ | |
| 11754 match(Set cr (CmpI op1 op2)); | |
| 11755 | |
| 11756 format %{ "cmpl $op1, $op2" %} | |
| 11757 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 11758 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 11759 ins_pipe(ialu_cr_reg_imm); | |
| 11760 %} | |
| 11761 | |
| 11762 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2) | |
| 11763 %{ | |
| 11764 match(Set cr (CmpI op1 (LoadI op2))); | |
| 11765 | |
| 11766 ins_cost(500); // XXX | |
| 11767 format %{ "cmpl $op1, $op2" %} | |
| 11768 opcode(0x3B); /* Opcode 3B /r */ | |
| 11769 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11770 ins_pipe(ialu_cr_reg_mem); | |
| 11771 %} | |
| 11772 | |
| 11773 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero) | |
| 11774 %{ | |
| 11775 match(Set cr (CmpI src zero)); | |
| 11776 | |
| 11777 format %{ "testl $src, $src" %} | |
| 11778 opcode(0x85); | |
| 11779 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 11780 ins_pipe(ialu_cr_reg_imm); | |
| 11781 %} | |
| 11782 | |
| 11783 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero) | |
| 11784 %{ | |
| 11785 match(Set cr (CmpI (AndI src con) zero)); | |
| 11786 | |
| 11787 format %{ "testl $src, $con" %} | |
| 11788 opcode(0xF7, 0x00); | |
| 11789 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con)); | |
| 11790 ins_pipe(ialu_cr_reg_imm); | |
| 11791 %} | |
| 11792 | |
| 11793 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero) | |
| 11794 %{ | |
| 11795 match(Set cr (CmpI (AndI src (LoadI mem)) zero)); | |
| 11796 | |
| 11797 format %{ "testl $src, $mem" %} | |
| 11798 opcode(0x85); | |
| 11799 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem)); | |
| 11800 ins_pipe(ialu_cr_reg_mem); | |
| 11801 %} | |
| 11802 | |
| 11803 // Unsigned compare Instructions; really, same as signed except they | |
| 11804 // produce an rFlagsRegU instead of rFlagsReg. | |
| 11805 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2) | |
| 11806 %{ | |
| 11807 match(Set cr (CmpU op1 op2)); | |
| 11808 | |
| 11809 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 11810 opcode(0x3B); /* Opcode 3B /r */ | |
| 11811 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11812 ins_pipe(ialu_cr_reg_reg); | |
| 11813 %} | |
| 11814 | |
| 11815 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2) | |
| 11816 %{ | |
| 11817 match(Set cr (CmpU op1 op2)); | |
| 11818 | |
| 11819 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 11820 opcode(0x81,0x07); /* Opcode 81 /7 */ | |
| 11821 ins_encode(OpcSErm(op1, op2), Con8or32(op2)); | |
| 11822 ins_pipe(ialu_cr_reg_imm); | |
| 11823 %} | |
| 11824 | |
| 11825 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2) | |
| 11826 %{ | |
| 11827 match(Set cr (CmpU op1 (LoadI op2))); | |
| 11828 | |
| 11829 ins_cost(500); // XXX | |
| 11830 format %{ "cmpl $op1, $op2\t# unsigned" %} | |
| 11831 opcode(0x3B); /* Opcode 3B /r */ | |
| 11832 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11833 ins_pipe(ialu_cr_reg_mem); | |
| 11834 %} | |
| 11835 | |
| 11836 // // // Cisc-spilled version of cmpU_rReg | |
| 11837 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2) | |
| 11838 // //%{ | |
| 11839 // // match(Set cr (CmpU (LoadI op1) op2)); | |
| 11840 // // | |
| 11841 // // format %{ "CMPu $op1,$op2" %} | |
| 11842 // // ins_cost(500); | |
| 11843 // // opcode(0x39); /* Opcode 39 /r */ | |
| 11844 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 11845 // //%} | |
| 11846 | |
| 11847 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero) | |
| 11848 %{ | |
| 11849 match(Set cr (CmpU src zero)); | |
| 11850 | |
| 11851 format %{ "testl $src, $src\t# unsigned" %} | |
| 11852 opcode(0x85); | |
| 11853 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src)); | |
| 11854 ins_pipe(ialu_cr_reg_imm); | |
| 11855 %} | |
| 11856 | |
| 11857 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2) | |
| 11858 %{ | |
| 11859 match(Set cr (CmpP op1 op2)); | |
| 11860 | |
| 11861 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 11862 opcode(0x3B); /* Opcode 3B /r */ | |
| 11863 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 11864 ins_pipe(ialu_cr_reg_reg); | |
| 11865 %} | |
| 11866 | |
| 11867 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2) | |
| 11868 %{ | |
| 11869 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11870 | |
| 11871 ins_cost(500); // XXX | |
| 11872 format %{ "cmpq $op1, $op2\t# ptr" %} | |
| 11873 opcode(0x3B); /* Opcode 3B /r */ | |
| 11874 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11875 ins_pipe(ialu_cr_reg_mem); | |
| 11876 %} | |
| 11877 | |
| 11878 // // // Cisc-spilled version of cmpP_rReg | |
| 11879 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2) | |
| 11880 // //%{ | |
| 11881 // // match(Set cr (CmpP (LoadP op1) op2)); | |
| 11882 // // | |
| 11883 // // format %{ "CMPu $op1,$op2" %} | |
| 11884 // // ins_cost(500); | |
| 11885 // // opcode(0x39); /* Opcode 39 /r */ | |
| 11886 // // ins_encode( OpcP, reg_mem( op1, op2) ); | |
| 11887 // //%} | |
| 11888 | |
| 11889 // XXX this is generalized by compP_rReg_mem??? | |
| 11890 // Compare raw pointer (used in out-of-heap check). | |
| 11891 // Only works because non-oop pointers must be raw pointers | |
| 11892 // and raw pointers have no anti-dependencies. | |
| 11893 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2) | |
| 11894 %{ | |
| 11895 predicate(!n->in(2)->in(2)->bottom_type()->isa_oop_ptr()); | |
| 11896 match(Set cr (CmpP op1 (LoadP op2))); | |
| 11897 | |
| 11898 format %{ "cmpq $op1, $op2\t# raw ptr" %} | |
| 11899 opcode(0x3B); /* Opcode 3B /r */ | |
| 11900 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 11901 ins_pipe(ialu_cr_reg_mem); | |
| 11902 %} | |
| 11903 | |
| 11904 // This will generate a signed flags result. This should be OK since | |
| 11905 // any compare to a zero should be eq/neq. | |
| 11906 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero) | |
| 11907 %{ | |
| 11908 match(Set cr (CmpP src zero)); | |
| 11909 | |
| 11910 format %{ "testq $src, $src\t# ptr" %} | |
| 11911 opcode(0x85); | |
| 11912 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 11913 ins_pipe(ialu_cr_reg_imm); | |
| 11914 %} | |
| 11915 | |
| 11916 // This will generate a signed flags result. This should be OK since | |
| 11917 // any compare to a zero should be eq/neq. | |
|
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11918 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero) |
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11919 %{ |
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11920 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL)); |
| 0 | 11921 match(Set cr (CmpP (LoadP op) zero)); |
| 11922 | |
| 11923 ins_cost(500); // XXX | |
| 11924 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %} | |
| 11925 opcode(0xF7); /* Opcode F7 /0 */ | |
| 11926 ins_encode(REX_mem_wide(op), | |
| 11927 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); | |
| 11928 ins_pipe(ialu_cr_reg_imm); | |
| 11929 %} | |
| 11930 | |
|
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11931 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero) |
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11932 %{ |
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11933 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL)); |
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11934 match(Set cr (CmpP (LoadP mem) zero)); |
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11935 |
|
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11936 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %} |
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11937 ins_encode %{ |
|
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11938 __ cmpq(r12, $mem$$Address); |
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11939 %} |
|
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11940 ins_pipe(ialu_cr_reg_mem); |
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11941 %} |
|
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11942 |
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11943 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2) |
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11944 %{ |
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11945 match(Set cr (CmpN op1 op2)); |
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11946 |
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11947 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
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11948 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %} |
|
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11949 ins_pipe(ialu_cr_reg_reg); |
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11950 %} |
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11951 |
|
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11952 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem) |
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11953 %{ |
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11954 match(Set cr (CmpN src (LoadN mem))); |
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11955 |
|
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11956 format %{ "cmpl $src, $mem\t# compressed ptr" %} |
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11957 ins_encode %{ |
|
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11958 __ cmpl($src$$Register, $mem$$Address); |
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11959 %} |
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11960 ins_pipe(ialu_cr_reg_mem); |
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11961 %} |
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11962 |
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11963 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{ |
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11964 match(Set cr (CmpN op1 op2)); |
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11965 |
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11966 format %{ "cmpl $op1, $op2\t# compressed ptr" %} |
|
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11967 ins_encode %{ |
|
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11968 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant); |
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11969 %} |
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11970 ins_pipe(ialu_cr_reg_imm); |
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11971 %} |
|
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11972 |
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11973 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src) |
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11974 %{ |
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11975 match(Set cr (CmpN src (LoadN mem))); |
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11976 |
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11977 format %{ "cmpl $mem, $src\t# compressed ptr" %} |
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11978 ins_encode %{ |
|
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11979 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant); |
|
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11980 %} |
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11981 ins_pipe(ialu_cr_reg_mem); |
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11982 %} |
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11983 |
|
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11984 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ |
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11985 match(Set cr (CmpN src zero)); |
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11986 |
|
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11987 format %{ "testl $src, $src\t# compressed ptr" %} |
|
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11988 ins_encode %{ __ testl($src$$Register, $src$$Register); %} |
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|
11989 ins_pipe(ialu_cr_reg_imm); |
|
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|
11990 %} |
|
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|
11991 |
|
642
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11992 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero) |
|
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|
11993 %{ |
|
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|
11994 predicate(Universe::narrow_oop_base() != NULL); |
|
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11995 match(Set cr (CmpN (LoadN mem) zero)); |
|
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|
11996 |
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|
11997 ins_cost(500); // XXX |
|
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11998 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %} |
|
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11999 ins_encode %{ |
|
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|
12000 __ cmpl($mem$$Address, (int)0xFFFFFFFF); |
|
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|
12001 %} |
|
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|
12002 ins_pipe(ialu_cr_reg_mem); |
|
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|
12003 %} |
|
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|
12004 |
|
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|
12005 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero) |
|
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|
12006 %{ |
|
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|
12007 predicate(Universe::narrow_oop_base() == NULL); |
|
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|
12008 match(Set cr (CmpN (LoadN mem) zero)); |
|
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|
12009 |
|
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|
12010 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %} |
|
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|
12011 ins_encode %{ |
|
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|
12012 __ cmpl(r12, $mem$$Address); |
|
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|
12013 %} |
|
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|
12014 ins_pipe(ialu_cr_reg_mem); |
|
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|
12015 %} |
|
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|
12016 |
| 0 | 12017 // Yanked all unsigned pointer compare operations. |
| 12018 // Pointer compares are done with CmpP which is already unsigned. | |
| 12019 | |
| 12020 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2) | |
| 12021 %{ | |
| 12022 match(Set cr (CmpL op1 op2)); | |
| 12023 | |
| 12024 format %{ "cmpq $op1, $op2" %} | |
| 12025 opcode(0x3B); /* Opcode 3B /r */ | |
| 12026 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2)); | |
| 12027 ins_pipe(ialu_cr_reg_reg); | |
| 12028 %} | |
| 12029 | |
| 12030 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2) | |
| 12031 %{ | |
| 12032 match(Set cr (CmpL op1 op2)); | |
| 12033 | |
| 12034 format %{ "cmpq $op1, $op2" %} | |
| 12035 opcode(0x81, 0x07); /* Opcode 81 /7 */ | |
| 12036 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2)); | |
| 12037 ins_pipe(ialu_cr_reg_imm); | |
| 12038 %} | |
| 12039 | |
| 12040 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2) | |
| 12041 %{ | |
| 12042 match(Set cr (CmpL op1 (LoadL op2))); | |
| 12043 | |
| 12044 format %{ "cmpq $op1, $op2" %} | |
| 12045 opcode(0x3B); /* Opcode 3B /r */ | |
| 12046 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2)); | |
| 12047 ins_pipe(ialu_cr_reg_mem); | |
| 12048 %} | |
| 12049 | |
| 12050 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero) | |
| 12051 %{ | |
| 12052 match(Set cr (CmpL src zero)); | |
| 12053 | |
| 12054 format %{ "testq $src, $src" %} | |
| 12055 opcode(0x85); | |
| 12056 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src)); | |
| 12057 ins_pipe(ialu_cr_reg_imm); | |
| 12058 %} | |
| 12059 | |
| 12060 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero) | |
| 12061 %{ | |
| 12062 match(Set cr (CmpL (AndL src con) zero)); | |
| 12063 | |
| 12064 format %{ "testq $src, $con\t# long" %} | |
| 12065 opcode(0xF7, 0x00); | |
| 12066 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con)); | |
| 12067 ins_pipe(ialu_cr_reg_imm); | |
| 12068 %} | |
| 12069 | |
| 12070 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero) | |
| 12071 %{ | |
| 12072 match(Set cr (CmpL (AndL src (LoadL mem)) zero)); | |
| 12073 | |
| 12074 format %{ "testq $src, $mem" %} | |
| 12075 opcode(0x85); | |
| 12076 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem)); | |
| 12077 ins_pipe(ialu_cr_reg_mem); | |
| 12078 %} | |
| 12079 | |
| 12080 // Manifest a CmpL result in an integer register. Very painful. | |
| 12081 // This is the test to avoid. | |
| 12082 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags) | |
| 12083 %{ | |
| 12084 match(Set dst (CmpL3 src1 src2)); | |
| 12085 effect(KILL flags); | |
| 12086 | |
| 12087 ins_cost(275); // XXX | |
| 12088 format %{ "cmpq $src1, $src2\t# CmpL3\n\t" | |
| 12089 "movl $dst, -1\n\t" | |
| 12090 "jl,s done\n\t" | |
| 12091 "setne $dst\n\t" | |
| 12092 "movzbl $dst, $dst\n\t" | |
| 12093 "done:" %} | |
| 12094 ins_encode(cmpl3_flag(src1, src2, dst)); | |
| 12095 ins_pipe(pipe_slow); | |
| 12096 %} | |
| 12097 | |
| 12098 //----------Max and Min-------------------------------------------------------- | |
| 12099 // Min Instructions | |
| 12100 | |
| 12101 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr) | |
| 12102 %{ | |
| 12103 effect(USE_DEF dst, USE src, USE cr); | |
| 12104 | |
| 12105 format %{ "cmovlgt $dst, $src\t# min" %} | |
| 12106 opcode(0x0F, 0x4F); | |
| 12107 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 12108 ins_pipe(pipe_cmov_reg); | |
| 12109 %} | |
| 12110 | |
| 12111 | |
| 12112 instruct minI_rReg(rRegI dst, rRegI src) | |
| 12113 %{ | |
| 12114 match(Set dst (MinI dst src)); | |
| 12115 | |
| 12116 ins_cost(200); | |
| 12117 expand %{ | |
| 12118 rFlagsReg cr; | |
| 12119 compI_rReg(cr, dst, src); | |
| 12120 cmovI_reg_g(dst, src, cr); | |
| 12121 %} | |
| 12122 %} | |
| 12123 | |
| 12124 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr) | |
| 12125 %{ | |
| 12126 effect(USE_DEF dst, USE src, USE cr); | |
| 12127 | |
| 12128 format %{ "cmovllt $dst, $src\t# max" %} | |
| 12129 opcode(0x0F, 0x4C); | |
| 12130 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src)); | |
| 12131 ins_pipe(pipe_cmov_reg); | |
| 12132 %} | |
| 12133 | |
| 12134 | |
| 12135 instruct maxI_rReg(rRegI dst, rRegI src) | |
| 12136 %{ | |
| 12137 match(Set dst (MaxI dst src)); | |
| 12138 | |
| 12139 ins_cost(200); | |
| 12140 expand %{ | |
| 12141 rFlagsReg cr; | |
| 12142 compI_rReg(cr, dst, src); | |
| 12143 cmovI_reg_l(dst, src, cr); | |
| 12144 %} | |
| 12145 %} | |
| 12146 | |
| 12147 // ============================================================================ | |
| 12148 // Branch Instructions | |
| 12149 | |
| 12150 // Jump Direct - Label defines a relative address from JMP+1 | |
| 12151 instruct jmpDir(label labl) | |
| 12152 %{ | |
| 12153 match(Goto); | |
| 12154 effect(USE labl); | |
| 12155 | |
| 12156 ins_cost(300); | |
| 12157 format %{ "jmp $labl" %} | |
| 12158 size(5); | |
| 12159 opcode(0xE9); | |
| 12160 ins_encode(OpcP, Lbl(labl)); | |
| 12161 ins_pipe(pipe_jmp); | |
| 12162 ins_pc_relative(1); | |
| 12163 %} | |
| 12164 | |
| 12165 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12166 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl) | |
| 12167 %{ | |
| 12168 match(If cop cr); | |
| 12169 effect(USE labl); | |
| 12170 | |
| 12171 ins_cost(300); | |
| 12172 format %{ "j$cop $labl" %} | |
| 12173 size(6); | |
| 12174 opcode(0x0F, 0x80); | |
| 12175 ins_encode(Jcc(cop, labl)); | |
| 12176 ins_pipe(pipe_jcc); | |
| 12177 ins_pc_relative(1); | |
| 12178 %} | |
| 12179 | |
| 12180 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
| 12181 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl) | |
| 12182 %{ | |
| 12183 match(CountedLoopEnd cop cr); | |
| 12184 effect(USE labl); | |
| 12185 | |
| 12186 ins_cost(300); | |
| 12187 format %{ "j$cop $labl\t# loop end" %} | |
| 12188 size(6); | |
| 12189 opcode(0x0F, 0x80); | |
| 12190 ins_encode(Jcc(cop, labl)); | |
| 12191 ins_pipe(pipe_jcc); | |
| 12192 ins_pc_relative(1); | |
| 12193 %} | |
| 12194 | |
| 12195 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
415
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|
12196 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 12197 match(CountedLoopEnd cop cmp); |
| 12198 effect(USE labl); | |
| 12199 | |
| 12200 ins_cost(300); | |
| 12201 format %{ "j$cop,u $labl\t# loop end" %} | |
| 12202 size(6); | |
| 12203 opcode(0x0F, 0x80); | |
| 12204 ins_encode(Jcc(cop, labl)); | |
| 12205 ins_pipe(pipe_jcc); | |
| 12206 ins_pc_relative(1); | |
| 12207 %} | |
| 12208 | |
|
415
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parents:
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diff
changeset
|
12209 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
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diff
changeset
|
12210 match(CountedLoopEnd cop cmp); |
|
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changeset
|
12211 effect(USE labl); |
|
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diff
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|
12212 |
|
4d9884b01ba6
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changeset
|
12213 ins_cost(200); |
|
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diff
changeset
|
12214 format %{ "j$cop,u $labl\t# loop end" %} |
|
4d9884b01ba6
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diff
changeset
|
12215 size(6); |
|
4d9884b01ba6
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diff
changeset
|
12216 opcode(0x0F, 0x80); |
|
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diff
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|
12217 ins_encode(Jcc(cop, labl)); |
|
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diff
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|
12218 ins_pipe(pipe_jcc); |
|
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parents:
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diff
changeset
|
12219 ins_pc_relative(1); |
|
4d9884b01ba6
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diff
changeset
|
12220 %} |
|
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diff
changeset
|
12221 |
| 0 | 12222 // Jump Direct Conditional - using unsigned comparison |
|
415
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|
12223 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
| 0 | 12224 match(If cop cmp); |
| 12225 effect(USE labl); | |
| 12226 | |
| 12227 ins_cost(300); | |
|
415
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diff
changeset
|
12228 format %{ "j$cop,u $labl" %} |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
12229 size(6); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
12230 opcode(0x0F, 0x80); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
12231 ins_encode(Jcc(cop, labl)); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
12232 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
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diff
changeset
|
12233 ins_pc_relative(1); |
|
4d9884b01ba6
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diff
changeset
|
12234 %} |
|
4d9884b01ba6
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parents:
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diff
changeset
|
12235 |
|
4d9884b01ba6
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diff
changeset
|
12236 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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diff
changeset
|
12237 match(If cop cmp); |
|
4d9884b01ba6
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diff
changeset
|
12238 effect(USE labl); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
12239 |
|
4d9884b01ba6
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diff
changeset
|
12240 ins_cost(200); |
|
4d9884b01ba6
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diff
changeset
|
12241 format %{ "j$cop,u $labl" %} |
| 0 | 12242 size(6); |
| 12243 opcode(0x0F, 0x80); | |
| 12244 ins_encode(Jcc(cop, labl)); | |
| 12245 ins_pipe(pipe_jcc); | |
| 12246 ins_pc_relative(1); | |
| 12247 %} | |
| 12248 | |
|
415
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diff
changeset
|
12249 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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diff
changeset
|
12250 match(If cop cmp); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
12251 effect(USE labl); |
|
4d9884b01ba6
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parents:
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diff
changeset
|
12252 |
|
4d9884b01ba6
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never
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diff
changeset
|
12253 ins_cost(200); |
|
4d9884b01ba6
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parents:
403
diff
changeset
|
12254 format %{ $$template |
|
4d9884b01ba6
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never
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diff
changeset
|
12255 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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12256 $$emit$$"jp,u $labl\n\t" |
|
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12257 $$emit$$"j$cop,u $labl" |
|
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|
12258 } else { |
|
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|
12259 $$emit$$"jp,u done\n\t" |
|
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12260 $$emit$$"j$cop,u $labl\n\t" |
|
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12261 $$emit$$"done:" |
|
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|
12262 } |
|
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|
12263 %} |
|
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|
12264 size(12); |
|
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|
12265 opcode(0x0F, 0x80); |
|
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|
12266 ins_encode %{ |
|
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|
12267 Label* l = $labl$$label; |
|
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12268 $$$emit8$primary; |
|
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12269 emit_cc(cbuf, $secondary, Assembler::parity); |
|
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12270 int parity_disp = -1; |
|
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|
12271 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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12272 // the two jumps 6 bytes apart so the jump distances are too |
| 1748 | 12273 parity_disp = l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0; |
|
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|
12274 } else if ($cop$$cmpcode == Assembler::equal) { |
|
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|
12275 parity_disp = 6; |
|
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|
12276 } else { |
|
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|
12277 ShouldNotReachHere(); |
|
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|
12278 } |
|
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|
12279 emit_d32(cbuf, parity_disp); |
|
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|
12280 $$$emit8$primary; |
|
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|
12281 emit_cc(cbuf, $secondary, $cop$$cmpcode); |
| 1748 | 12282 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 4)) : 0; |
|
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|
12283 emit_d32(cbuf, disp); |
|
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|
12284 %} |
|
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|
12285 ins_pipe(pipe_jcc); |
|
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|
12286 ins_pc_relative(1); |
|
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|
12287 %} |
|
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|
12288 |
| 0 | 12289 // ============================================================================ |
| 12290 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary | |
| 12291 // superklass array for an instance of the superklass. Set a hidden | |
| 12292 // internal cache on a hit (cache is checked with exposed code in | |
| 12293 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The | |
| 12294 // encoding ALSO sets flags. | |
| 12295 | |
| 12296 instruct partialSubtypeCheck(rdi_RegP result, | |
| 12297 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 12298 rFlagsReg cr) | |
| 12299 %{ | |
| 12300 match(Set result (PartialSubtypeCheck sub super)); | |
| 12301 effect(KILL rcx, KILL cr); | |
| 12302 | |
| 12303 ins_cost(1100); // slightly larger than the next version | |
|
644
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|
12304 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t" |
| 0 | 12305 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" |
| 12306 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12307 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t" | |
| 12308 "jne,s miss\t\t# Missed: rdi not-zero\n\t" | |
| 12309 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t" | |
| 12310 "xorq $result, $result\t\t Hit: rdi zero\n\t" | |
| 12311 "miss:\t" %} | |
| 12312 | |
| 12313 opcode(0x1); // Force a XOR of RDI | |
| 12314 ins_encode(enc_PartialSubtypeCheck()); | |
| 12315 ins_pipe(pipe_slow); | |
| 12316 %} | |
| 12317 | |
| 12318 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr, | |
| 12319 rsi_RegP sub, rax_RegP super, rcx_RegI rcx, | |
| 12320 immP0 zero, | |
| 12321 rdi_RegP result) | |
| 12322 %{ | |
| 12323 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); | |
| 12324 effect(KILL rcx, KILL result); | |
| 12325 | |
| 12326 ins_cost(1000); | |
|
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|
12327 format %{ "movq rdi, [$sub + (sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())]\n\t" |
| 0 | 12328 "movl rcx, [rdi + arrayOopDesc::length_offset_in_bytes()]\t# length to scan\n\t" |
| 12329 "addq rdi, arrayOopDex::base_offset_in_bytes(T_OBJECT)\t# Skip to start of data; set NZ in case count is zero\n\t" | |
| 12330 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t" | |
| 12331 "jne,s miss\t\t# Missed: flags nz\n\t" | |
| 12332 "movq [$sub + (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes())], $super\t# Hit: update cache\n\t" | |
| 12333 "miss:\t" %} | |
| 12334 | |
| 12335 opcode(0x0); // No need to XOR RDI | |
| 12336 ins_encode(enc_PartialSubtypeCheck()); | |
| 12337 ins_pipe(pipe_slow); | |
| 12338 %} | |
| 12339 | |
| 12340 // ============================================================================ | |
| 12341 // Branch Instructions -- short offset versions | |
| 12342 // | |
| 12343 // These instructions are used to replace jumps of a long offset (the default | |
| 12344 // match) with jumps of a shorter offset. These instructions are all tagged | |
| 12345 // with the ins_short_branch attribute, which causes the ADLC to suppress the | |
| 12346 // match rules in general matching. Instead, the ADLC generates a conversion | |
| 12347 // method in the MachNode which can be used to do in-place replacement of the | |
| 12348 // long variant with the shorter variant. The compiler will determine if a | |
| 12349 // branch can be taken by the is_short_branch_offset() predicate in the machine | |
| 12350 // specific code section of the file. | |
| 12351 | |
| 12352 // Jump Direct - Label defines a relative address from JMP+1 | |
|
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|
12353 instruct jmpDir_short(label labl) %{ |
| 0 | 12354 match(Goto); |
| 12355 effect(USE labl); | |
| 12356 | |
| 12357 ins_cost(300); | |
| 12358 format %{ "jmp,s $labl" %} | |
| 12359 size(2); | |
| 12360 opcode(0xEB); | |
| 12361 ins_encode(OpcP, LblShort(labl)); | |
| 12362 ins_pipe(pipe_jmp); | |
| 12363 ins_pc_relative(1); | |
| 12364 ins_short_branch(1); | |
| 12365 %} | |
| 12366 | |
| 12367 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
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|
12368 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 12369 match(If cop cr); |
| 12370 effect(USE labl); | |
| 12371 | |
| 12372 ins_cost(300); | |
| 12373 format %{ "j$cop,s $labl" %} | |
| 12374 size(2); | |
| 12375 opcode(0x70); | |
| 12376 ins_encode(JccShort(cop, labl)); | |
| 12377 ins_pipe(pipe_jcc); | |
| 12378 ins_pc_relative(1); | |
| 12379 ins_short_branch(1); | |
| 12380 %} | |
| 12381 | |
| 12382 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
415
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|
12383 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{ |
| 0 | 12384 match(CountedLoopEnd cop cr); |
| 12385 effect(USE labl); | |
| 12386 | |
| 12387 ins_cost(300); | |
|
415
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|
12388 format %{ "j$cop,s $labl\t# loop end" %} |
| 0 | 12389 size(2); |
| 12390 opcode(0x70); | |
| 12391 ins_encode(JccShort(cop, labl)); | |
| 12392 ins_pipe(pipe_jcc); | |
| 12393 ins_pc_relative(1); | |
| 12394 ins_short_branch(1); | |
| 12395 %} | |
| 12396 | |
| 12397 // Jump Direct Conditional - Label defines a relative address from Jcc+1 | |
|
415
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|
12398 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
12399 match(CountedLoopEnd cop cmp); |
|
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|
12400 effect(USE labl); |
|
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|
12401 |
|
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|
12402 ins_cost(300); |
|
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|
12403 format %{ "j$cop,us $labl\t# loop end" %} |
|
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|
12404 size(2); |
|
4d9884b01ba6
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changeset
|
12405 opcode(0x70); |
|
4d9884b01ba6
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|
12406 ins_encode(JccShort(cop, labl)); |
|
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parents:
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|
12407 ins_pipe(pipe_jcc); |
|
4d9884b01ba6
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|
12408 ins_pc_relative(1); |
|
4d9884b01ba6
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diff
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|
12409 ins_short_branch(1); |
|
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diff
changeset
|
12410 %} |
|
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changeset
|
12411 |
|
4d9884b01ba6
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changeset
|
12412 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 12413 match(CountedLoopEnd cop cmp); |
| 12414 effect(USE labl); | |
| 12415 | |
| 12416 ins_cost(300); | |
|
415
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|
12417 format %{ "j$cop,us $labl\t# loop end" %} |
|
4d9884b01ba6
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parents:
403
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changeset
|
12418 size(2); |
|
4d9884b01ba6
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changeset
|
12419 opcode(0x70); |
|
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|
12420 ins_encode(JccShort(cop, labl)); |
|
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|
12421 ins_pipe(pipe_jcc); |
|
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|
12422 ins_pc_relative(1); |
|
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|
12423 ins_short_branch(1); |
|
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diff
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|
12424 %} |
|
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|
12425 |
|
4d9884b01ba6
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changeset
|
12426 // Jump Direct Conditional - using unsigned comparison |
|
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|
12427 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{ |
|
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|
12428 match(If cop cmp); |
|
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|
12429 effect(USE labl); |
|
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|
12430 |
|
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|
12431 ins_cost(300); |
| 0 | 12432 format %{ "j$cop,us $labl" %} |
| 12433 size(2); | |
| 12434 opcode(0x70); | |
| 12435 ins_encode(JccShort(cop, labl)); | |
| 12436 ins_pipe(pipe_jcc); | |
| 12437 ins_pc_relative(1); | |
| 12438 ins_short_branch(1); | |
| 12439 %} | |
| 12440 | |
|
415
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|
12441 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{ |
| 0 | 12442 match(If cop cmp); |
| 12443 effect(USE labl); | |
| 12444 | |
| 12445 ins_cost(300); | |
| 12446 format %{ "j$cop,us $labl" %} | |
| 12447 size(2); | |
| 12448 opcode(0x70); | |
| 12449 ins_encode(JccShort(cop, labl)); | |
| 12450 ins_pipe(pipe_jcc); | |
| 12451 ins_pc_relative(1); | |
| 12452 ins_short_branch(1); | |
| 12453 %} | |
| 12454 | |
|
415
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|
12455 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{ |
|
4d9884b01ba6
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|
12456 match(If cop cmp); |
|
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|
12457 effect(USE labl); |
|
4d9884b01ba6
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changeset
|
12458 |
|
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changeset
|
12459 ins_cost(300); |
|
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diff
changeset
|
12460 format %{ $$template |
|
4d9884b01ba6
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|
12461 if ($cop$$cmpcode == Assembler::notEqual) { |
|
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|
12462 $$emit$$"jp,u,s $labl\n\t" |
|
4d9884b01ba6
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|
12463 $$emit$$"j$cop,u,s $labl" |
|
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|
12464 } else { |
|
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|
12465 $$emit$$"jp,u,s done\n\t" |
|
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|
12466 $$emit$$"j$cop,u,s $labl\n\t" |
|
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|
12467 $$emit$$"done:" |
|
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|
12468 } |
|
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|
12469 %} |
|
4d9884b01ba6
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403
diff
changeset
|
12470 size(4); |
|
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|
12471 opcode(0x70); |
|
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diff
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|
12472 ins_encode %{ |
|
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diff
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|
12473 Label* l = $labl$$label; |
|
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|
12474 emit_cc(cbuf, $primary, Assembler::parity); |
|
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|
12475 int parity_disp = -1; |
|
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|
12476 if ($cop$$cmpcode == Assembler::notEqual) { |
| 1748 | 12477 parity_disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0; |
|
415
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|
12478 } else if ($cop$$cmpcode == Assembler::equal) { |
|
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|
12479 parity_disp = 2; |
|
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diff
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|
12480 } else { |
|
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diff
changeset
|
12481 ShouldNotReachHere(); |
|
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diff
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|
12482 } |
|
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|
12483 emit_d8(cbuf, parity_disp); |
|
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|
12484 emit_cc(cbuf, $primary, $cop$$cmpcode); |
| 1748 | 12485 int disp = l ? (l->loc_pos() - (cbuf.insts_size() + 1)) : 0; |
|
415
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|
12486 emit_d8(cbuf, disp); |
|
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|
12487 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); |
|
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|
12488 assert(-128 <= parity_disp && parity_disp <= 127, "Displacement too large for short jmp"); |
|
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|
12489 %} |
|
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diff
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|
12490 ins_pipe(pipe_jcc); |
|
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diff
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|
12491 ins_pc_relative(1); |
|
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diff
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|
12492 ins_short_branch(1); |
|
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|
12493 %} |
|
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|
12494 |
| 0 | 12495 // ============================================================================ |
| 12496 // inlined locking and unlocking | |
| 12497 | |
| 12498 instruct cmpFastLock(rFlagsReg cr, | |
| 12499 rRegP object, rRegP box, rax_RegI tmp, rRegP scr) | |
| 12500 %{ | |
| 12501 match(Set cr (FastLock object box)); | |
| 12502 effect(TEMP tmp, TEMP scr); | |
| 12503 | |
| 12504 ins_cost(300); | |
| 12505 format %{ "fastlock $object,$box,$tmp,$scr" %} | |
| 12506 ins_encode(Fast_Lock(object, box, tmp, scr)); | |
| 12507 ins_pipe(pipe_slow); | |
| 12508 ins_pc_relative(1); | |
| 12509 %} | |
| 12510 | |
| 12511 instruct cmpFastUnlock(rFlagsReg cr, | |
| 12512 rRegP object, rax_RegP box, rRegP tmp) | |
| 12513 %{ | |
| 12514 match(Set cr (FastUnlock object box)); | |
| 12515 effect(TEMP tmp); | |
| 12516 | |
| 12517 ins_cost(300); | |
| 12518 format %{ "fastunlock $object, $box, $tmp" %} | |
| 12519 ins_encode(Fast_Unlock(object, box, tmp)); | |
| 12520 ins_pipe(pipe_slow); | |
| 12521 ins_pc_relative(1); | |
| 12522 %} | |
| 12523 | |
| 12524 | |
| 12525 // ============================================================================ | |
| 12526 // Safepoint Instructions | |
| 12527 instruct safePoint_poll(rFlagsReg cr) | |
| 12528 %{ | |
| 12529 match(SafePoint); | |
| 12530 effect(KILL cr); | |
| 12531 | |
| 12532 format %{ "testl rax, [rip + #offset_to_poll_page]\t" | |
| 12533 "# Safepoint: poll for GC" %} | |
| 12534 size(6); // Opcode + ModRM + Disp32 == 6 bytes | |
| 12535 ins_cost(125); | |
| 12536 ins_encode(enc_safepoint_poll); | |
| 12537 ins_pipe(ialu_reg_mem); | |
| 12538 %} | |
| 12539 | |
| 12540 // ============================================================================ | |
| 12541 // Procedure Call/Return Instructions | |
| 12542 // Call Java Static Instruction | |
| 12543 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12544 // compute_padding() functions will have to be adjusted. | |
|
1137
97125851f396
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|
12545 instruct CallStaticJavaDirect(method meth) %{ |
| 0 | 12546 match(CallStaticJava); |
|
1137
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diff
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|
12547 predicate(!((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
| 0 | 12548 effect(USE meth); |
| 12549 | |
| 12550 ins_cost(300); | |
| 12551 format %{ "call,static " %} | |
| 12552 opcode(0xE8); /* E8 cd */ | |
| 12553 ins_encode(Java_Static_Call(meth), call_epilog); | |
| 12554 ins_pipe(pipe_slow); | |
| 12555 ins_pc_relative(1); | |
| 12556 ins_alignment(4); | |
| 12557 %} | |
| 12558 | |
|
1137
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|
12559 // Call Java Static Instruction (method handle version) |
|
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diff
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|
12560 // Note: If this code changes, the corresponding ret_addr_offset() and |
|
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diff
changeset
|
12561 // compute_padding() functions will have to be adjusted. |
| 1567 | 12562 instruct CallStaticJavaHandle(method meth, rbp_RegP rbp_mh_SP_save) %{ |
|
1137
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|
12563 match(CallStaticJava); |
|
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diff
changeset
|
12564 predicate(((CallStaticJavaNode*) n)->is_method_handle_invoke()); |
|
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diff
changeset
|
12565 effect(USE meth); |
|
97125851f396
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parents:
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diff
changeset
|
12566 // RBP is saved by all callees (for interpreter stack correction). |
|
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diff
changeset
|
12567 // We use it here for a similar purpose, in {preserve,restore}_SP. |
|
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diff
changeset
|
12568 |
|
97125851f396
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diff
changeset
|
12569 ins_cost(300); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
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parents:
989
diff
changeset
|
12570 format %{ "call,static/MethodHandle " %} |
|
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parents:
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diff
changeset
|
12571 opcode(0xE8); /* E8 cd */ |
|
97125851f396
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parents:
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diff
changeset
|
12572 ins_encode(preserve_SP, |
|
97125851f396
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parents:
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diff
changeset
|
12573 Java_Static_Call(meth), |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
989
diff
changeset
|
12574 restore_SP, |
|
97125851f396
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diff
changeset
|
12575 call_epilog); |
|
97125851f396
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twisti
parents:
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diff
changeset
|
12576 ins_pipe(pipe_slow); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
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parents:
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diff
changeset
|
12577 ins_pc_relative(1); |
|
97125851f396
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diff
changeset
|
12578 ins_alignment(4); |
|
97125851f396
6829187: compiler optimizations required for JSR 292
twisti
parents:
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diff
changeset
|
12579 %} |
|
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diff
changeset
|
12580 |
| 0 | 12581 // Call Java Dynamic Instruction |
| 12582 // Note: If this code changes, the corresponding ret_addr_offset() and | |
| 12583 // compute_padding() functions will have to be adjusted. | |
| 12584 instruct CallDynamicJavaDirect(method meth) | |
| 12585 %{ | |
| 12586 match(CallDynamicJava); | |
| 12587 effect(USE meth); | |
| 12588 | |
| 12589 ins_cost(300); | |
| 12590 format %{ "movq rax, #Universe::non_oop_word()\n\t" | |
| 12591 "call,dynamic " %} | |
| 12592 opcode(0xE8); /* E8 cd */ | |
| 12593 ins_encode(Java_Dynamic_Call(meth), call_epilog); | |
| 12594 ins_pipe(pipe_slow); | |
| 12595 ins_pc_relative(1); | |
| 12596 ins_alignment(4); | |
| 12597 %} | |
| 12598 | |
| 12599 // Call Runtime Instruction | |
| 12600 instruct CallRuntimeDirect(method meth) | |
| 12601 %{ | |
| 12602 match(CallRuntime); | |
| 12603 effect(USE meth); | |
| 12604 | |
| 12605 ins_cost(300); | |
| 12606 format %{ "call,runtime " %} | |
| 12607 opcode(0xE8); /* E8 cd */ | |
| 12608 ins_encode(Java_To_Runtime(meth)); | |
| 12609 ins_pipe(pipe_slow); | |
| 12610 ins_pc_relative(1); | |
| 12611 %} | |
| 12612 | |
| 12613 // Call runtime without safepoint | |
| 12614 instruct CallLeafDirect(method meth) | |
| 12615 %{ | |
| 12616 match(CallLeaf); | |
| 12617 effect(USE meth); | |
| 12618 | |
| 12619 ins_cost(300); | |
| 12620 format %{ "call_leaf,runtime " %} | |
| 12621 opcode(0xE8); /* E8 cd */ | |
| 12622 ins_encode(Java_To_Runtime(meth)); | |
| 12623 ins_pipe(pipe_slow); | |
| 12624 ins_pc_relative(1); | |
| 12625 %} | |
| 12626 | |
| 12627 // Call runtime without safepoint | |
| 12628 instruct CallLeafNoFPDirect(method meth) | |
| 12629 %{ | |
| 12630 match(CallLeafNoFP); | |
| 12631 effect(USE meth); | |
| 12632 | |
| 12633 ins_cost(300); | |
| 12634 format %{ "call_leaf_nofp,runtime " %} | |
| 12635 opcode(0xE8); /* E8 cd */ | |
| 12636 ins_encode(Java_To_Runtime(meth)); | |
| 12637 ins_pipe(pipe_slow); | |
| 12638 ins_pc_relative(1); | |
| 12639 %} | |
| 12640 | |
| 12641 // Return Instruction | |
| 12642 // Remove the return address & jump to it. | |
| 12643 // Notice: We always emit a nop after a ret to make sure there is room | |
| 12644 // for safepoint patching | |
| 12645 instruct Ret() | |
| 12646 %{ | |
| 12647 match(Return); | |
| 12648 | |
| 12649 format %{ "ret" %} | |
| 12650 opcode(0xC3); | |
| 12651 ins_encode(OpcP); | |
| 12652 ins_pipe(pipe_jmp); | |
| 12653 %} | |
| 12654 | |
| 12655 // Tail Call; Jump from runtime stub to Java code. | |
| 12656 // Also known as an 'interprocedural jump'. | |
| 12657 // Target of jump will eventually return to caller. | |
| 12658 // TailJump below removes the return address. | |
| 12659 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop) | |
| 12660 %{ | |
| 12661 match(TailCall jump_target method_oop); | |
| 12662 | |
| 12663 ins_cost(300); | |
| 12664 format %{ "jmp $jump_target\t# rbx holds method oop" %} | |
| 12665 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12666 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 12667 ins_pipe(pipe_jmp); | |
| 12668 %} | |
| 12669 | |
| 12670 // Tail Jump; remove the return address; jump to target. | |
| 12671 // TailCall above leaves the return address around. | |
| 12672 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop) | |
| 12673 %{ | |
| 12674 match(TailJump jump_target ex_oop); | |
| 12675 | |
| 12676 ins_cost(300); | |
| 12677 format %{ "popq rdx\t# pop return address\n\t" | |
| 12678 "jmp $jump_target" %} | |
| 12679 opcode(0xFF, 0x4); /* Opcode FF /4 */ | |
| 12680 ins_encode(Opcode(0x5a), // popq rdx | |
| 12681 REX_reg(jump_target), OpcP, reg_opc(jump_target)); | |
| 12682 ins_pipe(pipe_jmp); | |
| 12683 %} | |
| 12684 | |
| 12685 // Create exception oop: created by stack-crawling runtime code. | |
| 12686 // Created exception is now available to this handler, and is setup | |
| 12687 // just prior to jumping to this handler. No code emitted. | |
| 12688 instruct CreateException(rax_RegP ex_oop) | |
| 12689 %{ | |
| 12690 match(Set ex_oop (CreateEx)); | |
| 12691 | |
| 12692 size(0); | |
| 12693 // use the following format syntax | |
| 12694 format %{ "# exception oop is in rax; no code emitted" %} | |
| 12695 ins_encode(); | |
| 12696 ins_pipe(empty); | |
| 12697 %} | |
| 12698 | |
| 12699 // Rethrow exception: | |
| 12700 // The exception oop will come in the first argument position. | |
| 12701 // Then JUMP (not call) to the rethrow stub code. | |
| 12702 instruct RethrowException() | |
| 12703 %{ | |
| 12704 match(Rethrow); | |
| 12705 | |
| 12706 // use the following format syntax | |
| 12707 format %{ "jmp rethrow_stub" %} | |
| 12708 ins_encode(enc_rethrow); | |
| 12709 ins_pipe(pipe_jmp); | |
| 12710 %} | |
| 12711 | |
| 12712 | |
| 12713 //----------PEEPHOLE RULES----------------------------------------------------- | |
| 12714 // These must follow all instruction definitions as they use the names | |
| 12715 // defined in the instructions definitions. | |
| 12716 // | |
| 605 | 12717 // peepmatch ( root_instr_name [preceding_instruction]* ); |
| 0 | 12718 // |
| 12719 // peepconstraint %{ | |
| 12720 // (instruction_number.operand_name relational_op instruction_number.operand_name | |
| 12721 // [, ...] ); | |
| 12722 // // instruction numbers are zero-based using left to right order in peepmatch | |
| 12723 // | |
| 12724 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); | |
| 12725 // // provide an instruction_number.operand_name for each operand that appears | |
| 12726 // // in the replacement instruction's match rule | |
| 12727 // | |
| 12728 // ---------VM FLAGS--------------------------------------------------------- | |
| 12729 // | |
| 12730 // All peephole optimizations can be turned off using -XX:-OptoPeephole | |
| 12731 // | |
| 12732 // Each peephole rule is given an identifying number starting with zero and | |
| 12733 // increasing by one in the order seen by the parser. An individual peephole | |
| 12734 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# | |
| 12735 // on the command-line. | |
| 12736 // | |
| 12737 // ---------CURRENT LIMITATIONS---------------------------------------------- | |
| 12738 // | |
| 12739 // Only match adjacent instructions in same basic block | |
| 12740 // Only equality constraints | |
| 12741 // Only constraints between operands, not (0.dest_reg == RAX_enc) | |
| 12742 // Only one replacement instruction | |
| 12743 // | |
| 12744 // ---------EXAMPLE---------------------------------------------------------- | |
| 12745 // | |
| 12746 // // pertinent parts of existing instructions in architecture description | |
| 12747 // instruct movI(rRegI dst, rRegI src) | |
| 12748 // %{ | |
| 12749 // match(Set dst (CopyI src)); | |
| 12750 // %} | |
| 12751 // | |
| 12752 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr) | |
| 12753 // %{ | |
| 12754 // match(Set dst (AddI dst src)); | |
| 12755 // effect(KILL cr); | |
| 12756 // %} | |
| 12757 // | |
| 12758 // // Change (inc mov) to lea | |
| 12759 // peephole %{ | |
| 12760 // // increment preceeded by register-register move | |
| 12761 // peepmatch ( incI_rReg movI ); | |
| 12762 // // require that the destination register of the increment | |
| 12763 // // match the destination register of the move | |
| 12764 // peepconstraint ( 0.dst == 1.dst ); | |
| 12765 // // construct a replacement instruction that sets | |
| 12766 // // the destination to ( move's source register + one ) | |
| 12767 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) ); | |
| 12768 // %} | |
| 12769 // | |
| 12770 | |
| 12771 // Implementation no longer uses movX instructions since | |
| 12772 // machine-independent system no longer uses CopyX nodes. | |
| 12773 // | |
| 12774 // peephole | |
| 12775 // %{ | |
| 12776 // peepmatch (incI_rReg movI); | |
| 12777 // peepconstraint (0.dst == 1.dst); | |
| 12778 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 12779 // %} | |
| 12780 | |
| 12781 // peephole | |
| 12782 // %{ | |
| 12783 // peepmatch (decI_rReg movI); | |
| 12784 // peepconstraint (0.dst == 1.dst); | |
| 12785 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 12786 // %} | |
| 12787 | |
| 12788 // peephole | |
| 12789 // %{ | |
| 12790 // peepmatch (addI_rReg_imm movI); | |
| 12791 // peepconstraint (0.dst == 1.dst); | |
| 12792 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src)); | |
| 12793 // %} | |
| 12794 | |
| 12795 // peephole | |
| 12796 // %{ | |
| 12797 // peepmatch (incL_rReg movL); | |
| 12798 // peepconstraint (0.dst == 1.dst); | |
| 12799 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 12800 // %} | |
| 12801 | |
| 12802 // peephole | |
| 12803 // %{ | |
| 12804 // peepmatch (decL_rReg movL); | |
| 12805 // peepconstraint (0.dst == 1.dst); | |
| 12806 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 12807 // %} | |
| 12808 | |
| 12809 // peephole | |
| 12810 // %{ | |
| 12811 // peepmatch (addL_rReg_imm movL); | |
| 12812 // peepconstraint (0.dst == 1.dst); | |
| 12813 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src)); | |
| 12814 // %} | |
| 12815 | |
| 12816 // peephole | |
| 12817 // %{ | |
| 12818 // peepmatch (addP_rReg_imm movP); | |
| 12819 // peepconstraint (0.dst == 1.dst); | |
| 12820 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src)); | |
| 12821 // %} | |
| 12822 | |
| 12823 // // Change load of spilled value to only a spill | |
| 12824 // instruct storeI(memory mem, rRegI src) | |
| 12825 // %{ | |
| 12826 // match(Set mem (StoreI mem src)); | |
| 12827 // %} | |
| 12828 // | |
| 12829 // instruct loadI(rRegI dst, memory mem) | |
| 12830 // %{ | |
| 12831 // match(Set dst (LoadI mem)); | |
| 12832 // %} | |
| 12833 // | |
| 12834 | |
| 12835 peephole | |
| 12836 %{ | |
| 12837 peepmatch (loadI storeI); | |
| 12838 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 12839 peepreplace (storeI(1.mem 1.mem 1.src)); | |
| 12840 %} | |
| 12841 | |
| 12842 peephole | |
| 12843 %{ | |
| 12844 peepmatch (loadL storeL); | |
| 12845 peepconstraint (1.src == 0.dst, 1.mem == 0.mem); | |
| 12846 peepreplace (storeL(1.mem 1.mem 1.src)); | |
| 12847 %} | |
| 12848 | |
| 12849 //----------SMARTSPILL RULES--------------------------------------------------- | |
| 12850 // These must follow all instruction definitions as they use the names | |
| 12851 // defined in the instructions definitions. |