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annotate src/os_cpu/windows_x86/vm/orderAccess_windows_x86.inline.hpp @ 2057:89bf01e6b049
Treat C1XOptions fields as final.
author | Thomas Wuerthinger <wuerthinger@ssw.jku.at> |
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date | Fri, 14 Jan 2011 16:29:42 +0100 |
parents | f95d63e2154a |
children | 4fc084dac61e |
rev | line source |
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0 | 1 /* |
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6973570: OrderAccess::storestore() scales poorly on multi-socket x64 and sparc: cache-line ping-ponging
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2 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP |
26 #define OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP | |
27 | |
28 #include "runtime/orderAccess.hpp" | |
29 #include "vm_version_x86.hpp" | |
30 | |
0 | 31 #pragma warning(disable: 4035) // Disables warnings reporting missing return statement |
32 | |
33 // Implementation of class OrderAccess. | |
34 | |
35 inline void OrderAccess::loadload() { acquire(); } | |
36 inline void OrderAccess::storestore() { release(); } | |
37 inline void OrderAccess::loadstore() { acquire(); } | |
38 inline void OrderAccess::storeload() { fence(); } | |
39 | |
40 inline void OrderAccess::acquire() { | |
41 #ifndef AMD64 | |
42 __asm { | |
43 mov eax, dword ptr [esp]; | |
44 } | |
45 #endif // !AMD64 | |
46 } | |
47 | |
48 inline void OrderAccess::release() { | |
49 // A volatile store has release semantics. | |
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50 volatile jint local_dummy = 0; |
0 | 51 } |
52 | |
53 inline void OrderAccess::fence() { | |
54 #ifdef AMD64 | |
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55 StubRoutines_fence(); |
0 | 56 #else |
57 if (os::is_MP()) { | |
58 __asm { | |
59 lock add dword ptr [esp], 0; | |
60 } | |
61 } | |
62 #endif // AMD64 | |
63 } | |
64 | |
65 inline jbyte OrderAccess::load_acquire(volatile jbyte* p) { return *p; } | |
66 inline jshort OrderAccess::load_acquire(volatile jshort* p) { return *p; } | |
67 inline jint OrderAccess::load_acquire(volatile jint* p) { return *p; } | |
68 inline jlong OrderAccess::load_acquire(volatile jlong* p) { return *p; } | |
69 inline jubyte OrderAccess::load_acquire(volatile jubyte* p) { return *p; } | |
70 inline jushort OrderAccess::load_acquire(volatile jushort* p) { return *p; } | |
71 inline juint OrderAccess::load_acquire(volatile juint* p) { return *p; } | |
72 inline julong OrderAccess::load_acquire(volatile julong* p) { return *p; } | |
73 inline jfloat OrderAccess::load_acquire(volatile jfloat* p) { return *p; } | |
74 inline jdouble OrderAccess::load_acquire(volatile jdouble* p) { return *p; } | |
75 | |
76 inline intptr_t OrderAccess::load_ptr_acquire(volatile intptr_t* p) { return *p; } | |
77 inline void* OrderAccess::load_ptr_acquire(volatile void* p) { return *(void* volatile *)p; } | |
78 inline void* OrderAccess::load_ptr_acquire(const volatile void* p) { return *(void* const volatile *)p; } | |
79 | |
80 inline void OrderAccess::release_store(volatile jbyte* p, jbyte v) { *p = v; } | |
81 inline void OrderAccess::release_store(volatile jshort* p, jshort v) { *p = v; } | |
82 inline void OrderAccess::release_store(volatile jint* p, jint v) { *p = v; } | |
83 inline void OrderAccess::release_store(volatile jlong* p, jlong v) { *p = v; } | |
84 inline void OrderAccess::release_store(volatile jubyte* p, jubyte v) { *p = v; } | |
85 inline void OrderAccess::release_store(volatile jushort* p, jushort v) { *p = v; } | |
86 inline void OrderAccess::release_store(volatile juint* p, juint v) { *p = v; } | |
87 inline void OrderAccess::release_store(volatile julong* p, julong v) { *p = v; } | |
88 inline void OrderAccess::release_store(volatile jfloat* p, jfloat v) { *p = v; } | |
89 inline void OrderAccess::release_store(volatile jdouble* p, jdouble v) { *p = v; } | |
90 | |
91 inline void OrderAccess::release_store_ptr(volatile intptr_t* p, intptr_t v) { *p = v; } | |
92 inline void OrderAccess::release_store_ptr(volatile void* p, void* v) { *(void* volatile *)p = v; } | |
93 | |
94 inline void OrderAccess::store_fence(jbyte* p, jbyte v) { | |
95 #ifdef AMD64 | |
96 *p = v; fence(); | |
97 #else | |
98 __asm { | |
99 mov edx, p; | |
100 mov al, v; | |
101 xchg al, byte ptr [edx]; | |
102 } | |
103 #endif // AMD64 | |
104 } | |
105 | |
106 inline void OrderAccess::store_fence(jshort* p, jshort v) { | |
107 #ifdef AMD64 | |
108 *p = v; fence(); | |
109 #else | |
110 __asm { | |
111 mov edx, p; | |
112 mov ax, v; | |
113 xchg ax, word ptr [edx]; | |
114 } | |
115 #endif // AMD64 | |
116 } | |
117 | |
118 inline void OrderAccess::store_fence(jint* p, jint v) { | |
119 #ifdef AMD64 | |
120 *p = v; fence(); | |
121 #else | |
122 __asm { | |
123 mov edx, p; | |
124 mov eax, v; | |
125 xchg eax, dword ptr [edx]; | |
126 } | |
127 #endif // AMD64 | |
128 } | |
129 | |
130 inline void OrderAccess::store_fence(jlong* p, jlong v) { *p = v; fence(); } | |
131 inline void OrderAccess::store_fence(jubyte* p, jubyte v) { store_fence((jbyte*)p, (jbyte)v); } | |
132 inline void OrderAccess::store_fence(jushort* p, jushort v) { store_fence((jshort*)p, (jshort)v); } | |
133 inline void OrderAccess::store_fence(juint* p, juint v) { store_fence((jint*)p, (jint)v); } | |
134 inline void OrderAccess::store_fence(julong* p, julong v) { store_fence((jlong*)p, (jlong)v); } | |
135 inline void OrderAccess::store_fence(jfloat* p, jfloat v) { *p = v; fence(); } | |
136 inline void OrderAccess::store_fence(jdouble* p, jdouble v) { *p = v; fence(); } | |
137 | |
138 inline void OrderAccess::store_ptr_fence(intptr_t* p, intptr_t v) { | |
139 #ifdef AMD64 | |
140 *p = v; fence(); | |
141 #else | |
142 store_fence((jint*)p, (jint)v); | |
143 #endif // AMD64 | |
144 } | |
145 | |
146 inline void OrderAccess::store_ptr_fence(void** p, void* v) { | |
147 #ifdef AMD64 | |
148 *p = v; fence(); | |
149 #else | |
150 store_fence((jint*)p, (jint)v); | |
151 #endif // AMD64 | |
152 } | |
153 | |
154 // Must duplicate definitions instead of calling store_fence because we don't want to cast away volatile. | |
155 inline void OrderAccess::release_store_fence(volatile jbyte* p, jbyte v) { | |
156 #ifdef AMD64 | |
157 *p = v; fence(); | |
158 #else | |
159 __asm { | |
160 mov edx, p; | |
161 mov al, v; | |
162 xchg al, byte ptr [edx]; | |
163 } | |
164 #endif // AMD64 | |
165 } | |
166 | |
167 inline void OrderAccess::release_store_fence(volatile jshort* p, jshort v) { | |
168 #ifdef AMD64 | |
169 *p = v; fence(); | |
170 #else | |
171 __asm { | |
172 mov edx, p; | |
173 mov ax, v; | |
174 xchg ax, word ptr [edx]; | |
175 } | |
176 #endif // AMD64 | |
177 } | |
178 | |
179 inline void OrderAccess::release_store_fence(volatile jint* p, jint v) { | |
180 #ifdef AMD64 | |
181 *p = v; fence(); | |
182 #else | |
183 __asm { | |
184 mov edx, p; | |
185 mov eax, v; | |
186 xchg eax, dword ptr [edx]; | |
187 } | |
188 #endif // AMD64 | |
189 } | |
190 | |
191 inline void OrderAccess::release_store_fence(volatile jlong* p, jlong v) { *p = v; fence(); } | |
192 | |
193 inline void OrderAccess::release_store_fence(volatile jubyte* p, jubyte v) { release_store_fence((volatile jbyte*)p, (jbyte)v); } | |
194 inline void OrderAccess::release_store_fence(volatile jushort* p, jushort v) { release_store_fence((volatile jshort*)p, (jshort)v); } | |
195 inline void OrderAccess::release_store_fence(volatile juint* p, juint v) { release_store_fence((volatile jint*)p, (jint)v); } | |
196 inline void OrderAccess::release_store_fence(volatile julong* p, julong v) { release_store_fence((volatile jlong*)p, (jlong)v); } | |
197 inline void OrderAccess::release_store_fence(volatile jfloat* p, jfloat v) { *p = v; fence(); } | |
198 inline void OrderAccess::release_store_fence(volatile jdouble* p, jdouble v) { *p = v; fence(); } | |
199 | |
200 inline void OrderAccess::release_store_ptr_fence(volatile intptr_t* p, intptr_t v) { | |
201 #ifdef AMD64 | |
202 *p = v; fence(); | |
203 #else | |
204 release_store_fence((volatile jint*)p, (jint)v); | |
205 #endif // AMD64 | |
206 } | |
207 | |
208 inline void OrderAccess::release_store_ptr_fence(volatile void* p, void* v) { | |
209 #ifdef AMD64 | |
210 *(void* volatile *)p = v; fence(); | |
211 #else | |
212 release_store_fence((volatile jint*)p, (jint)v); | |
213 #endif // AMD64 | |
214 } | |
215 | |
216 #pragma warning(default: 4035) // Enables warnings reporting missing return statement | |
1972 | 217 |
218 #endif // OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP |