Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/c1_FrameMap_sparc.cpp @ 6812:988bf00cc564
7200261: G1: Liveness counting inconsistencies during marking verification
Summary: The clipping code in the routine that sets the bits for a range of cards, in the liveness accounting verification code was incorrect. It set all the bits in the card bitmap from the given starting index which would lead to spurious marking verification failures.
Reviewed-by: brutisso, jwilhelm, jmasa
| author | johnc |
|---|---|
| date | Thu, 27 Sep 2012 15:44:01 -0700 |
| parents | 8a02ca5e5576 |
| children | b9a9ed0f8eeb |
| rev | line source |
|---|---|
| 0 | 1 /* |
| 1579 | 2 * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
|
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #include "precompiled.hpp" |
| 26 #include "c1/c1_FrameMap.hpp" | |
| 27 #include "c1/c1_LIR.hpp" | |
| 28 #include "runtime/sharedRuntime.hpp" | |
| 29 #include "vmreg_sparc.inline.hpp" | |
| 0 | 30 |
| 31 | |
| 32 const int FrameMap::pd_c_runtime_reserved_arg_size = 7; | |
| 33 | |
| 34 | |
| 35 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) { | |
| 36 LIR_Opr opr = LIR_OprFact::illegalOpr; | |
| 37 VMReg r_1 = reg->first(); | |
| 38 VMReg r_2 = reg->second(); | |
| 39 if (r_1->is_stack()) { | |
| 40 // Convert stack slot to an SP offset | |
| 41 // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value | |
| 42 // so we must add it in here. | |
| 43 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; | |
| 44 opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type)); | |
| 45 } else if (r_1->is_Register()) { | |
| 46 Register reg = r_1->as_Register(); | |
| 47 if (outgoing) { | |
| 48 assert(!reg->is_in(), "should be using I regs"); | |
| 49 } else { | |
| 50 assert(!reg->is_out(), "should be using O regs"); | |
| 51 } | |
| 52 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { | |
| 53 opr = as_long_opr(reg); | |
| 54 } else if (type == T_OBJECT || type == T_ARRAY) { | |
| 55 opr = as_oop_opr(reg); | |
| 56 } else { | |
| 57 opr = as_opr(reg); | |
| 58 } | |
| 59 } else if (r_1->is_FloatRegister()) { | |
| 60 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); | |
| 61 FloatRegister f = r_1->as_FloatRegister(); | |
| 62 if (type == T_DOUBLE) { | |
| 63 opr = as_double_opr(f); | |
| 64 } else { | |
| 65 opr = as_float_opr(f); | |
| 66 } | |
| 67 } | |
| 68 return opr; | |
| 69 } | |
| 70 | |
| 71 // FrameMap | |
| 72 //-------------------------------------------------------- | |
| 73 | |
| 74 FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs]; | |
| 75 | |
| 76 // some useful constant RInfo's: | |
| 77 LIR_Opr FrameMap::in_long_opr; | |
| 78 LIR_Opr FrameMap::out_long_opr; | |
| 1783 | 79 LIR_Opr FrameMap::g1_long_single_opr; |
| 0 | 80 |
| 81 LIR_Opr FrameMap::F0_opr; | |
| 82 LIR_Opr FrameMap::F0_double_opr; | |
| 83 | |
| 84 LIR_Opr FrameMap::G0_opr; | |
| 85 LIR_Opr FrameMap::G1_opr; | |
| 86 LIR_Opr FrameMap::G2_opr; | |
| 87 LIR_Opr FrameMap::G3_opr; | |
| 88 LIR_Opr FrameMap::G4_opr; | |
| 89 LIR_Opr FrameMap::G5_opr; | |
| 90 LIR_Opr FrameMap::G6_opr; | |
| 91 LIR_Opr FrameMap::G7_opr; | |
| 92 LIR_Opr FrameMap::O0_opr; | |
| 93 LIR_Opr FrameMap::O1_opr; | |
| 94 LIR_Opr FrameMap::O2_opr; | |
| 95 LIR_Opr FrameMap::O3_opr; | |
| 96 LIR_Opr FrameMap::O4_opr; | |
| 97 LIR_Opr FrameMap::O5_opr; | |
| 98 LIR_Opr FrameMap::O6_opr; | |
| 99 LIR_Opr FrameMap::O7_opr; | |
| 100 LIR_Opr FrameMap::L0_opr; | |
| 101 LIR_Opr FrameMap::L1_opr; | |
| 102 LIR_Opr FrameMap::L2_opr; | |
| 103 LIR_Opr FrameMap::L3_opr; | |
| 104 LIR_Opr FrameMap::L4_opr; | |
| 105 LIR_Opr FrameMap::L5_opr; | |
| 106 LIR_Opr FrameMap::L6_opr; | |
| 107 LIR_Opr FrameMap::L7_opr; | |
| 108 LIR_Opr FrameMap::I0_opr; | |
| 109 LIR_Opr FrameMap::I1_opr; | |
| 110 LIR_Opr FrameMap::I2_opr; | |
| 111 LIR_Opr FrameMap::I3_opr; | |
| 112 LIR_Opr FrameMap::I4_opr; | |
| 113 LIR_Opr FrameMap::I5_opr; | |
| 114 LIR_Opr FrameMap::I6_opr; | |
| 115 LIR_Opr FrameMap::I7_opr; | |
| 116 | |
| 117 LIR_Opr FrameMap::G0_oop_opr; | |
| 118 LIR_Opr FrameMap::G1_oop_opr; | |
| 119 LIR_Opr FrameMap::G2_oop_opr; | |
| 120 LIR_Opr FrameMap::G3_oop_opr; | |
| 121 LIR_Opr FrameMap::G4_oop_opr; | |
| 122 LIR_Opr FrameMap::G5_oop_opr; | |
| 123 LIR_Opr FrameMap::G6_oop_opr; | |
| 124 LIR_Opr FrameMap::G7_oop_opr; | |
| 125 LIR_Opr FrameMap::O0_oop_opr; | |
| 126 LIR_Opr FrameMap::O1_oop_opr; | |
| 127 LIR_Opr FrameMap::O2_oop_opr; | |
| 128 LIR_Opr FrameMap::O3_oop_opr; | |
| 129 LIR_Opr FrameMap::O4_oop_opr; | |
| 130 LIR_Opr FrameMap::O5_oop_opr; | |
| 131 LIR_Opr FrameMap::O6_oop_opr; | |
| 132 LIR_Opr FrameMap::O7_oop_opr; | |
| 133 LIR_Opr FrameMap::L0_oop_opr; | |
| 134 LIR_Opr FrameMap::L1_oop_opr; | |
| 135 LIR_Opr FrameMap::L2_oop_opr; | |
| 136 LIR_Opr FrameMap::L3_oop_opr; | |
| 137 LIR_Opr FrameMap::L4_oop_opr; | |
| 138 LIR_Opr FrameMap::L5_oop_opr; | |
| 139 LIR_Opr FrameMap::L6_oop_opr; | |
| 140 LIR_Opr FrameMap::L7_oop_opr; | |
| 141 LIR_Opr FrameMap::I0_oop_opr; | |
| 142 LIR_Opr FrameMap::I1_oop_opr; | |
| 143 LIR_Opr FrameMap::I2_oop_opr; | |
| 144 LIR_Opr FrameMap::I3_oop_opr; | |
| 145 LIR_Opr FrameMap::I4_oop_opr; | |
| 146 LIR_Opr FrameMap::I5_oop_opr; | |
| 147 LIR_Opr FrameMap::I6_oop_opr; | |
| 148 LIR_Opr FrameMap::I7_oop_opr; | |
| 149 | |
|
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150 LIR_Opr FrameMap::G0_metadata_opr; |
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151 LIR_Opr FrameMap::G1_metadata_opr; |
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152 LIR_Opr FrameMap::G2_metadata_opr; |
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153 LIR_Opr FrameMap::G3_metadata_opr; |
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154 LIR_Opr FrameMap::G4_metadata_opr; |
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155 LIR_Opr FrameMap::G5_metadata_opr; |
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156 LIR_Opr FrameMap::G6_metadata_opr; |
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157 LIR_Opr FrameMap::G7_metadata_opr; |
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158 LIR_Opr FrameMap::O0_metadata_opr; |
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159 LIR_Opr FrameMap::O1_metadata_opr; |
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160 LIR_Opr FrameMap::O2_metadata_opr; |
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161 LIR_Opr FrameMap::O3_metadata_opr; |
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162 LIR_Opr FrameMap::O4_metadata_opr; |
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163 LIR_Opr FrameMap::O5_metadata_opr; |
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164 LIR_Opr FrameMap::O6_metadata_opr; |
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165 LIR_Opr FrameMap::O7_metadata_opr; |
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166 LIR_Opr FrameMap::L0_metadata_opr; |
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167 LIR_Opr FrameMap::L1_metadata_opr; |
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168 LIR_Opr FrameMap::L2_metadata_opr; |
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169 LIR_Opr FrameMap::L3_metadata_opr; |
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170 LIR_Opr FrameMap::L4_metadata_opr; |
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171 LIR_Opr FrameMap::L5_metadata_opr; |
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172 LIR_Opr FrameMap::L6_metadata_opr; |
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173 LIR_Opr FrameMap::L7_metadata_opr; |
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174 LIR_Opr FrameMap::I0_metadata_opr; |
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175 LIR_Opr FrameMap::I1_metadata_opr; |
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176 LIR_Opr FrameMap::I2_metadata_opr; |
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177 LIR_Opr FrameMap::I3_metadata_opr; |
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178 LIR_Opr FrameMap::I4_metadata_opr; |
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179 LIR_Opr FrameMap::I5_metadata_opr; |
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180 LIR_Opr FrameMap::I6_metadata_opr; |
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181 LIR_Opr FrameMap::I7_metadata_opr; |
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182 |
| 0 | 183 LIR_Opr FrameMap::SP_opr; |
| 184 LIR_Opr FrameMap::FP_opr; | |
| 185 | |
| 186 LIR_Opr FrameMap::Oexception_opr; | |
| 187 LIR_Opr FrameMap::Oissuing_pc_opr; | |
| 188 | |
| 189 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; | |
| 190 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; | |
| 191 | |
| 192 | |
| 193 FloatRegister FrameMap::nr2floatreg (int rnr) { | |
| 194 assert(_init_done, "tables not initialized"); | |
| 195 debug_only(fpu_range_check(rnr);) | |
| 196 return _fpu_regs[rnr]; | |
| 197 } | |
| 198 | |
| 199 | |
| 200 // returns true if reg could be smashed by a callee. | |
| 201 bool FrameMap::is_caller_save_register (LIR_Opr reg) { | |
| 202 if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; } | |
| 203 if (reg->is_double_cpu()) { | |
| 204 return is_caller_save_register(reg->as_register_lo()) || | |
| 205 is_caller_save_register(reg->as_register_hi()); | |
| 206 } | |
| 207 return is_caller_save_register(reg->as_register()); | |
| 208 } | |
| 209 | |
| 210 | |
| 211 NEEDS_CLEANUP // once the new calling convention is enabled, we no | |
| 212 // longer need to treat I5, I4 and L0 specially | |
| 213 // Because the interpreter destroys caller's I5, I4 and L0, | |
| 214 // we must spill them before doing a Java call as we may land in | |
| 215 // interpreter. | |
| 216 bool FrameMap::is_caller_save_register (Register r) { | |
| 217 return (r->is_global() && (r != G0)) || r->is_out(); | |
| 218 } | |
| 219 | |
| 220 | |
| 1584 | 221 void FrameMap::initialize() { |
| 222 assert(!_init_done, "once"); | |
| 0 | 223 |
| 224 int i=0; | |
| 225 // Register usage: | |
| 226 // O6: sp | |
| 227 // I6: fp | |
| 228 // I7: return address | |
| 229 // G0: zero | |
| 230 // G2: thread | |
| 231 // G7: not available | |
| 232 // G6: not available | |
| 233 /* 0 */ map_register(i++, L0); | |
| 234 /* 1 */ map_register(i++, L1); | |
| 235 /* 2 */ map_register(i++, L2); | |
| 236 /* 3 */ map_register(i++, L3); | |
| 237 /* 4 */ map_register(i++, L4); | |
| 238 /* 5 */ map_register(i++, L5); | |
| 239 /* 6 */ map_register(i++, L6); | |
| 240 /* 7 */ map_register(i++, L7); | |
| 241 | |
| 242 /* 8 */ map_register(i++, I0); | |
| 243 /* 9 */ map_register(i++, I1); | |
| 244 /* 10 */ map_register(i++, I2); | |
| 245 /* 11 */ map_register(i++, I3); | |
| 246 /* 12 */ map_register(i++, I4); | |
| 247 /* 13 */ map_register(i++, I5); | |
| 248 /* 14 */ map_register(i++, O0); | |
| 249 /* 15 */ map_register(i++, O1); | |
| 250 /* 16 */ map_register(i++, O2); | |
| 251 /* 17 */ map_register(i++, O3); | |
| 252 /* 18 */ map_register(i++, O4); | |
| 253 /* 19 */ map_register(i++, O5); // <- last register visible in RegAlloc (RegAlloc::nof+cpu_regs) | |
| 254 /* 20 */ map_register(i++, G1); | |
| 255 /* 21 */ map_register(i++, G3); | |
| 256 /* 22 */ map_register(i++, G4); | |
| 257 /* 23 */ map_register(i++, G5); | |
| 258 /* 24 */ map_register(i++, G0); | |
| 259 | |
| 260 // the following registers are not normally available | |
| 261 /* 25 */ map_register(i++, O7); | |
| 262 /* 26 */ map_register(i++, G2); | |
| 263 /* 27 */ map_register(i++, O6); | |
| 264 /* 28 */ map_register(i++, I6); | |
| 265 /* 29 */ map_register(i++, I7); | |
| 266 /* 30 */ map_register(i++, G6); | |
| 267 /* 31 */ map_register(i++, G7); | |
| 268 assert(i == nof_cpu_regs, "number of CPU registers"); | |
| 269 | |
| 270 for (i = 0; i < nof_fpu_regs; i++) { | |
| 271 _fpu_regs[i] = as_FloatRegister(i); | |
| 272 } | |
| 273 | |
| 274 _init_done = true; | |
| 275 | |
| 276 in_long_opr = as_long_opr(I0); | |
| 277 out_long_opr = as_long_opr(O0); | |
| 1783 | 278 g1_long_single_opr = as_long_single_opr(G1); |
| 0 | 279 |
| 280 G0_opr = as_opr(G0); | |
| 281 G1_opr = as_opr(G1); | |
| 282 G2_opr = as_opr(G2); | |
| 283 G3_opr = as_opr(G3); | |
| 284 G4_opr = as_opr(G4); | |
| 285 G5_opr = as_opr(G5); | |
| 286 G6_opr = as_opr(G6); | |
| 287 G7_opr = as_opr(G7); | |
| 288 O0_opr = as_opr(O0); | |
| 289 O1_opr = as_opr(O1); | |
| 290 O2_opr = as_opr(O2); | |
| 291 O3_opr = as_opr(O3); | |
| 292 O4_opr = as_opr(O4); | |
| 293 O5_opr = as_opr(O5); | |
| 294 O6_opr = as_opr(O6); | |
| 295 O7_opr = as_opr(O7); | |
| 296 L0_opr = as_opr(L0); | |
| 297 L1_opr = as_opr(L1); | |
| 298 L2_opr = as_opr(L2); | |
| 299 L3_opr = as_opr(L3); | |
| 300 L4_opr = as_opr(L4); | |
| 301 L5_opr = as_opr(L5); | |
| 302 L6_opr = as_opr(L6); | |
| 303 L7_opr = as_opr(L7); | |
| 304 I0_opr = as_opr(I0); | |
| 305 I1_opr = as_opr(I1); | |
| 306 I2_opr = as_opr(I2); | |
| 307 I3_opr = as_opr(I3); | |
| 308 I4_opr = as_opr(I4); | |
| 309 I5_opr = as_opr(I5); | |
| 310 I6_opr = as_opr(I6); | |
| 311 I7_opr = as_opr(I7); | |
| 312 | |
| 313 G0_oop_opr = as_oop_opr(G0); | |
| 314 G1_oop_opr = as_oop_opr(G1); | |
| 315 G2_oop_opr = as_oop_opr(G2); | |
| 316 G3_oop_opr = as_oop_opr(G3); | |
| 317 G4_oop_opr = as_oop_opr(G4); | |
| 318 G5_oop_opr = as_oop_opr(G5); | |
| 319 G6_oop_opr = as_oop_opr(G6); | |
| 320 G7_oop_opr = as_oop_opr(G7); | |
| 321 O0_oop_opr = as_oop_opr(O0); | |
| 322 O1_oop_opr = as_oop_opr(O1); | |
| 323 O2_oop_opr = as_oop_opr(O2); | |
| 324 O3_oop_opr = as_oop_opr(O3); | |
| 325 O4_oop_opr = as_oop_opr(O4); | |
| 326 O5_oop_opr = as_oop_opr(O5); | |
| 327 O6_oop_opr = as_oop_opr(O6); | |
| 328 O7_oop_opr = as_oop_opr(O7); | |
| 329 L0_oop_opr = as_oop_opr(L0); | |
| 330 L1_oop_opr = as_oop_opr(L1); | |
| 331 L2_oop_opr = as_oop_opr(L2); | |
| 332 L3_oop_opr = as_oop_opr(L3); | |
| 333 L4_oop_opr = as_oop_opr(L4); | |
| 334 L5_oop_opr = as_oop_opr(L5); | |
| 335 L6_oop_opr = as_oop_opr(L6); | |
| 336 L7_oop_opr = as_oop_opr(L7); | |
| 337 I0_oop_opr = as_oop_opr(I0); | |
| 338 I1_oop_opr = as_oop_opr(I1); | |
| 339 I2_oop_opr = as_oop_opr(I2); | |
| 340 I3_oop_opr = as_oop_opr(I3); | |
| 341 I4_oop_opr = as_oop_opr(I4); | |
| 342 I5_oop_opr = as_oop_opr(I5); | |
| 343 I6_oop_opr = as_oop_opr(I6); | |
| 344 I7_oop_opr = as_oop_opr(I7); | |
| 345 | |
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346 G0_metadata_opr = as_metadata_opr(G0); |
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347 G1_metadata_opr = as_metadata_opr(G1); |
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348 G2_metadata_opr = as_metadata_opr(G2); |
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349 G3_metadata_opr = as_metadata_opr(G3); |
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350 G4_metadata_opr = as_metadata_opr(G4); |
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351 G5_metadata_opr = as_metadata_opr(G5); |
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352 G6_metadata_opr = as_metadata_opr(G6); |
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353 G7_metadata_opr = as_metadata_opr(G7); |
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354 O0_metadata_opr = as_metadata_opr(O0); |
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355 O1_metadata_opr = as_metadata_opr(O1); |
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356 O2_metadata_opr = as_metadata_opr(O2); |
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357 O3_metadata_opr = as_metadata_opr(O3); |
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358 O4_metadata_opr = as_metadata_opr(O4); |
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359 O5_metadata_opr = as_metadata_opr(O5); |
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360 O6_metadata_opr = as_metadata_opr(O6); |
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361 O7_metadata_opr = as_metadata_opr(O7); |
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362 L0_metadata_opr = as_metadata_opr(L0); |
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363 L1_metadata_opr = as_metadata_opr(L1); |
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364 L2_metadata_opr = as_metadata_opr(L2); |
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365 L3_metadata_opr = as_metadata_opr(L3); |
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366 L4_metadata_opr = as_metadata_opr(L4); |
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367 L5_metadata_opr = as_metadata_opr(L5); |
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368 L6_metadata_opr = as_metadata_opr(L6); |
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369 L7_metadata_opr = as_metadata_opr(L7); |
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370 I0_metadata_opr = as_metadata_opr(I0); |
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371 I1_metadata_opr = as_metadata_opr(I1); |
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372 I2_metadata_opr = as_metadata_opr(I2); |
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373 I3_metadata_opr = as_metadata_opr(I3); |
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374 I4_metadata_opr = as_metadata_opr(I4); |
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375 I5_metadata_opr = as_metadata_opr(I5); |
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376 I6_metadata_opr = as_metadata_opr(I6); |
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377 I7_metadata_opr = as_metadata_opr(I7); |
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378 |
| 0 | 379 FP_opr = as_pointer_opr(FP); |
| 380 SP_opr = as_pointer_opr(SP); | |
| 381 | |
| 382 F0_opr = as_float_opr(F0); | |
| 383 F0_double_opr = as_double_opr(F0); | |
| 384 | |
| 385 Oexception_opr = as_oop_opr(Oexception); | |
| 386 Oissuing_pc_opr = as_opr(Oissuing_pc); | |
| 387 | |
| 388 _caller_save_cpu_regs[0] = FrameMap::O0_opr; | |
| 389 _caller_save_cpu_regs[1] = FrameMap::O1_opr; | |
| 390 _caller_save_cpu_regs[2] = FrameMap::O2_opr; | |
| 391 _caller_save_cpu_regs[3] = FrameMap::O3_opr; | |
| 392 _caller_save_cpu_regs[4] = FrameMap::O4_opr; | |
| 393 _caller_save_cpu_regs[5] = FrameMap::O5_opr; | |
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394 _caller_save_cpu_regs[6] = FrameMap::G1_opr; |
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395 _caller_save_cpu_regs[7] = FrameMap::G3_opr; |
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396 _caller_save_cpu_regs[8] = FrameMap::G4_opr; |
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397 _caller_save_cpu_regs[9] = FrameMap::G5_opr; |
| 0 | 398 for (int i = 0; i < nof_caller_save_fpu_regs; i++) { |
| 399 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i); | |
| 400 } | |
| 401 } | |
| 402 | |
| 403 | |
| 404 Address FrameMap::make_new_address(ByteSize sp_offset) const { | |
| 727 | 405 return Address(SP, STACK_BIAS + in_bytes(sp_offset)); |
| 0 | 406 } |
| 407 | |
| 408 | |
| 409 VMReg FrameMap::fpu_regname (int n) { | |
| 410 return as_FloatRegister(n)->as_VMReg(); | |
| 411 } | |
| 412 | |
| 413 | |
| 414 LIR_Opr FrameMap::stack_pointer() { | |
| 415 return SP_opr; | |
| 416 } | |
| 417 | |
| 418 | |
| 1564 | 419 // JSR 292 |
| 420 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { | |
| 421 assert(L7 == L7_mh_SP_save, "must be same register"); | |
| 422 return L7_opr; | |
| 423 } | |
| 424 | |
| 425 | |
| 0 | 426 bool FrameMap::validate_frame() { |
| 427 int max_offset = in_bytes(framesize_in_bytes()); | |
| 428 int java_index = 0; | |
| 429 for (int i = 0; i < _incoming_arguments->length(); i++) { | |
| 430 LIR_Opr opr = _incoming_arguments->at(i); | |
| 431 if (opr->is_stack()) { | |
| 432 max_offset = MAX2(_argument_locations->at(java_index), max_offset); | |
| 433 } | |
| 434 java_index += type2size[opr->type()]; | |
| 435 } | |
| 436 return Assembler::is_simm13(max_offset + STACK_BIAS); | |
| 437 } |