Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/register_sparc.hpp @ 6812:988bf00cc564
7200261: G1: Liveness counting inconsistencies during marking verification
Summary: The clipping code in the routine that sets the bits for a range of cards, in the liveness accounting verification code was incorrect. It set all the bits in the card bitmap from the given starting index which would lead to spurious marking verification failures.
Reviewed-by: brutisso, jwilhelm, jmasa
author | johnc |
---|---|
date | Thu, 27 Sep 2012 15:44:01 -0700 |
parents | f95d63e2154a |
children | 46c544b8fbfc |
rev | line source |
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0 | 1 /* |
1972 | 2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. |
0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
1552
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
0 | 22 * |
23 */ | |
24 | |
1972 | 25 #ifndef CPU_SPARC_VM_REGISTER_SPARC_HPP |
26 #define CPU_SPARC_VM_REGISTER_SPARC_HPP | |
27 | |
28 #include "asm/register.hpp" | |
29 #include "vm_version_sparc.hpp" | |
30 | |
0 | 31 // forward declaration |
32 class Address; | |
33 class VMRegImpl; | |
34 typedef VMRegImpl* VMReg; | |
35 | |
36 | |
37 // Use Register as shortcut | |
38 class RegisterImpl; | |
39 typedef RegisterImpl* Register; | |
40 | |
41 | |
42 inline Register as_Register(int encoding) { | |
43 return (Register)(intptr_t) encoding; | |
44 } | |
45 | |
46 // The implementation of integer registers for the SPARC architecture | |
47 class RegisterImpl: public AbstractRegisterImpl { | |
48 public: | |
49 enum { | |
50 log_set_size = 3, // the number of bits to encode the set register number | |
51 number_of_sets = 4, // the number of registers sets (in, local, out, global) | |
52 number_of_registers = number_of_sets << log_set_size, | |
53 | |
54 iset_no = 3, ibase = iset_no << log_set_size, // the in register set | |
55 lset_no = 2, lbase = lset_no << log_set_size, // the local register set | |
56 oset_no = 1, obase = oset_no << log_set_size, // the output register set | |
57 gset_no = 0, gbase = gset_no << log_set_size // the global register set | |
58 }; | |
59 | |
60 | |
61 friend Register as_Register(int encoding); | |
62 // set specific construction | |
63 friend Register as_iRegister(int number); | |
64 friend Register as_lRegister(int number); | |
65 friend Register as_oRegister(int number); | |
66 friend Register as_gRegister(int number); | |
67 | |
68 VMReg as_VMReg(); | |
69 | |
70 // accessors | |
71 int encoding() const { assert(is_valid(), "invalid register"); return value(); } | |
72 const char* name() const; | |
73 | |
74 // testers | |
75 bool is_valid() const { return (0 <= (value()&0x7F) && (value()&0x7F) < number_of_registers); } | |
76 bool is_even() const { return (encoding() & 1) == 0; } | |
77 bool is_in() const { return (encoding() >> log_set_size) == iset_no; } | |
78 bool is_local() const { return (encoding() >> log_set_size) == lset_no; } | |
79 bool is_out() const { return (encoding() >> log_set_size) == oset_no; } | |
80 bool is_global() const { return (encoding() >> log_set_size) == gset_no; } | |
81 | |
82 // derived registers, offsets, and addresses | |
83 Register successor() const { return as_Register(encoding() + 1); } | |
84 | |
85 int input_number() const { | |
86 assert(is_in(), "must be input register"); | |
87 return encoding() - ibase; | |
88 } | |
89 | |
90 Register after_save() const { | |
91 assert(is_out() || is_global(), "register not visible after save"); | |
92 return is_out() ? as_Register(encoding() + (ibase - obase)) : (const Register)this; | |
93 } | |
94 | |
95 Register after_restore() const { | |
96 assert(is_in() || is_global(), "register not visible after restore"); | |
97 return is_in() ? as_Register(encoding() + (obase - ibase)) : (const Register)this; | |
98 } | |
99 | |
100 int sp_offset_in_saved_window() const { | |
101 assert(is_in() || is_local(), "only i and l registers are saved in frame"); | |
102 return encoding() - lbase; | |
103 } | |
104 | |
105 inline Address address_in_saved_window() const; // implemented in assembler_sparc.hpp | |
106 }; | |
107 | |
108 | |
109 // set specific construction | |
110 inline Register as_iRegister(int number) { return as_Register(RegisterImpl::ibase + number); } | |
111 inline Register as_lRegister(int number) { return as_Register(RegisterImpl::lbase + number); } | |
112 inline Register as_oRegister(int number) { return as_Register(RegisterImpl::obase + number); } | |
113 inline Register as_gRegister(int number) { return as_Register(RegisterImpl::gbase + number); } | |
114 | |
115 // The integer registers of the SPARC architecture | |
116 | |
117 CONSTANT_REGISTER_DECLARATION(Register, noreg , (-1)); | |
118 | |
119 CONSTANT_REGISTER_DECLARATION(Register, G0 , (RegisterImpl::gbase + 0)); | |
120 CONSTANT_REGISTER_DECLARATION(Register, G1 , (RegisterImpl::gbase + 1)); | |
121 CONSTANT_REGISTER_DECLARATION(Register, G2 , (RegisterImpl::gbase + 2)); | |
122 CONSTANT_REGISTER_DECLARATION(Register, G3 , (RegisterImpl::gbase + 3)); | |
123 CONSTANT_REGISTER_DECLARATION(Register, G4 , (RegisterImpl::gbase + 4)); | |
124 CONSTANT_REGISTER_DECLARATION(Register, G5 , (RegisterImpl::gbase + 5)); | |
125 CONSTANT_REGISTER_DECLARATION(Register, G6 , (RegisterImpl::gbase + 6)); | |
126 CONSTANT_REGISTER_DECLARATION(Register, G7 , (RegisterImpl::gbase + 7)); | |
127 | |
128 CONSTANT_REGISTER_DECLARATION(Register, O0 , (RegisterImpl::obase + 0)); | |
129 CONSTANT_REGISTER_DECLARATION(Register, O1 , (RegisterImpl::obase + 1)); | |
130 CONSTANT_REGISTER_DECLARATION(Register, O2 , (RegisterImpl::obase + 2)); | |
131 CONSTANT_REGISTER_DECLARATION(Register, O3 , (RegisterImpl::obase + 3)); | |
132 CONSTANT_REGISTER_DECLARATION(Register, O4 , (RegisterImpl::obase + 4)); | |
133 CONSTANT_REGISTER_DECLARATION(Register, O5 , (RegisterImpl::obase + 5)); | |
134 CONSTANT_REGISTER_DECLARATION(Register, O6 , (RegisterImpl::obase + 6)); | |
135 CONSTANT_REGISTER_DECLARATION(Register, O7 , (RegisterImpl::obase + 7)); | |
136 | |
137 CONSTANT_REGISTER_DECLARATION(Register, L0 , (RegisterImpl::lbase + 0)); | |
138 CONSTANT_REGISTER_DECLARATION(Register, L1 , (RegisterImpl::lbase + 1)); | |
139 CONSTANT_REGISTER_DECLARATION(Register, L2 , (RegisterImpl::lbase + 2)); | |
140 CONSTANT_REGISTER_DECLARATION(Register, L3 , (RegisterImpl::lbase + 3)); | |
141 CONSTANT_REGISTER_DECLARATION(Register, L4 , (RegisterImpl::lbase + 4)); | |
142 CONSTANT_REGISTER_DECLARATION(Register, L5 , (RegisterImpl::lbase + 5)); | |
143 CONSTANT_REGISTER_DECLARATION(Register, L6 , (RegisterImpl::lbase + 6)); | |
144 CONSTANT_REGISTER_DECLARATION(Register, L7 , (RegisterImpl::lbase + 7)); | |
145 | |
146 CONSTANT_REGISTER_DECLARATION(Register, I0 , (RegisterImpl::ibase + 0)); | |
147 CONSTANT_REGISTER_DECLARATION(Register, I1 , (RegisterImpl::ibase + 1)); | |
148 CONSTANT_REGISTER_DECLARATION(Register, I2 , (RegisterImpl::ibase + 2)); | |
149 CONSTANT_REGISTER_DECLARATION(Register, I3 , (RegisterImpl::ibase + 3)); | |
150 CONSTANT_REGISTER_DECLARATION(Register, I4 , (RegisterImpl::ibase + 4)); | |
151 CONSTANT_REGISTER_DECLARATION(Register, I5 , (RegisterImpl::ibase + 5)); | |
152 CONSTANT_REGISTER_DECLARATION(Register, I6 , (RegisterImpl::ibase + 6)); | |
153 CONSTANT_REGISTER_DECLARATION(Register, I7 , (RegisterImpl::ibase + 7)); | |
154 | |
155 CONSTANT_REGISTER_DECLARATION(Register, FP , (RegisterImpl::ibase + 6)); | |
156 CONSTANT_REGISTER_DECLARATION(Register, SP , (RegisterImpl::obase + 6)); | |
157 | |
158 // | |
159 // Because sparc has so many registers, #define'ing values for the is | |
160 // beneficial in code size and the cost of some of the dangers of | |
161 // defines. We don't use them on Intel because win32 uses asm | |
162 // directives which use the same names for registers as Hotspot does, | |
163 // so #defines would screw up the inline assembly. If a particular | |
164 // file has a problem with these defines then it's possible to turn | |
165 // them off in that file by defining DONT_USE_REGISTER_DEFINES. | |
166 // register_definition_sparc.cpp does that so that it's able to | |
167 // provide real definitions of these registers for use in debuggers | |
168 // and such. | |
169 // | |
170 | |
171 #ifndef DONT_USE_REGISTER_DEFINES | |
172 #define noreg ((Register)(noreg_RegisterEnumValue)) | |
173 | |
174 #define G0 ((Register)(G0_RegisterEnumValue)) | |
175 #define G1 ((Register)(G1_RegisterEnumValue)) | |
176 #define G2 ((Register)(G2_RegisterEnumValue)) | |
177 #define G3 ((Register)(G3_RegisterEnumValue)) | |
178 #define G4 ((Register)(G4_RegisterEnumValue)) | |
179 #define G5 ((Register)(G5_RegisterEnumValue)) | |
180 #define G6 ((Register)(G6_RegisterEnumValue)) | |
181 #define G7 ((Register)(G7_RegisterEnumValue)) | |
182 | |
183 #define O0 ((Register)(O0_RegisterEnumValue)) | |
184 #define O1 ((Register)(O1_RegisterEnumValue)) | |
185 #define O2 ((Register)(O2_RegisterEnumValue)) | |
186 #define O3 ((Register)(O3_RegisterEnumValue)) | |
187 #define O4 ((Register)(O4_RegisterEnumValue)) | |
188 #define O5 ((Register)(O5_RegisterEnumValue)) | |
189 #define O6 ((Register)(O6_RegisterEnumValue)) | |
190 #define O7 ((Register)(O7_RegisterEnumValue)) | |
191 | |
192 #define L0 ((Register)(L0_RegisterEnumValue)) | |
193 #define L1 ((Register)(L1_RegisterEnumValue)) | |
194 #define L2 ((Register)(L2_RegisterEnumValue)) | |
195 #define L3 ((Register)(L3_RegisterEnumValue)) | |
196 #define L4 ((Register)(L4_RegisterEnumValue)) | |
197 #define L5 ((Register)(L5_RegisterEnumValue)) | |
198 #define L6 ((Register)(L6_RegisterEnumValue)) | |
199 #define L7 ((Register)(L7_RegisterEnumValue)) | |
200 | |
201 #define I0 ((Register)(I0_RegisterEnumValue)) | |
202 #define I1 ((Register)(I1_RegisterEnumValue)) | |
203 #define I2 ((Register)(I2_RegisterEnumValue)) | |
204 #define I3 ((Register)(I3_RegisterEnumValue)) | |
205 #define I4 ((Register)(I4_RegisterEnumValue)) | |
206 #define I5 ((Register)(I5_RegisterEnumValue)) | |
207 #define I6 ((Register)(I6_RegisterEnumValue)) | |
208 #define I7 ((Register)(I7_RegisterEnumValue)) | |
209 | |
210 #define FP ((Register)(FP_RegisterEnumValue)) | |
211 #define SP ((Register)(SP_RegisterEnumValue)) | |
212 #endif // DONT_USE_REGISTER_DEFINES | |
213 | |
214 // Use FloatRegister as shortcut | |
215 class FloatRegisterImpl; | |
216 typedef FloatRegisterImpl* FloatRegister; | |
217 | |
218 | |
219 // construction | |
220 inline FloatRegister as_FloatRegister(int encoding) { | |
221 return (FloatRegister)(intptr_t)encoding; | |
222 } | |
223 | |
224 // The implementation of float registers for the SPARC architecture | |
225 | |
226 class FloatRegisterImpl: public AbstractRegisterImpl { | |
227 public: | |
228 enum { | |
229 number_of_registers = 64 | |
230 }; | |
231 | |
232 enum Width { | |
233 S = 1, D = 2, Q = 3 | |
234 }; | |
235 | |
236 // construction | |
237 VMReg as_VMReg( ); | |
238 | |
239 // accessors | |
240 int encoding() const { assert(is_valid(), "invalid register"); return value(); } | |
241 | |
242 public: | |
243 int encoding(Width w) const { | |
244 const int c = encoding(); | |
245 switch (w) { | |
246 case S: | |
247 assert(c < 32, "bad single float register"); | |
248 return c; | |
249 | |
250 case D: | |
251 assert(c < 64 && (c & 1) == 0, "bad double float register"); | |
252 assert(c < 32 || VM_Version::v9_instructions_work(), "V9 float work only on V9 platform"); | |
253 return (c & 0x1e) | ((c & 0x20) >> 5); | |
254 | |
255 case Q: | |
256 assert(c < 64 && (c & 3) == 0, "bad quad float register"); | |
257 assert(c < 32 || VM_Version::v9_instructions_work(), "V9 float work only on V9 platform"); | |
258 return (c & 0x1c) | ((c & 0x20) >> 5); | |
259 } | |
260 ShouldNotReachHere(); | |
261 return -1; | |
262 } | |
263 | |
264 bool is_valid() const { return 0 <= value() && value() < number_of_registers; } | |
265 const char* name() const; | |
266 | |
267 FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } | |
268 }; | |
269 | |
270 | |
271 // The float registers of the SPARC architecture | |
272 | |
273 CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1)); | |
274 | |
275 CONSTANT_REGISTER_DECLARATION(FloatRegister, F0 , ( 0)); | |
276 CONSTANT_REGISTER_DECLARATION(FloatRegister, F1 , ( 1)); | |
277 CONSTANT_REGISTER_DECLARATION(FloatRegister, F2 , ( 2)); | |
278 CONSTANT_REGISTER_DECLARATION(FloatRegister, F3 , ( 3)); | |
279 CONSTANT_REGISTER_DECLARATION(FloatRegister, F4 , ( 4)); | |
280 CONSTANT_REGISTER_DECLARATION(FloatRegister, F5 , ( 5)); | |
281 CONSTANT_REGISTER_DECLARATION(FloatRegister, F6 , ( 6)); | |
282 CONSTANT_REGISTER_DECLARATION(FloatRegister, F7 , ( 7)); | |
283 CONSTANT_REGISTER_DECLARATION(FloatRegister, F8 , ( 8)); | |
284 CONSTANT_REGISTER_DECLARATION(FloatRegister, F9 , ( 9)); | |
285 CONSTANT_REGISTER_DECLARATION(FloatRegister, F10 , (10)); | |
286 CONSTANT_REGISTER_DECLARATION(FloatRegister, F11 , (11)); | |
287 CONSTANT_REGISTER_DECLARATION(FloatRegister, F12 , (12)); | |
288 CONSTANT_REGISTER_DECLARATION(FloatRegister, F13 , (13)); | |
289 CONSTANT_REGISTER_DECLARATION(FloatRegister, F14 , (14)); | |
290 CONSTANT_REGISTER_DECLARATION(FloatRegister, F15 , (15)); | |
291 CONSTANT_REGISTER_DECLARATION(FloatRegister, F16 , (16)); | |
292 CONSTANT_REGISTER_DECLARATION(FloatRegister, F17 , (17)); | |
293 CONSTANT_REGISTER_DECLARATION(FloatRegister, F18 , (18)); | |
294 CONSTANT_REGISTER_DECLARATION(FloatRegister, F19 , (19)); | |
295 CONSTANT_REGISTER_DECLARATION(FloatRegister, F20 , (20)); | |
296 CONSTANT_REGISTER_DECLARATION(FloatRegister, F21 , (21)); | |
297 CONSTANT_REGISTER_DECLARATION(FloatRegister, F22 , (22)); | |
298 CONSTANT_REGISTER_DECLARATION(FloatRegister, F23 , (23)); | |
299 CONSTANT_REGISTER_DECLARATION(FloatRegister, F24 , (24)); | |
300 CONSTANT_REGISTER_DECLARATION(FloatRegister, F25 , (25)); | |
301 CONSTANT_REGISTER_DECLARATION(FloatRegister, F26 , (26)); | |
302 CONSTANT_REGISTER_DECLARATION(FloatRegister, F27 , (27)); | |
303 CONSTANT_REGISTER_DECLARATION(FloatRegister, F28 , (28)); | |
304 CONSTANT_REGISTER_DECLARATION(FloatRegister, F29 , (29)); | |
305 CONSTANT_REGISTER_DECLARATION(FloatRegister, F30 , (30)); | |
306 CONSTANT_REGISTER_DECLARATION(FloatRegister, F31 , (31)); | |
307 | |
308 CONSTANT_REGISTER_DECLARATION(FloatRegister, F32 , (32)); | |
309 CONSTANT_REGISTER_DECLARATION(FloatRegister, F34 , (34)); | |
310 CONSTANT_REGISTER_DECLARATION(FloatRegister, F36 , (36)); | |
311 CONSTANT_REGISTER_DECLARATION(FloatRegister, F38 , (38)); | |
312 CONSTANT_REGISTER_DECLARATION(FloatRegister, F40 , (40)); | |
313 CONSTANT_REGISTER_DECLARATION(FloatRegister, F42 , (42)); | |
314 CONSTANT_REGISTER_DECLARATION(FloatRegister, F44 , (44)); | |
315 CONSTANT_REGISTER_DECLARATION(FloatRegister, F46 , (46)); | |
316 CONSTANT_REGISTER_DECLARATION(FloatRegister, F48 , (48)); | |
317 CONSTANT_REGISTER_DECLARATION(FloatRegister, F50 , (50)); | |
318 CONSTANT_REGISTER_DECLARATION(FloatRegister, F52 , (52)); | |
319 CONSTANT_REGISTER_DECLARATION(FloatRegister, F54 , (54)); | |
320 CONSTANT_REGISTER_DECLARATION(FloatRegister, F56 , (56)); | |
321 CONSTANT_REGISTER_DECLARATION(FloatRegister, F58 , (58)); | |
322 CONSTANT_REGISTER_DECLARATION(FloatRegister, F60 , (60)); | |
323 CONSTANT_REGISTER_DECLARATION(FloatRegister, F62 , (62)); | |
324 | |
325 | |
326 #ifndef DONT_USE_REGISTER_DEFINES | |
327 #define fnoreg ((FloatRegister)(fnoreg_FloatRegisterEnumValue)) | |
328 #define F0 ((FloatRegister)( F0_FloatRegisterEnumValue)) | |
329 #define F1 ((FloatRegister)( F1_FloatRegisterEnumValue)) | |
330 #define F2 ((FloatRegister)( F2_FloatRegisterEnumValue)) | |
331 #define F3 ((FloatRegister)( F3_FloatRegisterEnumValue)) | |
332 #define F4 ((FloatRegister)( F4_FloatRegisterEnumValue)) | |
333 #define F5 ((FloatRegister)( F5_FloatRegisterEnumValue)) | |
334 #define F6 ((FloatRegister)( F6_FloatRegisterEnumValue)) | |
335 #define F7 ((FloatRegister)( F7_FloatRegisterEnumValue)) | |
336 #define F8 ((FloatRegister)( F8_FloatRegisterEnumValue)) | |
337 #define F9 ((FloatRegister)( F9_FloatRegisterEnumValue)) | |
338 #define F10 ((FloatRegister)( F10_FloatRegisterEnumValue)) | |
339 #define F11 ((FloatRegister)( F11_FloatRegisterEnumValue)) | |
340 #define F12 ((FloatRegister)( F12_FloatRegisterEnumValue)) | |
341 #define F13 ((FloatRegister)( F13_FloatRegisterEnumValue)) | |
342 #define F14 ((FloatRegister)( F14_FloatRegisterEnumValue)) | |
343 #define F15 ((FloatRegister)( F15_FloatRegisterEnumValue)) | |
344 #define F16 ((FloatRegister)( F16_FloatRegisterEnumValue)) | |
345 #define F17 ((FloatRegister)( F17_FloatRegisterEnumValue)) | |
346 #define F18 ((FloatRegister)( F18_FloatRegisterEnumValue)) | |
347 #define F19 ((FloatRegister)( F19_FloatRegisterEnumValue)) | |
348 #define F20 ((FloatRegister)( F20_FloatRegisterEnumValue)) | |
349 #define F21 ((FloatRegister)( F21_FloatRegisterEnumValue)) | |
350 #define F22 ((FloatRegister)( F22_FloatRegisterEnumValue)) | |
351 #define F23 ((FloatRegister)( F23_FloatRegisterEnumValue)) | |
352 #define F24 ((FloatRegister)( F24_FloatRegisterEnumValue)) | |
353 #define F25 ((FloatRegister)( F25_FloatRegisterEnumValue)) | |
354 #define F26 ((FloatRegister)( F26_FloatRegisterEnumValue)) | |
355 #define F27 ((FloatRegister)( F27_FloatRegisterEnumValue)) | |
356 #define F28 ((FloatRegister)( F28_FloatRegisterEnumValue)) | |
357 #define F29 ((FloatRegister)( F29_FloatRegisterEnumValue)) | |
358 #define F30 ((FloatRegister)( F30_FloatRegisterEnumValue)) | |
359 #define F31 ((FloatRegister)( F31_FloatRegisterEnumValue)) | |
360 #define F32 ((FloatRegister)( F32_FloatRegisterEnumValue)) | |
361 #define F34 ((FloatRegister)( F34_FloatRegisterEnumValue)) | |
362 #define F36 ((FloatRegister)( F36_FloatRegisterEnumValue)) | |
363 #define F38 ((FloatRegister)( F38_FloatRegisterEnumValue)) | |
364 #define F40 ((FloatRegister)( F40_FloatRegisterEnumValue)) | |
365 #define F42 ((FloatRegister)( F42_FloatRegisterEnumValue)) | |
366 #define F44 ((FloatRegister)( F44_FloatRegisterEnumValue)) | |
367 #define F46 ((FloatRegister)( F46_FloatRegisterEnumValue)) | |
368 #define F48 ((FloatRegister)( F48_FloatRegisterEnumValue)) | |
369 #define F50 ((FloatRegister)( F50_FloatRegisterEnumValue)) | |
370 #define F52 ((FloatRegister)( F52_FloatRegisterEnumValue)) | |
371 #define F54 ((FloatRegister)( F54_FloatRegisterEnumValue)) | |
372 #define F56 ((FloatRegister)( F56_FloatRegisterEnumValue)) | |
373 #define F58 ((FloatRegister)( F58_FloatRegisterEnumValue)) | |
374 #define F60 ((FloatRegister)( F60_FloatRegisterEnumValue)) | |
375 #define F62 ((FloatRegister)( F62_FloatRegisterEnumValue)) | |
376 #endif // DONT_USE_REGISTER_DEFINES | |
377 | |
378 // Maximum number of incoming arguments that can be passed in i registers. | |
379 const int SPARC_ARGS_IN_REGS_NUM = 6; | |
380 | |
381 class ConcreteRegisterImpl : public AbstractRegisterImpl { | |
382 public: | |
383 enum { | |
384 // This number must be large enough to cover REG_COUNT (defined by c2) registers. | |
385 // There is no requirement that any ordering here matches any ordering c2 gives | |
386 // it's optoregs. | |
387 number_of_registers = 2*RegisterImpl::number_of_registers + | |
388 FloatRegisterImpl::number_of_registers + | |
389 1 + // ccr | |
390 4 // fcc | |
391 }; | |
392 static const int max_gpr; | |
393 static const int max_fpr; | |
394 | |
395 }; | |
396 | |
397 // Single, Double and Quad fp reg classes. These exist to map the ADLC | |
398 // encoding for a floating point register, to the FloatRegister number | |
399 // desired by the macroassembler. A FloatRegister is a number between | |
400 // 0 and 63 passed around as a pointer. For ADLC, an fp register encoding | |
401 // is the actual bit encoding used by the sparc hardware. When ADLC used | |
402 // the macroassembler to generate an instruction that references, e.g., a | |
403 // double fp reg, it passed the bit encoding to the macroassembler via | |
404 // as_FloatRegister, which, for double regs > 30, returns an illegal | |
405 // register number. | |
406 // | |
407 // Therefore we provide the following classes for use by ADLC. Their | |
408 // sole purpose is to convert from sparc register encodings to FloatRegisters. | |
409 // At some future time, we might replace FloatRegister with these classes, | |
410 // hence the definitions of as_xxxFloatRegister as class methods rather | |
411 // than as external inline routines. | |
412 | |
413 class SingleFloatRegisterImpl; | |
414 typedef SingleFloatRegisterImpl *SingleFloatRegister; | |
415 | |
416 inline FloatRegister as_SingleFloatRegister(int encoding); | |
417 class SingleFloatRegisterImpl { | |
418 public: | |
419 friend inline FloatRegister as_SingleFloatRegister(int encoding) { | |
420 assert(encoding < 32, "bad single float register encoding"); | |
421 return as_FloatRegister(encoding); | |
422 } | |
423 }; | |
424 | |
425 | |
426 class DoubleFloatRegisterImpl; | |
427 typedef DoubleFloatRegisterImpl *DoubleFloatRegister; | |
428 | |
429 inline FloatRegister as_DoubleFloatRegister(int encoding); | |
430 class DoubleFloatRegisterImpl { | |
431 public: | |
432 friend inline FloatRegister as_DoubleFloatRegister(int encoding) { | |
433 assert(encoding < 32, "bad double float register encoding"); | |
434 return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1e) ); | |
435 } | |
436 }; | |
437 | |
438 | |
439 class QuadFloatRegisterImpl; | |
440 typedef QuadFloatRegisterImpl *QuadFloatRegister; | |
441 | |
442 class QuadFloatRegisterImpl { | |
443 public: | |
444 friend FloatRegister as_QuadFloatRegister(int encoding) { | |
445 assert(encoding < 32 && ((encoding & 2) == 0), "bad quad float register encoding"); | |
446 return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1c) ); | |
447 } | |
448 }; | |
1972 | 449 |
450 #endif // CPU_SPARC_VM_REGISTER_SPARC_HPP |