Mercurial > hg > graal-compiler
annotate src/cpu/sparc/vm/vm_version_sparc.hpp @ 6812:988bf00cc564
7200261: G1: Liveness counting inconsistencies during marking verification
Summary: The clipping code in the routine that sets the bits for a range of cards, in the liveness accounting verification code was incorrect. It set all the bits in the card bitmap from the given starting index which would lead to spurious marking verification failures.
Reviewed-by: brutisso, jwilhelm, jmasa
| author | johnc |
|---|---|
| date | Thu, 27 Sep 2012 15:44:01 -0700 |
| parents | 8cb110fd7627 |
| children | 3a327d0b8586 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. |
| 0 | 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 * | |
| 5 * This code is free software; you can redistribute it and/or modify it | |
| 6 * under the terms of the GNU General Public License version 2 only, as | |
| 7 * published by the Free Software Foundation. | |
| 8 * | |
| 9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
| 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 12 * version 2 for more details (a copy is included in the LICENSE file that | |
| 13 * accompanied this code). | |
| 14 * | |
| 15 * You should have received a copy of the GNU General Public License version | |
| 16 * 2 along with this work; if not, write to the Free Software Foundation, | |
| 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
| 18 * | |
|
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
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20 * or visit www.oracle.com if you need additional information or have any |
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21 * questions. |
| 0 | 22 * |
| 23 */ | |
| 24 | |
| 1972 | 25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP |
| 26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP | |
| 27 | |
| 28 #include "runtime/globals_extension.hpp" | |
| 29 #include "runtime/vm_version.hpp" | |
| 30 | |
| 0 | 31 class VM_Version: public Abstract_VM_Version { |
| 32 protected: | |
| 33 enum Feature_Flag { | |
| 3839 | 34 v8_instructions = 0, |
| 35 hardware_mul32 = 1, | |
| 36 hardware_div32 = 2, | |
| 37 hardware_fsmuld = 3, | |
| 38 hardware_popc = 4, | |
| 39 v9_instructions = 5, | |
| 40 vis1_instructions = 6, | |
| 41 vis2_instructions = 7, | |
| 42 sun4v_instructions = 8, | |
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43 blk_init_instructions = 9, |
| 3839 | 44 fmaf_instructions = 10, |
| 45 fmau_instructions = 11, | |
| 46 vis3_instructions = 12, | |
| 6269 | 47 cbcond_instructions = 13, |
| 48 sparc64_family = 14, | |
| 49 M_family = 15, | |
| 50 T_family = 16, | |
| 51 T1_model = 17 | |
| 0 | 52 }; |
| 53 | |
| 54 enum Feature_Flag_Set { | |
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55 unknown_m = 0, |
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56 all_features_m = -1, |
| 0 | 57 |
| 3839 | 58 v8_instructions_m = 1 << v8_instructions, |
| 59 hardware_mul32_m = 1 << hardware_mul32, | |
| 60 hardware_div32_m = 1 << hardware_div32, | |
| 61 hardware_fsmuld_m = 1 << hardware_fsmuld, | |
| 62 hardware_popc_m = 1 << hardware_popc, | |
| 63 v9_instructions_m = 1 << v9_instructions, | |
| 64 vis1_instructions_m = 1 << vis1_instructions, | |
| 65 vis2_instructions_m = 1 << vis2_instructions, | |
| 66 sun4v_m = 1 << sun4v_instructions, | |
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67 blk_init_instructions_m = 1 << blk_init_instructions, |
| 3839 | 68 fmaf_instructions_m = 1 << fmaf_instructions, |
| 69 fmau_instructions_m = 1 << fmau_instructions, | |
| 70 vis3_instructions_m = 1 << vis3_instructions, | |
| 6269 | 71 cbcond_instructions_m = 1 << cbcond_instructions, |
| 3839 | 72 sparc64_family_m = 1 << sparc64_family, |
| 6269 | 73 M_family_m = 1 << M_family, |
| 3839 | 74 T_family_m = 1 << T_family, |
| 75 T1_model_m = 1 << T1_model, | |
| 0 | 76 |
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77 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m, |
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78 generic_v9_m = generic_v8_m | v9_instructions_m, |
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79 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m, |
| 0 | 80 |
| 81 // Temporary until we have something more accurate | |
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82 niagara1_unique_m = sun4v_m, |
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83 niagara1_m = generic_v9_m | niagara1_unique_m |
| 0 | 84 }; |
| 85 | |
| 86 static int _features; | |
| 87 static const char* _features_str; | |
| 88 | |
| 89 static void print_features(); | |
| 90 static int determine_features(); | |
| 91 static int platform_features(int features); | |
| 92 | |
| 2080 | 93 // Returns true if the platform is in the niagara line (T series) |
| 6269 | 94 static bool is_M_family(int features) { return (features & M_family_m) != 0; } |
| 2080 | 95 static bool is_T_family(int features) { return (features & T_family_m) != 0; } |
| 96 static bool is_niagara() { return is_T_family(_features); } | |
| 97 DEBUG_ONLY( static bool is_niagara(int features) { return (features & sun4v_m) != 0; } ) | |
| 98 | |
| 99 // Returns true if it is niagara1 (T1). | |
| 100 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); } | |
| 0 | 101 |
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102 static int maximum_niagara1_processor_count() { return 32; } |
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103 |
| 0 | 104 public: |
| 105 // Initialization | |
| 106 static void initialize(); | |
| 107 | |
| 108 // Instruction support | |
| 109 static bool has_v8() { return (_features & v8_instructions_m) != 0; } | |
| 110 static bool has_v9() { return (_features & v9_instructions_m) != 0; } | |
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111 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; } |
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112 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; } |
| 0 | 113 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; } |
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114 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; } |
| 0 | 115 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; } |
| 116 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; } | |
| 2080 | 117 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; } |
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118 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; } |
| 3839 | 119 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; } |
| 0 | 120 |
| 121 static bool supports_compare_and_exchange() | |
| 122 { return has_v9(); } | |
| 123 | |
| 2080 | 124 // Returns true if the platform is in the niagara line (T series) |
| 125 // and newer than the niagara1. | |
| 126 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); } | |
| 3854 | 127 static bool is_T4() { return is_T_family(_features) && has_cbcond(); } |
| 3839 | 128 |
| 2080 | 129 // Fujitsu SPARC64 |
| 130 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; } | |
| 0 | 131 |
| 3839 | 132 static bool is_sun4v() { return (_features & sun4v_m) != 0; } |
| 133 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); } | |
| 134 | |
| 2080 | 135 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); } |
| 136 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); } | |
| 3854 | 137 |
| 3839 | 138 // T4 and newer Sparc have fast RDPC instruction. |
| 3854 | 139 static bool has_fast_rdpc() { return is_T4(); } |
| 140 | |
| 3892 | 141 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it. |
| 142 static bool has_block_zeroing() { return has_blk_init() && is_T4(); } | |
| 0 | 143 |
| 144 static const char* cpu_features() { return _features_str; } | |
| 145 | |
| 3854 | 146 static intx prefetch_data_size() { |
| 147 return is_T4() ? 32 : 64; // default prefetch block size on sparc | |
| 0 | 148 } |
| 149 | |
| 150 // Prefetch | |
| 151 static intx prefetch_copy_interval_in_bytes() { | |
| 152 intx interval = PrefetchCopyIntervalInBytes; | |
| 153 return interval >= 0 ? interval : (has_v9() ? 512 : 0); | |
| 154 } | |
| 155 static intx prefetch_scan_interval_in_bytes() { | |
| 156 intx interval = PrefetchScanIntervalInBytes; | |
| 157 return interval >= 0 ? interval : (has_v9() ? 512 : 0); | |
| 158 } | |
| 159 static intx prefetch_fields_ahead() { | |
| 160 intx count = PrefetchFieldsAhead; | |
| 161 return count >= 0 ? count : (is_ultra3() ? 1 : 0); | |
| 162 } | |
| 163 | |
| 164 static intx allocate_prefetch_distance() { | |
| 165 // This method should be called before allocate_prefetch_style(). | |
| 166 intx count = AllocatePrefetchDistance; | |
| 167 if (count < 0) { // default is not defined ? | |
| 168 count = 512; | |
| 169 } | |
| 170 return count; | |
| 171 } | |
| 172 static intx allocate_prefetch_style() { | |
| 173 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); | |
| 174 // Return 0 if AllocatePrefetchDistance was not defined. | |
| 175 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; | |
| 176 } | |
| 177 | |
| 178 // Legacy | |
| 179 static bool v8_instructions_work() { return has_v8() && !has_v9(); } | |
| 180 static bool v9_instructions_work() { return has_v9(); } | |
| 181 | |
| 182 // Assembler testing | |
| 183 static void allow_all(); | |
| 184 static void revert(); | |
| 185 | |
| 186 // Override the Abstract_VM_Version implementation. | |
| 187 static uint page_size_count() { return is_sun4v() ? 4 : 2; } | |
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188 |
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189 // Calculates the number of parallel threads |
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190 static unsigned int calc_parallel_worker_threads(); |
| 0 | 191 }; |
| 1972 | 192 |
| 193 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP |