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comparison src/cpu/x86/vm/assembler_x86.hpp @ 6614:006050192a5a

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6340864: Implement vectorization optimizations in hotspot-server Summary: Added asm encoding and mach nodes for vector arithmetic instructions on x86. Reviewed-by: roland
author kvn
date Mon, 20 Aug 2012 09:07:21 -0700
parents 1d7922586cf6
children da91efe96a93
comparison
equal deleted inserted replaced
6594:d5ec46c7da5c 6614:006050192a5a
615 615
616 void simd_prefix(XMMRegister dst, Address src, 616 void simd_prefix(XMMRegister dst, Address src,
617 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) { 617 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
618 simd_prefix(dst, xnoreg, src, pre, opc); 618 simd_prefix(dst, xnoreg, src, pre, opc);
619 } 619 }
620
620 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) { 621 void simd_prefix(Address dst, XMMRegister src, VexSimdPrefix pre) {
621 simd_prefix(src, dst, pre); 622 simd_prefix(src, dst, pre);
622 } 623 }
623 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src, 624 void simd_prefix_q(XMMRegister dst, XMMRegister nds, Address src,
624 VexSimdPrefix pre) { 625 VexSimdPrefix pre) {
625 bool rex_w = true; 626 bool rex_w = true;
626 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w); 627 simd_prefix(dst, nds, src, pre, VEX_OPCODE_0F, rex_w);
627 } 628 }
628 629
629
630 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, 630 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
631 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F, 631 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F,
632 bool rex_w = false, bool vector256 = false); 632 bool rex_w = false, bool vector256 = false);
633
634 int simd_prefix_and_encode(XMMRegister dst, XMMRegister src,
635 VexSimdPrefix pre, VexOpcode opc = VEX_OPCODE_0F) {
636 return simd_prefix_and_encode(dst, xnoreg, src, pre, opc);
637 }
638 633
639 // Move/convert 32-bit integer value. 634 // Move/convert 32-bit integer value.
640 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src, 635 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, Register src,
641 VexSimdPrefix pre) { 636 VexSimdPrefix pre) {
642 // It is OK to cast from Register to XMMRegister to pass argument here 637 // It is OK to cast from Register to XMMRegister to pass argument here
675 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); 670 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
676 // only 32bit?? 671 // only 32bit??
677 void emit_arith(int op1, int op2, Register dst, jobject obj); 672 void emit_arith(int op1, int op2, Register dst, jobject obj);
678 void emit_arith(int op1, int op2, Register dst, Register src); 673 void emit_arith(int op1, int op2, Register dst, Register src);
679 674
675 void emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre);
676 void emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre);
677 void emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre);
678 void emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre);
679 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
680 Address src, VexSimdPrefix pre, bool vector256);
681 void emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
682 XMMRegister src, VexSimdPrefix pre, bool vector256);
683
680 void emit_operand(Register reg, 684 void emit_operand(Register reg,
681 Register base, Register index, Address::ScaleFactor scale, 685 Register base, Register index, Address::ScaleFactor scale,
682 int disp, 686 int disp,
683 RelocationHolder const& rspec, 687 RelocationHolder const& rspec,
684 int rip_relative_correction = 0); 688 int rip_relative_correction = 0);
888 892
889 void andq(Address dst, int32_t imm32); 893 void andq(Address dst, int32_t imm32);
890 void andq(Register dst, int32_t imm32); 894 void andq(Register dst, int32_t imm32);
891 void andq(Register dst, Address src); 895 void andq(Register dst, Address src);
892 void andq(Register dst, Register src); 896 void andq(Register dst, Register src);
893
894 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values
895 void andpd(XMMRegister dst, XMMRegister src);
896
897 // Bitwise Logical AND of Packed Single-Precision Floating-Point Values
898 void andps(XMMRegister dst, XMMRegister src);
899 897
900 void bsfl(Register dst, Register src); 898 void bsfl(Register dst, Register src);
901 void bsrl(Register dst, Register src); 899 void bsrl(Register dst, Register src);
902 900
903 #ifdef _LP64 901 #ifdef _LP64
1434 void prefetcht0(Address src); 1432 void prefetcht0(Address src);
1435 void prefetcht1(Address src); 1433 void prefetcht1(Address src);
1436 void prefetcht2(Address src); 1434 void prefetcht2(Address src);
1437 void prefetchw(Address src); 1435 void prefetchw(Address src);
1438 1436
1439 // POR - Bitwise logical OR
1440 void por(XMMRegister dst, XMMRegister src);
1441 void por(XMMRegister dst, Address src);
1442
1443 // Shuffle Packed Doublewords 1437 // Shuffle Packed Doublewords
1444 void pshufd(XMMRegister dst, XMMRegister src, int mode); 1438 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1445 void pshufd(XMMRegister dst, Address src, int mode); 1439 void pshufd(XMMRegister dst, Address src, int mode);
1446 1440
1447 // Shuffle Packed Low Words 1441 // Shuffle Packed Low Words
1448 void pshuflw(XMMRegister dst, XMMRegister src, int mode); 1442 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1449 void pshuflw(XMMRegister dst, Address src, int mode); 1443 void pshuflw(XMMRegister dst, Address src, int mode);
1450 1444
1451 // Shift Right by bits Logical Quadword Immediate
1452 void psrlq(XMMRegister dst, int shift);
1453
1454 // Shift Right by bytes Logical DoubleQuadword Immediate 1445 // Shift Right by bytes Logical DoubleQuadword Immediate
1455 void psrldq(XMMRegister dst, int shift); 1446 void psrldq(XMMRegister dst, int shift);
1456 1447
1457 // Logical Compare Double Quadword 1448 // Logical Compare Double Quadword
1458 void ptest(XMMRegister dst, XMMRegister src); 1449 void ptest(XMMRegister dst, XMMRegister src);
1472 #ifndef _LP64 // no 32bit push/pop on amd64 1463 #ifndef _LP64 // no 32bit push/pop on amd64
1473 void pushl(Address src); 1464 void pushl(Address src);
1474 #endif 1465 #endif
1475 1466
1476 void pushq(Address src); 1467 void pushq(Address src);
1477
1478 // Xor Packed Byte Integer Values
1479 void pxor(XMMRegister dst, Address src);
1480 void pxor(XMMRegister dst, XMMRegister src);
1481 1468
1482 void rcll(Register dst, int imm8); 1469 void rcll(Register dst, int imm8);
1483 1470
1484 void rclq(Register dst, int imm8); 1471 void rclq(Register dst, int imm8);
1485 1472
1599 void xorl(Register dst, Register src); 1586 void xorl(Register dst, Register src);
1600 1587
1601 void xorq(Register dst, Address src); 1588 void xorq(Register dst, Address src);
1602 void xorq(Register dst, Register src); 1589 void xorq(Register dst, Register src);
1603 1590
1604 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1605 void xorpd(XMMRegister dst, XMMRegister src);
1606
1607 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1608 void xorps(XMMRegister dst, XMMRegister src);
1609
1610 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 1591 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
1611 1592
1612 // AVX 3-operands scalar instructions (encoded with VEX prefix) 1593 // AVX 3-operands scalar instructions (encoded with VEX prefix)
1594
1613 void vaddsd(XMMRegister dst, XMMRegister nds, Address src); 1595 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
1614 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1596 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1615 void vaddss(XMMRegister dst, XMMRegister nds, Address src); 1597 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
1616 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1598 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1617 void vdivsd(XMMRegister dst, XMMRegister nds, Address src); 1599 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
1625 void vsubsd(XMMRegister dst, XMMRegister nds, Address src); 1607 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
1626 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 1608 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
1627 void vsubss(XMMRegister dst, XMMRegister nds, Address src); 1609 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
1628 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); 1610 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
1629 1611
1630 // AVX Vector instrucitons. 1612
1631 void vandpd(XMMRegister dst, XMMRegister nds, Address src); 1613 //====================VECTOR ARITHMETIC=====================================
1632 void vandps(XMMRegister dst, XMMRegister nds, Address src); 1614
1633 void vxorpd(XMMRegister dst, XMMRegister nds, Address src); 1615 // Add Packed Floating-Point Values
1634 void vxorps(XMMRegister dst, XMMRegister nds, Address src); 1616 void addpd(XMMRegister dst, XMMRegister src);
1617 void addps(XMMRegister dst, XMMRegister src);
1618 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1619 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1620 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1621 void vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1622
1623 // Subtract Packed Floating-Point Values
1624 void subpd(XMMRegister dst, XMMRegister src);
1625 void subps(XMMRegister dst, XMMRegister src);
1626 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1627 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1628 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1629 void vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1630
1631 // Multiply Packed Floating-Point Values
1632 void mulpd(XMMRegister dst, XMMRegister src);
1633 void mulps(XMMRegister dst, XMMRegister src);
1634 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1635 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1636 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1637 void vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1638
1639 // Divide Packed Floating-Point Values
1640 void divpd(XMMRegister dst, XMMRegister src);
1641 void divps(XMMRegister dst, XMMRegister src);
1642 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1643 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1644 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1645 void vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1646
1647 // Bitwise Logical AND of Packed Floating-Point Values
1648 void andpd(XMMRegister dst, XMMRegister src);
1649 void andps(XMMRegister dst, XMMRegister src);
1650 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1651 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1652 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1653 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1654
1655 // Bitwise Logical XOR of Packed Floating-Point Values
1656 void xorpd(XMMRegister dst, XMMRegister src);
1657 void xorps(XMMRegister dst, XMMRegister src);
1635 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1658 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1636 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1659 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1660 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1661 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1662
1663 // Add packed integers
1664 void paddb(XMMRegister dst, XMMRegister src);
1665 void paddw(XMMRegister dst, XMMRegister src);
1666 void paddd(XMMRegister dst, XMMRegister src);
1667 void paddq(XMMRegister dst, XMMRegister src);
1668 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1669 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1670 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1671 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1672 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1673 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1674 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1675 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1676
1677 // Sub packed integers
1678 void psubb(XMMRegister dst, XMMRegister src);
1679 void psubw(XMMRegister dst, XMMRegister src);
1680 void psubd(XMMRegister dst, XMMRegister src);
1681 void psubq(XMMRegister dst, XMMRegister src);
1682 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1683 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1684 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1685 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1686 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1687 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1688 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1689 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1690
1691 // Multiply packed integers (only shorts and ints)
1692 void pmullw(XMMRegister dst, XMMRegister src);
1693 void pmulld(XMMRegister dst, XMMRegister src);
1694 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1695 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1696 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1697 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1698
1699 // Shift left packed integers
1700 void psllw(XMMRegister dst, int shift);
1701 void pslld(XMMRegister dst, int shift);
1702 void psllq(XMMRegister dst, int shift);
1703 void psllw(XMMRegister dst, XMMRegister shift);
1704 void pslld(XMMRegister dst, XMMRegister shift);
1705 void psllq(XMMRegister dst, XMMRegister shift);
1706 void vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1707 void vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1708 void vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1709 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1710 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1711 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1712
1713 // Logical shift right packed integers
1714 void psrlw(XMMRegister dst, int shift);
1715 void psrld(XMMRegister dst, int shift);
1716 void psrlq(XMMRegister dst, int shift);
1717 void psrlw(XMMRegister dst, XMMRegister shift);
1718 void psrld(XMMRegister dst, XMMRegister shift);
1719 void psrlq(XMMRegister dst, XMMRegister shift);
1720 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1721 void vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1722 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1723 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1724 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1725 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1726
1727 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
1728 void psraw(XMMRegister dst, int shift);
1729 void psrad(XMMRegister dst, int shift);
1730 void psraw(XMMRegister dst, XMMRegister shift);
1731 void psrad(XMMRegister dst, XMMRegister shift);
1732 void vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1733 void vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256);
1734 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1735 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256);
1736
1737 // And packed integers
1738 void pand(XMMRegister dst, XMMRegister src);
1739 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1740 void vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1741
1742 // Or packed integers
1743 void por(XMMRegister dst, XMMRegister src);
1744 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1745 void vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1746
1747 // Xor packed integers
1748 void pxor(XMMRegister dst, XMMRegister src);
1637 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256); 1749 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256);
1750 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256);
1751
1752 // Copy low 128bit into high 128bit of YMM registers.
1638 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src); 1753 void vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1639 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src); 1754 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src);
1640 1755
1641 // AVX instruction which is used to clear upper 128 bits of YMM registers and 1756 // AVX instruction which is used to clear upper 128 bits of YMM registers and
1642 // to avoid transaction penalty between AVX and SSE states. There is no 1757 // to avoid transaction penalty between AVX and SSE states. There is no
2530 2645
2531 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); } 2646 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
2532 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); } 2647 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
2533 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2648 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2534 2649
2535 void vandpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vandpd(dst, nds, src); } 2650 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
2536 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2651 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
2537 2652 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2538 void vandps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vandps(dst, nds, src); } 2653
2539 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2654 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
2655 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
2656 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2540 2657
2541 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); } 2658 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
2542 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); } 2659 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
2543 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2660 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2544 2661
2563 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2680 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
2564 2681
2565 // AVX Vector instructions 2682 // AVX Vector instructions
2566 2683
2567 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); } 2684 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
2568 void vxorpd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorpd(dst, nds, src); } 2685 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
2569 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2686 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2570 2687
2571 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); } 2688 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
2572 void vxorps(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vxorps(dst, nds, src); } 2689 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
2573 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src); 2690 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
2574 2691
2575 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { 2692 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2693 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
2694 Assembler::vpxor(dst, nds, src, vector256);
2695 else
2696 Assembler::vxorpd(dst, nds, src, vector256);
2697 }
2698 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
2576 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2 2699 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
2577 Assembler::vpxor(dst, nds, src, vector256); 2700 Assembler::vpxor(dst, nds, src, vector256);
2578 else 2701 else
2579 Assembler::vxorpd(dst, nds, src, vector256); 2702 Assembler::vxorpd(dst, nds, src, vector256);
2580 } 2703 }