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7079329: Adjust allocation prefetching for T4 Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes Reviewed-by: iveresov, phh, twisti
author kvn
date Tue, 16 Aug 2011 16:59:46 -0700
parents 95134e034042
children bd87c0dcaba5
comparison
equal deleted inserted replaced
3853:11211f7cb5a0 3854:1af104d6cf99
468 468
469 %} 469 %}
470 470
471 source %{ 471 source %{
472 #define __ _masm. 472 #define __ _masm.
473
474 // Block initializing store
475 #define ASI_BLK_INIT_QUAD_LDD_P 0xE2
476 473
477 // tertiary op of a LoadP or StoreP encoding 474 // tertiary op of a LoadP or StoreP encoding
478 #define REGP_OP true 475 #define REGP_OP true
479 476
480 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 477 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
2817 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ 2814 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
2818 MacroAssembler _masm(&cbuf); 2815 MacroAssembler _masm(&cbuf);
2819 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); 2816 Register nof_bytes_arg = reg_to_register_object($cnt$$reg);
2820 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); 2817 Register nof_bytes_tmp = reg_to_register_object($temp$$reg);
2821 Register base_pointer_arg = reg_to_register_object($base$$reg); 2818 Register base_pointer_arg = reg_to_register_object($base$$reg);
2822 2819
2823 Label loop; 2820 Label loop;
2824 __ mov(nof_bytes_arg, nof_bytes_tmp); 2821 __ mov(nof_bytes_arg, nof_bytes_tmp);
2825 2822
2826 // Loop and clear, walking backwards through the array. 2823 // Loop and clear, walking backwards through the array.
2827 // nof_bytes_tmp (if >0) is always the number of bytes to zero 2824 // nof_bytes_tmp (if >0) is always the number of bytes to zero
2828 __ bind(loop); 2825 __ bind(loop);
2829 __ deccc(nof_bytes_tmp, 8); 2826 __ deccc(nof_bytes_tmp, 8);
2830 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 2827 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
6267 // Must be safe to execute with invalid address (cannot fault). 6264 // Must be safe to execute with invalid address (cannot fault).
6268 6265
6269 instruct prefetchr( memory mem ) %{ 6266 instruct prefetchr( memory mem ) %{
6270 match( PrefetchRead mem ); 6267 match( PrefetchRead mem );
6271 ins_cost(MEMORY_REF_COST); 6268 ins_cost(MEMORY_REF_COST);
6269 size(4);
6272 6270
6273 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} 6271 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6274 opcode(Assembler::prefetch_op3); 6272 opcode(Assembler::prefetch_op3);
6275 ins_encode( form3_mem_prefetch_read( mem ) ); 6273 ins_encode( form3_mem_prefetch_read( mem ) );
6276 ins_pipe(iload_mem); 6274 ins_pipe(iload_mem);
6277 %} 6275 %}
6278 6276
6279 instruct prefetchw( memory mem ) %{ 6277 instruct prefetchw( memory mem ) %{
6280 predicate(AllocatePrefetchStyle != 3 );
6281 match( PrefetchWrite mem ); 6278 match( PrefetchWrite mem );
6282 ins_cost(MEMORY_REF_COST); 6279 ins_cost(MEMORY_REF_COST);
6280 size(4);
6283 6281
6284 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} 6282 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6285 opcode(Assembler::prefetch_op3); 6283 opcode(Assembler::prefetch_op3);
6286 ins_encode( form3_mem_prefetch_write( mem ) ); 6284 ins_encode( form3_mem_prefetch_write( mem ) );
6287 ins_pipe(iload_mem); 6285 ins_pipe(iload_mem);
6288 %} 6286 %}
6289 6287
6290 // Use BIS instruction to prefetch. 6288 // Prefetch instructions for allocation.
6291 instruct prefetchw_bis( memory mem ) %{ 6289
6292 predicate(AllocatePrefetchStyle == 3); 6290 instruct prefetchAlloc( memory mem ) %{
6293 match( PrefetchWrite mem ); 6291 predicate(AllocatePrefetchInstr == 0);
6292 match( PrefetchAllocation mem );
6294 ins_cost(MEMORY_REF_COST); 6293 ins_cost(MEMORY_REF_COST);
6295 6294 size(4);
6296 format %{ "STXA G0,$mem\t! // Block initializing store" %} 6295
6297 ins_encode %{ 6296 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6298 Register base = as_Register($mem$$base); 6297 opcode(Assembler::prefetch_op3);
6299 int disp = $mem$$disp; 6298 ins_encode( form3_mem_prefetch_write( mem ) );
6300 if (disp != 0) { 6299 ins_pipe(iload_mem);
6301 __ add(base, AllocatePrefetchStepSize, base); 6300 %}
6302 } 6301
6303 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); 6302 // Use BIS instruction to prefetch for allocation.
6303 // Could fault, need space at the end of TLAB.
6304 instruct prefetchAlloc_bis( iRegP dst ) %{
6305 predicate(AllocatePrefetchInstr == 1);
6306 match( PrefetchAllocation dst );
6307 ins_cost(MEMORY_REF_COST);
6308 size(4);
6309
6310 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6311 ins_encode %{
6312 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6304 %} 6313 %}
6305 ins_pipe(istore_mem_reg); 6314 ins_pipe(istore_mem_reg);
6306 %} 6315 %}
6316
6317 // Next code is used for finding next cache line address to prefetch.
6318 #ifndef _LP64
6319 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6320 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6321 ins_cost(DEFAULT_COST);
6322 size(4);
6323
6324 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6325 ins_encode %{
6326 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6327 %}
6328 ins_pipe(ialu_reg_imm);
6329 %}
6330 #else
6331 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6332 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6333 ins_cost(DEFAULT_COST);
6334 size(4);
6335
6336 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6337 ins_encode %{
6338 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6339 %}
6340 ins_pipe(ialu_reg_imm);
6341 %}
6342 #endif
6307 6343
6308 //----------Store Instructions------------------------------------------------- 6344 //----------Store Instructions-------------------------------------------------
6309 // Store Byte 6345 // Store Byte
6310 instruct storeB(memory mem, iRegI src) %{ 6346 instruct storeB(memory mem, iRegI src) %{
6311 match(Set mem (StoreB mem src)); 6347 match(Set mem (StoreB mem src));