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comparison src/cpu/x86/vm/x86_32.ad @ 3854:1af104d6cf99

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7079329: Adjust allocation prefetching for T4 Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes Reviewed-by: iveresov, phh, twisti
author kvn
date Tue, 16 Aug 2011 16:59:46 -0700
parents 95134e034042
children d8cb48376797
comparison
equal deleted inserted replaced
3853:11211f7cb5a0 3854:1af104d6cf99
7323 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); 7323 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3);
7324 match(PrefetchRead mem); 7324 match(PrefetchRead mem);
7325 ins_cost(100); 7325 ins_cost(100);
7326 7326
7327 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} 7327 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %}
7328 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */ 7328 ins_encode %{
7329 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); 7329 __ prefetchr($mem$$Address);
7330 %}
7330 ins_pipe(ialu_mem); 7331 ins_pipe(ialu_mem);
7331 %} 7332 %}
7332 7333
7333 instruct prefetchrNTA( memory mem ) %{ 7334 instruct prefetchrNTA( memory mem ) %{
7334 predicate(UseSSE>=1 && ReadPrefetchInstr==0); 7335 predicate(UseSSE>=1 && ReadPrefetchInstr==0);
7335 match(PrefetchRead mem); 7336 match(PrefetchRead mem);
7336 ins_cost(100); 7337 ins_cost(100);
7337 7338
7338 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} 7339 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %}
7339 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ 7340 ins_encode %{
7340 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); 7341 __ prefetchnta($mem$$Address);
7342 %}
7341 ins_pipe(ialu_mem); 7343 ins_pipe(ialu_mem);
7342 %} 7344 %}
7343 7345
7344 instruct prefetchrT0( memory mem ) %{ 7346 instruct prefetchrT0( memory mem ) %{
7345 predicate(UseSSE>=1 && ReadPrefetchInstr==1); 7347 predicate(UseSSE>=1 && ReadPrefetchInstr==1);
7346 match(PrefetchRead mem); 7348 match(PrefetchRead mem);
7347 ins_cost(100); 7349 ins_cost(100);
7348 7350
7349 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} 7351 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %}
7350 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ 7352 ins_encode %{
7351 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); 7353 __ prefetcht0($mem$$Address);
7354 %}
7352 ins_pipe(ialu_mem); 7355 ins_pipe(ialu_mem);
7353 %} 7356 %}
7354 7357
7355 instruct prefetchrT2( memory mem ) %{ 7358 instruct prefetchrT2( memory mem ) %{
7356 predicate(UseSSE>=1 && ReadPrefetchInstr==2); 7359 predicate(UseSSE>=1 && ReadPrefetchInstr==2);
7357 match(PrefetchRead mem); 7360 match(PrefetchRead mem);
7358 ins_cost(100); 7361 ins_cost(100);
7359 7362
7360 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} 7363 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %}
7361 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ 7364 ins_encode %{
7362 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); 7365 __ prefetcht2($mem$$Address);
7366 %}
7363 ins_pipe(ialu_mem); 7367 ins_pipe(ialu_mem);
7364 %} 7368 %}
7365 7369
7366 instruct prefetchw0( memory mem ) %{ 7370 instruct prefetchw0( memory mem ) %{
7367 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); 7371 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch());
7372 ins_encode(); 7376 ins_encode();
7373 ins_pipe(empty); 7377 ins_pipe(empty);
7374 %} 7378 %}
7375 7379
7376 instruct prefetchw( memory mem ) %{ 7380 instruct prefetchw( memory mem ) %{
7377 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || AllocatePrefetchInstr==3); 7381 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch());
7378 match( PrefetchWrite mem ); 7382 match( PrefetchWrite mem );
7379 ins_cost(100); 7383 ins_cost(100);
7380 7384
7381 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} 7385 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %}
7382 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ 7386 ins_encode %{
7383 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); 7387 __ prefetchw($mem$$Address);
7388 %}
7384 ins_pipe(ialu_mem); 7389 ins_pipe(ialu_mem);
7385 %} 7390 %}
7386 7391
7387 instruct prefetchwNTA( memory mem ) %{ 7392 instruct prefetchwNTA( memory mem ) %{
7388 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); 7393 predicate(UseSSE>=1);
7389 match(PrefetchWrite mem); 7394 match(PrefetchWrite mem);
7390 ins_cost(100); 7395 ins_cost(100);
7391 7396
7392 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} 7397 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %}
7393 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ 7398 ins_encode %{
7394 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); 7399 __ prefetchnta($mem$$Address);
7400 %}
7395 ins_pipe(ialu_mem); 7401 ins_pipe(ialu_mem);
7396 %} 7402 %}
7397 7403
7398 instruct prefetchwT0( memory mem ) %{ 7404 // Prefetch instructions for allocation.
7405
7406 instruct prefetchAlloc0( memory mem ) %{
7407 predicate(UseSSE==0 && AllocatePrefetchInstr!=3);
7408 match(PrefetchAllocation mem);
7409 ins_cost(0);
7410 size(0);
7411 format %{ "Prefetch allocation (non-SSE is empty encoding)" %}
7412 ins_encode();
7413 ins_pipe(empty);
7414 %}
7415
7416 instruct prefetchAlloc( memory mem ) %{
7417 predicate(AllocatePrefetchInstr==3);
7418 match( PrefetchAllocation mem );
7419 ins_cost(100);
7420
7421 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %}
7422 ins_encode %{
7423 __ prefetchw($mem$$Address);
7424 %}
7425 ins_pipe(ialu_mem);
7426 %}
7427
7428 instruct prefetchAllocNTA( memory mem ) %{
7429 predicate(UseSSE>=1 && AllocatePrefetchInstr==0);
7430 match(PrefetchAllocation mem);
7431 ins_cost(100);
7432
7433 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %}
7434 ins_encode %{
7435 __ prefetchnta($mem$$Address);
7436 %}
7437 ins_pipe(ialu_mem);
7438 %}
7439
7440 instruct prefetchAllocT0( memory mem ) %{
7399 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); 7441 predicate(UseSSE>=1 && AllocatePrefetchInstr==1);
7400 match(PrefetchWrite mem); 7442 match(PrefetchAllocation mem);
7401 ins_cost(100); 7443 ins_cost(100);
7402 7444
7403 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %} 7445 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %}
7404 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ 7446 ins_encode %{
7405 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); 7447 __ prefetcht0($mem$$Address);
7448 %}
7406 ins_pipe(ialu_mem); 7449 ins_pipe(ialu_mem);
7407 %} 7450 %}
7408 7451
7409 instruct prefetchwT2( memory mem ) %{ 7452 instruct prefetchAllocT2( memory mem ) %{
7410 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); 7453 predicate(UseSSE>=1 && AllocatePrefetchInstr==2);
7411 match(PrefetchWrite mem); 7454 match(PrefetchAllocation mem);
7412 ins_cost(100); 7455 ins_cost(100);
7413 7456
7414 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %} 7457 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %}
7415 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ 7458 ins_encode %{
7416 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); 7459 __ prefetcht2($mem$$Address);
7460 %}
7417 ins_pipe(ialu_mem); 7461 ins_pipe(ialu_mem);
7418 %} 7462 %}
7419 7463
7420 //----------Store Instructions------------------------------------------------- 7464 //----------Store Instructions-------------------------------------------------
7421 7465