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comparison src/cpu/x86/vm/x86_64.ad @ 3854:1af104d6cf99

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7079329: Adjust allocation prefetching for T4 Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes Reviewed-by: iveresov, phh, twisti
author kvn
date Tue, 16 Aug 2011 16:59:46 -0700
parents 95134e034042
children d8cb48376797
comparison
equal deleted inserted replaced
3853:11211f7cb5a0 3854:1af104d6cf99
6615 predicate(ReadPrefetchInstr==3); 6615 predicate(ReadPrefetchInstr==3);
6616 match(PrefetchRead mem); 6616 match(PrefetchRead mem);
6617 ins_cost(125); 6617 ins_cost(125);
6618 6618
6619 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %} 6619 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
6620 opcode(0x0F, 0x0D); /* Opcode 0F 0D /0 */ 6620 ins_encode %{
6621 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); 6621 __ prefetchr($mem$$Address);
6622 %}
6622 ins_pipe(ialu_mem); 6623 ins_pipe(ialu_mem);
6623 %} 6624 %}
6624 6625
6625 instruct prefetchrNTA( memory mem ) %{ 6626 instruct prefetchrNTA( memory mem ) %{
6626 predicate(ReadPrefetchInstr==0); 6627 predicate(ReadPrefetchInstr==0);
6627 match(PrefetchRead mem); 6628 match(PrefetchRead mem);
6628 ins_cost(125); 6629 ins_cost(125);
6629 6630
6630 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %} 6631 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
6631 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ 6632 ins_encode %{
6632 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); 6633 __ prefetchnta($mem$$Address);
6634 %}
6633 ins_pipe(ialu_mem); 6635 ins_pipe(ialu_mem);
6634 %} 6636 %}
6635 6637
6636 instruct prefetchrT0( memory mem ) %{ 6638 instruct prefetchrT0( memory mem ) %{
6637 predicate(ReadPrefetchInstr==1); 6639 predicate(ReadPrefetchInstr==1);
6638 match(PrefetchRead mem); 6640 match(PrefetchRead mem);
6639 ins_cost(125); 6641 ins_cost(125);
6640 6642
6641 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %} 6643 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
6642 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ 6644 ins_encode %{
6643 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); 6645 __ prefetcht0($mem$$Address);
6646 %}
6644 ins_pipe(ialu_mem); 6647 ins_pipe(ialu_mem);
6645 %} 6648 %}
6646 6649
6647 instruct prefetchrT2( memory mem ) %{ 6650 instruct prefetchrT2( memory mem ) %{
6648 predicate(ReadPrefetchInstr==2); 6651 predicate(ReadPrefetchInstr==2);
6649 match(PrefetchRead mem); 6652 match(PrefetchRead mem);
6650 ins_cost(125); 6653 ins_cost(125);
6651 6654
6652 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %} 6655 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
6653 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ 6656 ins_encode %{
6654 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); 6657 __ prefetcht2($mem$$Address);
6658 %}
6655 ins_pipe(ialu_mem); 6659 ins_pipe(ialu_mem);
6656 %} 6660 %}
6657 6661
6658 instruct prefetchw( memory mem ) %{ 6662 instruct prefetchwNTA( memory mem ) %{
6659 predicate(AllocatePrefetchInstr==3);
6660 match(PrefetchWrite mem); 6663 match(PrefetchWrite mem);
6661 ins_cost(125); 6664 ins_cost(125);
6662 6665
6663 format %{ "PREFETCHW $mem\t# Prefetch into level 1 cache and mark modified" %} 6666 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
6664 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ 6667 ins_encode %{
6665 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); 6668 __ prefetchnta($mem$$Address);
6669 %}
6666 ins_pipe(ialu_mem); 6670 ins_pipe(ialu_mem);
6667 %} 6671 %}
6668 6672
6669 instruct prefetchwNTA( memory mem ) %{ 6673 // Prefetch instructions for allocation.
6674
6675 instruct prefetchAlloc( memory mem ) %{
6676 predicate(AllocatePrefetchInstr==3);
6677 match(PrefetchAllocation mem);
6678 ins_cost(125);
6679
6680 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
6681 ins_encode %{
6682 __ prefetchw($mem$$Address);
6683 %}
6684 ins_pipe(ialu_mem);
6685 %}
6686
6687 instruct prefetchAllocNTA( memory mem ) %{
6670 predicate(AllocatePrefetchInstr==0); 6688 predicate(AllocatePrefetchInstr==0);
6671 match(PrefetchWrite mem); 6689 match(PrefetchAllocation mem);
6672 ins_cost(125); 6690 ins_cost(125);
6673 6691
6674 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %} 6692 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
6675 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ 6693 ins_encode %{
6676 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x00, mem)); 6694 __ prefetchnta($mem$$Address);
6695 %}
6677 ins_pipe(ialu_mem); 6696 ins_pipe(ialu_mem);
6678 %} 6697 %}
6679 6698
6680 instruct prefetchwT0( memory mem ) %{ 6699 instruct prefetchAllocT0( memory mem ) %{
6681 predicate(AllocatePrefetchInstr==1); 6700 predicate(AllocatePrefetchInstr==1);
6682 match(PrefetchWrite mem); 6701 match(PrefetchAllocation mem);
6683 ins_cost(125); 6702 ins_cost(125);
6684 6703
6685 format %{ "PREFETCHT0 $mem\t# Prefetch to level 1 and 2 caches for write" %} 6704 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
6686 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ 6705 ins_encode %{
6687 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x01, mem)); 6706 __ prefetcht0($mem$$Address);
6707 %}
6688 ins_pipe(ialu_mem); 6708 ins_pipe(ialu_mem);
6689 %} 6709 %}
6690 6710
6691 instruct prefetchwT2( memory mem ) %{ 6711 instruct prefetchAllocT2( memory mem ) %{
6692 predicate(AllocatePrefetchInstr==2); 6712 predicate(AllocatePrefetchInstr==2);
6693 match(PrefetchWrite mem); 6713 match(PrefetchAllocation mem);
6694 ins_cost(125); 6714 ins_cost(125);
6695 6715
6696 format %{ "PREFETCHT2 $mem\t# Prefetch to level 2 cache for write" %} 6716 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
6697 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ 6717 ins_encode %{
6698 ins_encode(REX_mem(mem), OpcP, OpcS, RM_opc_mem(0x03, mem)); 6718 __ prefetcht2($mem$$Address);
6719 %}
6699 ins_pipe(ialu_mem); 6720 ins_pipe(ialu_mem);
6700 %} 6721 %}
6701 6722
6702 //----------Store Instructions------------------------------------------------- 6723 //----------Store Instructions-------------------------------------------------
6703 6724