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comparison src/cpu/x86/vm/vm_version_x86.cpp @ 4771:22cee0ee8927

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Merge
author kvn
date Fri, 06 Jan 2012 20:09:20 -0800
parents 7ab5f6318694 127b3692c168
children 0368109684cb
comparison
equal deleted inserted replaced
4755:2b3acb34791f 4771:22cee0ee8927
48 int VM_Version::_cpuFeatures; 48 int VM_Version::_cpuFeatures;
49 const char* VM_Version::_features_str = ""; 49 const char* VM_Version::_features_str = "";
50 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; 50 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
51 51
52 static BufferBlob* stub_blob; 52 static BufferBlob* stub_blob;
53 static const int stub_size = 500; 53 static const int stub_size = 550;
54 54
55 extern "C" { 55 extern "C" {
56 typedef void (*getPsrInfo_stub_t)(void*); 56 typedef void (*getPsrInfo_stub_t)(void*);
57 } 57 }
58 static getPsrInfo_stub_t getPsrInfo_stub = NULL; 58 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
71 const int CPU_FAMILY_SHIFT = 8; 71 const int CPU_FAMILY_SHIFT = 8;
72 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); 72 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
73 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); 73 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
74 74
75 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; 75 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
76 Label ext_cpuid1, ext_cpuid5, ext_cpuid7, done; 76 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done;
77 77
78 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub"); 78 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
79 # define __ _masm-> 79 # define __ _masm->
80 80
81 address start = __ pc(); 81 address start = __ pc();
227 __ movl(Address(rsi, 0), rax); 227 __ movl(Address(rsi, 0), rax);
228 __ movl(Address(rsi, 4), rbx); 228 __ movl(Address(rsi, 4), rbx);
229 __ movl(Address(rsi, 8), rcx); 229 __ movl(Address(rsi, 8), rcx);
230 __ movl(Address(rsi,12), rdx); 230 __ movl(Address(rsi,12), rdx);
231 231
232 //
233 // Check if OS has enabled XGETBV instruction to access XCR0
234 // (OSXSAVE feature flag) and CPU supports AVX
235 //
236 __ andl(rcx, 0x18000000);
237 __ cmpl(rcx, 0x18000000);
238 __ jccb(Assembler::notEqual, sef_cpuid);
239
240 //
241 // XCR0, XFEATURE_ENABLED_MASK register
242 //
243 __ xorl(rcx, rcx); // zero for XCR0 register
244 __ xgetbv();
245 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
246 __ movl(Address(rsi, 0), rax);
247 __ movl(Address(rsi, 4), rdx);
248
249 //
250 // cpuid(0x7) Structured Extended Features
251 //
252 __ bind(sef_cpuid);
253 __ movl(rax, 7);
254 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
255 __ jccb(Assembler::greater, ext_cpuid);
256
257 __ xorl(rcx, rcx);
258 __ cpuid();
259 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
260 __ movl(Address(rsi, 0), rax);
261 __ movl(Address(rsi, 4), rbx);
262
263 //
264 // Extended cpuid(0x80000000)
265 //
266 __ bind(ext_cpuid);
232 __ movl(rax, 0x80000000); 267 __ movl(rax, 0x80000000);
233 __ cpuid(); 268 __ cpuid();
234 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? 269 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
235 __ jcc(Assembler::belowEqual, done); 270 __ jcc(Assembler::belowEqual, done);
236 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? 271 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
371 _cpuFeatures &= ~CPU_SSE2; 406 _cpuFeatures &= ~CPU_SSE2;
372 407
373 if (UseSSE < 1) 408 if (UseSSE < 1)
374 _cpuFeatures &= ~CPU_SSE; 409 _cpuFeatures &= ~CPU_SSE;
375 410
411 if (UseAVX < 2)
412 _cpuFeatures &= ~CPU_AVX2;
413
414 if (UseAVX < 1)
415 _cpuFeatures &= ~CPU_AVX;
416
376 if (logical_processors_per_package() == 1) { 417 if (logical_processors_per_package() == 1) {
377 // HT processor could be installed on a system which doesn't support HT. 418 // HT processor could be installed on a system which doesn't support HT.
378 _cpuFeatures &= ~CPU_HT; 419 _cpuFeatures &= ~CPU_HT;
379 } 420 }
380 421
381 char buf[256]; 422 char buf[256];
382 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 423 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
383 cores_per_cpu(), threads_per_core(), 424 cores_per_cpu(), threads_per_core(),
384 cpu_family(), _model, _stepping, 425 cpu_family(), _model, _stepping,
385 (supports_cmov() ? ", cmov" : ""), 426 (supports_cmov() ? ", cmov" : ""),
386 (supports_cmpxchg8() ? ", cx8" : ""), 427 (supports_cmpxchg8() ? ", cx8" : ""),
387 (supports_fxsr() ? ", fxsr" : ""), 428 (supports_fxsr() ? ", fxsr" : ""),
391 (supports_sse3() ? ", sse3" : ""), 432 (supports_sse3() ? ", sse3" : ""),
392 (supports_ssse3()? ", ssse3": ""), 433 (supports_ssse3()? ", ssse3": ""),
393 (supports_sse4_1() ? ", sse4.1" : ""), 434 (supports_sse4_1() ? ", sse4.1" : ""),
394 (supports_sse4_2() ? ", sse4.2" : ""), 435 (supports_sse4_2() ? ", sse4.2" : ""),
395 (supports_popcnt() ? ", popcnt" : ""), 436 (supports_popcnt() ? ", popcnt" : ""),
437 (supports_avx() ? ", avx" : ""),
438 (supports_avx2() ? ", avx2" : ""),
396 (supports_mmx_ext() ? ", mmxext" : ""), 439 (supports_mmx_ext() ? ", mmxext" : ""),
397 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), 440 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
398 (supports_lzcnt() ? ", lzcnt": ""), 441 (supports_lzcnt() ? ", lzcnt": ""),
399 (supports_sse4a() ? ", sse4a": ""), 442 (supports_sse4a() ? ", sse4a": ""),
400 (supports_ht() ? ", ht": ""), 443 (supports_ht() ? ", ht": ""),
404 _features_str = strdup(buf); 447 _features_str = strdup(buf);
405 448
406 // UseSSE is set to the smaller of what hardware supports and what 449 // UseSSE is set to the smaller of what hardware supports and what
407 // the command line requires. I.e., you cannot set UseSSE to 2 on 450 // the command line requires. I.e., you cannot set UseSSE to 2 on
408 // older Pentiums which do not support it. 451 // older Pentiums which do not support it.
409 if( UseSSE > 4 ) UseSSE=4; 452 if (UseSSE > 4) UseSSE=4;
410 if( UseSSE < 0 ) UseSSE=0; 453 if (UseSSE < 0) UseSSE=0;
411 if( !supports_sse4_1() ) // Drop to 3 if no SSE4 support 454 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
412 UseSSE = MIN2((intx)3,UseSSE); 455 UseSSE = MIN2((intx)3,UseSSE);
413 if( !supports_sse3() ) // Drop to 2 if no SSE3 support 456 if (!supports_sse3()) // Drop to 2 if no SSE3 support
414 UseSSE = MIN2((intx)2,UseSSE); 457 UseSSE = MIN2((intx)2,UseSSE);
415 if( !supports_sse2() ) // Drop to 1 if no SSE2 support 458 if (!supports_sse2()) // Drop to 1 if no SSE2 support
416 UseSSE = MIN2((intx)1,UseSSE); 459 UseSSE = MIN2((intx)1,UseSSE);
417 if( !supports_sse () ) // Drop to 0 if no SSE support 460 if (!supports_sse ()) // Drop to 0 if no SSE support
418 UseSSE = 0; 461 UseSSE = 0;
462
463 if (UseAVX > 2) UseAVX=2;
464 if (UseAVX < 0) UseAVX=0;
465 if (!supports_avx2()) // Drop to 1 if no AVX2 support
466 UseAVX = MIN2((intx)1,UseAVX);
467 if (!supports_avx ()) // Drop to 0 if no AVX support
468 UseAVX = 0;
419 469
420 // On new cpus instructions which update whole XMM register should be used 470 // On new cpus instructions which update whole XMM register should be used
421 // to prevent partial register stall due to dependencies on high half. 471 // to prevent partial register stall due to dependencies on high half.
422 // 472 //
423 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) 473 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
549 // Use population count instruction if available. 599 // Use population count instruction if available.
550 if (supports_popcnt()) { 600 if (supports_popcnt()) {
551 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 601 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
552 UsePopCountInstruction = true; 602 UsePopCountInstruction = true;
553 } 603 }
604 } else if (UsePopCountInstruction) {
605 warning("POPCNT instruction is not available on this CPU");
606 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
554 } 607 }
555 608
556 #ifdef COMPILER2 609 #ifdef COMPILER2
557 if (UseFPUForSpilling) { 610 if (UseFPUForSpilling) {
558 if (UseSSE < 2) { 611 if (UseSSE < 2) {
620 673
621 #ifndef PRODUCT 674 #ifndef PRODUCT
622 if (PrintMiscellaneous && Verbose) { 675 if (PrintMiscellaneous && Verbose) {
623 tty->print_cr("Logical CPUs per core: %u", 676 tty->print_cr("Logical CPUs per core: %u",
624 logical_processors_per_package()); 677 logical_processors_per_package());
625 tty->print_cr("UseSSE=%d",UseSSE); 678 tty->print("UseSSE=%d",UseSSE);
679 if (UseAVX > 0) {
680 tty->print(" UseAVX=%d",UseAVX);
681 }
682 tty->cr();
626 tty->print("Allocation"); 683 tty->print("Allocation");
627 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { 684 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
628 tty->print_cr(": no prefetching"); 685 tty->print_cr(": no prefetching");
629 } else { 686 } else {
630 tty->print(" prefetching: "); 687 tty->print(" prefetching: ");