Mercurial > hg > graal-compiler

comparison src/cpu/sparc/vm/sparc.ad @ 1748:3e8fbc61cee8

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
6978355: renaming for 6961697 Summary: This is the renaming part of 6961697 to keep the actual changes small for review. Reviewed-by: kvn, never
author twisti
date Wed, 25 Aug 2010 05:27:54 -0700
parents e9ff18c4ace7
children ae065c367d93
comparison
equal deleted inserted replaced
1747:53dbe853fb3a 1748:3e8fbc61cee8
675 (f25 << 25) | 675 (f25 << 25) |
676 (f22 << 22) | 676 (f22 << 22) |
677 (f20 << 20) | 677 (f20 << 20) |
678 (f19 << 19) | 678 (f19 << 19) |
679 (f0 << 0); 679 (f0 << 0);
680 *((int*)(cbuf.code_end())) = op; 680 cbuf.insts()->emit_int32(op);
681 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
682 } 681 }
683 682
684 // Standard Sparc opcode form2 field breakdown 683 // Standard Sparc opcode form2 field breakdown
685 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 684 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
686 f0 >>= 10; // Drop 10 bits 685 f0 >>= 10; // Drop 10 bits
687 f0 &= (1<<22)-1; // Mask displacement to 22 bits 686 f0 &= (1<<22)-1; // Mask displacement to 22 bits
688 int op = (f30 << 30) | 687 int op = (f30 << 30) |
689 (f25 << 25) | 688 (f25 << 25) |
690 (f22 << 22) | 689 (f22 << 22) |
691 (f0 << 0); 690 (f0 << 0);
692 *((int*)(cbuf.code_end())) = op; 691 cbuf.insts()->emit_int32(op);
693 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
694 } 692 }
695 693
696 // Standard Sparc opcode form3 field breakdown 694 // Standard Sparc opcode form3 field breakdown
697 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 695 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
698 int op = (f30 << 30) | 696 int op = (f30 << 30) |
699 (f25 << 25) | 697 (f25 << 25) |
700 (f19 << 19) | 698 (f19 << 19) |
701 (f14 << 14) | 699 (f14 << 14) |
702 (f5 << 5) | 700 (f5 << 5) |
703 (f0 << 0); 701 (f0 << 0);
704 *((int*)(cbuf.code_end())) = op; 702 cbuf.insts()->emit_int32(op);
705 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
706 } 703 }
707 704
708 // Standard Sparc opcode form3 field breakdown 705 // Standard Sparc opcode form3 field breakdown
709 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 706 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
710 simm13 &= (1<<13)-1; // Mask to 13 bits 707 simm13 &= (1<<13)-1; // Mask to 13 bits
712 (f25 << 25) | 709 (f25 << 25) |
713 (f19 << 19) | 710 (f19 << 19) |
714 (f14 << 14) | 711 (f14 << 14) |
715 (1 << 13) | // bit to indicate immediate-mode 712 (1 << 13) | // bit to indicate immediate-mode
716 (simm13<<0); 713 (simm13<<0);
717 *((int*)(cbuf.code_end())) = op; 714 cbuf.insts()->emit_int32(op);
718 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
719 } 715 }
720 716
721 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 717 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
722 simm10 &= (1<<10)-1; // Mask to 10 bits 718 simm10 &= (1<<10)-1; // Mask to 10 bits
723 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 719 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
908 // use reg-imm form 904 // use reg-imm form
909 instr |= 0x00002000; // set bit 13 to one 905 instr |= 0x00002000; // set bit 13 to one
910 instr |= disp & 0x1FFF; 906 instr |= disp & 0x1FFF;
911 } 907 }
912 908
913 uint *code = (uint*)cbuf.code_end(); 909 cbuf.insts()->emit_int32(instr);
914 *code = instr;
915 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
916 910
917 #ifdef ASSERT 911 #ifdef ASSERT
918 { 912 {
919 MacroAssembler _masm(&cbuf); 913 MacroAssembler _masm(&cbuf);
920 if (is_verified_oop_base) { 914 if (is_verified_oop_base) {
1530 // Stub is fixed up when the corresponding call is converted from calling 1524 // Stub is fixed up when the corresponding call is converted from calling
1531 // compiled code to calling interpreted code. 1525 // compiled code to calling interpreted code.
1532 // set (empty), G5 1526 // set (empty), G5
1533 // jmp -1 1527 // jmp -1
1534 1528
1535 address mark = cbuf.inst_mark(); // get mark within main instrs section 1529 address mark = cbuf.insts_mark(); // get mark within main instrs section
1536 1530
1537 MacroAssembler _masm(&cbuf); 1531 MacroAssembler _masm(&cbuf);
1538 1532
1539 address base = 1533 address base =
1540 __ start_a_stub(Compile::MAX_stubs_size); 1534 __ start_a_stub(Compile::MAX_stubs_size);
1630 } 1624 }
1631 1625
1632 // Emit exception handler code. 1626 // Emit exception handler code.
1633 int emit_exception_handler(CodeBuffer& cbuf) { 1627 int emit_exception_handler(CodeBuffer& cbuf) {
1634 Register temp_reg = G3; 1628 Register temp_reg = G3;
1635 AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin()); 1629 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1636 MacroAssembler _masm(&cbuf); 1630 MacroAssembler _masm(&cbuf);
1637 1631
1638 address base = 1632 address base =
1639 __ start_a_stub(size_exception_handler()); 1633 __ start_a_stub(size_exception_handler());
1640 if (base == NULL) return 0; // CodeBuffer::expand failed 1634 if (base == NULL) return 0; // CodeBuffer::expand failed
2290 (1 << 18) | // cc2 bit for 'icc' 2284 (1 << 18) | // cc2 bit for 'icc'
2291 ($cmp$$cmpcode << 14) | 2285 ($cmp$$cmpcode << 14) |
2292 (0 << 13) | // select register move 2286 (0 << 13) | // select register move
2293 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2287 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2294 ($src$$reg << 0); 2288 ($src$$reg << 0);
2295 *((int*)(cbuf.code_end())) = op; 2289 cbuf.insts()->emit_int32(op);
2296 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2297 %} 2290 %}
2298 2291
2299 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2292 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2300 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2293 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2301 int op = (Assembler::arith_op << 30) | 2294 int op = (Assembler::arith_op << 30) |
2304 (1 << 18) | // cc2 bit for 'icc' 2297 (1 << 18) | // cc2 bit for 'icc'
2305 ($cmp$$cmpcode << 14) | 2298 ($cmp$$cmpcode << 14) |
2306 (1 << 13) | // select immediate move 2299 (1 << 13) | // select immediate move
2307 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2300 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2308 (simm11 << 0); 2301 (simm11 << 0);
2309 *((int*)(cbuf.code_end())) = op; 2302 cbuf.insts()->emit_int32(op);
2310 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2311 %} 2303 %}
2312 2304
2313 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2305 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2314 int op = (Assembler::arith_op << 30) | 2306 int op = (Assembler::arith_op << 30) |
2315 ($dst$$reg << 25) | 2307 ($dst$$reg << 25) |
2317 (0 << 18) | // cc2 bit for 'fccX' 2309 (0 << 18) | // cc2 bit for 'fccX'
2318 ($cmp$$cmpcode << 14) | 2310 ($cmp$$cmpcode << 14) |
2319 (0 << 13) | // select register move 2311 (0 << 13) | // select register move
2320 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2312 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2321 ($src$$reg << 0); 2313 ($src$$reg << 0);
2322 *((int*)(cbuf.code_end())) = op; 2314 cbuf.insts()->emit_int32(op);
2323 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2324 %} 2315 %}
2325 2316
2326 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2317 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2327 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2318 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2328 int op = (Assembler::arith_op << 30) | 2319 int op = (Assembler::arith_op << 30) |
2331 (0 << 18) | // cc2 bit for 'fccX' 2322 (0 << 18) | // cc2 bit for 'fccX'
2332 ($cmp$$cmpcode << 14) | 2323 ($cmp$$cmpcode << 14) |
2333 (1 << 13) | // select immediate move 2324 (1 << 13) | // select immediate move
2334 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2325 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2335 (simm11 << 0); 2326 (simm11 << 0);
2336 *((int*)(cbuf.code_end())) = op; 2327 cbuf.insts()->emit_int32(op);
2337 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2338 %} 2328 %}
2339 2329
2340 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2330 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2341 int op = (Assembler::arith_op << 30) | 2331 int op = (Assembler::arith_op << 30) |
2342 ($dst$$reg << 25) | 2332 ($dst$$reg << 25) |
2345 ($cmp$$cmpcode << 14) | 2335 ($cmp$$cmpcode << 14) |
2346 (1 << 13) | // select register move 2336 (1 << 13) | // select register move
2347 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2337 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2348 ($primary << 5) | // select single, double or quad 2338 ($primary << 5) | // select single, double or quad
2349 ($src$$reg << 0); 2339 ($src$$reg << 0);
2350 *((int*)(cbuf.code_end())) = op; 2340 cbuf.insts()->emit_int32(op);
2351 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2352 %} 2341 %}
2353 2342
2354 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2343 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2355 int op = (Assembler::arith_op << 30) | 2344 int op = (Assembler::arith_op << 30) |
2356 ($dst$$reg << 25) | 2345 ($dst$$reg << 25) |
2358 (0 << 18) | 2347 (0 << 18) |
2359 ($cmp$$cmpcode << 14) | 2348 ($cmp$$cmpcode << 14) |
2360 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2349 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2361 ($primary << 5) | // select single, double or quad 2350 ($primary << 5) | // select single, double or quad
2362 ($src$$reg << 0); 2351 ($src$$reg << 0);
2363 *((int*)(cbuf.code_end())) = op; 2352 cbuf.insts()->emit_int32(op);
2364 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2365 %} 2353 %}
2366 2354
2367 // Used by the MIN/MAX encodings. Same as a CMOV, but 2355 // Used by the MIN/MAX encodings. Same as a CMOV, but
2368 // the condition comes from opcode-field instead of an argument. 2356 // the condition comes from opcode-field instead of an argument.
2369 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2357 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2373 (1 << 18) | // cc2 bit for 'icc' 2361 (1 << 18) | // cc2 bit for 'icc'
2374 ($primary << 14) | 2362 ($primary << 14) |
2375 (0 << 13) | // select register move 2363 (0 << 13) | // select register move
2376 (0 << 11) | // cc1, cc0 bits for 'icc' 2364 (0 << 11) | // cc1, cc0 bits for 'icc'
2377 ($src$$reg << 0); 2365 ($src$$reg << 0);
2378 *((int*)(cbuf.code_end())) = op; 2366 cbuf.insts()->emit_int32(op);
2379 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2380 %} 2367 %}
2381 2368
2382 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2369 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2383 int op = (Assembler::arith_op << 30) | 2370 int op = (Assembler::arith_op << 30) |
2384 ($dst$$reg << 25) | 2371 ($dst$$reg << 25) |
2386 (6 << 16) | // cc2 bit for 'xcc' 2373 (6 << 16) | // cc2 bit for 'xcc'
2387 ($primary << 14) | 2374 ($primary << 14) |
2388 (0 << 13) | // select register move 2375 (0 << 13) | // select register move
2389 (0 << 11) | // cc1, cc0 bits for 'icc' 2376 (0 << 11) | // cc1, cc0 bits for 'icc'
2390 ($src$$reg << 0); 2377 ($src$$reg << 0);
2391 *((int*)(cbuf.code_end())) = op; 2378 cbuf.insts()->emit_int32(op);
2392 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
2393 %} 2379 %}
2394 2380
2395 // Utility encoding for loading a 64 bit Pointer into a register 2381 // Utility encoding for loading a 64 bit Pointer into a register
2396 // The 64 bit pointer is stored in the generated code stream 2382 // The 64 bit pointer is stored in the generated code stream
2397 enc_class SetPtr( immP src, iRegP rd ) %{ 2383 enc_class SetPtr( immP src, iRegP rd ) %{
3053 3039
3054 __ bind(Ldone); 3040 __ bind(Ldone);
3055 %} 3041 %}
3056 3042
3057 enc_class enc_rethrow() %{ 3043 enc_class enc_rethrow() %{
3058 cbuf.set_inst_mark(); 3044 cbuf.set_insts_mark();
3059 Register temp_reg = G3; 3045 Register temp_reg = G3;
3060 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 3046 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3061 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 3047 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3062 MacroAssembler _masm(&cbuf); 3048 MacroAssembler _masm(&cbuf);
3063 #ifdef ASSERT 3049 #ifdef ASSERT
3074 __ delayed()->nop(); 3060 __ delayed()->nop();
3075 %} 3061 %}
3076 3062
3077 enc_class emit_mem_nop() %{ 3063 enc_class emit_mem_nop() %{
3078 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3064 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3079 unsigned int *code = (unsigned int*)cbuf.code_end(); 3065 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3080 *code = (unsigned int)0xc0839040;
3081 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3082 %} 3066 %}
3083 3067
3084 enc_class emit_fadd_nop() %{ 3068 enc_class emit_fadd_nop() %{
3085 // Generates the instruction FMOVS f31,f31 3069 // Generates the instruction FMOVS f31,f31
3086 unsigned int *code = (unsigned int*)cbuf.code_end(); 3070 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3087 *code = (unsigned int)0xbfa0003f;
3088 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3089 %} 3071 %}
3090 3072
3091 enc_class emit_br_nop() %{ 3073 enc_class emit_br_nop() %{
3092 // Generates the instruction BPN,PN . 3074 // Generates the instruction BPN,PN .
3093 unsigned int *code = (unsigned int*)cbuf.code_end(); 3075 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3094 *code = (unsigned int)0x00400000;
3095 cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
3096 %} 3076 %}
3097 3077
3098 enc_class enc_membar_acquire %{ 3078 enc_class enc_membar_acquire %{
3099 MacroAssembler _masm(&cbuf); 3079 MacroAssembler _masm(&cbuf);
3100 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 3080 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );