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comparison src/cpu/sparc/vm/assembler_sparc.hpp @ 14909:4ca6dc0799b6

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Backout jdk9 merge
author Gilles Duboscq <duboscq@ssw.jku.at>
date Tue, 01 Apr 2014 13:57:07 +0200
parents 00f5eff62d18
children 89152779163c
comparison
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14908:8db6e76cb658 14909:4ca6dc0799b6
1 /* 1 /*
2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
86 subcc_op3 = 0x14, 86 subcc_op3 = 0x14,
87 andncc_op3 = 0x15, 87 andncc_op3 = 0x15,
88 orncc_op3 = 0x16, 88 orncc_op3 = 0x16,
89 xnorcc_op3 = 0x17, 89 xnorcc_op3 = 0x17,
90 addccc_op3 = 0x18, 90 addccc_op3 = 0x18,
91 aes4_op3 = 0x19,
92 umulcc_op3 = 0x1a, 91 umulcc_op3 = 0x1a,
93 smulcc_op3 = 0x1b, 92 smulcc_op3 = 0x1b,
94 subccc_op3 = 0x1c, 93 subccc_op3 = 0x1c,
95 udivcc_op3 = 0x1e, 94 udivcc_op3 = 0x1e,
96 sdivcc_op3 = 0x1f, 95 sdivcc_op3 = 0x1f,
120 saved_op3 = 0x31, 119 saved_op3 = 0x31,
121 120
122 fpop1_op3 = 0x34, 121 fpop1_op3 = 0x34,
123 fpop2_op3 = 0x35, 122 fpop2_op3 = 0x35,
124 impdep1_op3 = 0x36, 123 impdep1_op3 = 0x36,
125 aes3_op3 = 0x36,
126 flog3_op3 = 0x36,
127 impdep2_op3 = 0x37, 124 impdep2_op3 = 0x37,
128 jmpl_op3 = 0x38, 125 jmpl_op3 = 0x38,
129 rett_op3 = 0x39, 126 rett_op3 = 0x39,
130 trap_op3 = 0x3a, 127 trap_op3 = 0x3a,
131 flush_op3 = 0x3b, 128 flush_op3 = 0x3b,
173 cc_bit_op3 = 0x10 170 cc_bit_op3 = 0x10
174 }; 171 };
175 172
176 enum opfs { 173 enum opfs {
177 // selected opfs 174 // selected opfs
178 fmovs_opf = 0x01, 175 fmovs_opf = 0x01,
179 fmovd_opf = 0x02, 176 fmovd_opf = 0x02,
180 177
181 fnegs_opf = 0x05, 178 fnegs_opf = 0x05,
182 fnegd_opf = 0x06, 179 fnegd_opf = 0x06,
183 180
184 fadds_opf = 0x41, 181 fadds_opf = 0x41,
185 faddd_opf = 0x42, 182 faddd_opf = 0x42,
186 fsubs_opf = 0x45, 183 fsubs_opf = 0x45,
187 fsubd_opf = 0x46, 184 fsubd_opf = 0x46,
188 185
189 fmuls_opf = 0x49, 186 fmuls_opf = 0x49,
190 fmuld_opf = 0x4a, 187 fmuld_opf = 0x4a,
191 fdivs_opf = 0x4d, 188 fdivs_opf = 0x4d,
192 fdivd_opf = 0x4e, 189 fdivd_opf = 0x4e,
193 190
194 fcmps_opf = 0x51, 191 fcmps_opf = 0x51,
195 fcmpd_opf = 0x52, 192 fcmpd_opf = 0x52,
196 193
197 fstox_opf = 0x81, 194 fstox_opf = 0x81,
198 fdtox_opf = 0x82, 195 fdtox_opf = 0x82,
199 fxtos_opf = 0x84, 196 fxtos_opf = 0x84,
200 fxtod_opf = 0x88, 197 fxtod_opf = 0x88,
201 fitos_opf = 0xc4, 198 fitos_opf = 0xc4,
202 fdtos_opf = 0xc6, 199 fdtos_opf = 0xc6,
203 fitod_opf = 0xc8, 200 fitod_opf = 0xc8,
204 fstod_opf = 0xc9, 201 fstod_opf = 0xc9,
205 fstoi_opf = 0xd1, 202 fstoi_opf = 0xd1,
206 fdtoi_opf = 0xd2, 203 fdtoi_opf = 0xd2,
207 204
208 mdtox_opf = 0x110, 205 mdtox_opf = 0x110,
209 mstouw_opf = 0x111, 206 mstouw_opf = 0x111,
210 mstosw_opf = 0x113, 207 mstosw_opf = 0x113,
211 mxtod_opf = 0x118, 208 mxtod_opf = 0x118,
212 mwtos_opf = 0x119, 209 mwtos_opf = 0x119
213
214 aes_kexpand0_opf = 0x130,
215 aes_kexpand2_opf = 0x131
216 };
217
218 enum op5s {
219 aes_eround01_op5 = 0x00,
220 aes_eround23_op5 = 0x01,
221 aes_dround01_op5 = 0x02,
222 aes_dround23_op5 = 0x03,
223 aes_eround01_l_op5 = 0x04,
224 aes_eround23_l_op5 = 0x05,
225 aes_dround01_l_op5 = 0x06,
226 aes_dround23_l_op5 = 0x07,
227 aes_kexpand1_op5 = 0x08
228 }; 210 };
229 211
230 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez }; 212 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez };
231 213
232 enum Condition { 214 enum Condition {
443 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); } 425 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); }
444 static int imm_asi( int x) { return u_field(x, 12, 5); } 426 static int imm_asi( int x) { return u_field(x, 12, 5); }
445 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); } 427 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); }
446 static int opf_low6( int w) { return u_field(w, 10, 5); } 428 static int opf_low6( int w) { return u_field(w, 10, 5); }
447 static int opf_low5( int w) { return u_field(w, 9, 5); } 429 static int opf_low5( int w) { return u_field(w, 9, 5); }
448 static int op5( int x) { return u_field(x, 8, 5); }
449 static int trapcc( CC cc) { return u_field(cc, 12, 11); } 430 static int trapcc( CC cc) { return u_field(cc, 12, 11); }
450 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit 431 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit
451 static int opf( int x) { return u_field(x, 13, 5); } 432 static int opf( int x) { return u_field(x, 13, 5); }
452 433
453 static bool is_cbcond( int x ) { 434 static bool is_cbcond( int x ) {
468 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } 449 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); }
469 450
470 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; 451 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); };
471 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; 452 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); };
472 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; 453 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); };
473 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); };
474 454
475 // some float instructions use this encoding on the op3 field 455 // some float instructions use this encoding on the op3 field
476 static int alt_op3(int op, FloatRegisterImpl::Width w) { 456 static int alt_op3(int op, FloatRegisterImpl::Width w) {
477 int r; 457 int r;
478 switch(w) { 458 switch(w) {
577 // create a low10 __value__ (not a field) for a given a 32-bit constant 557 // create a low10 __value__ (not a field) for a given a 32-bit constant
578 static int low10( int x ) { 558 static int low10( int x ) {
579 return x & ((1 << 10) - 1); 559 return x & ((1 << 10) - 1);
580 } 560 }
581 561
582 // AES crypto instructions supported only on certain processors
583 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); }
584
585 // instruction only in VIS1
586 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); }
587
588 // instruction only in VIS3 562 // instruction only in VIS3
589 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); } 563 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); }
590 564
591 // instruction only in v9 565 // instruction only in v9
592 static void v9_only() { } // do nothing 566 static void v9_only() { } // do nothing
706 void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 680 void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
707 void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 681 void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); }
708 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 682 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); }
709 683
710 684
711 // 4-operand AES instructions
712
713 void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
714 void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
715 void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); }
716 void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); }
717 void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
718 void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
719 void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
720 void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); }
721 void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); }
722
723
724 // 3-operand AES instructions
725
726 void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); }
727 void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); }
728
729 // pp 136 685 // pp 136
730 686
731 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none); 687 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none);
732 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L); 688 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L);
733 689
825 // pp 163 781 // pp 163
826 782
827 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); } 783 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); }
828 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); } 784 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); }
829 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); } 785 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); }
830
831 // FXORs/FXORd instructions
832
833 void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); }
834 786
835 // pp 164 787 // pp 164
836 788
837 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); } 789 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); }
838 790