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comparison src/share/vm/opto/chaitin.cpp @ 14909:4ca6dc0799b6

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Backout jdk9 merge
author Gilles Duboscq <duboscq@ssw.jku.at>
date Tue, 01 Apr 2014 13:57:07 +0200
parents 1077c8270209
children 042b5e9aeb76
comparison
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14908:8db6e76cb658 14909:4ca6dc0799b6
208 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling")) 208 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling"))
209 #endif 209 #endif
210 { 210 {
211 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); ) 211 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); )
212 212
213 _high_frequency_lrg = MIN2(double(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency()); 213 _high_frequency_lrg = MIN2(float(OPTO_LRG_HIGH_FREQ), _cfg.get_outer_loop_frequency());
214 214
215 // Build a list of basic blocks, sorted by frequency 215 // Build a list of basic blocks, sorted by frequency
216 _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks()); 216 _blks = NEW_RESOURCE_ARRAY(Block *, _cfg.number_of_blocks());
217 // Experiment with sorting strategies to speed compilation 217 // Experiment with sorting strategies to speed compilation
218 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket 218 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket
759 // Check for vector live range (only if vector register is used). 759 // Check for vector live range (only if vector register is used).
760 // On SPARC vector uses RegD which could be misaligned so it is not 760 // On SPARC vector uses RegD which could be misaligned so it is not
761 // processes as vector in RA. 761 // processes as vector in RA.
762 if (RegMask::is_vector(ireg)) 762 if (RegMask::is_vector(ireg))
763 lrg._is_vector = 1; 763 lrg._is_vector = 1;
764 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD || ireg == Op_RegL, 764 assert(n_type->isa_vect() == NULL || lrg._is_vector || ireg == Op_RegD,
765 "vector must be in vector registers"); 765 "vector must be in vector registers");
766 766
767 // Check for bound register masks 767 // Check for bound register masks
768 const RegMask &lrgmask = lrg.mask(); 768 const RegMask &lrgmask = lrg.mask();
769 if (lrgmask.is_bound(ireg)) { 769 if (lrgmask.is_bound(ireg)) {
959 // Check for bound register masks 959 // Check for bound register masks
960 const RegMask &lrgmask = lrg.mask(); 960 const RegMask &lrgmask = lrg.mask();
961 int kreg = n->in(k)->ideal_reg(); 961 int kreg = n->in(k)->ideal_reg();
962 bool is_vect = RegMask::is_vector(kreg); 962 bool is_vect = RegMask::is_vector(kreg);
963 assert(n->in(k)->bottom_type()->isa_vect() == NULL || 963 assert(n->in(k)->bottom_type()->isa_vect() == NULL ||
964 is_vect || kreg == Op_RegD || kreg == Op_RegL, 964 is_vect || kreg == Op_RegD,
965 "vector must be in vector registers"); 965 "vector must be in vector registers");
966 if (lrgmask.is_bound(kreg)) 966 if (lrgmask.is_bound(kreg))
967 lrg._is_bound = 1; 967 lrg._is_bound = 1;
968 968
969 // If this use of a double forces a mis-aligned double, 969 // If this use of a double forces a mis-aligned double,
1680 // Initialize it once and make it shared: 1680 // Initialize it once and make it shared:
1681 // set control to _root and place it into Start block 1681 // set control to _root and place it into Start block
1682 // (where top() node is placed). 1682 // (where top() node is placed).
1683 base->init_req(0, _cfg.get_root_node()); 1683 base->init_req(0, _cfg.get_root_node());
1684 Block *startb = _cfg.get_block_for_node(C->top()); 1684 Block *startb = _cfg.get_block_for_node(C->top());
1685 uint node_pos = startb->find_node(C->top()); 1685 startb->insert_node(base, startb->find_node(C->top()));
1686 startb->insert_node(base, node_pos);
1687 _cfg.map_node_to_block(base, startb); 1686 _cfg.map_node_to_block(base, startb);
1688 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet"); 1687 assert(_lrg_map.live_range_id(base) == 0, "should not have LRG yet");
1689
1690 // The loadConP0 might have projection nodes depending on architecture
1691 // Add the projection nodes to the CFG
1692 for (DUIterator_Fast imax, i = base->fast_outs(imax); i < imax; i++) {
1693 Node* use = base->fast_out(i);
1694 if (use->is_MachProj()) {
1695 startb->insert_node(use, ++node_pos);
1696 _cfg.map_node_to_block(use, startb);
1697 new_lrg(use, maxlrg++);
1698 }
1699 }
1700 } 1688 }
1701 if (_lrg_map.live_range_id(base) == 0) { 1689 if (_lrg_map.live_range_id(base) == 0) {
1702 new_lrg(base, maxlrg++); 1690 new_lrg(base, maxlrg++);
1703 } 1691 }
1704 assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared"); 1692 assert(base->in(0) == _cfg.get_root_node() && _cfg.get_block_for_node(base) == _cfg.get_block_for_node(C->top()), "base NULL should be shared");
1797 Node *phi = n->in(1); 1785 Node *phi = n->in(1);
1798 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) { 1786 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) {
1799 Block *phi_block = _cfg.get_block_for_node(phi); 1787 Block *phi_block = _cfg.get_block_for_node(phi);
1800 if (_cfg.get_block_for_node(phi_block->pred(2)) == block) { 1788 if (_cfg.get_block_for_node(phi_block->pred(2)) == block) {
1801 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI]; 1789 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI];
1802 Node *spill = new (C) MachSpillCopyNode(MachSpillCopyNode::LoopPhiInput, phi, *mask, *mask); 1790 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask );
1803 insert_proj( phi_block, 1, spill, maxlrg++ ); 1791 insert_proj( phi_block, 1, spill, maxlrg++ );
1804 n->set_req(1,spill); 1792 n->set_req(1,spill);
1805 must_recompute_live = true; 1793 must_recompute_live = true;
1806 } 1794 }
1807 } 1795 }