comparison src/share/vm/opto/machnode.hpp @ 14909:4ca6dc0799b6

Backout jdk9 merge
author Gilles Duboscq <duboscq@ssw.jku.at>
date Tue, 01 Apr 2014 13:57:07 +0200
parents 04e7587c97dc
children 52b4284cb496
comparison
equal deleted inserted replaced
14908:8db6e76cb658 14909:4ca6dc0799b6
29 #include "opto/matcher.hpp" 29 #include "opto/matcher.hpp"
30 #include "opto/multnode.hpp" 30 #include "opto/multnode.hpp"
31 #include "opto/node.hpp" 31 #include "opto/node.hpp"
32 #include "opto/regmask.hpp" 32 #include "opto/regmask.hpp"
33 33
34 class BiasedLockingCounters;
35 class BufferBlob; 34 class BufferBlob;
36 class CodeBuffer; 35 class CodeBuffer;
37 class JVMState; 36 class JVMState;
38 class MachCallDynamicJavaNode; 37 class MachCallDynamicJavaNode;
39 class MachCallJavaNode; 38 class MachCallJavaNode;
101 } 100 }
102 XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const { 101 XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
103 return ::as_XMMRegister(reg(ra_, node, idx)); 102 return ::as_XMMRegister(reg(ra_, node, idx));
104 } 103 }
105 #endif 104 #endif
106 // CondRegister reg converter
107 #if defined(PPC64)
108 ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node) const {
109 return ::as_ConditionRegister(reg(ra_, node));
110 }
111 ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
112 return ::as_ConditionRegister(reg(ra_, node, idx));
113 }
114 #endif
115 105
116 virtual intptr_t constant() const; 106 virtual intptr_t constant() const;
117 virtual relocInfo::relocType constant_reloc() const; 107 virtual relocInfo::relocType constant_reloc() const;
118 virtual jdouble constantD() const; 108 virtual jdouble constantD() const;
119 virtual jfloat constantF() const; 109 virtual jfloat constantF() const;
163 // Methods to output the text version of the operand 153 // Methods to output the text version of the operand
164 virtual void int_format(PhaseRegAlloc *,const MachNode *node, outputStream *st) const = 0; 154 virtual void int_format(PhaseRegAlloc *,const MachNode *node, outputStream *st) const = 0;
165 virtual void ext_format(PhaseRegAlloc *,const MachNode *node,int idx, outputStream *st) const=0; 155 virtual void ext_format(PhaseRegAlloc *,const MachNode *node,int idx, outputStream *st) const=0;
166 156
167 virtual void dump_spec(outputStream *st) const; // Print per-operand info 157 virtual void dump_spec(outputStream *st) const; // Print per-operand info
168 158 #endif
169 // Check whether o is a valid oper.
170 static bool notAnOper(const MachOper *o) {
171 if (o == NULL) return true;
172 if (((intptr_t)o & 1) != 0) return true;
173 if (*(address*)o == badAddress) return true; // kill by Node::destruct
174 return false;
175 }
176 #endif // !PRODUCT
177 }; 159 };
178 160
179 //------------------------------MachNode--------------------------------------- 161 //------------------------------MachNode---------------------------------------
180 // Base type for all machine specific nodes. All node classes generated by the 162 // Base type for all machine specific nodes. All node classes generated by the
181 // ADLC inherit from this class. 163 // ADLC inherit from this class.
189 virtual int Opcode() const; // Always equal to MachNode 171 virtual int Opcode() const; // Always equal to MachNode
190 virtual uint rule() const = 0; // Machine-specific opcode 172 virtual uint rule() const = 0; // Machine-specific opcode
191 // Number of inputs which come before the first operand. 173 // Number of inputs which come before the first operand.
192 // Generally at least 1, to skip the Control input 174 // Generally at least 1, to skip the Control input
193 virtual uint oper_input_base() const { return 1; } 175 virtual uint oper_input_base() const { return 1; }
194 // Position of constant base node in node's inputs. -1 if
195 // no constant base node input.
196 virtual uint mach_constant_base_node_input() const { return (uint)-1; }
197 176
198 // Copy inputs and operands to new node of instruction. 177 // Copy inputs and operands to new node of instruction.
199 // Called from cisc_version() and short_branch_version(). 178 // Called from cisc_version() and short_branch_version().
200 // !!!! The method's body is defined in ad_<arch>.cpp file. 179 // !!!! The method's body is defined in ad_<arch>.cpp file.
201 void fill_new_machnode(MachNode *n, Compile* C) const; 180 void fill_new_machnode(MachNode *n, Compile* C) const;
214 // instruction implemented with a call 193 // instruction implemented with a call
215 bool has_call() const { return (flags() & Flag_has_call) != 0; } 194 bool has_call() const { return (flags() & Flag_has_call) != 0; }
216 195
217 // First index in _in[] corresponding to operand, or -1 if there is none 196 // First index in _in[] corresponding to operand, or -1 if there is none
218 int operand_index(uint operand) const; 197 int operand_index(uint operand) const;
219 int operand_index(const MachOper *oper) const;
220 198
221 // Register class input is expected in 199 // Register class input is expected in
222 virtual const RegMask &in_RegMask(uint) const; 200 virtual const RegMask &in_RegMask(uint) const;
223 201
224 // cisc-spillable instructions redefine for use by in_RegMask 202 // cisc-spillable instructions redefine for use by in_RegMask
240 MachOper **_opnds; 218 MachOper **_opnds;
241 uint num_opnds() const { return _num_opnds; } 219 uint num_opnds() const { return _num_opnds; }
242 220
243 // Emit bytes into cbuf 221 // Emit bytes into cbuf
244 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 222 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
245 // Expand node after register allocation.
246 // Node is replaced by several nodes in the postalloc expand phase.
247 // Corresponding methods are generated for nodes if they specify
248 // postalloc_expand. See block.cpp for more documentation.
249 virtual bool requires_postalloc_expand() const { return false; }
250 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
251 // Size of instruction in bytes 223 // Size of instruction in bytes
252 virtual uint size(PhaseRegAlloc *ra_) const; 224 virtual uint size(PhaseRegAlloc *ra_) const;
253 // Helper function that computes size by emitting code 225 // Helper function that computes size by emitting code
254 virtual uint emit_size(PhaseRegAlloc *ra_) const; 226 virtual uint emit_size(PhaseRegAlloc *ra_) const;
255 227
261 // instruction to properly align it. 233 // instruction to properly align it.
262 virtual int compute_padding(int current_offset) const { return 0; } 234 virtual int compute_padding(int current_offset) const { return 0; }
263 235
264 // Return number of relocatable values contained in this instruction 236 // Return number of relocatable values contained in this instruction
265 virtual int reloc() const { return 0; } 237 virtual int reloc() const { return 0; }
266
267 // Return number of words used for double constants in this instruction
268 virtual int ins_num_consts() const { return 0; }
269 238
270 // Hash and compare over operands. Used to do GVN on machine Nodes. 239 // Hash and compare over operands. Used to do GVN on machine Nodes.
271 virtual uint hash() const; 240 virtual uint hash() const;
272 virtual uint cmp( const Node &n ) const; 241 virtual uint cmp( const Node &n ) const;
273 242
322 291
323 // Get the pipeline info 292 // Get the pipeline info
324 static const Pipeline *pipeline_class(); 293 static const Pipeline *pipeline_class();
325 virtual const Pipeline *pipeline() const; 294 virtual const Pipeline *pipeline() const;
326 295
327 // Returns true if this node is a check that can be implemented with a trap.
328 virtual bool is_TrapBasedCheckNode() const { return false; }
329
330 #ifndef PRODUCT 296 #ifndef PRODUCT
331 virtual const char *Name() const = 0; // Machine-specific name 297 virtual const char *Name() const = 0; // Machine-specific name
332 virtual void dump_spec(outputStream *st) const; // Print per-node info 298 virtual void dump_spec(outputStream *st) const; // Print per-node info
333 void dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual 299 void dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual
334 #endif 300 #endif
388 } 354 }
389 virtual const class Type* bottom_type() const { return TypeRawPtr::NOTNULL; } 355 virtual const class Type* bottom_type() const { return TypeRawPtr::NOTNULL; }
390 virtual uint ideal_reg() const { return Op_RegP; } 356 virtual uint ideal_reg() const { return Op_RegP; }
391 virtual uint oper_input_base() const { return 1; } 357 virtual uint oper_input_base() const { return 1; }
392 358
393 virtual bool requires_postalloc_expand() const;
394 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
395
396 virtual void emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const; 359 virtual void emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const;
397 virtual uint size(PhaseRegAlloc* ra_) const; 360 virtual uint size(PhaseRegAlloc* ra_) const;
398 virtual bool pinned() const { return UseRDPCForConstantTableBase; } 361 virtual bool pinned() const { return UseRDPCForConstantTableBase; }
399 362
400 static const RegMask& static_out_RegMask() { return _out_RegMask; } 363 static const RegMask& static_out_RegMask() { return _out_RegMask; }
430 return MachConstantBaseNode::static_out_RegMask(); 393 return MachConstantBaseNode::static_out_RegMask();
431 return MachNode::in_RegMask(idx); 394 return MachNode::in_RegMask(idx);
432 } 395 }
433 396
434 // Input edge of MachConstantBaseNode. 397 // Input edge of MachConstantBaseNode.
435 virtual uint mach_constant_base_node_input() const { return req() - 1; } 398 uint mach_constant_base_node_input() const { return req() - 1; }
436 399
437 int constant_offset(); 400 int constant_offset();
438 int constant_offset() const { return ((MachConstantNode*) this)->constant_offset(); } 401 int constant_offset() const { return ((MachConstantNode*) this)->constant_offset(); }
439 // Unchecked version to avoid assertions in debug output.
440 int constant_offset_unchecked() const;
441 }; 402 };
442 403
443 //------------------------------MachUEPNode----------------------------------- 404 //------------------------------MachUEPNode-----------------------------------
444 // Machine Unvalidated Entry Point Node 405 // Machine Unvalidated Entry Point Node
445 class MachUEPNode : public MachIdealNode { 406 class MachUEPNode : public MachIdealNode {
518 479
519 //------------------------------MachSpillCopyNode------------------------------ 480 //------------------------------MachSpillCopyNode------------------------------
520 // Machine SpillCopy Node. Copies 1 or 2 words from any location to any 481 // Machine SpillCopy Node. Copies 1 or 2 words from any location to any
521 // location (stack or register). 482 // location (stack or register).
522 class MachSpillCopyNode : public MachIdealNode { 483 class MachSpillCopyNode : public MachIdealNode {
523 public:
524 enum SpillType {
525 TwoAddress, // Inserted when coalescing of a two-address-instruction node and its input fails
526 PhiInput, // Inserted when coalescing of a phi node and its input fails
527 DebugUse, // Inserted as debug info spills to safepoints in non-frequent blocks
528 LoopPhiInput, // Pre-split compares of loop-phis
529 Definition, // An lrg marked as spilled will be spilled to memory right after its definition,
530 // if in high pressure region or the lrg is bound
531 RegToReg, // A register to register move
532 RegToMem, // A register to memory move
533 MemToReg, // A memory to register move
534 PhiLocationDifferToInputLocation, // When coalescing phi nodes in PhaseChaitin::Split(), a move spill is inserted if
535 // the phi and its input resides at different locations (i.e. reg or mem)
536 BasePointerToMem, // Spill base pointer to memory at safepoint
537 InputToRematerialization, // When rematerializing a node we stretch the inputs live ranges, and they might be
538 // stretched beyond a new definition point, therefore we split out new copies instead
539 CallUse, // Spill use at a call
540 Bound // An lrg marked as spill that is bound and needs to be spilled at a use
541 };
542 private:
543 const RegMask *_in; // RegMask for input 484 const RegMask *_in; // RegMask for input
544 const RegMask *_out; // RegMask for output 485 const RegMask *_out; // RegMask for output
545 const Type *_type; 486 const Type *_type;
546 const SpillType _spill_type; 487 public:
547 public: 488 MachSpillCopyNode( Node *n, const RegMask &in, const RegMask &out ) :
548 MachSpillCopyNode(SpillType spill_type, Node *n, const RegMask &in, const RegMask &out ) : 489 MachIdealNode(), _in(&in), _out(&out), _type(n->bottom_type()) {
549 MachIdealNode(), _spill_type(spill_type), _in(&in), _out(&out), _type(n->bottom_type()) {
550 init_class_id(Class_MachSpillCopy); 490 init_class_id(Class_MachSpillCopy);
551 init_flags(Flag_is_Copy); 491 init_flags(Flag_is_Copy);
552 add_req(NULL); 492 add_req(NULL);
553 add_req(n); 493 add_req(n);
554 } 494 }
563 uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const; 503 uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const;
564 504
565 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 505 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
566 virtual uint size(PhaseRegAlloc *ra_) const; 506 virtual uint size(PhaseRegAlloc *ra_) const;
567 507
568 508 #ifndef PRODUCT
569 #ifndef PRODUCT 509 virtual const char *Name() const { return "MachSpillCopy"; }
570 virtual const char *Name() const {
571 switch (_spill_type) {
572 case TwoAddress:
573 return "TwoAddressSpillCopy";
574 case PhiInput:
575 return "PhiInputSpillCopy";
576 case DebugUse:
577 return "DebugUseSpillCopy";
578 case LoopPhiInput:
579 return "LoopPhiInputSpillCopy";
580 case Definition:
581 return "DefinitionSpillCopy";
582 case RegToReg:
583 return "RegToRegSpillCopy";
584 case RegToMem:
585 return "RegToMemSpillCopy";
586 case MemToReg:
587 return "MemToRegSpillCopy";
588 case PhiLocationDifferToInputLocation:
589 return "PhiLocationDifferToInputLocationSpillCopy";
590 case BasePointerToMem:
591 return "BasePointerToMemSpillCopy";
592 case InputToRematerialization:
593 return "InputToRematerializationSpillCopy";
594 case CallUse:
595 return "CallUseSpillCopy";
596 case Bound:
597 return "BoundSpillCopy";
598 default:
599 assert(false, "Must have valid spill type");
600 return "MachSpillCopy";
601 }
602 }
603
604 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 510 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
605 #endif 511 #endif
606 }; 512 };
607 513
608 //------------------------------MachBranchNode-------------------------------- 514 //------------------------------MachBranchNode--------------------------------