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comparison src/cpu/x86/vm/assembler_x86_64.hpp @ 360:5d254928c888

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Merge
author ysr
date Wed, 27 Aug 2008 11:20:46 -0700
parents 1ee8caae33af
children
comparison
equal deleted inserted replaced
341:d60e4e6d7f72 360:5d254928c888
220 // Address. An index of 4 (rsp) corresponds to having no index, so convert 220 // Address. An index of 4 (rsp) corresponds to having no index, so convert
221 // that to noreg for the Address constructor. 221 // that to noreg for the Address constructor.
222 static Address make_raw(int base, int index, int scale, int disp); 222 static Address make_raw(int base, int index, int scale, int disp);
223 223
224 static Address make_array(ArrayAddress); 224 static Address make_array(ArrayAddress);
225 Register base() const {
226 return _base;
227 }
228
229 Register index() const {
230 return _index;
231 }
232
233 int disp() const {
234 return _disp;
235 }
236
225 237
226 private: 238 private:
227 bool base_needs_rex() const { 239 bool base_needs_rex() const {
228 return _base != noreg && _base->encoding() >= 8; 240 return _base != noreg && _base->encoding() >= 8;
229 } 241 }
1202 void store_check(Register obj, Address dst); // same as above, dst 1214 void store_check(Register obj, Address dst); // same as above, dst
1203 // is exact store 1215 // is exact store
1204 // location (reg. is 1216 // location (reg. is
1205 // destroyed) 1217 // destroyed)
1206 1218
1219 void g1_write_barrier_pre(Register obj, Register tmp, Register tmp2, bool tosca_live );
1220 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp, Register tmp2);
1221
1207 // split store_check(Register obj) to enhance instruction interleaving 1222 // split store_check(Register obj) to enhance instruction interleaving
1208 void store_check_part_1(Register obj); 1223 void store_check_part_1(Register obj);
1209 void store_check_part_2(Register obj); 1224 void store_check_part_2(Register obj);
1210 1225
1211 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 1226 // C 'boolean' to Java boolean: x == 0 ? 0 : 1