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comparison src/cpu/x86/vm/x86_64.ad @ 4761:65149e74c706

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7121648: Use 3-operands SIMD instructions on x86 with AVX Summary: Use 3-operands SIMD instructions in C2 generated code for machines with AVX. Reviewed-by: never
author kvn
date Tue, 20 Dec 2011 00:55:02 -0800
parents 127b3692c168
children 069ab3f976d3
comparison
equal deleted inserted replaced
4760:669f6a7d5b70 4761:65149e74c706
9871 emit_cmpfp3(_masm, $dst$$Register); 9871 emit_cmpfp3(_masm, $dst$$Register);
9872 %} 9872 %}
9873 ins_pipe(pipe_slow); 9873 ins_pipe(pipe_slow);
9874 %} 9874 %}
9875 9875
9876 instruct addF_reg(regF dst, regF src)
9877 %{
9878 match(Set dst (AddF dst src));
9879
9880 format %{ "addss $dst, $src" %}
9881 ins_cost(150); // XXX
9882 ins_encode %{
9883 __ addss($dst$$XMMRegister, $src$$XMMRegister);
9884 %}
9885 ins_pipe(pipe_slow);
9886 %}
9887
9888 instruct addF_mem(regF dst, memory src)
9889 %{
9890 match(Set dst (AddF dst (LoadF src)));
9891
9892 format %{ "addss $dst, $src" %}
9893 ins_cost(150); // XXX
9894 ins_encode %{
9895 __ addss($dst$$XMMRegister, $src$$Address);
9896 %}
9897 ins_pipe(pipe_slow);
9898 %}
9899
9900 instruct addF_imm(regF dst, immF con) %{
9901 match(Set dst (AddF dst con));
9902 format %{ "addss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
9903 ins_cost(150); // XXX
9904 ins_encode %{
9905 __ addss($dst$$XMMRegister, $constantaddress($con));
9906 %}
9907 ins_pipe(pipe_slow);
9908 %}
9909
9910 instruct addD_reg(regD dst, regD src)
9911 %{
9912 match(Set dst (AddD dst src));
9913
9914 format %{ "addsd $dst, $src" %}
9915 ins_cost(150); // XXX
9916 ins_encode %{
9917 __ addsd($dst$$XMMRegister, $src$$XMMRegister);
9918 %}
9919 ins_pipe(pipe_slow);
9920 %}
9921
9922 instruct addD_mem(regD dst, memory src)
9923 %{
9924 match(Set dst (AddD dst (LoadD src)));
9925
9926 format %{ "addsd $dst, $src" %}
9927 ins_cost(150); // XXX
9928 ins_encode %{
9929 __ addsd($dst$$XMMRegister, $src$$Address);
9930 %}
9931 ins_pipe(pipe_slow);
9932 %}
9933
9934 instruct addD_imm(regD dst, immD con) %{
9935 match(Set dst (AddD dst con));
9936 format %{ "addsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
9937 ins_cost(150); // XXX
9938 ins_encode %{
9939 __ addsd($dst$$XMMRegister, $constantaddress($con));
9940 %}
9941 ins_pipe(pipe_slow);
9942 %}
9943
9944 instruct subF_reg(regF dst, regF src)
9945 %{
9946 match(Set dst (SubF dst src));
9947
9948 format %{ "subss $dst, $src" %}
9949 ins_cost(150); // XXX
9950 ins_encode %{
9951 __ subss($dst$$XMMRegister, $src$$XMMRegister);
9952 %}
9953 ins_pipe(pipe_slow);
9954 %}
9955
9956 instruct subF_mem(regF dst, memory src)
9957 %{
9958 match(Set dst (SubF dst (LoadF src)));
9959
9960 format %{ "subss $dst, $src" %}
9961 ins_cost(150); // XXX
9962 ins_encode %{
9963 __ subss($dst$$XMMRegister, $src$$Address);
9964 %}
9965 ins_pipe(pipe_slow);
9966 %}
9967
9968 instruct subF_imm(regF dst, immF con) %{
9969 match(Set dst (SubF dst con));
9970 format %{ "subss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
9971 ins_cost(150); // XXX
9972 ins_encode %{
9973 __ subss($dst$$XMMRegister, $constantaddress($con));
9974 %}
9975 ins_pipe(pipe_slow);
9976 %}
9977
9978 instruct subD_reg(regD dst, regD src)
9979 %{
9980 match(Set dst (SubD dst src));
9981
9982 format %{ "subsd $dst, $src" %}
9983 ins_cost(150); // XXX
9984 ins_encode %{
9985 __ subsd($dst$$XMMRegister, $src$$XMMRegister);
9986 %}
9987 ins_pipe(pipe_slow);
9988 %}
9989
9990 instruct subD_mem(regD dst, memory src)
9991 %{
9992 match(Set dst (SubD dst (LoadD src)));
9993
9994 format %{ "subsd $dst, $src" %}
9995 ins_cost(150); // XXX
9996 ins_encode %{
9997 __ subsd($dst$$XMMRegister, $src$$Address);
9998 %}
9999 ins_pipe(pipe_slow);
10000 %}
10001
10002 instruct subD_imm(regD dst, immD con) %{
10003 match(Set dst (SubD dst con));
10004 format %{ "subsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
10005 ins_cost(150); // XXX
10006 ins_encode %{
10007 __ subsd($dst$$XMMRegister, $constantaddress($con));
10008 %}
10009 ins_pipe(pipe_slow);
10010 %}
10011
10012 instruct mulF_reg(regF dst, regF src)
10013 %{
10014 match(Set dst (MulF dst src));
10015
10016 format %{ "mulss $dst, $src" %}
10017 ins_cost(150); // XXX
10018 ins_encode %{
10019 __ mulss($dst$$XMMRegister, $src$$XMMRegister);
10020 %}
10021 ins_pipe(pipe_slow);
10022 %}
10023
10024 instruct mulF_mem(regF dst, memory src)
10025 %{
10026 match(Set dst (MulF dst (LoadF src)));
10027
10028 format %{ "mulss $dst, $src" %}
10029 ins_cost(150); // XXX
10030 ins_encode %{
10031 __ mulss($dst$$XMMRegister, $src$$Address);
10032 %}
10033 ins_pipe(pipe_slow);
10034 %}
10035
10036 instruct mulF_imm(regF dst, immF con) %{
10037 match(Set dst (MulF dst con));
10038 format %{ "mulss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
10039 ins_cost(150); // XXX
10040 ins_encode %{
10041 __ mulss($dst$$XMMRegister, $constantaddress($con));
10042 %}
10043 ins_pipe(pipe_slow);
10044 %}
10045
10046 instruct mulD_reg(regD dst, regD src)
10047 %{
10048 match(Set dst (MulD dst src));
10049
10050 format %{ "mulsd $dst, $src" %}
10051 ins_cost(150); // XXX
10052 ins_encode %{
10053 __ mulsd($dst$$XMMRegister, $src$$XMMRegister);
10054 %}
10055 ins_pipe(pipe_slow);
10056 %}
10057
10058 instruct mulD_mem(regD dst, memory src)
10059 %{
10060 match(Set dst (MulD dst (LoadD src)));
10061
10062 format %{ "mulsd $dst, $src" %}
10063 ins_cost(150); // XXX
10064 ins_encode %{
10065 __ mulsd($dst$$XMMRegister, $src$$Address);
10066 %}
10067 ins_pipe(pipe_slow);
10068 %}
10069
10070 instruct mulD_imm(regD dst, immD con) %{
10071 match(Set dst (MulD dst con));
10072 format %{ "mulsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
10073 ins_cost(150); // XXX
10074 ins_encode %{
10075 __ mulsd($dst$$XMMRegister, $constantaddress($con));
10076 %}
10077 ins_pipe(pipe_slow);
10078 %}
10079
10080 instruct divF_reg(regF dst, regF src)
10081 %{
10082 match(Set dst (DivF dst src));
10083
10084 format %{ "divss $dst, $src" %}
10085 ins_cost(150); // XXX
10086 ins_encode %{
10087 __ divss($dst$$XMMRegister, $src$$XMMRegister);
10088 %}
10089 ins_pipe(pipe_slow);
10090 %}
10091
10092 instruct divF_mem(regF dst, memory src)
10093 %{
10094 match(Set dst (DivF dst (LoadF src)));
10095
10096 format %{ "divss $dst, $src" %}
10097 ins_cost(150); // XXX
10098 ins_encode %{
10099 __ divss($dst$$XMMRegister, $src$$Address);
10100 %}
10101 ins_pipe(pipe_slow);
10102 %}
10103
10104 instruct divF_imm(regF dst, immF con) %{
10105 match(Set dst (DivF dst con));
10106 format %{ "divss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
10107 ins_cost(150); // XXX
10108 ins_encode %{
10109 __ divss($dst$$XMMRegister, $constantaddress($con));
10110 %}
10111 ins_pipe(pipe_slow);
10112 %}
10113
10114 instruct divD_reg(regD dst, regD src)
10115 %{
10116 match(Set dst (DivD dst src));
10117
10118 format %{ "divsd $dst, $src" %}
10119 ins_cost(150); // XXX
10120 ins_encode %{
10121 __ divsd($dst$$XMMRegister, $src$$XMMRegister);
10122 %}
10123 ins_pipe(pipe_slow);
10124 %}
10125
10126 instruct divD_mem(regD dst, memory src)
10127 %{
10128 match(Set dst (DivD dst (LoadD src)));
10129
10130 format %{ "divsd $dst, $src" %}
10131 ins_cost(150); // XXX
10132 ins_encode %{
10133 __ divsd($dst$$XMMRegister, $src$$Address);
10134 %}
10135 ins_pipe(pipe_slow);
10136 %}
10137
10138 instruct divD_imm(regD dst, immD con) %{
10139 match(Set dst (DivD dst con));
10140 format %{ "divsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
10141 ins_cost(150); // XXX
10142 ins_encode %{
10143 __ divsd($dst$$XMMRegister, $constantaddress($con));
10144 %}
10145 ins_pipe(pipe_slow);
10146 %}
10147
10148 instruct sqrtF_reg(regF dst, regF src)
10149 %{
10150 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
10151
10152 format %{ "sqrtss $dst, $src" %}
10153 ins_cost(150); // XXX
10154 ins_encode %{
10155 __ sqrtss($dst$$XMMRegister, $src$$XMMRegister);
10156 %}
10157 ins_pipe(pipe_slow);
10158 %}
10159
10160 instruct sqrtF_mem(regF dst, memory src)
10161 %{
10162 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF src)))));
10163
10164 format %{ "sqrtss $dst, $src" %}
10165 ins_cost(150); // XXX
10166 ins_encode %{
10167 __ sqrtss($dst$$XMMRegister, $src$$Address);
10168 %}
10169 ins_pipe(pipe_slow);
10170 %}
10171
10172 instruct sqrtF_imm(regF dst, immF con) %{
10173 match(Set dst (ConvD2F (SqrtD (ConvF2D con))));
10174 format %{ "sqrtss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
10175 ins_cost(150); // XXX
10176 ins_encode %{
10177 __ sqrtss($dst$$XMMRegister, $constantaddress($con));
10178 %}
10179 ins_pipe(pipe_slow);
10180 %}
10181
10182 instruct sqrtD_reg(regD dst, regD src)
10183 %{
10184 match(Set dst (SqrtD src));
10185
10186 format %{ "sqrtsd $dst, $src" %}
10187 ins_cost(150); // XXX
10188 ins_encode %{
10189 __ sqrtsd($dst$$XMMRegister, $src$$XMMRegister);
10190 %}
10191 ins_pipe(pipe_slow);
10192 %}
10193
10194 instruct sqrtD_mem(regD dst, memory src)
10195 %{
10196 match(Set dst (SqrtD (LoadD src)));
10197
10198 format %{ "sqrtsd $dst, $src" %}
10199 ins_cost(150); // XXX
10200 ins_encode %{
10201 __ sqrtsd($dst$$XMMRegister, $src$$Address);
10202 %}
10203 ins_pipe(pipe_slow);
10204 %}
10205
10206 instruct sqrtD_imm(regD dst, immD con) %{
10207 match(Set dst (SqrtD con));
10208 format %{ "sqrtsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
10209 ins_cost(150); // XXX
10210 ins_encode %{
10211 __ sqrtsd($dst$$XMMRegister, $constantaddress($con));
10212 %}
10213 ins_pipe(pipe_slow);
10214 %}
10215
10216 instruct absF_reg(regF dst)
10217 %{
10218 match(Set dst (AbsF dst));
10219 ins_cost(150); // XXX
10220 format %{ "andps $dst, [0x7fffffff]\t# abs float by sign masking" %}
10221 ins_encode %{
10222 __ andps($dst$$XMMRegister,
10223 ExternalAddress((address) StubRoutines::x86::float_sign_mask()));
10224 %}
10225 ins_pipe(pipe_slow);
10226 %}
10227
10228 instruct absD_reg(regD dst)
10229 %{
10230 match(Set dst (AbsD dst));
10231 ins_cost(150); // XXX
10232 format %{ "andpd $dst, [0x7fffffffffffffff]\t"
10233 "# abs double by sign masking" %}
10234 ins_encode %{
10235 __ andpd($dst$$XMMRegister,
10236 ExternalAddress((address) StubRoutines::x86::double_sign_mask()));
10237 %}
10238 ins_pipe(pipe_slow);
10239 %}
10240
10241 instruct negF_reg(regF dst)
10242 %{
10243 match(Set dst (NegF dst));
10244 ins_cost(150); // XXX
10245 format %{ "xorps $dst, [0x80000000]\t# neg float by sign flipping" %}
10246 ins_encode %{
10247 __ xorps($dst$$XMMRegister,
10248 ExternalAddress((address) StubRoutines::x86::float_sign_flip()));
10249 %}
10250 ins_pipe(pipe_slow);
10251 %}
10252
10253 instruct negD_reg(regD dst)
10254 %{
10255 match(Set dst (NegD dst));
10256 ins_cost(150); // XXX
10257 format %{ "xorpd $dst, [0x8000000000000000]\t"
10258 "# neg double by sign flipping" %}
10259 ins_encode %{
10260 __ xorpd($dst$$XMMRegister,
10261 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10262 %}
10263 ins_pipe(pipe_slow);
10264 %}
10265
10266 // -----------Trig and Trancendental Instructions------------------------------ 9876 // -----------Trig and Trancendental Instructions------------------------------
10267 instruct cosD_reg(regD dst) %{ 9877 instruct cosD_reg(regD dst) %{
10268 match(Set dst (CosD dst)); 9878 match(Set dst (CosD dst));
10269 9879
10270 format %{ "dcos $dst\n\t" %} 9880 format %{ "dcos $dst\n\t" %}