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comparison src/share/vm/c1/c1_LIR.cpp @ 6795:7eca5de9e0b6

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7023898: Intrinsify AtomicLongFieldUpdater.getAndIncrement() Summary: use shorter instruction sequences for atomic add and atomic exchange when possible. Reviewed-by: kvn, jrose
author roland
date Thu, 20 Sep 2012 16:49:17 +0200
parents 8a02ca5e5576
children 203f64878aab
comparison
equal deleted inserted replaced
6794:8ae8f9dd7099 6795:7eca5de9e0b6
262 262
263 void LIR_Op2::verify() const { 263 void LIR_Op2::verify() const {
264 #ifdef ASSERT 264 #ifdef ASSERT
265 switch (code()) { 265 switch (code()) {
266 case lir_cmove: 266 case lir_cmove:
267 case lir_xchg:
267 break; 268 break;
268 269
269 default: 270 default:
270 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), 271 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
271 "can't produce oops from arith"); 272 "can't produce oops from arith");
628 case lir_logic_or: 629 case lir_logic_or:
629 case lir_logic_xor: 630 case lir_logic_xor:
630 case lir_shl: 631 case lir_shl:
631 case lir_shr: 632 case lir_shr:
632 case lir_ushr: 633 case lir_ushr:
634 case lir_xadd:
635 case lir_xchg:
633 { 636 {
634 assert(op->as_Op2() != NULL, "must be"); 637 assert(op->as_Op2() != NULL, "must be");
635 LIR_Op2* op2 = (LIR_Op2*)op; 638 LIR_Op2* op2 = (LIR_Op2*)op;
636 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 639 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
637 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 640 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
639 if (op2->_info) do_info(op2->_info); 642 if (op2->_info) do_info(op2->_info);
640 if (op2->_opr1->is_valid()) do_input(op2->_opr1); 643 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
641 if (op2->_opr2->is_valid()) do_input(op2->_opr2); 644 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
642 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 645 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
643 if (op2->_result->is_valid()) do_output(op2->_result); 646 if (op2->_result->is_valid()) do_output(op2->_result);
647 if (op->code() == lir_xchg || op->code() == lir_xadd) {
648 // on ARM and PPC, return value is loaded first so could
649 // destroy inputs. On other platforms that implement those
650 // (x86, sparc), the extra constrainsts are harmless.
651 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
652 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
653 }
644 654
645 break; 655 break;
646 } 656 }
647 657
648 // special handling for cmove: right input operand must not be equal 658 // special handling for cmove: right input operand must not be equal
1731 case lir_logic_xor: s = "logic_xor"; break; 1741 case lir_logic_xor: s = "logic_xor"; break;
1732 case lir_shl: s = "shift_left"; break; 1742 case lir_shl: s = "shift_left"; break;
1733 case lir_shr: s = "shift_right"; break; 1743 case lir_shr: s = "shift_right"; break;
1734 case lir_ushr: s = "ushift_right"; break; 1744 case lir_ushr: s = "ushift_right"; break;
1735 case lir_alloc_array: s = "alloc_array"; break; 1745 case lir_alloc_array: s = "alloc_array"; break;
1746 case lir_xadd: s = "xadd"; break;
1747 case lir_xchg: s = "xchg"; break;
1736 // LIR_Op3 1748 // LIR_Op3
1737 case lir_idiv: s = "idiv"; break; 1749 case lir_idiv: s = "idiv"; break;
1738 case lir_irem: s = "irem"; break; 1750 case lir_irem: s = "irem"; break;
1739 // LIR_OpJavaCall 1751 // LIR_OpJavaCall
1740 case lir_static_call: s = "static"; break; 1752 case lir_static_call: s = "static"; break;