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comparison src/cpu/x86/vm/x86_32.ad @ 6143:8b0a4867acf0

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7174218: remove AtomicLongCSImpl intrinsics Reviewed-by: kvn, twisti Contributed-by: Krystal Mok <sajia@taobao.com>
author twisti
date Tue, 12 Jun 2012 14:31:44 -0700
parents ccaa67adfe5b
children 8c92982cbbc4
comparison
equal deleted inserted replaced
6142:121e5708ae96 6143:8b0a4867acf0
7796 ins_cost(125); 7796 ins_cost(125);
7797 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} 7797 format %{ "MOV $dst,$mem\t# Load ptr. locked" %}
7798 opcode(0x8B); 7798 opcode(0x8B);
7799 ins_encode( OpcP, RegMem(dst,mem)); 7799 ins_encode( OpcP, RegMem(dst,mem));
7800 ins_pipe( ialu_reg_mem ); 7800 ins_pipe( ialu_reg_mem );
7801 %}
7802
7803 // LoadLong-locked - same as a volatile long load when used with compare-swap
7804 instruct loadLLocked(stackSlotL dst, memory mem) %{
7805 predicate(UseSSE<=1);
7806 match(Set dst (LoadLLocked mem));
7807
7808 ins_cost(200);
7809 format %{ "FILD $mem\t# Atomic volatile long load\n\t"
7810 "FISTp $dst" %}
7811 ins_encode(enc_loadL_volatile(mem,dst));
7812 ins_pipe( fpu_reg_mem );
7813 %}
7814
7815 instruct loadLX_Locked(stackSlotL dst, memory mem, regD tmp) %{
7816 predicate(UseSSE>=2);
7817 match(Set dst (LoadLLocked mem));
7818 effect(TEMP tmp);
7819 ins_cost(180);
7820 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7821 "MOVSD $dst,$tmp" %}
7822 ins_encode %{
7823 __ movdbl($tmp$$XMMRegister, $mem$$Address);
7824 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister);
7825 %}
7826 ins_pipe( pipe_slow );
7827 %}
7828
7829 instruct loadLX_reg_Locked(eRegL dst, memory mem, regD tmp) %{
7830 predicate(UseSSE>=2);
7831 match(Set dst (LoadLLocked mem));
7832 effect(TEMP tmp);
7833 ins_cost(160);
7834 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t"
7835 "MOVD $dst.lo,$tmp\n\t"
7836 "PSRLQ $tmp,32\n\t"
7837 "MOVD $dst.hi,$tmp" %}
7838 ins_encode %{
7839 __ movdbl($tmp$$XMMRegister, $mem$$Address);
7840 __ movdl($dst$$Register, $tmp$$XMMRegister);
7841 __ psrlq($tmp$$XMMRegister, 32);
7842 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister);
7843 %}
7844 ins_pipe( pipe_slow );
7845 %} 7801 %}
7846 7802
7847 // Conditional-store of the updated heap-top. 7803 // Conditional-store of the updated heap-top.
7848 // Used during allocation of the shared heap. 7804 // Used during allocation of the shared heap.
7849 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. 7805 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.