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comparison src/cpu/ppc/vm/register_ppc.hpp @ 14726:92aa6797d639

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Backed out merge changeset: b51e29501f30 Backed out merge revision to its first parent (8f483e200405)
author Doug Simon <doug.simon@oracle.com>
date Mon, 24 Mar 2014 21:30:43 +0100
parents 58cf34613a72
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14719:0bdd0d157040 14726:92aa6797d639
1 /* 1 /*
2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved. 2 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2014 SAP AG. All rights reserved. 3 * Copyright 2012, 2013 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 * 5 *
6 * This code is free software; you can redistribute it and/or modify it 6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as 7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
577 #define F13_ARG13 AS_REGISTER(FloatRegister, F13) 577 #define F13_ARG13 AS_REGISTER(FloatRegister, F13)
578 #endif 578 #endif
579 579
580 // Register declarations to be used in frame manager assembly code. 580 // Register declarations to be used in frame manager assembly code.
581 // Use only non-volatile registers in order to keep values across C-calls. 581 // Use only non-volatile registers in order to keep values across C-calls.
582 #ifdef CC_INTERP
583 REGISTER_DECLARATION(Register, R14_state, R14); // address of new cInterpreter. 582 REGISTER_DECLARATION(Register, R14_state, R14); // address of new cInterpreter.
584 REGISTER_DECLARATION(Register, R15_prev_state, R15); // address of old cInterpreter 583 REGISTER_DECLARATION(Register, R15_prev_state, R15); // address of old cInterpreter
585 #else // CC_INTERP
586 REGISTER_DECLARATION(Register, R14_bcp, R14);
587 REGISTER_DECLARATION(Register, R15_esp, R15);
588 REGISTER_DECLARATION(FloatRegister, F15_ftos, F15);
589 #endif // CC_INTERP
590 REGISTER_DECLARATION(Register, R16_thread, R16); // address of current thread 584 REGISTER_DECLARATION(Register, R16_thread, R16); // address of current thread
591 REGISTER_DECLARATION(Register, R17_tos, R17); // address of Java tos (prepushed). 585 REGISTER_DECLARATION(Register, R17_tos, R17); // address of Java tos (prepushed).
592 REGISTER_DECLARATION(Register, R18_locals, R18); // address of first param slot (receiver). 586 REGISTER_DECLARATION(Register, R18_locals, R18); // address of first param slot (receiver).
593 REGISTER_DECLARATION(Register, R19_method, R19); // address of current method 587 REGISTER_DECLARATION(Register, R19_method, R19); // address of current method
594 #ifndef DONT_USE_REGISTER_DEFINES 588 #ifndef DONT_USE_REGISTER_DEFINES
595 #ifdef CC_INTERP
596 #define R14_state AS_REGISTER(Register, R14) 589 #define R14_state AS_REGISTER(Register, R14)
597 #define R15_prev_state AS_REGISTER(Register, R15) 590 #define R15_prev_state AS_REGISTER(Register, R15)
598 #else // CC_INTERP
599 #define R14_bcp AS_REGISTER(Register, R14)
600 #define R15_esp AS_REGISTER(Register, R15)
601 #define F15_ftos AS_REGISTER(FloatRegister, F15)
602 #endif // CC_INTERP
603 #define R16_thread AS_REGISTER(Register, R16) 591 #define R16_thread AS_REGISTER(Register, R16)
604 #define R17_tos AS_REGISTER(Register, R17) 592 #define R17_tos AS_REGISTER(Register, R17)
605 #define R18_locals AS_REGISTER(Register, R18) 593 #define R18_locals AS_REGISTER(Register, R18)
606 #define R19_method AS_REGISTER(Register, R19) 594 #define R19_method AS_REGISTER(Register, R19)
607 #define R21_sender_SP AS_REGISTER(Register, R21) 595 #define R21_sender_SP AS_REGISTER(Register, R21)
618 REGISTER_DECLARATION(Register, R25_tmp5, R25); 606 REGISTER_DECLARATION(Register, R25_tmp5, R25);
619 REGISTER_DECLARATION(Register, R26_tmp6, R26); 607 REGISTER_DECLARATION(Register, R26_tmp6, R26);
620 REGISTER_DECLARATION(Register, R27_tmp7, R27); 608 REGISTER_DECLARATION(Register, R27_tmp7, R27);
621 REGISTER_DECLARATION(Register, R28_tmp8, R28); 609 REGISTER_DECLARATION(Register, R28_tmp8, R28);
622 REGISTER_DECLARATION(Register, R29_tmp9, R29); 610 REGISTER_DECLARATION(Register, R29_tmp9, R29);
623 #ifndef CC_INTERP
624 REGISTER_DECLARATION(Register, R24_dispatch_addr, R24);
625 REGISTER_DECLARATION(Register, R25_templateTableBase, R25);
626 REGISTER_DECLARATION(Register, R26_monitor, R26);
627 REGISTER_DECLARATION(Register, R27_constPoolCache, R27);
628 REGISTER_DECLARATION(Register, R28_mdx, R28);
629 #endif // CC_INTERP
630
631 #ifndef DONT_USE_REGISTER_DEFINES 611 #ifndef DONT_USE_REGISTER_DEFINES
632 #define R21_tmp1 AS_REGISTER(Register, R21) 612 #define R21_tmp1 AS_REGISTER(Register, R21)
633 #define R22_tmp2 AS_REGISTER(Register, R22) 613 #define R22_tmp2 AS_REGISTER(Register, R22)
634 #define R23_tmp3 AS_REGISTER(Register, R23) 614 #define R23_tmp3 AS_REGISTER(Register, R23)
635 #define R24_tmp4 AS_REGISTER(Register, R24) 615 #define R24_tmp4 AS_REGISTER(Register, R24)
636 #define R25_tmp5 AS_REGISTER(Register, R25) 616 #define R25_tmp5 AS_REGISTER(Register, R25)
637 #define R26_tmp6 AS_REGISTER(Register, R26) 617 #define R26_tmp6 AS_REGISTER(Register, R26)
638 #define R27_tmp7 AS_REGISTER(Register, R27) 618 #define R27_tmp7 AS_REGISTER(Register, R27)
639 #define R28_tmp8 AS_REGISTER(Register, R28) 619 #define R28_tmp8 AS_REGISTER(Register, R28)
640 #define R29_tmp9 AS_REGISTER(Register, R29) 620 #define R29_tmp9 AS_REGISTER(Register, R29)
641 #ifndef CC_INTERP
642 // Lmonitors : monitor pointer
643 // LcpoolCache: constant pool cache
644 // mdx: method data index
645 #define R24_dispatch_addr AS_REGISTER(Register, R24)
646 #define R25_templateTableBase AS_REGISTER(Register, R25)
647 #define R26_monitor AS_REGISTER(Register, R26)
648 #define R27_constPoolCache AS_REGISTER(Register, R27)
649 #define R28_mdx AS_REGISTER(Register, R28)
650 #endif
651 621
652 #define CCR4_is_synced AS_REGISTER(ConditionRegister, CCR4) 622 #define CCR4_is_synced AS_REGISTER(ConditionRegister, CCR4)
653 #endif 623 #endif
654 624
655 // Scratch registers are volatile. 625 // Scratch registers are volatile.