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comparison src/cpu/x86/vm/assembler_x86.hpp @ 14726:92aa6797d639

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Backed out merge changeset: b51e29501f30 Backed out merge revision to its first parent (8f483e200405)
author Doug Simon <doug.simon@oracle.com>
date Mon, 24 Mar 2014 21:30:43 +0100
parents b51e29501f30
children
comparison
equal deleted inserted replaced
14719:0bdd0d157040 14726:92aa6797d639
588 int dst_enc = dst->encoding(); 588 int dst_enc = dst->encoding();
589 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 589 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
590 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256); 590 vex_prefix(src, nds_enc, dst_enc, pre, VEX_OPCODE_0F, false, vector256);
591 } 591 }
592 592
593 void vex_prefix_0F38(Register dst, Register nds, Address src) {
594 bool vex_w = false;
595 bool vector256 = false;
596 vex_prefix(src, nds->encoding(), dst->encoding(),
597 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
598 }
599
600 void vex_prefix_0F38_q(Register dst, Register nds, Address src) {
601 bool vex_w = true;
602 bool vector256 = false;
603 vex_prefix(src, nds->encoding(), dst->encoding(),
604 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
605 }
606 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, 593 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
607 VexSimdPrefix pre, VexOpcode opc, 594 VexSimdPrefix pre, VexOpcode opc,
608 bool vex_w, bool vector256); 595 bool vex_w, bool vector256);
609 596
610 int vex_prefix_0F38_and_encode(Register dst, Register nds, Register src) {
611 bool vex_w = false;
612 bool vector256 = false;
613 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
614 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
615 }
616 int vex_prefix_0F38_and_encode_q(Register dst, Register nds, Register src) {
617 bool vex_w = true;
618 bool vector256 = false;
619 return vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(),
620 VEX_SIMD_NONE, VEX_OPCODE_0F_38, vex_w, vector256);
621 }
622 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, 597 int vex_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src,
623 VexSimdPrefix pre, bool vector256 = false, 598 VexSimdPrefix pre, bool vector256 = false,
624 VexOpcode opc = VEX_OPCODE_0F) { 599 VexOpcode opc = VEX_OPCODE_0F) {
625 int src_enc = src->encoding(); 600 int src_enc = src->encoding();
626 int dst_enc = dst->encoding(); 601 int dst_enc = dst->encoding();
919 894
920 void andq(Address dst, int32_t imm32); 895 void andq(Address dst, int32_t imm32);
921 void andq(Register dst, int32_t imm32); 896 void andq(Register dst, int32_t imm32);
922 void andq(Register dst, Address src); 897 void andq(Register dst, Address src);
923 void andq(Register dst, Register src); 898 void andq(Register dst, Register src);
924
925 // BMI instructions
926 void andnl(Register dst, Register src1, Register src2);
927 void andnl(Register dst, Register src1, Address src2);
928 void andnq(Register dst, Register src1, Register src2);
929 void andnq(Register dst, Register src1, Address src2);
930
931 void blsil(Register dst, Register src);
932 void blsil(Register dst, Address src);
933 void blsiq(Register dst, Register src);
934 void blsiq(Register dst, Address src);
935
936 void blsmskl(Register dst, Register src);
937 void blsmskl(Register dst, Address src);
938 void blsmskq(Register dst, Register src);
939 void blsmskq(Register dst, Address src);
940
941 void blsrl(Register dst, Register src);
942 void blsrl(Register dst, Address src);
943 void blsrq(Register dst, Register src);
944 void blsrq(Register dst, Address src);
945 899
946 void bsfl(Register dst, Register src); 900 void bsfl(Register dst, Register src);
947 void bsrl(Register dst, Register src); 901 void bsrl(Register dst, Register src);
948 902
949 #ifdef _LP64 903 #ifdef _LP64
1618 void testl(Register dst, Address src); 1572 void testl(Register dst, Address src);
1619 1573
1620 void testq(Register dst, int32_t imm32); 1574 void testq(Register dst, int32_t imm32);
1621 void testq(Register dst, Register src); 1575 void testq(Register dst, Register src);
1622 1576
1623 // BMI - count trailing zeros
1624 void tzcntl(Register dst, Register src);
1625 void tzcntq(Register dst, Register src);
1626 1577
1627 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 1578 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1628 void ucomisd(XMMRegister dst, Address src); 1579 void ucomisd(XMMRegister dst, Address src);
1629 void ucomisd(XMMRegister dst, XMMRegister src); 1580 void ucomisd(XMMRegister dst, XMMRegister src);
1630 1581