Mercurial > hg > graal-compiler
comparison src/cpu/sparc/vm/assembler_sparc.hpp @ 0:a61af66fc99e jdk7-b24
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author | duke |
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date | Sat, 01 Dec 2007 00:00:00 +0000 |
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children | ba764ed4b6f2 |
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1 /* | |
2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved. | |
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
4 * | |
5 * This code is free software; you can redistribute it and/or modify it | |
6 * under the terms of the GNU General Public License version 2 only, as | |
7 * published by the Free Software Foundation. | |
8 * | |
9 * This code is distributed in the hope that it will be useful, but WITHOUT | |
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
12 * version 2 for more details (a copy is included in the LICENSE file that | |
13 * accompanied this code). | |
14 * | |
15 * You should have received a copy of the GNU General Public License version | |
16 * 2 along with this work; if not, write to the Free Software Foundation, | |
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
18 * | |
19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
20 * CA 95054 USA or visit www.sun.com if you need additional information or | |
21 * have any questions. | |
22 * | |
23 */ | |
24 | |
25 class BiasedLockingCounters; | |
26 | |
27 // <sys/trap.h> promises that the system will not use traps 16-31 | |
28 #define ST_RESERVED_FOR_USER_0 0x10 | |
29 | |
30 /* Written: David Ungar 4/19/97 */ | |
31 | |
32 // Contains all the definitions needed for sparc assembly code generation. | |
33 | |
34 // Register aliases for parts of the system: | |
35 | |
36 // 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe | |
37 // across context switches in V8+ ABI. Of course, there are no 64 bit regs | |
38 // in V8 ABI. All 64 bits are preserved in V9 ABI for all registers. | |
39 | |
40 // g2-g4 are scratch registers called "application globals". Their | |
41 // meaning is reserved to the "compilation system"--which means us! | |
42 // They are are not supposed to be touched by ordinary C code, although | |
43 // highly-optimized C code might steal them for temps. They are safe | |
44 // across thread switches, and the ABI requires that they be safe | |
45 // across function calls. | |
46 // | |
47 // g1 and g3 are touched by more modules. V8 allows g1 to be clobbered | |
48 // across func calls, and V8+ also allows g5 to be clobbered across | |
49 // func calls. Also, g1 and g5 can get touched while doing shared | |
50 // library loading. | |
51 // | |
52 // We must not touch g7 (it is the thread-self register) and g6 is | |
53 // reserved for certain tools. g0, of course, is always zero. | |
54 // | |
55 // (Sources: SunSoft Compilers Group, thread library engineers.) | |
56 | |
57 // %%%% The interpreter should be revisited to reduce global scratch regs. | |
58 | |
59 // This global always holds the current JavaThread pointer: | |
60 | |
61 REGISTER_DECLARATION(Register, G2_thread , G2); | |
62 | |
63 // The following globals are part of the Java calling convention: | |
64 | |
65 REGISTER_DECLARATION(Register, G5_method , G5); | |
66 REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method); | |
67 REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method); | |
68 | |
69 // The following globals are used for the new C1 & interpreter calling convention: | |
70 REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument | |
71 | |
72 // This local is used to preserve G2_thread in the interpreter and in stubs: | |
73 REGISTER_DECLARATION(Register, L7_thread_cache , L7); | |
74 | |
75 // These globals are used as scratch registers in the interpreter: | |
76 | |
77 REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch | |
78 REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME | |
79 REGISTER_DECLARATION(Register, G3_scratch , G3); | |
80 REGISTER_DECLARATION(Register, G4_scratch , G4); | |
81 | |
82 // These globals are used as short-lived scratch registers in the compiler: | |
83 | |
84 REGISTER_DECLARATION(Register, Gtemp , G5); | |
85 | |
86 // The compiler requires that G5_megamorphic_method is G5_inline_cache_klass, | |
87 // because a single patchable "set" instruction (NativeMovConstReg, | |
88 // or NativeMovConstPatching for compiler1) instruction | |
89 // serves to set up either quantity, depending on whether the compiled | |
90 // call site is an inline cache or is megamorphic. See the function | |
91 // CompiledIC::set_to_megamorphic. | |
92 // | |
93 // On the other hand, G5_inline_cache_klass must differ from G5_method, | |
94 // because both registers are needed for an inline cache that calls | |
95 // an interpreted method. | |
96 // | |
97 // Note that G5_method is only the method-self for the interpreter, | |
98 // and is logically unrelated to G5_megamorphic_method. | |
99 // | |
100 // Invariants on G2_thread (the JavaThread pointer): | |
101 // - it should not be used for any other purpose anywhere | |
102 // - it must be re-initialized by StubRoutines::call_stub() | |
103 // - it must be preserved around every use of call_VM | |
104 | |
105 // We can consider using g2/g3/g4 to cache more values than the | |
106 // JavaThread, such as the card-marking base or perhaps pointers into | |
107 // Eden. It's something of a waste to use them as scratch temporaries, | |
108 // since they are not supposed to be volatile. (Of course, if we find | |
109 // that Java doesn't benefit from application globals, then we can just | |
110 // use them as ordinary temporaries.) | |
111 // | |
112 // Since g1 and g5 (and/or g6) are the volatile (caller-save) registers, | |
113 // it makes sense to use them routinely for procedure linkage, | |
114 // whenever the On registers are not applicable. Examples: G5_method, | |
115 // G5_inline_cache_klass, and a double handful of miscellaneous compiler | |
116 // stubs. This means that compiler stubs, etc., should be kept to a | |
117 // maximum of two or three G-register arguments. | |
118 | |
119 | |
120 // stub frames | |
121 | |
122 REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself | |
123 | |
124 // Interpreter frames | |
125 | |
126 #ifdef CC_INTERP | |
127 REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer | |
128 REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch | |
129 REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only) | |
130 REGISTER_DECLARATION(Register, L2_scratch , L2); | |
131 REGISTER_DECLARATION(Register, L3_scratch , L3); | |
132 REGISTER_DECLARATION(Register, L4_scratch , L4); | |
133 REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses | |
134 REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses | |
135 REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache | |
136 REGISTER_DECLARATION(Register, O5_savedSP , O5); | |
137 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply | |
138 // a copy SP, so in 64-bit it's a biased value. The bias | |
139 // is added and removed as needed in the frame code. | |
140 // Interface to signature handler | |
141 REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler | |
142 REGISTER_DECLARATION(Register, Lmethod , L6); // methodOop when calling signature handler | |
143 | |
144 #else | |
145 REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer | |
146 REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode | |
147 REGISTER_DECLARATION(Register, Lmethod , L2); | |
148 REGISTER_DECLARATION(Register, Llocals , L3); | |
149 REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler | |
150 // must match Llocals in asm interpreter | |
151 REGISTER_DECLARATION(Register, Lmonitors , L4); | |
152 REGISTER_DECLARATION(Register, Lbyte_code , L5); | |
153 // When calling out from the interpreter we record SP so that we can remove any extra stack | |
154 // space allocated during adapter transitions. This register is only live from the point | |
155 // of the call until we return. | |
156 REGISTER_DECLARATION(Register, Llast_SP , L5); | |
157 REGISTER_DECLARATION(Register, Lscratch , L5); | |
158 REGISTER_DECLARATION(Register, Lscratch2 , L6); | |
159 REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache | |
160 | |
161 REGISTER_DECLARATION(Register, O5_savedSP , O5); | |
162 REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply | |
163 // a copy SP, so in 64-bit it's a biased value. The bias | |
164 // is added and removed as needed in the frame code. | |
165 REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables | |
166 REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode | |
167 REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data | |
168 #endif /* CC_INTERP */ | |
169 | |
170 // NOTE: Lscratch2 and LcpoolCache point to the same registers in | |
171 // the interpreter code. If Lscratch2 needs to be used for some | |
172 // purpose than LcpoolCache should be restore after that for | |
173 // the interpreter to work right | |
174 // (These assignments must be compatible with L7_thread_cache; see above.) | |
175 | |
176 // Since Lbcp points into the middle of the method object, | |
177 // it is temporarily converted into a "bcx" during GC. | |
178 | |
179 // Exception processing | |
180 // These registers are passed into exception handlers. | |
181 // All exception handlers require the exception object being thrown. | |
182 // In addition, an nmethod's exception handler must be passed | |
183 // the address of the call site within the nmethod, to allow | |
184 // proper selection of the applicable catch block. | |
185 // (Interpreter frames use their own bcp() for this purpose.) | |
186 // | |
187 // The Oissuing_pc value is not always needed. When jumping to a | |
188 // handler that is known to be interpreted, the Oissuing_pc value can be | |
189 // omitted. An actual catch block in compiled code receives (from its | |
190 // nmethod's exception handler) the thrown exception in the Oexception, | |
191 // but it doesn't need the Oissuing_pc. | |
192 // | |
193 // If an exception handler (either interpreted or compiled) | |
194 // discovers there is no applicable catch block, it updates | |
195 // the Oissuing_pc to the continuation PC of its own caller, | |
196 // pops back to that caller's stack frame, and executes that | |
197 // caller's exception handler. Obviously, this process will | |
198 // iterate until the control stack is popped back to a method | |
199 // containing an applicable catch block. A key invariant is | |
200 // that the Oissuing_pc value is always a value local to | |
201 // the method whose exception handler is currently executing. | |
202 // | |
203 // Note: The issuing PC value is __not__ a raw return address (I7 value). | |
204 // It is a "return pc", the address __following__ the call. | |
205 // Raw return addresses are converted to issuing PCs by frame::pc(), | |
206 // or by stubs. Issuing PCs can be used directly with PC range tables. | |
207 // | |
208 REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown | |
209 REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from | |
210 | |
211 | |
212 // These must occur after the declarations above | |
213 #ifndef DONT_USE_REGISTER_DEFINES | |
214 | |
215 #define Gthread AS_REGISTER(Register, Gthread) | |
216 #define Gmethod AS_REGISTER(Register, Gmethod) | |
217 #define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method) | |
218 #define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg) | |
219 #define Gargs AS_REGISTER(Register, Gargs) | |
220 #define Lthread_cache AS_REGISTER(Register, Lthread_cache) | |
221 #define Gframe_size AS_REGISTER(Register, Gframe_size) | |
222 #define Gtemp AS_REGISTER(Register, Gtemp) | |
223 | |
224 #ifdef CC_INTERP | |
225 #define Lstate AS_REGISTER(Register, Lstate) | |
226 #define Lesp AS_REGISTER(Register, Lesp) | |
227 #define L1_scratch AS_REGISTER(Register, L1_scratch) | |
228 #define Lmirror AS_REGISTER(Register, Lmirror) | |
229 #define L2_scratch AS_REGISTER(Register, L2_scratch) | |
230 #define L3_scratch AS_REGISTER(Register, L3_scratch) | |
231 #define L4_scratch AS_REGISTER(Register, L4_scratch) | |
232 #define Lscratch AS_REGISTER(Register, Lscratch) | |
233 #define Lscratch2 AS_REGISTER(Register, Lscratch2) | |
234 #define L7_scratch AS_REGISTER(Register, L7_scratch) | |
235 #define Ostate AS_REGISTER(Register, Ostate) | |
236 #else | |
237 #define Lesp AS_REGISTER(Register, Lesp) | |
238 #define Lbcp AS_REGISTER(Register, Lbcp) | |
239 #define Lmethod AS_REGISTER(Register, Lmethod) | |
240 #define Llocals AS_REGISTER(Register, Llocals) | |
241 #define Lmonitors AS_REGISTER(Register, Lmonitors) | |
242 #define Lbyte_code AS_REGISTER(Register, Lbyte_code) | |
243 #define Lscratch AS_REGISTER(Register, Lscratch) | |
244 #define Lscratch2 AS_REGISTER(Register, Lscratch2) | |
245 #define LcpoolCache AS_REGISTER(Register, LcpoolCache) | |
246 #endif /* ! CC_INTERP */ | |
247 | |
248 #define Lentry_args AS_REGISTER(Register, Lentry_args) | |
249 #define I5_savedSP AS_REGISTER(Register, I5_savedSP) | |
250 #define O5_savedSP AS_REGISTER(Register, O5_savedSP) | |
251 #define IdispatchAddress AS_REGISTER(Register, IdispatchAddress) | |
252 #define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr) | |
253 #define IdispatchTables AS_REGISTER(Register, IdispatchTables) | |
254 | |
255 #define Oexception AS_REGISTER(Register, Oexception) | |
256 #define Oissuing_pc AS_REGISTER(Register, Oissuing_pc) | |
257 | |
258 | |
259 #endif | |
260 | |
261 // Address is an abstraction used to represent a memory location. | |
262 // | |
263 // Note: A register location is represented via a Register, not | |
264 // via an address for efficiency & simplicity reasons. | |
265 | |
266 class Address VALUE_OBJ_CLASS_SPEC { | |
267 private: | |
268 Register _base; | |
269 #ifdef _LP64 | |
270 int _hi32; // bits 63::32 | |
271 int _low32; // bits 31::0 | |
272 #endif | |
273 int _hi; | |
274 int _disp; | |
275 RelocationHolder _rspec; | |
276 | |
277 RelocationHolder rspec_from_rtype(relocInfo::relocType rt, address a = NULL) { | |
278 switch (rt) { | |
279 case relocInfo::external_word_type: | |
280 return external_word_Relocation::spec(a); | |
281 case relocInfo::internal_word_type: | |
282 return internal_word_Relocation::spec(a); | |
283 #ifdef _LP64 | |
284 case relocInfo::opt_virtual_call_type: | |
285 return opt_virtual_call_Relocation::spec(); | |
286 case relocInfo::static_call_type: | |
287 return static_call_Relocation::spec(); | |
288 case relocInfo::runtime_call_type: | |
289 return runtime_call_Relocation::spec(); | |
290 #endif | |
291 case relocInfo::none: | |
292 return RelocationHolder(); | |
293 default: | |
294 ShouldNotReachHere(); | |
295 return RelocationHolder(); | |
296 } | |
297 } | |
298 | |
299 public: | |
300 Address(Register b, address a, relocInfo::relocType rt = relocInfo::none) | |
301 : _rspec(rspec_from_rtype(rt, a)) | |
302 { | |
303 _base = b; | |
304 #ifdef _LP64 | |
305 _hi32 = (intptr_t)a >> 32; // top 32 bits in 64 bit word | |
306 _low32 = (intptr_t)a & ~0; // low 32 bits in 64 bit word | |
307 #endif | |
308 _hi = (intptr_t)a & ~0x3ff; // top 22 bits in low word | |
309 _disp = (intptr_t)a & 0x3ff; // bottom 10 bits | |
310 } | |
311 | |
312 Address(Register b, address a, RelocationHolder const& rspec) | |
313 : _rspec(rspec) | |
314 { | |
315 _base = b; | |
316 #ifdef _LP64 | |
317 _hi32 = (intptr_t)a >> 32; // top 32 bits in 64 bit word | |
318 _low32 = (intptr_t)a & ~0; // low 32 bits in 64 bit word | |
319 #endif | |
320 _hi = (intptr_t)a & ~0x3ff; // top 22 bits | |
321 _disp = (intptr_t)a & 0x3ff; // bottom 10 bits | |
322 } | |
323 | |
324 Address(Register b, intptr_t h, intptr_t d, RelocationHolder const& rspec = RelocationHolder()) | |
325 : _rspec(rspec) | |
326 { | |
327 _base = b; | |
328 #ifdef _LP64 | |
329 // [RGV] Put in Assert to force me to check usage of this constructor | |
330 assert( h == 0, "Check usage of this constructor" ); | |
331 _hi32 = h; | |
332 _low32 = d; | |
333 _hi = h; | |
334 _disp = d; | |
335 #else | |
336 _hi = h; | |
337 _disp = d; | |
338 #endif | |
339 } | |
340 | |
341 Address() | |
342 : _rspec(RelocationHolder()) | |
343 { | |
344 _base = G0; | |
345 #ifdef _LP64 | |
346 _hi32 = 0; | |
347 _low32 = 0; | |
348 #endif | |
349 _hi = 0; | |
350 _disp = 0; | |
351 } | |
352 | |
353 // fancier constructors | |
354 | |
355 enum addr_type { | |
356 extra_in_argument, // in the In registers | |
357 extra_out_argument // in the Outs | |
358 }; | |
359 | |
360 Address( addr_type, int ); | |
361 | |
362 // accessors | |
363 | |
364 Register base() const { return _base; } | |
365 #ifdef _LP64 | |
366 int hi32() const { return _hi32; } | |
367 int low32() const { return _low32; } | |
368 #endif | |
369 int hi() const { return _hi; } | |
370 int disp() const { return _disp; } | |
371 #ifdef _LP64 | |
372 intptr_t value() const { return ((intptr_t)_hi32 << 32) | | |
373 (intptr_t)(uint32_t)_low32; } | |
374 #else | |
375 int value() const { return _hi | _disp; } | |
376 #endif | |
377 const relocInfo::relocType rtype() { return _rspec.type(); } | |
378 const RelocationHolder& rspec() { return _rspec; } | |
379 | |
380 RelocationHolder rspec(int offset) const { | |
381 return offset == 0 ? _rspec : _rspec.plus(offset); | |
382 } | |
383 | |
384 inline bool is_simm13(int offset = 0); // check disp+offset for overflow | |
385 | |
386 Address split_disp() const { // deal with disp overflow | |
387 Address a = (*this); | |
388 int hi_disp = _disp & ~0x3ff; | |
389 if (hi_disp != 0) { | |
390 a._disp -= hi_disp; | |
391 a._hi += hi_disp; | |
392 } | |
393 return a; | |
394 } | |
395 | |
396 Address after_save() const { | |
397 Address a = (*this); | |
398 a._base = a._base->after_save(); | |
399 return a; | |
400 } | |
401 | |
402 Address after_restore() const { | |
403 Address a = (*this); | |
404 a._base = a._base->after_restore(); | |
405 return a; | |
406 } | |
407 | |
408 friend class Assembler; | |
409 }; | |
410 | |
411 | |
412 inline Address RegisterImpl::address_in_saved_window() const { | |
413 return (Address(SP, 0, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS)); | |
414 } | |
415 | |
416 | |
417 | |
418 // Argument is an abstraction used to represent an outgoing | |
419 // actual argument or an incoming formal parameter, whether | |
420 // it resides in memory or in a register, in a manner consistent | |
421 // with the SPARC Application Binary Interface, or ABI. This is | |
422 // often referred to as the native or C calling convention. | |
423 | |
424 class Argument VALUE_OBJ_CLASS_SPEC { | |
425 private: | |
426 int _number; | |
427 bool _is_in; | |
428 | |
429 public: | |
430 #ifdef _LP64 | |
431 enum { | |
432 n_register_parameters = 6, // only 6 registers may contain integer parameters | |
433 n_float_register_parameters = 16 // Can have up to 16 floating registers | |
434 }; | |
435 #else | |
436 enum { | |
437 n_register_parameters = 6 // only 6 registers may contain integer parameters | |
438 }; | |
439 #endif | |
440 | |
441 // creation | |
442 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {} | |
443 | |
444 int number() const { return _number; } | |
445 bool is_in() const { return _is_in; } | |
446 bool is_out() const { return !is_in(); } | |
447 | |
448 Argument successor() const { return Argument(number() + 1, is_in()); } | |
449 Argument as_in() const { return Argument(number(), true ); } | |
450 Argument as_out() const { return Argument(number(), false); } | |
451 | |
452 // locating register-based arguments: | |
453 bool is_register() const { return _number < n_register_parameters; } | |
454 | |
455 #ifdef _LP64 | |
456 // locating Floating Point register-based arguments: | |
457 bool is_float_register() const { return _number < n_float_register_parameters; } | |
458 | |
459 FloatRegister as_float_register() const { | |
460 assert(is_float_register(), "must be a register argument"); | |
461 return as_FloatRegister(( number() *2 ) + 1); | |
462 } | |
463 FloatRegister as_double_register() const { | |
464 assert(is_float_register(), "must be a register argument"); | |
465 return as_FloatRegister(( number() *2 )); | |
466 } | |
467 #endif | |
468 | |
469 Register as_register() const { | |
470 assert(is_register(), "must be a register argument"); | |
471 return is_in() ? as_iRegister(number()) : as_oRegister(number()); | |
472 } | |
473 | |
474 // locating memory-based arguments | |
475 Address as_address() const { | |
476 assert(!is_register(), "must be a memory argument"); | |
477 return address_in_frame(); | |
478 } | |
479 | |
480 // When applied to a register-based argument, give the corresponding address | |
481 // into the 6-word area "into which callee may store register arguments" | |
482 // (This is a different place than the corresponding register-save area location.) | |
483 Address address_in_frame() const { | |
484 return Address( is_in() ? Address::extra_in_argument | |
485 : Address::extra_out_argument, | |
486 _number ); | |
487 } | |
488 | |
489 // debugging | |
490 const char* name() const; | |
491 | |
492 friend class Assembler; | |
493 }; | |
494 | |
495 | |
496 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction | |
497 // level; i.e., what you write | |
498 // is what you get. The Assembler is generating code into a CodeBuffer. | |
499 | |
500 class Assembler : public AbstractAssembler { | |
501 protected: | |
502 | |
503 static void print_instruction(int inst); | |
504 static int patched_branch(int dest_pos, int inst, int inst_pos); | |
505 static int branch_destination(int inst, int pos); | |
506 | |
507 | |
508 friend class AbstractAssembler; | |
509 | |
510 // code patchers need various routines like inv_wdisp() | |
511 friend class NativeInstruction; | |
512 friend class NativeGeneralJump; | |
513 friend class Relocation; | |
514 friend class Label; | |
515 | |
516 public: | |
517 // op carries format info; see page 62 & 267 | |
518 | |
519 enum ops { | |
520 call_op = 1, // fmt 1 | |
521 branch_op = 0, // also sethi (fmt2) | |
522 arith_op = 2, // fmt 3, arith & misc | |
523 ldst_op = 3 // fmt 3, load/store | |
524 }; | |
525 | |
526 enum op2s { | |
527 bpr_op2 = 3, | |
528 fb_op2 = 6, | |
529 fbp_op2 = 5, | |
530 br_op2 = 2, | |
531 bp_op2 = 1, | |
532 cb_op2 = 7, // V8 | |
533 sethi_op2 = 4 | |
534 }; | |
535 | |
536 enum op3s { | |
537 // selected op3s | |
538 add_op3 = 0x00, | |
539 and_op3 = 0x01, | |
540 or_op3 = 0x02, | |
541 xor_op3 = 0x03, | |
542 sub_op3 = 0x04, | |
543 andn_op3 = 0x05, | |
544 orn_op3 = 0x06, | |
545 xnor_op3 = 0x07, | |
546 addc_op3 = 0x08, | |
547 mulx_op3 = 0x09, | |
548 umul_op3 = 0x0a, | |
549 smul_op3 = 0x0b, | |
550 subc_op3 = 0x0c, | |
551 udivx_op3 = 0x0d, | |
552 udiv_op3 = 0x0e, | |
553 sdiv_op3 = 0x0f, | |
554 | |
555 addcc_op3 = 0x10, | |
556 andcc_op3 = 0x11, | |
557 orcc_op3 = 0x12, | |
558 xorcc_op3 = 0x13, | |
559 subcc_op3 = 0x14, | |
560 andncc_op3 = 0x15, | |
561 orncc_op3 = 0x16, | |
562 xnorcc_op3 = 0x17, | |
563 addccc_op3 = 0x18, | |
564 umulcc_op3 = 0x1a, | |
565 smulcc_op3 = 0x1b, | |
566 subccc_op3 = 0x1c, | |
567 udivcc_op3 = 0x1e, | |
568 sdivcc_op3 = 0x1f, | |
569 | |
570 taddcc_op3 = 0x20, | |
571 tsubcc_op3 = 0x21, | |
572 taddcctv_op3 = 0x22, | |
573 tsubcctv_op3 = 0x23, | |
574 mulscc_op3 = 0x24, | |
575 sll_op3 = 0x25, | |
576 sllx_op3 = 0x25, | |
577 srl_op3 = 0x26, | |
578 srlx_op3 = 0x26, | |
579 sra_op3 = 0x27, | |
580 srax_op3 = 0x27, | |
581 rdreg_op3 = 0x28, | |
582 membar_op3 = 0x28, | |
583 | |
584 flushw_op3 = 0x2b, | |
585 movcc_op3 = 0x2c, | |
586 sdivx_op3 = 0x2d, | |
587 popc_op3 = 0x2e, | |
588 movr_op3 = 0x2f, | |
589 | |
590 sir_op3 = 0x30, | |
591 wrreg_op3 = 0x30, | |
592 saved_op3 = 0x31, | |
593 | |
594 fpop1_op3 = 0x34, | |
595 fpop2_op3 = 0x35, | |
596 impdep1_op3 = 0x36, | |
597 impdep2_op3 = 0x37, | |
598 jmpl_op3 = 0x38, | |
599 rett_op3 = 0x39, | |
600 trap_op3 = 0x3a, | |
601 flush_op3 = 0x3b, | |
602 save_op3 = 0x3c, | |
603 restore_op3 = 0x3d, | |
604 done_op3 = 0x3e, | |
605 retry_op3 = 0x3e, | |
606 | |
607 lduw_op3 = 0x00, | |
608 ldub_op3 = 0x01, | |
609 lduh_op3 = 0x02, | |
610 ldd_op3 = 0x03, | |
611 stw_op3 = 0x04, | |
612 stb_op3 = 0x05, | |
613 sth_op3 = 0x06, | |
614 std_op3 = 0x07, | |
615 ldsw_op3 = 0x08, | |
616 ldsb_op3 = 0x09, | |
617 ldsh_op3 = 0x0a, | |
618 ldx_op3 = 0x0b, | |
619 | |
620 ldstub_op3 = 0x0d, | |
621 stx_op3 = 0x0e, | |
622 swap_op3 = 0x0f, | |
623 | |
624 lduwa_op3 = 0x10, | |
625 ldxa_op3 = 0x1b, | |
626 | |
627 stwa_op3 = 0x14, | |
628 stxa_op3 = 0x1e, | |
629 | |
630 ldf_op3 = 0x20, | |
631 ldfsr_op3 = 0x21, | |
632 ldqf_op3 = 0x22, | |
633 lddf_op3 = 0x23, | |
634 stf_op3 = 0x24, | |
635 stfsr_op3 = 0x25, | |
636 stqf_op3 = 0x26, | |
637 stdf_op3 = 0x27, | |
638 | |
639 prefetch_op3 = 0x2d, | |
640 | |
641 | |
642 ldc_op3 = 0x30, | |
643 ldcsr_op3 = 0x31, | |
644 lddc_op3 = 0x33, | |
645 stc_op3 = 0x34, | |
646 stcsr_op3 = 0x35, | |
647 stdcq_op3 = 0x36, | |
648 stdc_op3 = 0x37, | |
649 | |
650 casa_op3 = 0x3c, | |
651 casxa_op3 = 0x3e, | |
652 | |
653 alt_bit_op3 = 0x10, | |
654 cc_bit_op3 = 0x10 | |
655 }; | |
656 | |
657 enum opfs { | |
658 // selected opfs | |
659 fmovs_opf = 0x01, | |
660 fmovd_opf = 0x02, | |
661 | |
662 fnegs_opf = 0x05, | |
663 fnegd_opf = 0x06, | |
664 | |
665 fadds_opf = 0x41, | |
666 faddd_opf = 0x42, | |
667 fsubs_opf = 0x45, | |
668 fsubd_opf = 0x46, | |
669 | |
670 fmuls_opf = 0x49, | |
671 fmuld_opf = 0x4a, | |
672 fdivs_opf = 0x4d, | |
673 fdivd_opf = 0x4e, | |
674 | |
675 fcmps_opf = 0x51, | |
676 fcmpd_opf = 0x52, | |
677 | |
678 fstox_opf = 0x81, | |
679 fdtox_opf = 0x82, | |
680 fxtos_opf = 0x84, | |
681 fxtod_opf = 0x88, | |
682 fitos_opf = 0xc4, | |
683 fdtos_opf = 0xc6, | |
684 fitod_opf = 0xc8, | |
685 fstod_opf = 0xc9, | |
686 fstoi_opf = 0xd1, | |
687 fdtoi_opf = 0xd2 | |
688 }; | |
689 | |
690 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 }; | |
691 | |
692 enum Condition { | |
693 // for FBfcc & FBPfcc instruction | |
694 f_never = 0, | |
695 f_notEqual = 1, | |
696 f_notZero = 1, | |
697 f_lessOrGreater = 2, | |
698 f_unorderedOrLess = 3, | |
699 f_less = 4, | |
700 f_unorderedOrGreater = 5, | |
701 f_greater = 6, | |
702 f_unordered = 7, | |
703 f_always = 8, | |
704 f_equal = 9, | |
705 f_zero = 9, | |
706 f_unorderedOrEqual = 10, | |
707 f_greaterOrEqual = 11, | |
708 f_unorderedOrGreaterOrEqual = 12, | |
709 f_lessOrEqual = 13, | |
710 f_unorderedOrLessOrEqual = 14, | |
711 f_ordered = 15, | |
712 | |
713 // V8 coproc, pp 123 v8 manual | |
714 | |
715 cp_always = 8, | |
716 cp_never = 0, | |
717 cp_3 = 7, | |
718 cp_2 = 6, | |
719 cp_2or3 = 5, | |
720 cp_1 = 4, | |
721 cp_1or3 = 3, | |
722 cp_1or2 = 2, | |
723 cp_1or2or3 = 1, | |
724 cp_0 = 9, | |
725 cp_0or3 = 10, | |
726 cp_0or2 = 11, | |
727 cp_0or2or3 = 12, | |
728 cp_0or1 = 13, | |
729 cp_0or1or3 = 14, | |
730 cp_0or1or2 = 15, | |
731 | |
732 | |
733 // for integers | |
734 | |
735 never = 0, | |
736 equal = 1, | |
737 zero = 1, | |
738 lessEqual = 2, | |
739 less = 3, | |
740 lessEqualUnsigned = 4, | |
741 lessUnsigned = 5, | |
742 carrySet = 5, | |
743 negative = 6, | |
744 overflowSet = 7, | |
745 always = 8, | |
746 notEqual = 9, | |
747 notZero = 9, | |
748 greater = 10, | |
749 greaterEqual = 11, | |
750 greaterUnsigned = 12, | |
751 greaterEqualUnsigned = 13, | |
752 carryClear = 13, | |
753 positive = 14, | |
754 overflowClear = 15 | |
755 }; | |
756 | |
757 enum CC { | |
758 icc = 0, xcc = 2, | |
759 // ptr_cc is the correct condition code for a pointer or intptr_t: | |
760 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc), | |
761 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3 | |
762 }; | |
763 | |
764 enum PrefetchFcn { | |
765 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4 | |
766 }; | |
767 | |
768 public: | |
769 // Helper functions for groups of instructions | |
770 | |
771 enum Predict { pt = 1, pn = 0 }; // pt = predict taken | |
772 | |
773 enum Membar_mask_bits { // page 184, v9 | |
774 StoreStore = 1 << 3, | |
775 LoadStore = 1 << 2, | |
776 StoreLoad = 1 << 1, | |
777 LoadLoad = 1 << 0, | |
778 | |
779 Sync = 1 << 6, | |
780 MemIssue = 1 << 5, | |
781 Lookaside = 1 << 4 | |
782 }; | |
783 | |
784 // test if x is within signed immediate range for nbits | |
785 static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 ) <= x && x < ( 1 << nbits-1 ); } | |
786 | |
787 // test if -4096 <= x <= 4095 | |
788 static bool is_simm13(int x) { return is_simm(x, 13); } | |
789 | |
790 enum ASIs { // page 72, v9 | |
791 ASI_PRIMARY = 0x80, | |
792 ASI_PRIMARY_LITTLE = 0x88 | |
793 // add more from book as needed | |
794 }; | |
795 | |
796 protected: | |
797 // helpers | |
798 | |
799 // x is supposed to fit in a field "nbits" wide | |
800 // and be sign-extended. Check the range. | |
801 | |
802 static void assert_signed_range(intptr_t x, int nbits) { | |
803 assert( nbits == 32 | |
804 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1), | |
805 "value out of range"); | |
806 } | |
807 | |
808 static void assert_signed_word_disp_range(intptr_t x, int nbits) { | |
809 assert( (x & 3) == 0, "not word aligned"); | |
810 assert_signed_range(x, nbits + 2); | |
811 } | |
812 | |
813 static void assert_unsigned_const(int x, int nbits) { | |
814 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range"); | |
815 } | |
816 | |
817 // fields: note bits numbered from LSB = 0, | |
818 // fields known by inclusive bit range | |
819 | |
820 static int fmask(juint hi_bit, juint lo_bit) { | |
821 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits"); | |
822 return (1 << ( hi_bit-lo_bit + 1 )) - 1; | |
823 } | |
824 | |
825 // inverse of u_field | |
826 | |
827 static int inv_u_field(int x, int hi_bit, int lo_bit) { | |
828 juint r = juint(x) >> lo_bit; | |
829 r &= fmask( hi_bit, lo_bit); | |
830 return int(r); | |
831 } | |
832 | |
833 | |
834 // signed version: extract from field and sign-extend | |
835 | |
836 static int inv_s_field(int x, int hi_bit, int lo_bit) { | |
837 int sign_shift = 31 - hi_bit; | |
838 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit); | |
839 } | |
840 | |
841 // given a field that ranges from hi_bit to lo_bit (inclusive, | |
842 // LSB = 0), and an unsigned value for the field, | |
843 // shift it into the field | |
844 | |
845 #ifdef ASSERT | |
846 static int u_field(int x, int hi_bit, int lo_bit) { | |
847 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0, | |
848 "value out of range"); | |
849 int r = x << lo_bit; | |
850 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); | |
851 return r; | |
852 } | |
853 #else | |
854 // make sure this is inlined as it will reduce code size significantly | |
855 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit)) | |
856 #endif | |
857 | |
858 static int inv_op( int x ) { return inv_u_field(x, 31, 30); } | |
859 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); } | |
860 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); } | |
861 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); } | |
862 | |
863 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; } | |
864 | |
865 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); } | |
866 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); } | |
867 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); } | |
868 | |
869 static int op( int x) { return u_field(x, 31, 30); } | |
870 static int rd( Register r) { return u_field(r->encoding(), 29, 25); } | |
871 static int fcn( int x) { return u_field(x, 29, 25); } | |
872 static int op3( int x) { return u_field(x, 24, 19); } | |
873 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); } | |
874 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); } | |
875 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); } | |
876 static int cond( int x) { return u_field(x, 28, 25); } | |
877 static int cond_mov( int x) { return u_field(x, 17, 14); } | |
878 static int rcond( RCondition x) { return u_field(x, 12, 10); } | |
879 static int op2( int x) { return u_field(x, 24, 22); } | |
880 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); } | |
881 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); } | |
882 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); } | |
883 static int imm_asi( int x) { return u_field(x, 12, 5); } | |
884 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); } | |
885 static int opf_low6( int w) { return u_field(w, 10, 5); } | |
886 static int opf_low5( int w) { return u_field(w, 9, 5); } | |
887 static int trapcc( CC cc) { return u_field(cc, 12, 11); } | |
888 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit | |
889 static int opf( int x) { return u_field(x, 13, 5); } | |
890 | |
891 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); } | |
892 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } | |
893 | |
894 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; | |
895 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; | |
896 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; | |
897 | |
898 // some float instructions use this encoding on the op3 field | |
899 static int alt_op3(int op, FloatRegisterImpl::Width w) { | |
900 int r; | |
901 switch(w) { | |
902 case FloatRegisterImpl::S: r = op + 0; break; | |
903 case FloatRegisterImpl::D: r = op + 3; break; | |
904 case FloatRegisterImpl::Q: r = op + 2; break; | |
905 default: ShouldNotReachHere(); break; | |
906 } | |
907 return op3(r); | |
908 } | |
909 | |
910 | |
911 // compute inverse of simm | |
912 static int inv_simm(int x, int nbits) { | |
913 return (int)(x << (32 - nbits)) >> (32 - nbits); | |
914 } | |
915 | |
916 static int inv_simm13( int x ) { return inv_simm(x, 13); } | |
917 | |
918 // signed immediate, in low bits, nbits long | |
919 static int simm(int x, int nbits) { | |
920 assert_signed_range(x, nbits); | |
921 return x & (( 1 << nbits ) - 1); | |
922 } | |
923 | |
924 // compute inverse of wdisp16 | |
925 static intptr_t inv_wdisp16(int x, intptr_t pos) { | |
926 int lo = x & (( 1 << 14 ) - 1); | |
927 int hi = (x >> 20) & 3; | |
928 if (hi >= 2) hi |= ~1; | |
929 return (((hi << 14) | lo) << 2) + pos; | |
930 } | |
931 | |
932 // word offset, 14 bits at LSend, 2 bits at B21, B20 | |
933 static int wdisp16(intptr_t x, intptr_t off) { | |
934 intptr_t xx = x - off; | |
935 assert_signed_word_disp_range(xx, 16); | |
936 int r = (xx >> 2) & ((1 << 14) - 1) | |
937 | ( ( (xx>>(2+14)) & 3 ) << 20 ); | |
938 assert( inv_wdisp16(r, off) == x, "inverse is not inverse"); | |
939 return r; | |
940 } | |
941 | |
942 | |
943 // word displacement in low-order nbits bits | |
944 | |
945 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) { | |
946 int pre_sign_extend = x & (( 1 << nbits ) - 1); | |
947 int r = pre_sign_extend >= ( 1 << (nbits-1) ) | |
948 ? pre_sign_extend | ~(( 1 << nbits ) - 1) | |
949 : pre_sign_extend; | |
950 return (r << 2) + pos; | |
951 } | |
952 | |
953 static int wdisp( intptr_t x, intptr_t off, int nbits ) { | |
954 intptr_t xx = x - off; | |
955 assert_signed_word_disp_range(xx, nbits); | |
956 int r = (xx >> 2) & (( 1 << nbits ) - 1); | |
957 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse"); | |
958 return r; | |
959 } | |
960 | |
961 | |
962 // Extract the top 32 bits in a 64 bit word | |
963 static int32_t hi32( int64_t x ) { | |
964 int32_t r = int32_t( (uint64_t)x >> 32 ); | |
965 return r; | |
966 } | |
967 | |
968 // given a sethi instruction, extract the constant, left-justified | |
969 static int inv_hi22( int x ) { | |
970 return x << 10; | |
971 } | |
972 | |
973 // create an imm22 field, given a 32-bit left-justified constant | |
974 static int hi22( int x ) { | |
975 int r = int( juint(x) >> 10 ); | |
976 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'"); | |
977 return r; | |
978 } | |
979 | |
980 // create a low10 __value__ (not a field) for a given a 32-bit constant | |
981 static int low10( int x ) { | |
982 return x & ((1 << 10) - 1); | |
983 } | |
984 | |
985 // instruction only in v9 | |
986 static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); } | |
987 | |
988 // instruction only in v8 | |
989 static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); } | |
990 | |
991 // instruction deprecated in v9 | |
992 static void v9_dep() { } // do nothing for now | |
993 | |
994 // some float instructions only exist for single prec. on v8 | |
995 static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); } | |
996 | |
997 // v8 has no CC field | |
998 static void v8_no_cc(CC cc) { if (cc) v9_only(); } | |
999 | |
1000 protected: | |
1001 // Simple delay-slot scheme: | |
1002 // In order to check the programmer, the assembler keeps track of deley slots. | |
1003 // It forbids CTIs in delay slots (conservative, but should be OK). | |
1004 // Also, when putting an instruction into a delay slot, you must say | |
1005 // asm->delayed()->add(...), in order to check that you don't omit | |
1006 // delay-slot instructions. | |
1007 // To implement this, we use a simple FSA | |
1008 | |
1009 #ifdef ASSERT | |
1010 #define CHECK_DELAY | |
1011 #endif | |
1012 #ifdef CHECK_DELAY | |
1013 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state; | |
1014 #endif | |
1015 | |
1016 public: | |
1017 // Tells assembler next instruction must NOT be in delay slot. | |
1018 // Use at start of multinstruction macros. | |
1019 void assert_not_delayed() { | |
1020 // This is a separate overloading to avoid creation of string constants | |
1021 // in non-asserted code--with some compilers this pollutes the object code. | |
1022 #ifdef CHECK_DELAY | |
1023 assert_not_delayed("next instruction should not be a delay slot"); | |
1024 #endif | |
1025 } | |
1026 void assert_not_delayed(const char* msg) { | |
1027 #ifdef CHECK_DELAY | |
1028 assert_msg ( delay_state == no_delay, msg); | |
1029 #endif | |
1030 } | |
1031 | |
1032 protected: | |
1033 // Delay slot helpers | |
1034 // cti is called when emitting control-transfer instruction, | |
1035 // BEFORE doing the emitting. | |
1036 // Only effective when assertion-checking is enabled. | |
1037 void cti() { | |
1038 #ifdef CHECK_DELAY | |
1039 assert_not_delayed("cti should not be in delay slot"); | |
1040 #endif | |
1041 } | |
1042 | |
1043 // called when emitting cti with a delay slot, AFTER emitting | |
1044 void has_delay_slot() { | |
1045 #ifdef CHECK_DELAY | |
1046 assert_not_delayed("just checking"); | |
1047 delay_state = at_delay_slot; | |
1048 #endif | |
1049 } | |
1050 | |
1051 public: | |
1052 // Tells assembler you know that next instruction is delayed | |
1053 Assembler* delayed() { | |
1054 #ifdef CHECK_DELAY | |
1055 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot"); | |
1056 delay_state = filling_delay_slot; | |
1057 #endif | |
1058 return this; | |
1059 } | |
1060 | |
1061 void flush() { | |
1062 #ifdef CHECK_DELAY | |
1063 assert ( delay_state == no_delay, "ending code with a delay slot"); | |
1064 #endif | |
1065 AbstractAssembler::flush(); | |
1066 } | |
1067 | |
1068 inline void emit_long(int); // shadows AbstractAssembler::emit_long | |
1069 inline void emit_data(int x) { emit_long(x); } | |
1070 inline void emit_data(int, RelocationHolder const&); | |
1071 inline void emit_data(int, relocInfo::relocType rtype); | |
1072 // helper for above fcns | |
1073 inline void check_delay(); | |
1074 | |
1075 | |
1076 public: | |
1077 // instructions, refer to page numbers in the SPARC Architecture Manual, V9 | |
1078 | |
1079 // pp 135 (addc was addx in v8) | |
1080 | |
1081 inline void add( Register s1, Register s2, Register d ); | |
1082 inline void add( Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none); | |
1083 inline void add( Register s1, int simm13a, Register d, RelocationHolder const& rspec); | |
1084 inline void add( const Address& a, Register d, int offset = 0); | |
1085 | |
1086 void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1087 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1088 void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); } | |
1089 void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1090 void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1091 void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1092 | |
1093 // pp 136 | |
1094 | |
1095 inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none ); | |
1096 inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L); | |
1097 | |
1098 protected: // use MacroAssembler::br instead | |
1099 | |
1100 // pp 138 | |
1101 | |
1102 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); | |
1103 inline void fb( Condition c, bool a, Label& L ); | |
1104 | |
1105 // pp 141 | |
1106 | |
1107 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1108 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
1109 | |
1110 public: | |
1111 | |
1112 // pp 144 | |
1113 | |
1114 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); | |
1115 inline void br( Condition c, bool a, Label& L ); | |
1116 | |
1117 // pp 146 | |
1118 | |
1119 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1120 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
1121 | |
1122 // pp 121 (V8) | |
1123 | |
1124 inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); | |
1125 inline void cb( Condition c, bool a, Label& L ); | |
1126 | |
1127 // pp 149 | |
1128 | |
1129 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
1130 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
1131 | |
1132 // pp 150 | |
1133 | |
1134 // These instructions compare the contents of s2 with the contents of | |
1135 // memory at address in s1. If the values are equal, the contents of memory | |
1136 // at address s1 is swapped with the data in d. If the values are not equal, | |
1137 // the the contents of memory at s1 is loaded into d, without the swap. | |
1138 | |
1139 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } | |
1140 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } | |
1141 | |
1142 // pp 152 | |
1143 | |
1144 void udiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); } | |
1145 void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1146 void sdiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); } | |
1147 void sdiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1148 void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } | |
1149 void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1150 void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } | |
1151 void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1152 | |
1153 // pp 155 | |
1154 | |
1155 void done() { v9_only(); cti(); emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); } | |
1156 void retry() { v9_only(); cti(); emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); } | |
1157 | |
1158 // pp 156 | |
1159 | |
1160 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); } | |
1161 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); } | |
1162 | |
1163 // pp 157 | |
1164 | |
1165 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); } | |
1166 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); } | |
1167 | |
1168 // pp 159 | |
1169 | |
1170 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); } | |
1171 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); } | |
1172 | |
1173 // pp 160 | |
1174 | |
1175 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); } | |
1176 | |
1177 // pp 161 | |
1178 | |
1179 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); } | |
1180 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); } | |
1181 | |
1182 // pp 162 | |
1183 | |
1184 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); } | |
1185 | |
1186 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); } | |
1187 | |
1188 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available | |
1189 // on v8 to do negation of single, double and quad precision floats. | |
1190 | |
1191 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); } | |
1192 | |
1193 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); } | |
1194 | |
1195 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available | |
1196 // on v8 to do abs operation on single/double/quad precision floats. | |
1197 | |
1198 void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); } | |
1199 | |
1200 // pp 163 | |
1201 | |
1202 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); } | |
1203 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); } | |
1204 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); } | |
1205 | |
1206 // pp 164 | |
1207 | |
1208 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); } | |
1209 | |
1210 // pp 165 | |
1211 | |
1212 inline void flush( Register s1, Register s2 ); | |
1213 inline void flush( Register s1, int simm13a); | |
1214 | |
1215 // pp 167 | |
1216 | |
1217 void flushw() { v9_only(); emit_long( op(arith_op) | op3(flushw_op3) ); } | |
1218 | |
1219 // pp 168 | |
1220 | |
1221 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_long( op(branch_op) | u_field(const22a, 21, 0) ); } | |
1222 // v8 unimp == illtrap(0) | |
1223 | |
1224 // pp 169 | |
1225 | |
1226 void impdep1( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); } | |
1227 void impdep2( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); } | |
1228 | |
1229 // pp 149 (v8) | |
1230 | |
1231 void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); } | |
1232 void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); } | |
1233 | |
1234 // pp 170 | |
1235 | |
1236 void jmpl( Register s1, Register s2, Register d ); | |
1237 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() ); | |
1238 | |
1239 inline void jmpl( Address& a, Register d, int offset = 0); | |
1240 | |
1241 // 171 | |
1242 | |
1243 inline void ldf( FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d ); | |
1244 inline void ldf( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ); | |
1245 | |
1246 inline void ldf( FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0); | |
1247 | |
1248 | |
1249 inline void ldfsr( Register s1, Register s2 ); | |
1250 inline void ldfsr( Register s1, int simm13a); | |
1251 inline void ldxfsr( Register s1, Register s2 ); | |
1252 inline void ldxfsr( Register s1, int simm13a); | |
1253 | |
1254 // pp 94 (v8) | |
1255 | |
1256 inline void ldc( Register s1, Register s2, int crd ); | |
1257 inline void ldc( Register s1, int simm13a, int crd); | |
1258 inline void lddc( Register s1, Register s2, int crd ); | |
1259 inline void lddc( Register s1, int simm13a, int crd); | |
1260 inline void ldcsr( Register s1, Register s2, int crd ); | |
1261 inline void ldcsr( Register s1, int simm13a, int crd); | |
1262 | |
1263 | |
1264 // 173 | |
1265 | |
1266 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1267 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1268 | |
1269 // pp 175, lduw is ld on v8 | |
1270 | |
1271 inline void ldsb( Register s1, Register s2, Register d ); | |
1272 inline void ldsb( Register s1, int simm13a, Register d); | |
1273 inline void ldsh( Register s1, Register s2, Register d ); | |
1274 inline void ldsh( Register s1, int simm13a, Register d); | |
1275 inline void ldsw( Register s1, Register s2, Register d ); | |
1276 inline void ldsw( Register s1, int simm13a, Register d); | |
1277 inline void ldub( Register s1, Register s2, Register d ); | |
1278 inline void ldub( Register s1, int simm13a, Register d); | |
1279 inline void lduh( Register s1, Register s2, Register d ); | |
1280 inline void lduh( Register s1, int simm13a, Register d); | |
1281 inline void lduw( Register s1, Register s2, Register d ); | |
1282 inline void lduw( Register s1, int simm13a, Register d); | |
1283 inline void ldx( Register s1, Register s2, Register d ); | |
1284 inline void ldx( Register s1, int simm13a, Register d); | |
1285 inline void ld( Register s1, Register s2, Register d ); | |
1286 inline void ld( Register s1, int simm13a, Register d); | |
1287 inline void ldd( Register s1, Register s2, Register d ); | |
1288 inline void ldd( Register s1, int simm13a, Register d); | |
1289 | |
1290 inline void ldsb( const Address& a, Register d, int offset = 0 ); | |
1291 inline void ldsh( const Address& a, Register d, int offset = 0 ); | |
1292 inline void ldsw( const Address& a, Register d, int offset = 0 ); | |
1293 inline void ldub( const Address& a, Register d, int offset = 0 ); | |
1294 inline void lduh( const Address& a, Register d, int offset = 0 ); | |
1295 inline void lduw( const Address& a, Register d, int offset = 0 ); | |
1296 inline void ldx( const Address& a, Register d, int offset = 0 ); | |
1297 inline void ld( const Address& a, Register d, int offset = 0 ); | |
1298 inline void ldd( const Address& a, Register d, int offset = 0 ); | |
1299 | |
1300 // pp 177 | |
1301 | |
1302 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1303 void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1304 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1305 void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1306 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1307 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1308 void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1309 void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1310 void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1311 void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1312 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1313 void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1314 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1315 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1316 void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1317 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1318 | |
1319 // pp 179 | |
1320 | |
1321 inline void ldstub( Register s1, Register s2, Register d ); | |
1322 inline void ldstub( Register s1, int simm13a, Register d); | |
1323 | |
1324 // pp 180 | |
1325 | |
1326 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1327 void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1328 | |
1329 // pp 181 | |
1330 | |
1331 void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); } | |
1332 void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1333 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1334 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1335 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); } | |
1336 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1337 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1338 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1339 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); } | |
1340 void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1341 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1342 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1343 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); } | |
1344 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1345 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1346 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1347 void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); } | |
1348 void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1349 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1350 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1351 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); } | |
1352 void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1353 void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1354 void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1355 | |
1356 // pp 183 | |
1357 | |
1358 void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); } | |
1359 | |
1360 // pp 185 | |
1361 | |
1362 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); } | |
1363 | |
1364 // pp 189 | |
1365 | |
1366 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); } | |
1367 | |
1368 // pp 191 | |
1369 | |
1370 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); } | |
1371 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); } | |
1372 | |
1373 // pp 195 | |
1374 | |
1375 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); } | |
1376 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); } | |
1377 | |
1378 // pp 196 | |
1379 | |
1380 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); } | |
1381 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1382 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); } | |
1383 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1384 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); } | |
1385 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1386 | |
1387 // pp 197 | |
1388 | |
1389 void umul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); } | |
1390 void umul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1391 void smul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); } | |
1392 void smul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1393 void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1394 void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1395 void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1396 void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1397 | |
1398 // pp 199 | |
1399 | |
1400 void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); } | |
1401 void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1402 | |
1403 // pp 201 | |
1404 | |
1405 void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); } | |
1406 | |
1407 | |
1408 // pp 202 | |
1409 | |
1410 void popc( Register s, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); } | |
1411 void popc( int simm13a, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); } | |
1412 | |
1413 // pp 203 | |
1414 | |
1415 void prefetch( Register s1, Register s2, PrefetchFcn f); | |
1416 void prefetch( Register s1, int simm13a, PrefetchFcn f); | |
1417 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1418 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1419 | |
1420 inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0); | |
1421 | |
1422 // pp 208 | |
1423 | |
1424 // not implementing read privileged register | |
1425 | |
1426 inline void rdy( Register d) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); } | |
1427 inline void rdccr( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); } | |
1428 inline void rdasi( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); } | |
1429 inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon! | |
1430 inline void rdpc( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); } | |
1431 inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); } | |
1432 | |
1433 // pp 213 | |
1434 | |
1435 inline void rett( Register s1, Register s2); | |
1436 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none); | |
1437 | |
1438 // pp 214 | |
1439 | |
1440 void save( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); } | |
1441 void save( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1442 | |
1443 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); } | |
1444 void restore( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1445 | |
1446 // pp 216 | |
1447 | |
1448 void saved() { v9_only(); emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); } | |
1449 void restored() { v9_only(); emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); } | |
1450 | |
1451 // pp 217 | |
1452 | |
1453 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() ); | |
1454 // pp 218 | |
1455 | |
1456 void sll( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); } | |
1457 void sll( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } | |
1458 void srl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); } | |
1459 void srl( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } | |
1460 void sra( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); } | |
1461 void sra( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } | |
1462 | |
1463 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); } | |
1464 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } | |
1465 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); } | |
1466 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } | |
1467 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); } | |
1468 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } | |
1469 | |
1470 // pp 220 | |
1471 | |
1472 void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); } | |
1473 | |
1474 // pp 221 | |
1475 | |
1476 void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); } | |
1477 | |
1478 // pp 222 | |
1479 | |
1480 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2 ); | |
1481 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); | |
1482 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0); | |
1483 | |
1484 inline void stfsr( Register s1, Register s2 ); | |
1485 inline void stfsr( Register s1, int simm13a); | |
1486 inline void stxfsr( Register s1, Register s2 ); | |
1487 inline void stxfsr( Register s1, int simm13a); | |
1488 | |
1489 // pp 224 | |
1490 | |
1491 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1492 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1493 | |
1494 // p 226 | |
1495 | |
1496 inline void stb( Register d, Register s1, Register s2 ); | |
1497 inline void stb( Register d, Register s1, int simm13a); | |
1498 inline void sth( Register d, Register s1, Register s2 ); | |
1499 inline void sth( Register d, Register s1, int simm13a); | |
1500 inline void stw( Register d, Register s1, Register s2 ); | |
1501 inline void stw( Register d, Register s1, int simm13a); | |
1502 inline void st( Register d, Register s1, Register s2 ); | |
1503 inline void st( Register d, Register s1, int simm13a); | |
1504 inline void stx( Register d, Register s1, Register s2 ); | |
1505 inline void stx( Register d, Register s1, int simm13a); | |
1506 inline void std( Register d, Register s1, Register s2 ); | |
1507 inline void std( Register d, Register s1, int simm13a); | |
1508 | |
1509 inline void stb( Register d, const Address& a, int offset = 0 ); | |
1510 inline void sth( Register d, const Address& a, int offset = 0 ); | |
1511 inline void stw( Register d, const Address& a, int offset = 0 ); | |
1512 inline void stx( Register d, const Address& a, int offset = 0 ); | |
1513 inline void st( Register d, const Address& a, int offset = 0 ); | |
1514 inline void std( Register d, const Address& a, int offset = 0 ); | |
1515 | |
1516 // pp 177 | |
1517 | |
1518 void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1519 void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1520 void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1521 void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1522 void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1523 void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1524 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1525 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1526 void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1527 void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1528 | |
1529 // pp 97 (v8) | |
1530 | |
1531 inline void stc( int crd, Register s1, Register s2 ); | |
1532 inline void stc( int crd, Register s1, int simm13a); | |
1533 inline void stdc( int crd, Register s1, Register s2 ); | |
1534 inline void stdc( int crd, Register s1, int simm13a); | |
1535 inline void stcsr( int crd, Register s1, Register s2 ); | |
1536 inline void stcsr( int crd, Register s1, int simm13a); | |
1537 inline void stdcq( int crd, Register s1, Register s2 ); | |
1538 inline void stdcq( int crd, Register s1, int simm13a); | |
1539 | |
1540 // pp 230 | |
1541 | |
1542 void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); } | |
1543 void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1544 void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); } | |
1545 void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1546 void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); } | |
1547 void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1548 void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } | |
1549 void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1550 | |
1551 // pp 231 | |
1552 | |
1553 inline void swap( Register s1, Register s2, Register d ); | |
1554 inline void swap( Register s1, int simm13a, Register d); | |
1555 inline void swap( Address& a, Register d, int offset = 0 ); | |
1556 | |
1557 // pp 232 | |
1558 | |
1559 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } | |
1560 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1561 | |
1562 // pp 234, note op in book is wrong, see pp 268 | |
1563 | |
1564 void taddcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); } | |
1565 void taddcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1566 void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); } | |
1567 void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1568 | |
1569 // pp 235 | |
1570 | |
1571 void tsubcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); } | |
1572 void tsubcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1573 void tsubcctv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); } | |
1574 void tsubcctv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } | |
1575 | |
1576 // pp 237 | |
1577 | |
1578 void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); } | |
1579 void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); } | |
1580 // simple uncond. trap | |
1581 void trap( int trapa ) { trap( always, icc, G0, trapa ); } | |
1582 | |
1583 // pp 239 omit write priv register for now | |
1584 | |
1585 inline void wry( Register d) { v9_dep(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); } | |
1586 inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); } | |
1587 inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) | | |
1588 rs1(s) | | |
1589 op3(wrreg_op3) | | |
1590 u_field(2, 29, 25) | | |
1591 u_field(1, 13, 13) | | |
1592 simm(simm13a, 13)); } | |
1593 inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); } | |
1594 inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); } | |
1595 | |
1596 | |
1597 // Creation | |
1598 Assembler(CodeBuffer* code) : AbstractAssembler(code) { | |
1599 #ifdef CHECK_DELAY | |
1600 delay_state = no_delay; | |
1601 #endif | |
1602 } | |
1603 | |
1604 // Testing | |
1605 #ifndef PRODUCT | |
1606 void test_v9(); | |
1607 void test_v8_onlys(); | |
1608 #endif | |
1609 }; | |
1610 | |
1611 | |
1612 class RegistersForDebugging : public StackObj { | |
1613 public: | |
1614 intptr_t i[8], l[8], o[8], g[8]; | |
1615 float f[32]; | |
1616 double d[32]; | |
1617 | |
1618 void print(outputStream* s); | |
1619 | |
1620 static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); } | |
1621 static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); } | |
1622 static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); } | |
1623 static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); } | |
1624 static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); } | |
1625 static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); } | |
1626 | |
1627 // gen asm code to save regs | |
1628 static void save_registers(MacroAssembler* a); | |
1629 | |
1630 // restore global registers in case C code disturbed them | |
1631 static void restore_registers(MacroAssembler* a, Register r); | |
1632 }; | |
1633 | |
1634 | |
1635 // MacroAssembler extends Assembler by a few frequently used macros. | |
1636 // | |
1637 // Most of the standard SPARC synthetic ops are defined here. | |
1638 // Instructions for which a 'better' code sequence exists depending | |
1639 // on arguments should also go in here. | |
1640 | |
1641 #define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__) | |
1642 #define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__) | |
1643 #define JUMP(a, off) jump(a, off, __FILE__, __LINE__) | |
1644 #define JUMPL(a, d, off) jumpl(a, d, off, __FILE__, __LINE__) | |
1645 | |
1646 | |
1647 class MacroAssembler: public Assembler { | |
1648 protected: | |
1649 // Support for VM calls | |
1650 // This is the base routine called by the different versions of call_VM_leaf. The interpreter | |
1651 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1652 // additional registers when doing a VM call). | |
1653 #ifdef CC_INTERP | |
1654 #define VIRTUAL | |
1655 #else | |
1656 #define VIRTUAL virtual | |
1657 #endif | |
1658 | |
1659 VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments); | |
1660 | |
1661 // | |
1662 // It is imperative that all calls into the VM are handled via the call_VM macros. | |
1663 // They make sure that the stack linkage is setup correctly. call_VM's correspond | |
1664 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. | |
1665 // | |
1666 // This is the base routine called by the different versions of call_VM. The interpreter | |
1667 // may customize this version by overriding it for its purposes (e.g., to save/restore | |
1668 // additional registers when doing a VM call). | |
1669 // | |
1670 // A non-volatile java_thread_cache register should be specified so | |
1671 // that the G2_thread value can be preserved across the call. | |
1672 // (If java_thread_cache is noreg, then a slow get_thread call | |
1673 // will re-initialize the G2_thread.) call_VM_base returns the register that contains the | |
1674 // thread. | |
1675 // | |
1676 // If no last_java_sp is specified (noreg) than SP will be used instead. | |
1677 | |
1678 virtual void call_VM_base( | |
1679 Register oop_result, // where an oop-result ends up if any; use noreg otherwise | |
1680 Register java_thread_cache, // the thread if computed before ; use noreg otherwise | |
1681 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise | |
1682 address entry_point, // the entry point | |
1683 int number_of_arguments, // the number of arguments (w/o thread) to pop after call | |
1684 bool check_exception=true // flag which indicates if exception should be checked | |
1685 ); | |
1686 | |
1687 // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code. | |
1688 // The implementation is only non-empty for the InterpreterMacroAssembler, | |
1689 // as only the interpreter handles and ForceEarlyReturn PopFrame requests. | |
1690 virtual void check_and_handle_popframe(Register scratch_reg); | |
1691 virtual void check_and_handle_earlyret(Register scratch_reg); | |
1692 | |
1693 public: | |
1694 MacroAssembler(CodeBuffer* code) : Assembler(code) {} | |
1695 | |
1696 // Support for NULL-checks | |
1697 // | |
1698 // Generates code that causes a NULL OS exception if the content of reg is NULL. | |
1699 // If the accessed location is M[reg + offset] and the offset is known, provide the | |
1700 // offset. No explicit code generation is needed if the offset is within a certain | |
1701 // range (0 <= offset <= page_size). | |
1702 // | |
1703 // %%%%%% Currently not done for SPARC | |
1704 | |
1705 void null_check(Register reg, int offset = -1); | |
1706 static bool needs_explicit_null_check(intptr_t offset); | |
1707 | |
1708 // support for delayed instructions | |
1709 MacroAssembler* delayed() { Assembler::delayed(); return this; } | |
1710 | |
1711 // branches that use right instruction for v8 vs. v9 | |
1712 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1713 inline void br( Condition c, bool a, Predict p, Label& L ); | |
1714 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1715 inline void fb( Condition c, bool a, Predict p, Label& L ); | |
1716 | |
1717 // compares register with zero and branches (V9 and V8 instructions) | |
1718 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L); | |
1719 // Compares a pointer register with zero and branches on (not)null. | |
1720 // Does a test & branch on 32-bit systems and a register-branch on 64-bit. | |
1721 void br_null ( Register s1, bool a, Predict p, Label& L ); | |
1722 void br_notnull( Register s1, bool a, Predict p, Label& L ); | |
1723 | |
1724 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1725 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
1726 | |
1727 // Branch that tests xcc in LP64 and icc in !LP64 | |
1728 inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1729 inline void brx( Condition c, bool a, Predict p, Label& L ); | |
1730 | |
1731 // unconditional short branch | |
1732 inline void ba( bool a, Label& L ); | |
1733 | |
1734 // Branch that tests fp condition codes | |
1735 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); | |
1736 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); | |
1737 | |
1738 // get PC the best way | |
1739 inline int get_pc( Register d ); | |
1740 | |
1741 // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual) | |
1742 inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); } | |
1743 inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); } | |
1744 | |
1745 inline void jmp( Register s1, Register s2 ); | |
1746 inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); | |
1747 | |
1748 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
1749 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); | |
1750 inline void callr( Register s1, Register s2 ); | |
1751 inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); | |
1752 | |
1753 // Emits nothing on V8 | |
1754 inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none ); | |
1755 inline void iprefetch( Label& L); | |
1756 | |
1757 inline void tst( Register s ) { orcc( G0, s, G0 ); } | |
1758 | |
1759 #ifdef PRODUCT | |
1760 inline void ret( bool trace = TraceJumps ) { if (trace) { | |
1761 mov(I7, O7); // traceable register | |
1762 JMP(O7, 2 * BytesPerInstWord); | |
1763 } else { | |
1764 jmpl( I7, 2 * BytesPerInstWord, G0 ); | |
1765 } | |
1766 } | |
1767 | |
1768 inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord); | |
1769 else jmpl( O7, 2 * BytesPerInstWord, G0 ); } | |
1770 #else | |
1771 void ret( bool trace = TraceJumps ); | |
1772 void retl( bool trace = TraceJumps ); | |
1773 #endif /* PRODUCT */ | |
1774 | |
1775 // Required platform-specific helpers for Label::patch_instructions. | |
1776 // They _shadow_ the declarations in AbstractAssembler, which are undefined. | |
1777 void pd_patch_instruction(address branch, address target); | |
1778 #ifndef PRODUCT | |
1779 static void pd_print_patched_instruction(address branch); | |
1780 #endif | |
1781 | |
1782 // sethi Macro handles optimizations and relocations | |
1783 void sethi( Address& a, bool ForceRelocatable = false ); | |
1784 void sethi( intptr_t imm22a, Register d, bool ForceRelocatable = false, RelocationHolder const& rspec = RelocationHolder()); | |
1785 | |
1786 // compute the size of a sethi/set | |
1787 static int size_of_sethi( address a, bool worst_case = false ); | |
1788 static int worst_case_size_of_set(); | |
1789 | |
1790 // set may be either setsw or setuw (high 32 bits may be zero or sign) | |
1791 void set( intptr_t value, Register d, RelocationHolder const& rspec = RelocationHolder() ); | |
1792 void setsw( int value, Register d, RelocationHolder const& rspec = RelocationHolder() ); | |
1793 void set64( jlong value, Register d, Register tmp); | |
1794 | |
1795 // sign-extend 32 to 64 | |
1796 inline void signx( Register s, Register d ) { sra( s, G0, d); } | |
1797 inline void signx( Register d ) { sra( d, G0, d); } | |
1798 | |
1799 inline void not1( Register s, Register d ) { xnor( s, G0, d ); } | |
1800 inline void not1( Register d ) { xnor( d, G0, d ); } | |
1801 | |
1802 inline void neg( Register s, Register d ) { sub( G0, s, d ); } | |
1803 inline void neg( Register d ) { sub( G0, d, d ); } | |
1804 | |
1805 inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); } | |
1806 inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); } | |
1807 // Functions for isolating 64 bit atomic swaps for LP64 | |
1808 // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's | |
1809 inline void cas_ptr( Register s1, Register s2, Register d) { | |
1810 #ifdef _LP64 | |
1811 casx( s1, s2, d ); | |
1812 #else | |
1813 cas( s1, s2, d ); | |
1814 #endif | |
1815 } | |
1816 | |
1817 // Functions for isolating 64 bit shifts for LP64 | |
1818 inline void sll_ptr( Register s1, Register s2, Register d ); | |
1819 inline void sll_ptr( Register s1, int imm6a, Register d ); | |
1820 inline void srl_ptr( Register s1, Register s2, Register d ); | |
1821 inline void srl_ptr( Register s1, int imm6a, Register d ); | |
1822 | |
1823 // little-endian | |
1824 inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); } | |
1825 inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); } | |
1826 | |
1827 inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); } | |
1828 inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); } | |
1829 | |
1830 inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); } | |
1831 inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); } | |
1832 | |
1833 inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); } | |
1834 inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); } | |
1835 | |
1836 inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); } | |
1837 inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); } | |
1838 | |
1839 inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); } | |
1840 inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); } | |
1841 | |
1842 inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); } | |
1843 inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); } | |
1844 | |
1845 inline void clr( Register d ) { or3( G0, G0, d ); } | |
1846 | |
1847 inline void clrb( Register s1, Register s2); | |
1848 inline void clrh( Register s1, Register s2); | |
1849 inline void clr( Register s1, Register s2); | |
1850 inline void clrx( Register s1, Register s2); | |
1851 | |
1852 inline void clrb( Register s1, int simm13a); | |
1853 inline void clrh( Register s1, int simm13a); | |
1854 inline void clr( Register s1, int simm13a); | |
1855 inline void clrx( Register s1, int simm13a); | |
1856 | |
1857 // copy & clear upper word | |
1858 inline void clruw( Register s, Register d ) { srl( s, G0, d); } | |
1859 // clear upper word | |
1860 inline void clruwu( Register d ) { srl( d, G0, d); } | |
1861 | |
1862 // membar psuedo instruction. takes into account target memory model. | |
1863 inline void membar( Assembler::Membar_mask_bits const7a ); | |
1864 | |
1865 // returns if membar generates anything. | |
1866 inline bool membar_has_effect( Assembler::Membar_mask_bits const7a ); | |
1867 | |
1868 // mov pseudo instructions | |
1869 inline void mov( Register s, Register d) { | |
1870 if ( s != d ) or3( G0, s, d); | |
1871 else assert_not_delayed(); // Put something useful in the delay slot! | |
1872 } | |
1873 | |
1874 inline void mov_or_nop( Register s, Register d) { | |
1875 if ( s != d ) or3( G0, s, d); | |
1876 else nop(); | |
1877 } | |
1878 | |
1879 inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); } | |
1880 | |
1881 // address pseudos: make these names unlike instruction names to avoid confusion | |
1882 inline void split_disp( Address& a, Register temp ); | |
1883 inline intptr_t load_pc_address( Register reg, int bytes_to_skip ); | |
1884 inline void load_address( Address& a, int offset = 0 ); | |
1885 inline void load_contents( Address& a, Register d, int offset = 0 ); | |
1886 inline void load_ptr_contents( Address& a, Register d, int offset = 0 ); | |
1887 inline void store_contents( Register s, Address& a, int offset = 0 ); | |
1888 inline void store_ptr_contents( Register s, Address& a, int offset = 0 ); | |
1889 inline void jumpl_to( Address& a, Register d, int offset = 0 ); | |
1890 inline void jump_to( Address& a, int offset = 0 ); | |
1891 | |
1892 // ring buffer traceable jumps | |
1893 | |
1894 void jmp2( Register r1, Register r2, const char* file, int line ); | |
1895 void jmp ( Register r1, int offset, const char* file, int line ); | |
1896 | |
1897 void jumpl( Address& a, Register d, int offset, const char* file, int line ); | |
1898 void jump ( Address& a, int offset, const char* file, int line ); | |
1899 | |
1900 | |
1901 // argument pseudos: | |
1902 | |
1903 inline void load_argument( Argument& a, Register d ); | |
1904 inline void store_argument( Register s, Argument& a ); | |
1905 inline void store_ptr_argument( Register s, Argument& a ); | |
1906 inline void store_float_argument( FloatRegister s, Argument& a ); | |
1907 inline void store_double_argument( FloatRegister s, Argument& a ); | |
1908 inline void store_long_argument( Register s, Argument& a ); | |
1909 | |
1910 // handy macros: | |
1911 | |
1912 inline void round_to( Register r, int modulus ) { | |
1913 assert_not_delayed(); | |
1914 inc( r, modulus - 1 ); | |
1915 and3( r, -modulus, r ); | |
1916 } | |
1917 | |
1918 // -------------------------------------------------- | |
1919 | |
1920 // Functions for isolating 64 bit loads for LP64 | |
1921 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's | |
1922 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's | |
1923 inline void ld_ptr( Register s1, Register s2, Register d ); | |
1924 inline void ld_ptr( Register s1, int simm13a, Register d); | |
1925 inline void ld_ptr( const Address& a, Register d, int offset = 0 ); | |
1926 inline void st_ptr( Register d, Register s1, Register s2 ); | |
1927 inline void st_ptr( Register d, Register s1, int simm13a); | |
1928 inline void st_ptr( Register d, const Address& a, int offset = 0 ); | |
1929 | |
1930 // ld_long will perform ld for 32 bit VM's and ldx for 64 bit VM's | |
1931 // st_long will perform st for 32 bit VM's and stx for 64 bit VM's | |
1932 inline void ld_long( Register s1, Register s2, Register d ); | |
1933 inline void ld_long( Register s1, int simm13a, Register d ); | |
1934 inline void ld_long( const Address& a, Register d, int offset = 0 ); | |
1935 inline void st_long( Register d, Register s1, Register s2 ); | |
1936 inline void st_long( Register d, Register s1, int simm13a ); | |
1937 inline void st_long( Register d, const Address& a, int offset = 0 ); | |
1938 | |
1939 // -------------------------------------------------- | |
1940 | |
1941 public: | |
1942 // traps as per trap.h (SPARC ABI?) | |
1943 | |
1944 void breakpoint_trap(); | |
1945 void breakpoint_trap(Condition c, CC cc = icc); | |
1946 void flush_windows_trap(); | |
1947 void clean_windows_trap(); | |
1948 void get_psr_trap(); | |
1949 void set_psr_trap(); | |
1950 | |
1951 // V8/V9 flush_windows | |
1952 void flush_windows(); | |
1953 | |
1954 // Support for serializing memory accesses between threads | |
1955 void serialize_memory(Register thread, Register tmp1, Register tmp2); | |
1956 | |
1957 // Stack frame creation/removal | |
1958 void enter(); | |
1959 void leave(); | |
1960 | |
1961 // V8/V9 integer multiply | |
1962 void mult(Register s1, Register s2, Register d); | |
1963 void mult(Register s1, int simm13a, Register d); | |
1964 | |
1965 // V8/V9 read and write of condition codes. | |
1966 void read_ccr(Register d); | |
1967 void write_ccr(Register s); | |
1968 | |
1969 // Manipulation of C++ bools | |
1970 // These are idioms to flag the need for care with accessing bools but on | |
1971 // this platform we assume byte size | |
1972 | |
1973 inline void stbool( Register d, const Address& a, int offset = 0 ) { stb(d, a, offset); } | |
1974 inline void ldbool( const Address& a, Register d, int offset = 0 ) { ldsb( a, d, offset ); } | |
1975 inline void tstbool( Register s ) { tst(s); } | |
1976 inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); } | |
1977 | |
1978 // Support for managing the JavaThread pointer (i.e.; the reference to | |
1979 // thread-local information). | |
1980 void get_thread(); // load G2_thread | |
1981 void verify_thread(); // verify G2_thread contents | |
1982 void save_thread (const Register threache); // save to cache | |
1983 void restore_thread(const Register thread_cache); // restore from cache | |
1984 | |
1985 // Support for last Java frame (but use call_VM instead where possible) | |
1986 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc); | |
1987 void reset_last_Java_frame(void); | |
1988 | |
1989 // Call into the VM. | |
1990 // Passes the thread pointer (in O0) as a prepended argument. | |
1991 // Makes sure oop return values are visible to the GC. | |
1992 void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); | |
1993 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); | |
1994 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); | |
1995 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); | |
1996 | |
1997 // these overloadings are not presently used on SPARC: | |
1998 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); | |
1999 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); | |
2000 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); | |
2001 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); | |
2002 | |
2003 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0); | |
2004 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1); | |
2005 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2); | |
2006 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3); | |
2007 | |
2008 void get_vm_result (Register oop_result); | |
2009 void get_vm_result_2(Register oop_result); | |
2010 | |
2011 // vm result is currently getting hijacked to for oop preservation | |
2012 void set_vm_result(Register oop_result); | |
2013 | |
2014 // if call_VM_base was called with check_exceptions=false, then call | |
2015 // check_and_forward_exception to handle exceptions when it is safe | |
2016 void check_and_forward_exception(Register scratch_reg); | |
2017 | |
2018 private: | |
2019 // For V8 | |
2020 void read_ccr_trap(Register ccr_save); | |
2021 void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2); | |
2022 | |
2023 #ifdef ASSERT | |
2024 // For V8 debugging. Uses V8 instruction sequence and checks | |
2025 // result with V9 insturctions rdccr and wrccr. | |
2026 // Uses Gscatch and Gscatch2 | |
2027 void read_ccr_v8_assert(Register ccr_save); | |
2028 void write_ccr_v8_assert(Register ccr_save); | |
2029 #endif // ASSERT | |
2030 | |
2031 public: | |
2032 // Stores | |
2033 void store_check(Register tmp, Register obj); // store check for obj - register is destroyed afterwards | |
2034 void store_check(Register tmp, Register obj, Register offset); // store check for obj - register is destroyed afterwards | |
2035 | |
2036 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack | |
2037 void push_fTOS(); | |
2038 | |
2039 // pops double TOS element from CPU stack and pushes on FPU stack | |
2040 void pop_fTOS(); | |
2041 | |
2042 void empty_FPU_stack(); | |
2043 | |
2044 void push_IU_state(); | |
2045 void pop_IU_state(); | |
2046 | |
2047 void push_FPU_state(); | |
2048 void pop_FPU_state(); | |
2049 | |
2050 void push_CPU_state(); | |
2051 void pop_CPU_state(); | |
2052 | |
2053 // Debugging | |
2054 void _verify_oop(Register reg, const char * msg, const char * file, int line); | |
2055 void _verify_oop_addr(Address addr, const char * msg, const char * file, int line); | |
2056 | |
2057 #define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__) | |
2058 #define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__) | |
2059 | |
2060 // only if +VerifyOops | |
2061 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); | |
2062 // only if +VerifyFPU | |
2063 void stop(const char* msg); // prints msg, dumps registers and stops execution | |
2064 void warn(const char* msg); // prints msg, but don't stop | |
2065 void untested(const char* what = ""); | |
2066 void unimplemented(const char* what = "") { char* b = new char[1024]; sprintf(b, "unimplemented: %s", what); stop(b); } | |
2067 void should_not_reach_here() { stop("should not reach here"); } | |
2068 void print_CPU_state(); | |
2069 | |
2070 // oops in code | |
2071 Address allocate_oop_address( jobject obj, Register d ); // allocate_index | |
2072 Address constant_oop_address( jobject obj, Register d ); // find_index | |
2073 inline void set_oop ( jobject obj, Register d ); // uses allocate_oop_address | |
2074 inline void set_oop_constant( jobject obj, Register d ); // uses constant_oop_address | |
2075 inline void set_oop ( Address obj_addr ); // same as load_address | |
2076 | |
2077 // nop padding | |
2078 void align(int modulus); | |
2079 | |
2080 // declare a safepoint | |
2081 void safepoint(); | |
2082 | |
2083 // factor out part of stop into subroutine to save space | |
2084 void stop_subroutine(); | |
2085 // factor out part of verify_oop into subroutine to save space | |
2086 void verify_oop_subroutine(); | |
2087 | |
2088 // side-door communication with signalHandler in os_solaris.cpp | |
2089 static address _verify_oop_implicit_branch[3]; | |
2090 | |
2091 #ifndef PRODUCT | |
2092 static void test(); | |
2093 #endif | |
2094 | |
2095 // convert an incoming arglist to varargs format; put the pointer in d | |
2096 void set_varargs( Argument a, Register d ); | |
2097 | |
2098 int total_frame_size_in_bytes(int extraWords); | |
2099 | |
2100 // used when extraWords known statically | |
2101 void save_frame(int extraWords); | |
2102 void save_frame_c1(int size_in_bytes); | |
2103 // make a frame, and simultaneously pass up one or two register value | |
2104 // into the new register window | |
2105 void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register()); | |
2106 | |
2107 // give no. (outgoing) params, calc # of words will need on frame | |
2108 void calc_mem_param_words(Register Rparam_words, Register Rresult); | |
2109 | |
2110 // used to calculate frame size dynamically | |
2111 // result is in bytes and must be negated for save inst | |
2112 void calc_frame_size(Register extraWords, Register resultReg); | |
2113 | |
2114 // calc and also save | |
2115 void calc_frame_size_and_save(Register extraWords, Register resultReg); | |
2116 | |
2117 static void debug(char* msg, RegistersForDebugging* outWindow); | |
2118 | |
2119 // implementations of bytecodes used by both interpreter and compiler | |
2120 | |
2121 void lcmp( Register Ra_hi, Register Ra_low, | |
2122 Register Rb_hi, Register Rb_low, | |
2123 Register Rresult); | |
2124 | |
2125 void lneg( Register Rhi, Register Rlow ); | |
2126 | |
2127 void lshl( Register Rin_high, Register Rin_low, Register Rcount, | |
2128 Register Rout_high, Register Rout_low, Register Rtemp ); | |
2129 | |
2130 void lshr( Register Rin_high, Register Rin_low, Register Rcount, | |
2131 Register Rout_high, Register Rout_low, Register Rtemp ); | |
2132 | |
2133 void lushr( Register Rin_high, Register Rin_low, Register Rcount, | |
2134 Register Rout_high, Register Rout_low, Register Rtemp ); | |
2135 | |
2136 #ifdef _LP64 | |
2137 void lcmp( Register Ra, Register Rb, Register Rresult); | |
2138 #endif | |
2139 | |
2140 void float_cmp( bool is_float, int unordered_result, | |
2141 FloatRegister Fa, FloatRegister Fb, | |
2142 Register Rresult); | |
2143 | |
2144 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); | |
2145 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); } | |
2146 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); | |
2147 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); | |
2148 | |
2149 void save_all_globals_into_locals(); | |
2150 void restore_globals_from_locals(); | |
2151 | |
2152 void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, | |
2153 address lock_addr=0, bool use_call_vm=false); | |
2154 void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, | |
2155 address lock_addr=0, bool use_call_vm=false); | |
2156 void casn (Register addr_reg, Register cmp_reg, Register set_reg) ; | |
2157 | |
2158 // These set the icc condition code to equal if the lock succeeded | |
2159 // and notEqual if it failed and requires a slow case | |
2160 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox, Register Rscratch, | |
2161 BiasedLockingCounters* counters = NULL); | |
2162 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox, Register Rscratch); | |
2163 | |
2164 // Biased locking support | |
2165 // Upon entry, lock_reg must point to the lock record on the stack, | |
2166 // obj_reg must contain the target object, and mark_reg must contain | |
2167 // the target object's header. | |
2168 // Destroys mark_reg if an attempt is made to bias an anonymously | |
2169 // biased lock. In this case a failure will go either to the slow | |
2170 // case or fall through with the notEqual condition code set with | |
2171 // the expectation that the slow case in the runtime will be called. | |
2172 // In the fall-through case where the CAS-based lock is done, | |
2173 // mark_reg is not destroyed. | |
2174 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg, | |
2175 Label& done, Label* slow_case = NULL, | |
2176 BiasedLockingCounters* counters = NULL); | |
2177 // Upon entry, the base register of mark_addr must contain the oop. | |
2178 // Destroys temp_reg. | |
2179 | |
2180 // If allow_delay_slot_filling is set to true, the next instruction | |
2181 // emitted after this one will go in an annulled delay slot if the | |
2182 // biased locking exit case failed. | |
2183 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false); | |
2184 | |
2185 // allocation | |
2186 void eden_allocate( | |
2187 Register obj, // result: pointer to object after successful allocation | |
2188 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
2189 int con_size_in_bytes, // object size in bytes if known at compile time | |
2190 Register t1, // temp register | |
2191 Register t2, // temp register | |
2192 Label& slow_case // continuation point if fast allocation fails | |
2193 ); | |
2194 void tlab_allocate( | |
2195 Register obj, // result: pointer to object after successful allocation | |
2196 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise | |
2197 int con_size_in_bytes, // object size in bytes if known at compile time | |
2198 Register t1, // temp register | |
2199 Label& slow_case // continuation point if fast allocation fails | |
2200 ); | |
2201 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); | |
2202 | |
2203 // Stack overflow checking | |
2204 | |
2205 // Note: this clobbers G3_scratch | |
2206 void bang_stack_with_offset(int offset) { | |
2207 // stack grows down, caller passes positive offset | |
2208 assert(offset > 0, "must bang with negative offset"); | |
2209 set((-offset)+STACK_BIAS, G3_scratch); | |
2210 st(G0, SP, G3_scratch); | |
2211 } | |
2212 | |
2213 // Writes to stack successive pages until offset reached to check for | |
2214 // stack overflow + shadow pages. Clobbers tsp and scratch registers. | |
2215 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch); | |
2216 | |
2217 void verify_tlab(); | |
2218 | |
2219 Condition negate_condition(Condition cond); | |
2220 | |
2221 // Helper functions for statistics gathering. | |
2222 // Conditionally (non-atomically) increments passed counter address, preserving condition codes. | |
2223 void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2); | |
2224 // Unconditional increment. | |
2225 void inc_counter(address counter_addr, Register Rtemp1, Register Rtemp2); | |
2226 | |
2227 #undef VIRTUAL | |
2228 | |
2229 }; | |
2230 | |
2231 /** | |
2232 * class SkipIfEqual: | |
2233 * | |
2234 * Instantiating this class will result in assembly code being output that will | |
2235 * jump around any code emitted between the creation of the instance and it's | |
2236 * automatic destruction at the end of a scope block, depending on the value of | |
2237 * the flag passed to the constructor, which will be checked at run-time. | |
2238 */ | |
2239 class SkipIfEqual : public StackObj { | |
2240 private: | |
2241 MacroAssembler* _masm; | |
2242 Label _label; | |
2243 | |
2244 public: | |
2245 // 'temp' is a temp register that this object can use (and trash) | |
2246 SkipIfEqual(MacroAssembler*, Register temp, | |
2247 const bool* flag_addr, Assembler::Condition condition); | |
2248 ~SkipIfEqual(); | |
2249 }; | |
2250 | |
2251 #ifdef ASSERT | |
2252 // On RISC, there's no benefit to verifying instruction boundaries. | |
2253 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } | |
2254 #endif |