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comparison src/cpu/sparc/vm/c1_LIRAssembler_sparc.hpp @ 2002:ac637b7220d1

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6985015: C1 needs to support compressed oops Summary: This change implements compressed oops for C1 for x64 and sparc. The changes are mostly on the codegen level, with a few exceptions when we do access things outside of the heap that are uncompressed from the IR. Compressed oops are now also enabled with tiered. Reviewed-by: twisti, kvn, never, phh
author iveresov
date Tue, 30 Nov 2010 23:23:40 -0800
parents f95d63e2154a
children 898522ae3c32
comparison
equal deleted inserted replaced
1972:f95d63e2154a 2002:ac637b7220d1
38 // When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]). 38 // When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]).
39 // When disp > 13 bits long, code is emitted to set the displacement into the O7 register, 39 // When disp > 13 bits long, code is emitted to set the displacement into the O7 register,
40 // and then a load or store is emitted with ([O7] + [d]). 40 // and then a load or store is emitted with ([O7] + [d]).
41 // 41 //
42 42
43 // some load/store variants return the code_offset for proper positioning of debug info for null checks 43 int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned);
44 int store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide);
44 45
45 // load/store with 32 bit displacement 46 int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned);
46 int load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo* info = NULL); 47 int load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide);
47 void store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info = NULL);
48
49 // loadf/storef with 32 bit displacement
50 void load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
51 void store(FloatRegister d, Register s1, int disp, BasicType st_type, CodeEmitInfo* info = NULL);
52
53 // convienence methods for calling load/store with an Address
54 void load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
55 void store(Register d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
56 void load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
57 void store(FloatRegister d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
58
59 // convienence methods for calling load/store with an LIR_Address
60 void load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
61 void store(Register d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
62 void load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
63 void store(FloatRegister d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
64
65 int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned = false);
66 int store(LIR_Opr from_reg, Register base, Register disp, BasicType type);
67
68 int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned = false);
69 int load(Register base, Register disp, LIR_Opr to_reg, BasicType type);
70 48
71 void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no); 49 void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no);
72 50
73 int shift_amount(BasicType t); 51 int shift_amount(BasicType t);
74 52