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comparison src/cpu/x86/vm/c1_Defs_x86.hpp @ 2002:ac637b7220d1

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6985015: C1 needs to support compressed oops Summary: This change implements compressed oops for C1 for x64 and sparc. The changes are mostly on the codegen level, with a few exceptions when we do access things outside of the heap that are uncompressed from the IR. Compressed oops are now also enabled with tiered. Reviewed-by: twisti, kvn, never, phh
author iveresov
date Tue, 30 Nov 2010 23:23:40 -0800
parents f95d63e2154a
children
comparison
equal deleted inserted replaced
1972:f95d63e2154a 2002:ac637b7220d1
59 pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan 59 pd_nof_cpu_regs_linearscan = pd_nof_cpu_regs_frame_map, // number of registers visible to linear scan
60 pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan 60 pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
61 pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan 61 pd_nof_xmm_regs_linearscan = pd_nof_xmm_regs_frame_map, // number of registers visible to linear scan
62 pd_first_cpu_reg = 0, 62 pd_first_cpu_reg = 0,
63 pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11), 63 pd_last_cpu_reg = NOT_LP64(5) LP64_ONLY(11),
64 pd_first_byte_reg = 2, 64 pd_first_byte_reg = NOT_LP64(2) LP64_ONLY(0),
65 pd_last_byte_reg = 5, 65 pd_last_byte_reg = NOT_LP64(5) LP64_ONLY(11),
66 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map, 66 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
67 pd_last_fpu_reg = pd_first_fpu_reg + 7, 67 pd_last_fpu_reg = pd_first_fpu_reg + 7,
68 pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map, 68 pd_first_xmm_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map,
69 pd_last_xmm_reg = pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1 69 pd_last_xmm_reg = pd_first_xmm_reg + pd_nof_xmm_regs_frame_map - 1
70 }; 70 };