comparison src/share/vm/c1/c1_LIRAssembler.cpp @ 2002:ac637b7220d1

6985015: C1 needs to support compressed oops Summary: This change implements compressed oops for C1 for x64 and sparc. The changes are mostly on the codegen level, with a few exceptions when we do access things outside of the heap that are uncompressed from the IR. Compressed oops are now also enabled with tiered. Reviewed-by: twisti, kvn, never, phh
author iveresov
date Tue, 30 Nov 2010 23:23:40 -0800
parents f95d63e2154a
children 037c727f35fb
comparison
equal deleted inserted replaced
1972:f95d63e2154a 2002:ac637b7220d1
487 if (op->move_kind() == lir_move_volatile) { 487 if (op->move_kind() == lir_move_volatile) {
488 assert(op->patch_code() == lir_patch_none, "can't patch volatiles"); 488 assert(op->patch_code() == lir_patch_none, "can't patch volatiles");
489 volatile_move_op(op->in_opr(), op->result_opr(), op->type(), op->info()); 489 volatile_move_op(op->in_opr(), op->result_opr(), op->type(), op->info());
490 } else { 490 } else {
491 move_op(op->in_opr(), op->result_opr(), op->type(), 491 move_op(op->in_opr(), op->result_opr(), op->type(),
492 op->patch_code(), op->info(), op->pop_fpu_stack(), op->move_kind() == lir_move_unaligned); 492 op->patch_code(), op->info(), op->pop_fpu_stack(),
493 op->move_kind() == lir_move_unaligned,
494 op->move_kind() == lir_move_wide);
493 } 495 }
494 break; 496 break;
495 497
496 case lir_prefetchr: 498 case lir_prefetchr:
497 prefetchr(op->in_opr()); 499 prefetchr(op->in_opr());
756 758
757 reg2stack (src, dest, src->type(), pop_fpu_stack); 759 reg2stack (src, dest, src->type(), pop_fpu_stack);
758 } 760 }
759 761
760 762
761 void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned) { 763 void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool unaligned, bool wide) {
762 if (src->is_register()) { 764 if (src->is_register()) {
763 if (dest->is_register()) { 765 if (dest->is_register()) {
764 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here"); 766 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
765 reg2reg(src, dest); 767 reg2reg(src, dest);
766 } else if (dest->is_stack()) { 768 } else if (dest->is_stack()) {
767 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here"); 769 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
768 reg2stack(src, dest, type, pop_fpu_stack); 770 reg2stack(src, dest, type, pop_fpu_stack);
769 } else if (dest->is_address()) { 771 } else if (dest->is_address()) {
770 reg2mem(src, dest, type, patch_code, info, pop_fpu_stack, unaligned); 772 reg2mem(src, dest, type, patch_code, info, pop_fpu_stack, wide, unaligned);
771 } else { 773 } else {
772 ShouldNotReachHere(); 774 ShouldNotReachHere();
773 } 775 }
774 776
775 } else if (src->is_stack()) { 777 } else if (src->is_stack()) {
788 } else if (dest->is_stack()) { 790 } else if (dest->is_stack()) {
789 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here"); 791 assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
790 const2stack(src, dest); 792 const2stack(src, dest);
791 } else if (dest->is_address()) { 793 } else if (dest->is_address()) {
792 assert(patch_code == lir_patch_none, "no patching allowed here"); 794 assert(patch_code == lir_patch_none, "no patching allowed here");
793 const2mem(src, dest, type, info); 795 const2mem(src, dest, type, info, wide);
794 } else { 796 } else {
795 ShouldNotReachHere(); 797 ShouldNotReachHere();
796 } 798 }
797 799
798 } else if (src->is_address()) { 800 } else if (src->is_address()) {
799 mem2reg(src, dest, type, patch_code, info, unaligned); 801 mem2reg(src, dest, type, patch_code, info, wide, unaligned);
800 802
801 } else { 803 } else {
802 ShouldNotReachHere(); 804 ShouldNotReachHere();
803 } 805 }
804 } 806 }