Mercurial > hg > graal-compiler
comparison src/cpu/sparc/vm/stubGenerator_sparc.cpp @ 20313:b20a35eae442
8035968: Leverage CPU Instructions to Improve SHA Performance on SPARC
Summary: Add C2 SHA intrinsics on SPARC
Reviewed-by: kvn, roland
Contributed-by: james.cheng@oracle.com
author | kvn |
---|---|
date | Wed, 11 Jun 2014 11:05:10 -0700 |
parents | 0342d80559e0 |
children | 7848fc12602b |
comparison
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20312:922c87c9aed4 | 20313:b20a35eae442 |
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4573 __ delayed()->restore(); | 4573 __ delayed()->restore(); |
4574 | 4574 |
4575 return start; | 4575 return start; |
4576 } | 4576 } |
4577 | 4577 |
4578 address generate_sha1_implCompress(bool multi_block, const char *name) { | |
4579 __ align(CodeEntryAlignment); | |
4580 StubCodeMark mark(this, "StubRoutines", name); | |
4581 address start = __ pc(); | |
4582 | |
4583 Label L_sha1_loop, L_sha1_unaligned_input, L_sha1_unaligned_input_loop; | |
4584 int i; | |
4585 | |
4586 Register buf = O0; // byte[] source+offset | |
4587 Register state = O1; // int[] SHA.state | |
4588 Register ofs = O2; // int offset | |
4589 Register limit = O3; // int limit | |
4590 | |
4591 // load state into F0-F4 | |
4592 for (i = 0; i < 5; i++) { | |
4593 __ ldf(FloatRegisterImpl::S, state, i*4, as_FloatRegister(i)); | |
4594 } | |
4595 | |
4596 __ andcc(buf, 7, G0); | |
4597 __ br(Assembler::notZero, false, Assembler::pn, L_sha1_unaligned_input); | |
4598 __ delayed()->nop(); | |
4599 | |
4600 __ BIND(L_sha1_loop); | |
4601 // load buf into F8-F22 | |
4602 for (i = 0; i < 8; i++) { | |
4603 __ ldf(FloatRegisterImpl::D, buf, i*8, as_FloatRegister(i*2 + 8)); | |
4604 } | |
4605 __ sha1(); | |
4606 if (multi_block) { | |
4607 __ add(ofs, 64, ofs); | |
4608 __ add(buf, 64, buf); | |
4609 __ cmp_and_brx_short(ofs, limit, Assembler::lessEqual, Assembler::pt, L_sha1_loop); | |
4610 __ mov(ofs, O0); // to be returned | |
4611 } | |
4612 | |
4613 // store F0-F4 into state and return | |
4614 for (i = 0; i < 4; i++) { | |
4615 __ stf(FloatRegisterImpl::S, as_FloatRegister(i), state, i*4); | |
4616 } | |
4617 __ retl(); | |
4618 __ delayed()->stf(FloatRegisterImpl::S, F4, state, 0x10); | |
4619 | |
4620 __ BIND(L_sha1_unaligned_input); | |
4621 __ alignaddr(buf, G0, buf); | |
4622 | |
4623 __ BIND(L_sha1_unaligned_input_loop); | |
4624 // load buf into F8-F22 | |
4625 for (i = 0; i < 9; i++) { | |
4626 __ ldf(FloatRegisterImpl::D, buf, i*8, as_FloatRegister(i*2 + 8)); | |
4627 } | |
4628 for (i = 0; i < 8; i++) { | |
4629 __ faligndata(as_FloatRegister(i*2 + 8), as_FloatRegister(i*2 + 10), as_FloatRegister(i*2 + 8)); | |
4630 } | |
4631 __ sha1(); | |
4632 if (multi_block) { | |
4633 __ add(ofs, 64, ofs); | |
4634 __ add(buf, 64, buf); | |
4635 __ cmp_and_brx_short(ofs, limit, Assembler::lessEqual, Assembler::pt, L_sha1_unaligned_input_loop); | |
4636 __ mov(ofs, O0); // to be returned | |
4637 } | |
4638 | |
4639 // store F0-F4 into state and return | |
4640 for (i = 0; i < 4; i++) { | |
4641 __ stf(FloatRegisterImpl::S, as_FloatRegister(i), state, i*4); | |
4642 } | |
4643 __ retl(); | |
4644 __ delayed()->stf(FloatRegisterImpl::S, F4, state, 0x10); | |
4645 | |
4646 return start; | |
4647 } | |
4648 | |
4649 address generate_sha256_implCompress(bool multi_block, const char *name) { | |
4650 __ align(CodeEntryAlignment); | |
4651 StubCodeMark mark(this, "StubRoutines", name); | |
4652 address start = __ pc(); | |
4653 | |
4654 Label L_sha256_loop, L_sha256_unaligned_input, L_sha256_unaligned_input_loop; | |
4655 int i; | |
4656 | |
4657 Register buf = O0; // byte[] source+offset | |
4658 Register state = O1; // int[] SHA2.state | |
4659 Register ofs = O2; // int offset | |
4660 Register limit = O3; // int limit | |
4661 | |
4662 // load state into F0-F7 | |
4663 for (i = 0; i < 8; i++) { | |
4664 __ ldf(FloatRegisterImpl::S, state, i*4, as_FloatRegister(i)); | |
4665 } | |
4666 | |
4667 __ andcc(buf, 7, G0); | |
4668 __ br(Assembler::notZero, false, Assembler::pn, L_sha256_unaligned_input); | |
4669 __ delayed()->nop(); | |
4670 | |
4671 __ BIND(L_sha256_loop); | |
4672 // load buf into F8-F22 | |
4673 for (i = 0; i < 8; i++) { | |
4674 __ ldf(FloatRegisterImpl::D, buf, i*8, as_FloatRegister(i*2 + 8)); | |
4675 } | |
4676 __ sha256(); | |
4677 if (multi_block) { | |
4678 __ add(ofs, 64, ofs); | |
4679 __ add(buf, 64, buf); | |
4680 __ cmp_and_brx_short(ofs, limit, Assembler::lessEqual, Assembler::pt, L_sha256_loop); | |
4681 __ mov(ofs, O0); // to be returned | |
4682 } | |
4683 | |
4684 // store F0-F7 into state and return | |
4685 for (i = 0; i < 7; i++) { | |
4686 __ stf(FloatRegisterImpl::S, as_FloatRegister(i), state, i*4); | |
4687 } | |
4688 __ retl(); | |
4689 __ delayed()->stf(FloatRegisterImpl::S, F7, state, 0x1c); | |
4690 | |
4691 __ BIND(L_sha256_unaligned_input); | |
4692 __ alignaddr(buf, G0, buf); | |
4693 | |
4694 __ BIND(L_sha256_unaligned_input_loop); | |
4695 // load buf into F8-F22 | |
4696 for (i = 0; i < 9; i++) { | |
4697 __ ldf(FloatRegisterImpl::D, buf, i*8, as_FloatRegister(i*2 + 8)); | |
4698 } | |
4699 for (i = 0; i < 8; i++) { | |
4700 __ faligndata(as_FloatRegister(i*2 + 8), as_FloatRegister(i*2 + 10), as_FloatRegister(i*2 + 8)); | |
4701 } | |
4702 __ sha256(); | |
4703 if (multi_block) { | |
4704 __ add(ofs, 64, ofs); | |
4705 __ add(buf, 64, buf); | |
4706 __ cmp_and_brx_short(ofs, limit, Assembler::lessEqual, Assembler::pt, L_sha256_unaligned_input_loop); | |
4707 __ mov(ofs, O0); // to be returned | |
4708 } | |
4709 | |
4710 // store F0-F7 into state and return | |
4711 for (i = 0; i < 7; i++) { | |
4712 __ stf(FloatRegisterImpl::S, as_FloatRegister(i), state, i*4); | |
4713 } | |
4714 __ retl(); | |
4715 __ delayed()->stf(FloatRegisterImpl::S, F7, state, 0x1c); | |
4716 | |
4717 return start; | |
4718 } | |
4719 | |
4720 address generate_sha512_implCompress(bool multi_block, const char *name) { | |
4721 __ align(CodeEntryAlignment); | |
4722 StubCodeMark mark(this, "StubRoutines", name); | |
4723 address start = __ pc(); | |
4724 | |
4725 Label L_sha512_loop, L_sha512_unaligned_input, L_sha512_unaligned_input_loop; | |
4726 int i; | |
4727 | |
4728 Register buf = O0; // byte[] source+offset | |
4729 Register state = O1; // long[] SHA5.state | |
4730 Register ofs = O2; // int offset | |
4731 Register limit = O3; // int limit | |
4732 | |
4733 // load state into F0-F14 | |
4734 for (i = 0; i < 8; i++) { | |
4735 __ ldf(FloatRegisterImpl::D, state, i*8, as_FloatRegister(i*2)); | |
4736 } | |
4737 | |
4738 __ andcc(buf, 7, G0); | |
4739 __ br(Assembler::notZero, false, Assembler::pn, L_sha512_unaligned_input); | |
4740 __ delayed()->nop(); | |
4741 | |
4742 __ BIND(L_sha512_loop); | |
4743 // load buf into F16-F46 | |
4744 for (i = 0; i < 16; i++) { | |
4745 __ ldf(FloatRegisterImpl::D, buf, i*8, as_FloatRegister(i*2 + 16)); | |
4746 } | |
4747 __ sha512(); | |
4748 if (multi_block) { | |
4749 __ add(ofs, 128, ofs); | |
4750 __ add(buf, 128, buf); | |
4751 __ cmp_and_brx_short(ofs, limit, Assembler::lessEqual, Assembler::pt, L_sha512_loop); | |
4752 __ mov(ofs, O0); // to be returned | |
4753 } | |
4754 | |
4755 // store F0-F14 into state and return | |
4756 for (i = 0; i < 7; i++) { | |
4757 __ stf(FloatRegisterImpl::D, as_FloatRegister(i*2), state, i*8); | |
4758 } | |
4759 __ retl(); | |
4760 __ delayed()->stf(FloatRegisterImpl::D, F14, state, 0x38); | |
4761 | |
4762 __ BIND(L_sha512_unaligned_input); | |
4763 __ alignaddr(buf, G0, buf); | |
4764 | |
4765 __ BIND(L_sha512_unaligned_input_loop); | |
4766 // load buf into F16-F46 | |
4767 for (i = 0; i < 17; i++) { | |
4768 __ ldf(FloatRegisterImpl::D, buf, i*8, as_FloatRegister(i*2 + 16)); | |
4769 } | |
4770 for (i = 0; i < 16; i++) { | |
4771 __ faligndata(as_FloatRegister(i*2 + 16), as_FloatRegister(i*2 + 18), as_FloatRegister(i*2 + 16)); | |
4772 } | |
4773 __ sha512(); | |
4774 if (multi_block) { | |
4775 __ add(ofs, 128, ofs); | |
4776 __ add(buf, 128, buf); | |
4777 __ cmp_and_brx_short(ofs, limit, Assembler::lessEqual, Assembler::pt, L_sha512_unaligned_input_loop); | |
4778 __ mov(ofs, O0); // to be returned | |
4779 } | |
4780 | |
4781 // store F0-F14 into state and return | |
4782 for (i = 0; i < 7; i++) { | |
4783 __ stf(FloatRegisterImpl::D, as_FloatRegister(i*2), state, i*8); | |
4784 } | |
4785 __ retl(); | |
4786 __ delayed()->stf(FloatRegisterImpl::D, F14, state, 0x38); | |
4787 | |
4788 return start; | |
4789 } | |
4790 | |
4578 void generate_initial() { | 4791 void generate_initial() { |
4579 // Generates all stubs and initializes the entry points | 4792 // Generates all stubs and initializes the entry points |
4580 | 4793 |
4581 //------------------------------------------------------------------------------------------------------------------------ | 4794 //------------------------------------------------------------------------------------------------------------------------ |
4582 // entry points that exist in all platforms | 4795 // entry points that exist in all platforms |
4644 if (UseAESIntrinsics) { | 4857 if (UseAESIntrinsics) { |
4645 StubRoutines::_aescrypt_encryptBlock = generate_aescrypt_encryptBlock(); | 4858 StubRoutines::_aescrypt_encryptBlock = generate_aescrypt_encryptBlock(); |
4646 StubRoutines::_aescrypt_decryptBlock = generate_aescrypt_decryptBlock(); | 4859 StubRoutines::_aescrypt_decryptBlock = generate_aescrypt_decryptBlock(); |
4647 StubRoutines::_cipherBlockChaining_encryptAESCrypt = generate_cipherBlockChaining_encryptAESCrypt(); | 4860 StubRoutines::_cipherBlockChaining_encryptAESCrypt = generate_cipherBlockChaining_encryptAESCrypt(); |
4648 StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptAESCrypt_Parallel(); | 4861 StubRoutines::_cipherBlockChaining_decryptAESCrypt = generate_cipherBlockChaining_decryptAESCrypt_Parallel(); |
4862 } | |
4863 | |
4864 // generate SHA1/SHA256/SHA512 intrinsics code | |
4865 if (UseSHA1Intrinsics) { | |
4866 StubRoutines::_sha1_implCompress = generate_sha1_implCompress(false, "sha1_implCompress"); | |
4867 StubRoutines::_sha1_implCompressMB = generate_sha1_implCompress(true, "sha1_implCompressMB"); | |
4868 } | |
4869 if (UseSHA256Intrinsics) { | |
4870 StubRoutines::_sha256_implCompress = generate_sha256_implCompress(false, "sha256_implCompress"); | |
4871 StubRoutines::_sha256_implCompressMB = generate_sha256_implCompress(true, "sha256_implCompressMB"); | |
4872 } | |
4873 if (UseSHA512Intrinsics) { | |
4874 StubRoutines::_sha512_implCompress = generate_sha512_implCompress(false, "sha512_implCompress"); | |
4875 StubRoutines::_sha512_implCompressMB = generate_sha512_implCompress(true, "sha512_implCompressMB"); | |
4649 } | 4876 } |
4650 } | 4877 } |
4651 | 4878 |
4652 | 4879 |
4653 public: | 4880 public: |