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6703890: Compressed Oops: add LoadNKlass node to generate narrow oops (32-bits) compare instructions Summary: Add LoadNKlass and CMoveN nodes, use CmpN and ConN nodes to generate narrow oops compare instructions. Reviewed-by: never, rasbold
author kvn
date Wed, 21 May 2008 13:46:23 -0700
parents 885ed790ecf0
children 7793bd37a336
comparison
equal deleted inserted replaced
163:885ed790ecf0 164:c436414a719e
6061 6061
6062 // Load Klass Pointer 6062 // Load Klass Pointer
6063 instruct loadKlass(rRegP dst, memory mem) 6063 instruct loadKlass(rRegP dst, memory mem)
6064 %{ 6064 %{
6065 match(Set dst (LoadKlass mem)); 6065 match(Set dst (LoadKlass mem));
6066 predicate(!n->in(MemNode::Address)->bottom_type()->is_ptr_to_narrowoop());
6067 6066
6068 ins_cost(125); // XXX 6067 ins_cost(125); // XXX
6069 format %{ "movq $dst, $mem\t# class" %} 6068 format %{ "movq $dst, $mem\t# class" %}
6070 opcode(0x8B); 6069 opcode(0x8B);
6071 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem)); 6070 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
6072 ins_pipe(ialu_reg_mem); // XXX 6071 ins_pipe(ialu_reg_mem); // XXX
6073 %} 6072 %}
6074 6073
6075 // Load Klass Pointer 6074 // Load narrow Klass Pointer
6076 instruct loadKlassComp(rRegP dst, memory mem, rFlagsReg cr) 6075 instruct loadNKlass(rRegN dst, memory mem)
6077 %{ 6076 %{
6078 match(Set dst (LoadKlass mem)); 6077 match(Set dst (LoadNKlass mem));
6079 predicate(n->in(MemNode::Address)->bottom_type()->is_ptr_to_narrowoop());
6080 effect(KILL cr);
6081 6078
6082 ins_cost(125); // XXX 6079 ins_cost(125); // XXX
6083 format %{ "movl $dst, $mem\t# compressed class\n\t" 6080 format %{ "movl $dst, $mem\t# compressed klass ptr\n\t" %}
6084 "decode_heap_oop $dst,$dst" %}
6085 ins_encode %{ 6081 ins_encode %{
6086 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); 6082 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6087 Register dst = as_Register($dst$$reg); 6083 Register dst = as_Register($dst$$reg);
6088 __ movl(dst, addr); 6084 __ movl(dst, addr);
6089 // klass is never null in the header but this is generated for all
6090 // klass loads not just the _klass field in the header.
6091 __ decode_heap_oop(dst);
6092 %} 6085 %}
6093 ins_pipe(ialu_reg_mem); // XXX 6086 ins_pipe(ialu_reg_mem); // XXX
6094 %} 6087 %}
6095 6088
6096 // Load Float 6089 // Load Float
6356 __ xorq(dst, dst); 6349 __ xorq(dst, dst);
6357 %} 6350 %}
6358 ins_pipe(ialu_reg); 6351 ins_pipe(ialu_reg);
6359 %} 6352 %}
6360 6353
6361 instruct loadConN(rRegN dst, immN src, rFlagsReg cr) %{ 6354 instruct loadConN(rRegN dst, immN src) %{
6362 match(Set dst src); 6355 match(Set dst src);
6363 effect(KILL cr);
6364 6356
6365 ins_cost(125); 6357 ins_cost(125);
6366 format %{ "movq $dst, $src\t# compressed ptr\n\t" 6358 format %{ "movl $dst, $src\t# compressed ptr" %}
6367 "encode_heap_oop_not_null $dst,$dst" %}
6368 ins_encode %{ 6359 ins_encode %{
6369 address con = (address)$src$$constant; 6360 address con = (address)$src$$constant;
6370 Register dst = $dst$$Register; 6361 Register dst = $dst$$Register;
6371 if (con == NULL) { 6362 if (con == NULL) {
6372 ShouldNotReachHere(); 6363 ShouldNotReachHere();
6373 } else { 6364 } else {
6374 __ movoop(dst, (jobject)$src$$constant); 6365 __ set_narrow_oop(dst, (jobject)$src$$constant);
6375 __ encode_heap_oop_not_null(dst);
6376 } 6366 }
6377 %} 6367 %}
6378 ins_pipe(ialu_reg_fat); // XXX 6368 ins_pipe(ialu_reg_fat); // XXX
6379 %} 6369 %}
6380 6370
6637 instruct storeN(memory mem, rRegN src) 6627 instruct storeN(memory mem, rRegN src)
6638 %{ 6628 %{
6639 match(Set mem (StoreN mem src)); 6629 match(Set mem (StoreN mem src));
6640 6630
6641 ins_cost(125); // XXX 6631 ins_cost(125); // XXX
6642 format %{ "movl $mem, $src\t# ptr" %} 6632 format %{ "movl $mem, $src\t# compressed ptr" %}
6643 ins_encode %{ 6633 ins_encode %{
6644 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); 6634 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
6645 Register src = as_Register($src$$reg); 6635 Register src = as_Register($src$$reg);
6646 __ movl(addr, src); 6636 __ movl(addr, src);
6647 %} 6637 %}
7138 ins_cost(250); // XXX 7128 ins_cost(250); // XXX
7139 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %} 7129 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7140 opcode(0x0F, 0x40); 7130 opcode(0x0F, 0x40);
7141 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src)); 7131 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
7142 ins_pipe(pipe_cmov_mem); 7132 ins_pipe(pipe_cmov_mem);
7133 %}
7134
7135 // Conditional move
7136 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7137 %{
7138 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7139
7140 ins_cost(200); // XXX
7141 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7142 opcode(0x0F, 0x40);
7143 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7144 ins_pipe(pipe_cmov_reg);
7145 %}
7146
7147 // Conditional move
7148 instruct cmovN_regU(rRegN dst, rRegN src, rFlagsRegU cr, cmpOpU cop)
7149 %{
7150 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7151
7152 ins_cost(200); // XXX
7153 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7154 opcode(0x0F, 0x40);
7155 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
7156 ins_pipe(pipe_cmov_reg);
7143 %} 7157 %}
7144 7158
7145 // Conditional move 7159 // Conditional move
7146 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop) 7160 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7147 %{ 7161 %{
11053 ins_encode(REX_mem_wide(op), 11067 ins_encode(REX_mem_wide(op),
11054 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF)); 11068 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11055 ins_pipe(ialu_cr_reg_imm); 11069 ins_pipe(ialu_cr_reg_imm);
11056 %} 11070 %}
11057 11071
11072
11073 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11074 %{
11075 match(Set cr (CmpN op1 op2));
11076
11077 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11078 ins_encode %{ __ cmpl(as_Register($op1$$reg), as_Register($op2$$reg)); %}
11079 ins_pipe(ialu_cr_reg_reg);
11080 %}
11081
11082 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11083 %{
11084 match(Set cr (CmpN src (LoadN mem)));
11085
11086 ins_cost(500); // XXX
11087 format %{ "cmpl $src, mem\t# compressed ptr" %}
11088 ins_encode %{
11089 Address adr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
11090 __ cmpl(as_Register($src$$reg), adr);
11091 %}
11092 ins_pipe(ialu_cr_reg_mem);
11093 %}
11094
11058 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{ 11095 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11059 match(Set cr (CmpN src zero)); 11096 match(Set cr (CmpN src zero));
11060 11097
11061 format %{ "testl $src, $src" %} 11098 format %{ "testl $src, $src\t# compressed ptr" %}
11062 ins_encode %{ __ testl($src$$Register, $src$$Register); %} 11099 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11063 ins_pipe(ialu_cr_reg_imm); 11100 ins_pipe(ialu_cr_reg_imm);
11101 %}
11102
11103 instruct testN_reg_mem(rFlagsReg cr, memory mem, immN0 zero)
11104 %{
11105 match(Set cr (CmpN (LoadN mem) zero));
11106
11107 ins_cost(500); // XXX
11108 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11109 ins_encode %{
11110 Address addr = build_address($mem$$base, $mem$$index, $mem$$scale, $mem$$disp);
11111 __ cmpl(addr, (int)0xFFFFFFFF);
11112 %}
11113 ins_pipe(ialu_cr_reg_mem);
11064 %} 11114 %}
11065 11115
11066 // Yanked all unsigned pointer compare operations. 11116 // Yanked all unsigned pointer compare operations.
11067 // Pointer compares are done with CmpP which is already unsigned. 11117 // Pointer compares are done with CmpP which is already unsigned.
11068 11118