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comparison src/cpu/sparc/vm/nativeInst_sparc.hpp @ 6725:da91efe96a93

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6964458: Reimplement class meta-data storage to use native memory Summary: Remove PermGen, allocate meta-data in metaspace linked to class loaders, rewrite GC walking, rewrite and rename metadata to be C++ classes Reviewed-by: jmasa, stefank, never, coleenp, kvn, brutisso, mgerdin, dholmes, jrose, twisti, roland Contributed-by: jmasa <jon.masamitsu@oracle.com>, stefank <stefan.karlsson@oracle.com>, mgerdin <mikael.gerdin@oracle.com>, never <tom.rodriguez@oracle.com>
author coleenp
date Sat, 01 Sep 2012 13:25:18 -0400
parents 1d1603768966
children f0c2369fda5a
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6724:36d1d483d5d6 6725:da91efe96a93
1 /* 1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 * 4 *
5 * This code is free software; you can redistribute it and/or modify it 5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as 6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation. 7 * published by the Free Software Foundation.
244 // combine the fields of a sethi stream (7 instructions ) and an add, jmp or ld/st 244 // combine the fields of a sethi stream (7 instructions ) and an add, jmp or ld/st
245 static intptr_t data64( address pc, int arith_insn ) { 245 static intptr_t data64( address pc, int arith_insn ) {
246 assert(is_op2(*(unsigned int *)pc, Assembler::sethi_op2), "must be sethi"); 246 assert(is_op2(*(unsigned int *)pc, Assembler::sethi_op2), "must be sethi");
247 intptr_t hi = (intptr_t)gethi( (unsigned int *)pc ); 247 intptr_t hi = (intptr_t)gethi( (unsigned int *)pc );
248 intptr_t lo = (intptr_t)get_simm13(arith_insn); 248 intptr_t lo = (intptr_t)get_simm13(arith_insn);
249 assert((unsigned)lo < (1 << 10), "offset field of set_oop must be 10 bits"); 249 assert((unsigned)lo < (1 << 10), "offset field of set_metadata must be 10 bits");
250 return hi | lo; 250 return hi | lo;
251 } 251 }
252 252
253 // Regenerate the instruction sequence that performs the 64 bit 253 // Regenerate the instruction sequence that performs the 64 bit
254 // sethi. This only does the sethi. The disp field (bottom 10 bits) 254 // sethi. This only does the sethi. The disp field (bottom 10 bits)
259 // combine the fields of a sethi/simm13 pair (simm13 = or, add, jmpl, ld/st) 259 // combine the fields of a sethi/simm13 pair (simm13 = or, add, jmpl, ld/st)
260 static int data32(int sethi_insn, int arith_insn) { 260 static int data32(int sethi_insn, int arith_insn) {
261 assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi"); 261 assert(is_op2(sethi_insn, Assembler::sethi_op2), "must be sethi");
262 int hi = Assembler::inv_hi22(sethi_insn); 262 int hi = Assembler::inv_hi22(sethi_insn);
263 int lo = get_simm13(arith_insn); 263 int lo = get_simm13(arith_insn);
264 assert((unsigned)lo < (1 << 10), "offset field of set_oop must be 10 bits"); 264 assert((unsigned)lo < (1 << 10), "offset field of set_metadata must be 10 bits");
265 return hi | lo; 265 return hi | lo;
266 } 266 }
267 267
268 static int set_data32_sethi(int sethi_insn, int imm) { 268 static int set_data32_sethi(int sethi_insn, int imm) {
269 // note that Assembler::hi22 clips the low 10 bits for us 269 // note that Assembler::hi22 clips the low 10 bits for us
506 static void replace_mt_safe(address instr_addr, address code_buffer); 506 static void replace_mt_safe(address instr_addr, address code_buffer);
507 }; 507 };
508 508
509 #endif // _LP64 509 #endif // _LP64
510 510
511 // An interface for accessing/manipulating native set_oop imm, reg instructions. 511 // An interface for accessing/manipulating native set_metadata imm, reg instructions.
512 // (used to manipulate inlined data references, etc.) 512 // (used to manipulate inlined data references, etc.)
513 // set_oop imm, reg 513 // set_metadata imm, reg
514 // == sethi %hi22(imm), reg ; add reg, %lo10(imm), reg 514 // == sethi %hi22(imm), reg ; add reg, %lo10(imm), reg
515 class NativeMovConstReg; 515 class NativeMovConstReg;
516 inline NativeMovConstReg* nativeMovConstReg_at(address address); 516 inline NativeMovConstReg* nativeMovConstReg_at(address address);
517 class NativeMovConstReg: public NativeInstruction { 517 class NativeMovConstReg: public NativeInstruction {
518 public: 518 public:
562 } 562 }
563 563
564 }; 564 };
565 565
566 566
567 // An interface for accessing/manipulating native set_oop imm, reg instructions. 567 // An interface for accessing/manipulating native set_metadata imm, reg instructions.
568 // (used to manipulate inlined data references, etc.) 568 // (used to manipulate inlined data references, etc.)
569 // set_oop imm, reg 569 // set_metadata imm, reg
570 // == sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg 570 // == sethi %hi22(imm), reg; nop; add reg, %lo10(imm), reg
571 // 571 //
572 // Note that it is identical to NativeMovConstReg with the exception of a nop between the 572 // Note that it is identical to NativeMovConstReg with the exception of a nop between the
573 // sethi and the add. The nop is required to be in the delay slot of the call instruction 573 // sethi and the add. The nop is required to be in the delay slot of the call instruction
574 // which overwrites the sethi during patching. 574 // which overwrites the sethi during patching.