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comparison mx/mx_graal.py @ 21447:f172a195a8a9

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mx gate: bootstrap with -G:+SSA_LIR.
author Josef Eisl <josef.eisl@jku.at>
date Thu, 07 May 2015 14:47:27 +0200
parents 326a1f374198
children 2fe8729dd813 3b8bbf51d320
comparison
equal deleted inserted replaced
21446:43462ed89797 21447:f172a195a8a9
1682 with VM('graal', 'product'): 1682 with VM('graal', 'product'):
1683 with Task('BootstrapWithRegisterPressure:product', tasks) as t: 1683 with Task('BootstrapWithRegisterPressure:product', tasks) as t:
1684 if t: 1684 if t:
1685 registers = 'o0,o1,o2,o3,f8,f9,d32,d34' if platform.processor() == 'sparc' else 'rbx,r11,r10,r14,xmm3,xmm11,xmm14' 1685 registers = 'o0,o1,o2,o3,f8,f9,d32,d34' if platform.processor() == 'sparc' else 'rbx,r11,r10,r14,xmm3,xmm11,xmm14'
1686 vm(['-XX:-TieredCompilation', '-G:RegisterPressure=' + registers, '-esa', '-version']) 1686 vm(['-XX:-TieredCompilation', '-G:RegisterPressure=' + registers, '-esa', '-version'])
1687
1688 with VM('graal', 'product'):
1689 with Task('BootstrapSSAWithRegisterPressure:product', tasks) as t:
1690 if t:
1691 registers = 'o0,o1,o2,o3,f8,f9,d32,d34' if platform.processor() == 'sparc' else 'rbx,r11,r10,r14,xmm3,xmm11,xmm14'
1692 vm(['-XX:-TieredCompilation', '-G:+SSA_LIR', '-G:RegisterPressure=' + registers, '-esa', '-version'])
1687 1693
1688 with VM('graal', 'product'): 1694 with VM('graal', 'product'):
1689 with Task('BootstrapWithImmutableCode:product', tasks) as t: 1695 with Task('BootstrapWithImmutableCode:product', tasks) as t:
1690 if t: vm(['-XX:-TieredCompilation', '-G:+ImmutableCode', '-G:+VerifyPhases', '-esa', '-version']) 1696 if t: vm(['-XX:-TieredCompilation', '-G:+ImmutableCode', '-G:+VerifyPhases', '-esa', '-version'])
1691 1697