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comparison src/cpu/ppc/vm/assembler_ppc.hpp @ 20508:f6bde7889409

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8059592: Recent bugfixes in ppc64 port. Reviewed-by: kvn
author goetz
date Thu, 02 Oct 2014 09:32:53 +0200
parents b384ba33c9a0
children
comparison
equal deleted inserted replaced
20507:43ce58b4717b 20508:f6bde7889409
266 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1), 266 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1),
267 CMPLI_OPCODE = (10u << OPCODE_SHIFT), 267 CMPLI_OPCODE = (10u << OPCODE_SHIFT),
268 268
269 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1), 269 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1),
270 270
271 MTLR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 8 << SPR_0_4_SHIFT), 271 // Special purpose registers
272 MFLR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 8 << SPR_0_4_SHIFT), 272 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1),
273 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1),
274
275 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT),
276 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT),
277
278 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT),
279 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT),
280
281 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT),
282 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT),
283
284 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT),
285 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT),
286
287 MTTFHAR_OPCODE = (MTSPR_OPCODE | 128 << SPR_0_4_SHIFT),
288 MFTFHAR_OPCODE = (MFSPR_OPCODE | 128 << SPR_0_4_SHIFT),
289 MTTFIAR_OPCODE = (MTSPR_OPCODE | 129 << SPR_0_4_SHIFT),
290 MFTFIAR_OPCODE = (MFSPR_OPCODE | 129 << SPR_0_4_SHIFT),
291 MTTEXASR_OPCODE = (MTSPR_OPCODE | 130 << SPR_0_4_SHIFT),
292 MFTEXASR_OPCODE = (MFSPR_OPCODE | 130 << SPR_0_4_SHIFT),
293 MTTEXASRU_OPCODE = (MTSPR_OPCODE | 131 << SPR_0_4_SHIFT),
294 MFTEXASRU_OPCODE = (MFSPR_OPCODE | 131 << SPR_0_4_SHIFT),
295
296 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 256 << SPR_0_4_SHIFT),
297 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 256 << SPR_0_4_SHIFT),
298
299 MFTB_OPCODE = (MFSPR_OPCODE | 268 << SPR_0_4_SHIFT),
273 300
274 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1), 301 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1),
275 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1), 302 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1),
276 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1), 303 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1),
277 304
289 BXX_OPCODE = (18u << OPCODE_SHIFT), 316 BXX_OPCODE = (18u << OPCODE_SHIFT),
290 BCXX_OPCODE = (16u << OPCODE_SHIFT), 317 BCXX_OPCODE = (16u << OPCODE_SHIFT),
291 318
292 // CTR-related opcodes 319 // CTR-related opcodes
293 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1), 320 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1),
294 MTCTR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1 | 9 << SPR_0_4_SHIFT),
295 MFCTR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1 | 9 << SPR_0_4_SHIFT),
296
297 321
298 LWZ_OPCODE = (32u << OPCODE_SHIFT), 322 LWZ_OPCODE = (32u << OPCODE_SHIFT),
299 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1), 323 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1),
300 LWZU_OPCODE = (33u << OPCODE_SHIFT), 324 LWZU_OPCODE = (33u << OPCODE_SHIFT),
301 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1), 325 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1),
582 // not implemented yet 606 // not implemented yet
583 607
584 // Vector Status and Control 608 // Vector Status and Control
585 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ), 609 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ),
586 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ), 610 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ),
611
612 // AES (introduced with Power 8)
613 VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u),
614 VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u),
615 VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u),
616 VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u),
617 VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u),
618
619 // SHA (introduced with Power 8)
620 VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u),
621 VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u),
622
623 // Vector Binary Polynomial Multiplication (introduced with Power 8)
624 VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u),
625 VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u),
626 VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u),
627 VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u),
628
629 // Vector Permute and Xor (introduced with Power 8)
630 VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u),
631
632 // Transactional Memory instructions (introduced with Power 8)
633 TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1),
634 TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1),
635 TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1),
636 TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1),
637 TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1),
638 TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1),
639 TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1),
640 TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1),
641 TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1),
587 642
588 // Icache and dcache related instructions 643 // Icache and dcache related instructions
589 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1), 644 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1),
590 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1), 645 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1),
591 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1), 646 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1),
1417 inline void mfctr(Register d); 1472 inline void mfctr(Register d);
1418 inline void mtcrf(int fxm, Register s); 1473 inline void mtcrf(int fxm, Register s);
1419 inline void mfcr( Register d); 1474 inline void mfcr( Register d);
1420 inline void mcrf( ConditionRegister crd, ConditionRegister cra); 1475 inline void mcrf( ConditionRegister crd, ConditionRegister cra);
1421 inline void mtcr( Register s); 1476 inline void mtcr( Register s);
1477
1478 // Special purpose registers
1479 // Exception Register
1480 inline void mtxer(Register s1);
1481 inline void mfxer(Register d);
1482 // Vector Register Save Register
1483 inline void mtvrsave(Register s1);
1484 inline void mfvrsave(Register d);
1485 // Timebase
1486 inline void mftb(Register d);
1487 // Introduced with Power 8:
1488 // Data Stream Control Register
1489 inline void mtdscr(Register s1);
1490 inline void mfdscr(Register d );
1491 // Transactional Memory Registers
1492 inline void mftfhar(Register d);
1493 inline void mftfiar(Register d);
1494 inline void mftexasr(Register d);
1495 inline void mftexasru(Register d);
1422 1496
1423 // PPC 1, section 2.4.1 Branch Instructions 1497 // PPC 1, section 2.4.1 Branch Instructions
1424 inline void b( address a, relocInfo::relocType rt = relocInfo::none); 1498 inline void b( address a, relocInfo::relocType rt = relocInfo::none);
1425 inline void b( Label& L); 1499 inline void b( Label& L);
1426 inline void bl( address a, relocInfo::relocType rt = relocInfo::none); 1500 inline void bl( address a, relocInfo::relocType rt = relocInfo::none);
1858 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b); 1932 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
1859 // Vector Floating-Point not implemented yet 1933 // Vector Floating-Point not implemented yet
1860 inline void mtvscr( VectorRegister b); 1934 inline void mtvscr( VectorRegister b);
1861 inline void mfvscr( VectorRegister d); 1935 inline void mfvscr( VectorRegister d);
1862 1936
1937 // AES (introduced with Power 8)
1938 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
1939 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
1940 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
1941 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
1942 inline void vsbox( VectorRegister d, VectorRegister a);
1943
1944 // SHA (introduced with Power 8)
1945 // Not yet implemented.
1946
1947 // Vector Binary Polynomial Multiplication (introduced with Power 8)
1948 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
1949 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
1950 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
1951 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
1952
1953 // Vector Permute and Xor (introduced with Power 8)
1954 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
1955
1956 // Transactional Memory instructions (introduced with Power 8)
1957 inline void tbegin_(); // R=0
1958 inline void tbeginrot_(); // R=1 Rollback-Only Transaction
1959 inline void tend_(); // A=0
1960 inline void tendall_(); // A=1
1961 inline void tabort_(Register a);
1962 inline void tabortwc_(int t, Register a, Register b);
1963 inline void tabortwci_(int t, Register a, int si);
1964 inline void tabortdc_(int t, Register a, Register b);
1965 inline void tabortdci_(int t, Register a, int si);
1966 inline void tsuspend_(); // tsr with L=0
1967 inline void tresume_(); // tsr with L=1
1968 inline void tcheck(int f);
1969
1863 // The following encoders use r0 as second operand. These instructions 1970 // The following encoders use r0 as second operand. These instructions
1864 // read r0 as '0'. 1971 // read r0 as '0'.
1865 inline void lwzx( Register d, Register s2); 1972 inline void lwzx( Register d, Register s2);
1866 inline void lwz( Register d, int si16); 1973 inline void lwz( Register d, int si16);
1867 inline void lwax( Register d, Register s2); 1974 inline void lwax( Register d, Register s2);