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diff src/cpu/x86/vm/x86_32.ad @ 14428:044b28168e20

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8003854: PPC64 (part 115): Introduce PostallocExpand that expands nodes after register allocation Summary: added ability in C2 to expand mach nodes to several mach nodes after register allocation Reviewed-by: kvn
author goetz
date Thu, 14 Nov 2013 19:24:59 -0800
parents 2b8e28fdf503
children 50fdb38839eb
line wrap: on
line diff
--- a/src/cpu/x86/vm/x86_32.ad	Thu Nov 07 11:47:11 2013 +0100
+++ b/src/cpu/x86/vm/x86_32.ad	Thu Nov 14 19:24:59 2013 -0800
@@ -487,6 +487,11 @@
   return 0;  // absolute addressing, no offset
 }
 
+bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
+void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
+  ShouldNotReachHere();
+}
+
 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
   // Empty encoding
 }
@@ -1389,6 +1394,9 @@
 // No CMOVF/CMOVD with SSE/SSE2
 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
 
+// Does the CPU require late expand (see block.cpp for description of late expand)?
+const bool Matcher::require_postalloc_expand = false;
+
 // Should the Matcher clone shifts on addressing modes, expecting them to
 // be subsumed into complex addressing expressions or compute them into
 // registers?  True for Intel but false for most RISCs