Mercurial > hg > graal-compiler
diff src/cpu/ppc/vm/assembler_ppc.inline.hpp @ 14445:67fa91961822
8029940: PPC64 (part 122): C2 compiler port
Reviewed-by: kvn
author | goetz |
---|---|
date | Wed, 11 Dec 2013 00:06:11 +0100 |
parents | ec28f9c041ff |
children | e5e8aa897002 |
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--- a/src/cpu/ppc/vm/assembler_ppc.inline.hpp Tue Dec 10 14:29:43 2013 +0100 +++ b/src/cpu/ppc/vm/assembler_ppc.inline.hpp Wed Dec 11 00:06:11 2013 +0100 @@ -224,8 +224,12 @@ inline void Assembler::extrdi( Register a, Register s, int n, int b){ Assembler::rldicl(a, s, b+n, 64-n); } // testbit with condition register. inline void Assembler::testbitdi(ConditionRegister cr, Register a, Register s, int ui6) { - Assembler::rldicr(a, s, 63-ui6, 0); - Assembler::cmpdi(cr, a, 0); + if (cr == CCR0) { + Assembler::rldicr_(a, s, 63-ui6, 0); + } else { + Assembler::rldicr(a, s, 63-ui6, 0); + Assembler::cmpdi(cr, a, 0); + } } // rotate instructions @@ -423,6 +427,27 @@ inline void Assembler::crandc(int d, int s1, int s2) { emit_int32(CRANDC_OPCODE | bt(d) | ba(s1) | bb(s2)); } inline void Assembler::crorc( int d, int s1, int s2) { emit_int32(CRORC_OPCODE | bt(d) | ba(s1) | bb(s2)); } +// Conditional move (>= Power7) +inline void Assembler::isel(Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b) { + if (b == noreg) { + b = d; // Can be omitted if old value should be kept in "else" case. + } + Register first = a; + Register second = b; + if (inv) { + first = b; + second = a; // exchange + } + assert(first != R0, "r0 not allowed"); + isel(d, first, second, bi0(cr, cc)); +} +inline void Assembler::isel_0(Register d, ConditionRegister cr, Condition cc, Register b) { + if (b == noreg) { + b = d; // Can be omitted if old value should be kept in "else" case. + } + isel(d, R0, b, bi0(cr, cc)); +} + // PPC 2, section 3.2.1 Instruction Cache Instructions inline void Assembler::icbi( Register s1, Register s2) { emit_int32( ICBI_OPCODE | ra0mem(s1) | rb(s2) ); } // PPC 2, section 3.2.2 Data Cache Instructions @@ -445,10 +470,7 @@ inline void Assembler::ptesync() { Assembler::sync(2); } inline void Assembler::eieio() { emit_int32( EIEIO_OPCODE); } inline void Assembler::isync() { emit_int32( ISYNC_OPCODE); } - -inline void Assembler::release() { Assembler::lwsync(); } -inline void Assembler::acquire() { Assembler::lwsync(); } -inline void Assembler::fence() { Assembler::sync(); } +inline void Assembler::elemental_membar(int e) { assert(0 < e && e < 16, "invalid encoding"); emit_int32( SYNC_OPCODE | e1215(e)); } // atomics // Use ra0mem to disallow R0 as base. @@ -767,7 +789,6 @@ inline void Assembler::lvsl( VectorRegister d, Register s2) { emit_int32( LVSL_OPCODE | vrt(d) | rb(s2)); } inline void Assembler::lvsr( VectorRegister d, Register s2) { emit_int32( LVSR_OPCODE | vrt(d) | rb(s2)); } - inline void Assembler::load_const(Register d, void* x, Register tmp) { load_const(d, (long)x, tmp); }