Mercurial > hg > graal-compiler
diff src/cpu/x86/vm/interp_masm_x86_64.cpp @ 3852:fdb992d83a87
7071653: JSR 292: call site change notification should be pushed not pulled
Reviewed-by: kvn, never, bdelsart
author | twisti |
---|---|
date | Tue, 16 Aug 2011 04:14:05 -0700 |
parents | 341a57af9b0a |
children | f08d439fab8c |
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line diff
--- a/src/cpu/x86/vm/interp_masm_x86_64.cpp Thu Aug 11 12:08:11 2011 -0700 +++ b/src/cpu/x86/vm/interp_masm_x86_64.cpp Tue Aug 16 04:14:05 2011 -0700 @@ -233,7 +233,7 @@ Register index, int bcp_offset, size_t index_size) { - assert(cache != index, "must use different registers"); + assert_different_registers(cache, index); get_cache_index_at_bcp(index, bcp_offset, index_size); movptr(cache, Address(rbp, frame::interpreter_frame_cache_offset * wordSize)); assert(sizeof(ConstantPoolCacheEntry) == 4 * wordSize, "adjust code below"); @@ -242,6 +242,22 @@ } +void InterpreterMacroAssembler::get_cache_and_index_and_bytecode_at_bcp(Register cache, + Register index, + Register bytecode, + int byte_no, + int bcp_offset, + size_t index_size) { + get_cache_and_index_at_bcp(cache, index, bcp_offset, index_size); + // We use a 32-bit load here since the layout of 64-bit words on + // little-endian machines allow us that. + movl(bytecode, Address(cache, index, Address::times_ptr, constantPoolCacheOopDesc::base_offset() + ConstantPoolCacheEntry::indices_offset())); + const int shift_count = (1 + byte_no) * BitsPerByte; + shrl(bytecode, shift_count); + andl(bytecode, 0xFF); +} + + void InterpreterMacroAssembler::get_cache_entry_pointer_at_bcp(Register cache, Register tmp, int bcp_offset,