Mercurial > hg > graal-compiler
view src/cpu/sparc/vm/icache_sparc.hpp @ 12653:1a7e7011a341
* PTX kernel argument buffer now has naturally aligned arguments as required by PTX JIT compiler.
* Change dynamic loading of CUDA driver API functions to load 32-bit or 64-bit versions of depending on the the host architecture.
* Add ability to generate PTX kernels to be launched both on 32-bit and 64-bit hosts.
* Use Unified Virtual Memory APIs to perform array argument marshalling.
* PTX array storage test runs on the device and returns correct results.
* More integer test failures on GPU fixed.
author | S.Bharadwaj Yadavalli <bharadwaj.yadavalli@oracle.com> |
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date | Fri, 01 Nov 2013 18:34:03 -0400 |
parents | f95d63e2154a |
children |
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/* * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * */ #ifndef CPU_SPARC_VM_ICACHE_SPARC_HPP #define CPU_SPARC_VM_ICACHE_SPARC_HPP // Interface for updating the instruction cache. Whenever the VM modifies // code, part of the processor instruction cache potentially has to be flushed. class ICache : public AbstractICache { public: enum { stub_size = 160, // Size of the icache flush stub in bytes line_size = 8, // flush instruction affects a dword log2_line_size = 3 // log2(line_size) }; // Use default implementation }; #endif // CPU_SPARC_VM_ICACHE_SPARC_HPP