Mercurial > hg > graal-compiler
view src/cpu/zero/vm/icache_zero.hpp @ 18712:37a5c6b8b930
Log deopt before deoptimizing the frame
author | Tom Rodriguez <tom.rodriguez@oracle.com> |
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date | Wed, 17 Dec 2014 13:39:48 -0800 |
parents | f95d63e2154a |
children |
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/* * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. * Copyright 2007, 2009 Red Hat, Inc. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * */ #ifndef CPU_ZERO_VM_ICACHE_ZERO_HPP #define CPU_ZERO_VM_ICACHE_ZERO_HPP // Interface for updating the instruction cache. Whenever the VM // modifies code, part of the processor instruction cache potentially // has to be flushed. This implementation is empty: Zero never deals // with code, and LLVM handles cache flushing for Shark. class ICache : public AbstractICache { public: static void initialize() {} static void invalidate_word(address addr) {} static void invalidate_range(address start, int nbytes) {} }; #endif // CPU_ZERO_VM_ICACHE_ZERO_HPP