view src/cpu/ppc/vm/icache_ppc.cpp @ 14418:cfd05ec74089

8024342: PPC64 (part 111): Support for C calling conventions that require 64-bit ints. Summary: Some platforms, as ppc and s390x/zArch require that 32-bit ints are passed as 64-bit values to C functions. This change adds support to adapt the signature and to issue proper casts to c2-compiled stubs. The functions are used in generate_native_wrapper(). Adapt signature used by the compiler as in PhaseIdealLoop::intrinsify_fill(). Reviewed-by: kvn
author goetz
date Wed, 18 Sep 2013 14:34:56 -0700
parents ec28f9c041ff
children 67fa91961822
line wrap: on
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/*
 * Copyright (c) 2000, 2013, Oracle and/or its affiliates. All rights reserved.
 * Copyright 2012, 2013 SAP AG. All rights reserved.
 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 *
 * This code is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 only, as
 * published by the Free Software Foundation.
 *
 * This code is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * version 2 for more details (a copy is included in the LICENSE file that
 * accompanied this code).
 *
 * You should have received a copy of the GNU General Public License version
 * 2 along with this work; if not, write to the Free Software Foundation,
 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 *
 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 * or visit www.oracle.com if you need additional information or have any
 * questions.
 *
 */

#include "precompiled.hpp"
#include "assembler_ppc.inline.hpp"
#include "runtime/icache.hpp"

// Use inline assembler to implement icache flush.
int ppc64_flush_icache(address start, int lines, int magic){
  address end = start + (unsigned int)lines*ICache::line_size;
  assert(start <= end, "flush_icache parms");

  // store modified cache lines from data cache
  for (address a=start; a<end; a+=ICache::line_size) {
    __asm__ __volatile__(
       "dcbst 0, %0  \n"
       :
       : "r" (a)
       : "memory");
  }

  // sync instruction
  __asm__ __volatile__(
     "sync \n"
     :
     :
     : "memory");

  // invalidate respective cache lines in instruction cache
  for (address a=start; a<end; a+=ICache::line_size) {
    __asm__ __volatile__(
       "icbi 0, %0   \n"
       :
       : "r" (a)
       : "memory");
  }

  // discard fetched instructions
  __asm__ __volatile__(
                 "isync \n"
                 :
                 :
                 : "memory");

  return magic;
}

void ICacheStubGenerator::generate_icache_flush(ICache::flush_icache_stub_t* flush_icache_stub) {
  StubCodeMark mark(this, "ICache", "flush_icache_stub");

  *flush_icache_stub = (ICache::flush_icache_stub_t)ppc64_flush_icache;

  // First call to flush itself
  ICache::invalidate_range((address)(*flush_icache_stub), 0);
}