# HG changeset patch # User twisti # Date 1246026370 25200 # Node ID 18a08a7e16b5063c6c126d0ab76251f4d5c1befe # Parent 14367225a853ba52c7f6df78316715cde0e77823 5057225: Remove useless I2L conversions Summary: The optimizer should be told to normalize (AndL (ConvI2L x) 0xFF) to (ConvI2L (AndI x 0xFF)), and then the existing matcher rule will work for free. Reviewed-by: kvn diff -r 14367225a853 -r 18a08a7e16b5 src/cpu/sparc/vm/sparc.ad --- a/src/cpu/sparc/vm/sparc.ad Wed Jun 24 12:00:51 2009 -0700 +++ b/src/cpu/sparc/vm/sparc.ad Fri Jun 26 07:26:10 2009 -0700 @@ -1891,17 +1891,17 @@ // The intptr_t operand types, defined by textual substitution. // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) #ifdef _LP64 -#define immX immL -#define immX13 immL13 -#define immX13m7 immL13m7 -#define iRegX iRegL -#define g1RegX g1RegL +#define immX immL +#define immX13 immL13 +#define immX13m7 immL13m7 +#define iRegX iRegL +#define g1RegX g1RegL #else -#define immX immI -#define immX13 immI13 -#define immX13m7 immI13m7 -#define iRegX iRegI -#define g1RegX g1RegI +#define immX immI +#define immX13 immI13 +#define immX13m7 immI13m7 +#define iRegX iRegI +#define g1RegX g1RegI #endif //----------ENCODING BLOCK----------------------------------------------------- @@ -3446,6 +3446,15 @@ interface(CONST_INTER); %} +// Integer Immediate: 8-bit +operand immI8() %{ + predicate(Assembler::is_simm(n->get_int(), 8)); + match(ConI); + op_cost(0); + format %{ %} + interface(CONST_INTER); +%} + // Integer Immediate: 13-bit operand immI13() %{ predicate(Assembler::is_simm13(n->get_int())); @@ -3466,6 +3475,15 @@ interface(CONST_INTER); %} +// Integer Immediate: 16-bit +operand immI16() %{ + predicate(Assembler::is_simm(n->get_int(), 16)); + match(ConI); + op_cost(0); + format %{ %} + interface(CONST_INTER); +%} + // Unsigned (positive) Integer Immediate: 13-bit operand immU13() %{ predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); @@ -5544,7 +5562,7 @@ ins_encode %{ __ ldub($mem$$Address, $dst$$Register); %} - ins_pipe(iload_mask_mem); + ins_pipe(iload_mem); %} // Load Unsigned Byte (8bit UNsigned) into a Long Register @@ -5557,7 +5575,22 @@ ins_encode %{ __ ldub($mem$$Address, $dst$$Register); %} - ins_pipe(iload_mask_mem); + ins_pipe(iload_mem); +%} + +// Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register +instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ + match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); + ins_cost(MEMORY_REF_COST + DEFAULT_COST); + + size(2*4); + format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" + "AND $dst,$mask,$dst" %} + ins_encode %{ + __ ldub($mem$$Address, $dst$$Register); + __ and3($dst$$Register, $mask$$constant, $dst$$Register); + %} + ins_pipe(iload_mem); %} // Load Short (16bit signed) @@ -5610,7 +5643,7 @@ ins_encode %{ __ lduh($mem$$Address, $dst$$Register); %} - ins_pipe(iload_mask_mem); + ins_pipe(iload_mem); %} // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) @@ -5636,7 +5669,56 @@ ins_encode %{ __ lduh($mem$$Address, $dst$$Register); %} - ins_pipe(iload_mask_mem); + ins_pipe(iload_mem); +%} + +// Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register +instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ + match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); + ins_cost(MEMORY_REF_COST); + + size(4); + format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} + ins_encode %{ + __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE + %} + ins_pipe(iload_mem); +%} + +// Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register +instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ + match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); + ins_cost(MEMORY_REF_COST + DEFAULT_COST); + + size(2*4); + format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" + "AND $dst,$mask,$dst" %} + ins_encode %{ + Register Rdst = $dst$$Register; + __ lduh($mem$$Address, Rdst); + __ and3(Rdst, $mask$$constant, Rdst); + %} + ins_pipe(iload_mem); +%} + +// Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register +instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ + match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); + effect(TEMP dst, TEMP tmp); + ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); + + size(3*4); + format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" + "SET $mask,$tmp\n\t" + "AND $dst,$tmp,$dst" %} + ins_encode %{ + Register Rdst = $dst$$Register; + Register Rtmp = $tmp$$Register; + __ lduh($mem$$Address, Rdst); + __ set($mask$$constant, Rtmp); + __ and3(Rdst, Rtmp, Rdst); + %} + ins_pipe(iload_mem); %} // Load Integer @@ -5718,6 +5800,68 @@ ins_encode %{ __ ldsw($mem$$Address, $dst$$Register); %} + ins_pipe(iload_mask_mem); +%} + +// Load Integer with mask 0xFF into a Long Register +instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ + match(Set dst (ConvI2L (AndI (LoadI mem) mask))); + ins_cost(MEMORY_REF_COST); + + size(4); + format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} + ins_encode %{ + __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE + %} + ins_pipe(iload_mem); +%} + +// Load Integer with mask 0xFFFF into a Long Register +instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ + match(Set dst (ConvI2L (AndI (LoadI mem) mask))); + ins_cost(MEMORY_REF_COST); + + size(4); + format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} + ins_encode %{ + __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE + %} + ins_pipe(iload_mem); +%} + +// Load Integer with a 13-bit mask into a Long Register +instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ + match(Set dst (ConvI2L (AndI (LoadI mem) mask))); + ins_cost(MEMORY_REF_COST + DEFAULT_COST); + + size(2*4); + format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" + "AND $dst,$mask,$dst" %} + ins_encode %{ + Register Rdst = $dst$$Register; + __ lduw($mem$$Address, Rdst); + __ and3(Rdst, $mask$$constant, Rdst); + %} + ins_pipe(iload_mem); +%} + +// Load Integer with a 32-bit mask into a Long Register +instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ + match(Set dst (ConvI2L (AndI (LoadI mem) mask))); + effect(TEMP dst, TEMP tmp); + ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); + + size(3*4); + format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" + "SET $mask,$tmp\n\t" + "AND $dst,$tmp,$dst" %} + ins_encode %{ + Register Rdst = $dst$$Register; + Register Rtmp = $tmp$$Register; + __ lduw($mem$$Address, Rdst); + __ set($mask$$constant, Rtmp); + __ and3(Rdst, Rtmp, Rdst); + %} ins_pipe(iload_mem); %} diff -r 14367225a853 -r 18a08a7e16b5 src/cpu/x86/vm/x86_32.ad --- a/src/cpu/x86/vm/x86_32.ad Wed Jun 24 12:00:51 2009 -0700 +++ b/src/cpu/x86/vm/x86_32.ad Fri Jun 26 07:26:10 2009 -0700 @@ -6885,8 +6885,9 @@ %} // Load Byte (8bit signed) into Long Register -instruct loadB2L(eRegL dst, memory mem) %{ +instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ match(Set dst (ConvI2L (LoadB mem))); + effect(KILL cr); ins_cost(375); format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" @@ -6917,19 +6918,37 @@ %} // Load Unsigned Byte (8 bit UNsigned) into Long Register -instruct loadUB2L(eRegL dst, memory mem) -%{ +instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ match(Set dst (ConvI2L (LoadUB mem))); + effect(KILL cr); ins_cost(250); format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" "XOR $dst.hi,$dst.hi" %} ins_encode %{ - __ movzbl($dst$$Register, $mem$$Address); - __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); - %} - + Register Rdst = $dst$$Register; + __ movzbl(Rdst, $mem$$Address); + __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); + %} + + ins_pipe(ialu_reg_mem); +%} + +// Load Unsigned Byte (8 bit UNsigned) with mask into Long Register +instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ + match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); + effect(KILL cr); + + format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" + "XOR $dst.hi,$dst.hi\n\t" + "AND $dst.lo,$mask" %} + ins_encode %{ + Register Rdst = $dst$$Register; + __ movzbl(Rdst, $mem$$Address); + __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); + __ andl(Rdst, $mask$$constant); + %} ins_pipe(ialu_reg_mem); %} @@ -6960,8 +6979,9 @@ %} // Load Short (16bit signed) into Long Register -instruct loadS2L(eRegL dst, memory mem) %{ +instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ match(Set dst (ConvI2L (LoadS mem))); + effect(KILL cr); ins_cost(375); format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" @@ -7004,8 +7024,9 @@ %} // Load Unsigned Short/Char (16 bit UNsigned) into Long Register -instruct loadUS2L(eRegL dst, memory mem) %{ +instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ match(Set dst (ConvI2L (LoadUS mem))); + effect(KILL cr); ins_cost(250); format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" @@ -7019,6 +7040,38 @@ ins_pipe(ialu_reg_mem); %} +// Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register +instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ + match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); + effect(KILL cr); + + format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" + "XOR $dst.hi,$dst.hi" %} + ins_encode %{ + Register Rdst = $dst$$Register; + __ movzbl(Rdst, $mem$$Address); + __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); + %} + ins_pipe(ialu_reg_mem); +%} + +// Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register +instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ + match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); + effect(KILL cr); + + format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" + "XOR $dst.hi,$dst.hi\n\t" + "AND $dst.lo,$mask" %} + ins_encode %{ + Register Rdst = $dst$$Register; + __ movzwl(Rdst, $mem$$Address); + __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); + __ andl(Rdst, $mask$$constant); + %} + ins_pipe(ialu_reg_mem); +%} + // Load Integer instruct loadI(eRegI dst, memory mem) %{ match(Set dst (LoadI mem)); @@ -7082,8 +7135,9 @@ %} // Load Integer into Long Register -instruct loadI2L(eRegL dst, memory mem) %{ +instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ match(Set dst (ConvI2L (LoadI mem))); + effect(KILL cr); ins_cost(375); format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" @@ -7099,9 +7153,57 @@ ins_pipe(ialu_reg_mem); %} +// Load Integer with mask 0xFF into Long Register +instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ + match(Set dst (ConvI2L (AndI (LoadI mem) mask))); + effect(KILL cr); + + format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" + "XOR $dst.hi,$dst.hi" %} + ins_encode %{ + Register Rdst = $dst$$Register; + __ movzbl(Rdst, $mem$$Address); + __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); + %} + ins_pipe(ialu_reg_mem); +%} + +// Load Integer with mask 0xFFFF into Long Register +instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ + match(Set dst (ConvI2L (AndI (LoadI mem) mask))); + effect(KILL cr); + + format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" + "XOR $dst.hi,$dst.hi" %} + ins_encode %{ + Register Rdst = $dst$$Register; + __ movzwl(Rdst, $mem$$Address); + __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); + %} + ins_pipe(ialu_reg_mem); +%} + +// Load Integer with 32-bit mask into Long Register +instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ + match(Set dst (ConvI2L (AndI (LoadI mem) mask))); + effect(KILL cr); + + format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t" + "XOR $dst.hi,$dst.hi\n\t" + "AND $dst.lo,$mask" %} + ins_encode %{ + Register Rdst = $dst$$Register; + __ movl(Rdst, $mem$$Address); + __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); + __ andl(Rdst, $mask$$constant); + %} + ins_pipe(ialu_reg_mem); +%} + // Load Unsigned Integer into Long Register -instruct loadUI2L(eRegL dst, memory mem) %{ +instruct loadUI2L(eRegL dst, memory mem, eFlagsReg cr) %{ match(Set dst (LoadUI2L mem)); + effect(KILL cr); ins_cost(250); format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" @@ -7695,6 +7797,17 @@ ins_pipe( ialu_mem_long_reg ); %} +// Store Long to Integer +instruct storeL2I(memory mem, eRegL src) %{ + match(Set mem (StoreI mem (ConvL2I src))); + + format %{ "MOV $mem,$src.lo\t# long -> int" %} + ins_encode %{ + __ movl($mem$$Address, $src$$Register); + %} + ins_pipe(ialu_mem_reg); +%} + // Volatile Store Long. Must be atomic, so move it into // the FP TOS and then do a 64-bit FIST. Has to probe the // target address before the store (for null-ptr checks) diff -r 14367225a853 -r 18a08a7e16b5 src/cpu/x86/vm/x86_64.ad --- a/src/cpu/x86/vm/x86_64.ad Wed Jun 24 12:00:51 2009 -0700 +++ b/src/cpu/x86/vm/x86_64.ad Fri Jun 26 07:26:10 2009 -0700 @@ -6444,6 +6444,21 @@ ins_pipe(ialu_reg_mem); %} +// Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register +instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{ + match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); + effect(KILL cr); + + format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t" + "andl $dst, $mask" %} + ins_encode %{ + Register Rdst = $dst$$Register; + __ movzbq(Rdst, $mem$$Address); + __ andl(Rdst, $mask$$constant); + %} + ins_pipe(ialu_reg_mem); +%} + // Load Short (16 bit signed) instruct loadS(rRegI dst, memory mem) %{ @@ -6528,6 +6543,32 @@ ins_pipe(ialu_reg_mem); %} +// Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register +instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ + match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); + + format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %} + ins_encode %{ + __ movzbq($dst$$Register, $mem$$Address); + %} + ins_pipe(ialu_reg_mem); +%} + +// Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register +instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{ + match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); + effect(KILL cr); + + format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t" + "andl $dst, $mask" %} + ins_encode %{ + Register Rdst = $dst$$Register; + __ movzwq(Rdst, $mem$$Address); + __ andl(Rdst, $mask$$constant); + %} + ins_pipe(ialu_reg_mem); +%} + // Load Integer instruct loadI(rRegI dst, memory mem) %{ @@ -6606,6 +6647,43 @@ ins_pipe(ialu_reg_mem); %} +// Load Integer with mask 0xFF into Long Register +instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{ + match(Set dst (ConvI2L (AndI (LoadI mem) mask))); + + format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %} + ins_encode %{ + __ movzbq($dst$$Register, $mem$$Address); + %} + ins_pipe(ialu_reg_mem); +%} + +// Load Integer with mask 0xFFFF into Long Register +instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{ + match(Set dst (ConvI2L (AndI (LoadI mem) mask))); + + format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %} + ins_encode %{ + __ movzwq($dst$$Register, $mem$$Address); + %} + ins_pipe(ialu_reg_mem); +%} + +// Load Integer with a 32-bit mask into Long Register +instruct loadI2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{ + match(Set dst (ConvI2L (AndI (LoadI mem) mask))); + effect(KILL cr); + + format %{ "movl $dst, $mem\t# int & 32-bit mask -> long\n\t" + "andl $dst, $mask" %} + ins_encode %{ + Register Rdst = $dst$$Register; + __ movl(Rdst, $mem$$Address); + __ andl(Rdst, $mask$$constant); + %} + ins_pipe(ialu_reg_mem); +%} + // Load Unsigned Integer into Long Register instruct loadUI2L(rRegL dst, memory mem) %{ @@ -11673,8 +11751,9 @@ ins_cost(125); format %{ "movslq $dst, $src\t# i2l" %} - opcode(0x63); // needs REX.W - ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src)); + ins_encode %{ + __ movslq($dst$$Register, $src$$Register); + %} ins_pipe(ialu_reg_reg); %} diff -r 14367225a853 -r 18a08a7e16b5 src/share/vm/opto/mulnode.cpp --- a/src/share/vm/opto/mulnode.cpp Wed Jun 24 12:00:51 2009 -0700 +++ b/src/share/vm/opto/mulnode.cpp Fri Jun 26 07:26:10 2009 -0700 @@ -430,31 +430,28 @@ // x & x => x if (phase->eqv(in(1), in(2))) return in(1); - Node *load = in(1); - const TypeInt *t2 = phase->type( in(2) )->isa_int(); - if( t2 && t2->is_con() ) { + Node* in1 = in(1); + uint op = in1->Opcode(); + const TypeInt* t2 = phase->type(in(2))->isa_int(); + if (t2 && t2->is_con()) { int con = t2->get_con(); // Masking off high bits which are always zero is useless. const TypeInt* t1 = phase->type( in(1) )->isa_int(); if (t1 != NULL && t1->_lo >= 0) { - jint t1_support = ((jint)1 << (1 + log2_intptr(t1->_hi))) - 1; + jint t1_support = right_n_bits(1 + log2_intptr(t1->_hi)); if ((t1_support & con) == t1_support) - return load; + return in1; } - uint lop = load->Opcode(); - if( lop == Op_LoadUS && - con == 0x0000FFFF ) // Already zero-extended - return load; // Masking off the high bits of a unsigned-shift-right is not // needed either. - if( lop == Op_URShiftI ) { - const TypeInt *t12 = phase->type( load->in(2) )->isa_int(); - if( t12 && t12->is_con() ) { // Shift is by a constant + if (op == Op_URShiftI) { + const TypeInt* t12 = phase->type(in1->in(2))->isa_int(); + if (t12 && t12->is_con()) { // Shift is by a constant int shift = t12->get_con(); shift &= BitsPerJavaInteger - 1; // semantics of Java shifts int mask = max_juint >> shift; - if( (mask&con) == mask ) // If AND is useless, skip it - return load; + if ((mask & con) == mask) // If AND is useless, skip it + return in1; } } } @@ -476,26 +473,17 @@ return new (phase->C, 3) AndINode(load,phase->intcon(mask&0xFFFF)); // Masking bits off of a Short? Loading a Character does some masking - if( lop == Op_LoadS && - (mask & 0xFFFF0000) == 0 ) { + if (lop == Op_LoadS && (mask & 0xFFFF0000) == 0 ) { Node *ldus = new (phase->C, 3) LoadUSNode(load->in(MemNode::Control), - load->in(MemNode::Memory), - load->in(MemNode::Address), - load->adr_type()); + load->in(MemNode::Memory), + load->in(MemNode::Address), + load->adr_type()); ldus = phase->transform(ldus); - return new (phase->C, 3) AndINode(ldus, phase->intcon(mask&0xFFFF)); + return new (phase->C, 3) AndINode(ldus, phase->intcon(mask & 0xFFFF)); } - // Masking sign bits off of a Byte? Do an unsigned byte load. - if (lop == Op_LoadB && mask == 0x000000FF) { - return new (phase->C, 3) LoadUBNode(load->in(MemNode::Control), - load->in(MemNode::Memory), - load->in(MemNode::Address), - load->adr_type()); - } - - // Masking sign bits off of a Byte plus additional lower bits? Do - // an unsigned byte load plus an and. + // Masking sign bits off of a Byte? Do an unsigned byte load plus + // an and. if (lop == Op_LoadB && (mask & 0xFFFFFF00) == 0) { Node* ldub = new (phase->C, 3) LoadUBNode(load->in(MemNode::Control), load->in(MemNode::Memory), @@ -605,8 +593,13 @@ Node* in1 = in(1); uint op = in1->Opcode(); - // Masking sign bits off of an integer? Do an unsigned integer to long load. - if (op == Op_ConvI2L && in1->in(1)->Opcode() == Op_LoadI && mask == 0x00000000FFFFFFFFL) { + // Masking sign bits off of an integer? Do an unsigned integer to + // long load. + // NOTE: This check must be *before* we try to convert the AndLNode + // to an AndINode and commute it with ConvI2LNode because + // 0xFFFFFFFFL masks the whole integer and we get a sign extension, + // which is wrong. + if (op == Op_ConvI2L && in1->in(1)->Opcode() == Op_LoadI && mask == CONST64(0x00000000FFFFFFFF)) { Node* load = in1->in(1); return new (phase->C, 3) LoadUI2LNode(load->in(MemNode::Control), load->in(MemNode::Memory), @@ -614,9 +607,22 @@ load->adr_type()); } + // Are we masking a long that was converted from an int with a mask + // that fits in 32-bits? Commute them and use an AndINode. + if (op == Op_ConvI2L && (mask & CONST64(0xFFFFFFFF00000000)) == 0) { + // If we are doing an UI2L conversion (i.e. the mask is + // 0x00000000FFFFFFFF) we cannot convert the AndL to an AndI + // because the AndI would be optimized away later in Identity. + if (mask != CONST64(0x00000000FFFFFFFF)) { + Node* andi = new (phase->C, 3) AndINode(in1->in(1), phase->intcon(mask)); + andi = phase->transform(andi); + return new (phase->C, 2) ConvI2LNode(andi); + } + } + // Masking off sign bits? Dont make them! if (op == Op_RShiftL) { - const TypeInt *t12 = phase->type(in1->in(2))->isa_int(); + const TypeInt* t12 = phase->type(in1->in(2))->isa_int(); if( t12 && t12->is_con() ) { // Shift is by a constant int shift = t12->get_con(); shift &= BitsPerJavaLong - 1; // semantics of Java shifts @@ -626,7 +632,7 @@ if( (sign_bits_mask & mask) == 0 ) { // Use zero-fill shift instead Node *zshift = phase->transform(new (phase->C, 3) URShiftLNode(in1->in(1), in1->in(2))); - return new (phase->C, 3) AndLNode( zshift, in(2) ); + return new (phase->C, 3) AndLNode(zshift, in(2)); } } } diff -r 14367225a853 -r 18a08a7e16b5 test/compiler/5057225/Test5057225.java --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/test/compiler/5057225/Test5057225.java Fri Jun 26 07:26:10 2009 -0700 @@ -0,0 +1,140 @@ +/* + * Copyright 2009 Sun Microsystems, Inc. All Rights Reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, + * CA 95054 USA or visit www.sun.com if you need additional information or + * have any questions. + */ + +/** + * @test + * @bug 5057225 + * @summary Remove useless I2L conversions + * + * @run main/othervm -Xcomp -XX:CompileOnly=Test5057225.doload Test5057225 + */ + +import java.net.URLClassLoader; + +public class Test5057225 { + static byte[] ba = new byte[] { -1 }; + static short[] sa = new short[] { -1 }; + static int[] ia = new int[] { -1 }; + + static final long[] BYTE_MASKS = { + 0x0FL, + 0x7FL, // 7-bit + 0xFFL, + }; + + static final long[] SHORT_MASKS = { + 0x000FL, + 0x007FL, // 7-bit + 0x00FFL, + 0x0FFFL, + 0x3FFFL, // 14-bit + 0x7FFFL, // 15-bit + 0xFFFFL, + }; + + static final long[] INT_MASKS = { + 0x0000000FL, + 0x0000007FL, // 7-bit + 0x000000FFL, + 0x00000FFFL, + 0x00003FFFL, // 14-bit + 0x00007FFFL, // 15-bit + 0x0000FFFFL, + 0x00FFFFFFL, + 0x7FFFFFFFL, // 31-bit + 0xFFFFFFFFL, + }; + + public static void main(String[] args) throws Exception { + for (int i = 0; i < BYTE_MASKS.length; i++) { + System.setProperty("value", "" + BYTE_MASKS[i]); + loadAndRunClass("Test5057225$loadUB2L"); + } + + for (int i = 0; i < SHORT_MASKS.length; i++) { + System.setProperty("value", "" + SHORT_MASKS[i]); + loadAndRunClass("Test5057225$loadUS2L"); + } + + for (int i = 0; i < INT_MASKS.length; i++) { + System.setProperty("value", "" + INT_MASKS[i]); + loadAndRunClass("Test5057225$loadUI2L"); + } + } + + static void check(long result, long expected) { + if (result != expected) + throw new InternalError(result + " != " + expected); + } + + static void loadAndRunClass(String classname) throws Exception { + Class cl = Class.forName(classname); + URLClassLoader apploader = (URLClassLoader) cl.getClassLoader(); + ClassLoader loader = new URLClassLoader(apploader.getURLs(), apploader.getParent()); + Class c = loader.loadClass(classname); + Runnable r = (Runnable) c.newInstance(); + r.run(); + } + + public static class loadUB2L implements Runnable { + static final long MASK; + static { + long value = 0; + try { + value = Long.decode(System.getProperty("value")); + } catch (Throwable e) {} + MASK = value; + } + + public void run() { check(doload(ba), MASK); } + static long doload(byte[] ba) { return ba[0] & MASK; } + } + + public static class loadUS2L implements Runnable { + static final long MASK; + static { + long value = 0; + try { + value = Long.decode(System.getProperty("value")); + } catch (Throwable e) {} + MASK = value; + } + + public void run() { check(doload(sa), MASK); } + static long doload(short[] sa) { return sa[0] & MASK; } + } + + public static class loadUI2L implements Runnable { + static final long MASK; + static { + long value = 0; + try { + value = Long.decode(System.getProperty("value")); + } catch (Throwable e) {} + MASK = value; + } + + public void run() { check(doload(ia), MASK); } + static long doload(int[] ia) { return ia[0] & MASK; } + } +}