# HG changeset patch
# User Josef Eisl <josef.eisl@jku.at>
# Date 1439457641 -7200
# Node ID 417ae972af507f89676896ab00b46909e8461183
# Parent  cc1f997e618587a93385f8988a054a9f99a35900
TraceRA: handle ShadowedRegisterValue correctly.

diff -r cc1f997e6185 -r 417ae972af50 graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceLinearScanAssignLocationsPhase.java
--- a/graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceLinearScanAssignLocationsPhase.java	Thu Aug 13 11:18:25 2015 +0200
+++ b/graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceLinearScanAssignLocationsPhase.java	Thu Aug 13 11:20:41 2015 +0200
@@ -47,7 +47,7 @@
 
     @Override
     protected Value colorLirOperand(LIRInstruction op, Variable operand, OperandMode mode) {
-        if (!isBlockEndWithEdgeToUnallocatedTrace(op)) {
+        if (!isBlockEndWithEdgeToUnallocatedTrace(op, mode)) {
             return super.colorLirOperand(op, operand, mode);
         }
 
@@ -71,8 +71,8 @@
         return interval.location();
     }
 
-    private boolean isBlockEndWithEdgeToUnallocatedTrace(LIRInstruction op) {
-        if (!(op instanceof BlockEndOp)) {
+    private boolean isBlockEndWithEdgeToUnallocatedTrace(LIRInstruction op, OperandMode mode) {
+        if (!(op instanceof BlockEndOp) || !OperandMode.ALIVE.equals(mode)) {
             return false;
         }
         AbstractBlockBase<?> block = allocator.blockForId(op.id());
diff -r cc1f997e6185 -r 417ae972af50 graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceRegisterAllocationPhase.java
--- a/graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceRegisterAllocationPhase.java	Thu Aug 13 11:18:25 2015 +0200
+++ b/graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceRegisterAllocationPhase.java	Thu Aug 13 11:20:41 2015 +0200
@@ -28,6 +28,7 @@
 import java.util.*;
 
 import jdk.internal.jvmci.code.*;
+import jdk.internal.jvmci.meta.*;
 import jdk.internal.jvmci.options.*;
 
 import com.oracle.graal.compiler.common.alloc.*;
@@ -36,6 +37,7 @@
 import com.oracle.graal.debug.*;
 import com.oracle.graal.debug.Debug.Scope;
 import com.oracle.graal.lir.*;
+import com.oracle.graal.lir.LIRInstruction.*;
 import com.oracle.graal.lir.StandardOp.MoveOp;
 import com.oracle.graal.lir.gen.*;
 import com.oracle.graal.lir.gen.LIRGeneratorTool.SpillMoveFactory;
@@ -93,20 +95,48 @@
 
         new TraceGlobalMoveResolutionPhase(resultTraces).apply(target, lirGenRes, codeEmittingOrder, linearScanOrder, new AllocationContext(spillMoveFactory, registerAllocationConfig));
 
-        if (replaceStackToStackMoves(lir, spillMoveFactory)) {
-            Debug.dump(lir, "After fixing stack to stack moves");
-        }
-        /*
-         * Incoming Values are needed for the RegisterVerifier, otherwise SIGMAs/PHIs where the Out
-         * and In value matches (ie. there is no resolution move) are falsely detected as errors.
-         */
-        for (AbstractBlockBase<?> toBlock : lir.getControlFlowGraph().getBlocks()) {
-            if (toBlock.getPredecessorCount() != 0) {
-                SSIUtil.removeIncoming(lir, toBlock);
-            } else {
-                assert lir.getControlFlowGraph().getStartBlock().equals(toBlock);
+        try (Scope s = Debug.scope("TraceRegisterAllocationFixup")) {
+            if (replaceStackToStackMoves(lir, spillMoveFactory)) {
+                Debug.dump(lir, "After fixing stack to stack moves");
             }
-            SSIUtil.removeOutgoing(lir, toBlock);
+            InstructionValueProcedure removeShadowedValuesProc = new InstructionValueProcedure() {
+                public Value doValue(LIRInstruction op, Value value, OperandMode mode, EnumSet<OperandFlag> flags) {
+                    try (Indent i = Debug.logAndIndent("Fixup operand %s", value)) {
+                        if (TraceUtil.isShadowedRegisterValue(value)) {
+                            Debug.log("Replace ShadowedRegister value %s in instruction %s with register %s", value, op, TraceUtil.asShadowedRegisterValue(value).getRegister());
+                            return TraceUtil.asShadowedRegisterValue(value).getRegister();
+                        }
+                    }
+                    return value;
+                }
+            };
+            /*
+             * Incoming Values are needed for the RegisterVerifier, otherwise SIGMAs/PHIs where the
+             * Out and In value matches (ie. there is no resolution move) are falsely detected as
+             * errors.
+             */
+            for (AbstractBlockBase<?> block : lir.getControlFlowGraph().getBlocks()) {
+                try (Indent i = Debug.logAndIndent("Fixup Block %s", block)) {
+                    if (block.getPredecessorCount() != 0) {
+                        SSIUtil.removeIncoming(lir, block);
+                    } else {
+                        assert lir.getControlFlowGraph().getStartBlock().equals(block);
+                    }
+                    SSIUtil.removeOutgoing(lir, block);
+                    /*
+                     * BlockEndOps with real inputs (such as switch or if) might have a
+                     * ShadowedRegisterValue assigned because we can not tell if a values belongs to
+                     * the outgoing array or not. Hear we replace all remaining
+                     * ShadowedRegisterValues with the actual register. Because we only introduced
+                     * ShadowedRegisterValues for OperandMode.ALIVE there is no need to look at
+                     * other values.
+                     */
+                    LIRInstruction blockEndOp = SSIUtil.outgoingInst(lir, block);
+                    try (Indent i1 = Debug.logAndIndent("Fixup Instruction %s", blockEndOp)) {
+                        blockEndOp.forEachAlive(removeShadowedValuesProc);
+                    }
+                }
+            }
         }
     }
 
diff -r cc1f997e6185 -r 417ae972af50 graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceTrivialAllocator.java
--- a/graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceTrivialAllocator.java	Thu Aug 13 11:18:25 2015 +0200
+++ b/graal/com.oracle.graal.lir/src/com/oracle/graal/lir/alloc/trace/TraceTrivialAllocator.java	Thu Aug 13 11:20:41 2015 +0200
@@ -34,6 +34,7 @@
 import com.oracle.graal.compiler.common.alloc.TraceBuilder.TraceBuilderResult;
 import com.oracle.graal.compiler.common.cfg.*;
 import com.oracle.graal.lir.*;
+import com.oracle.graal.lir.LIRInstruction.OperandFlag;
 import com.oracle.graal.lir.StandardOp.BlockEndOp;
 import com.oracle.graal.lir.StandardOp.LabelOp;
 import com.oracle.graal.lir.gen.*;
@@ -72,7 +73,12 @@
 
         ValueProcedure outputConsumer = (value, mode, flags) -> {
             if (isVariable(value)) {
-                return variableMap.get(asVariable(value));
+                Value incomingValue = variableMap.get(asVariable(value));
+                if (TraceUtil.isShadowedRegisterValue(incomingValue) && !flags.contains(OperandFlag.COMPOSITE)) {
+                    /* Can not deal with a composite -> use the register instead. */
+                    return TraceUtil.asShadowedRegisterValue(incomingValue).getRegister();
+                }
+                return incomingValue;
             }
             return value;
         };