# HG changeset patch
# User mikael
# Date 1398834310 25200
# Node ID 7f77d17d0f13e83c051c36196e9f55c67b8b2521
# Parent  0fb5b60ab4a2ca161c1b943a639fe918301a459b
8042059: Various fixes to linux/sparc
Reviewed-by: twisti, kvn

diff -r 0fb5b60ab4a2 -r 7f77d17d0f13 agent/src/os/linux/libproc.h
--- a/agent/src/os/linux/libproc.h	Tue Apr 29 22:04:09 2014 -0700
+++ b/agent/src/os/linux/libproc.h	Tue Apr 29 22:05:10 2014 -0700
@@ -34,19 +34,7 @@
 #include "libproc_md.h"
 #endif
 
-#if defined(sparc) || defined(sparcv9)
-/*
-  If _LP64 is defined ptrace.h should be taken from /usr/include/asm-sparc64
-  otherwise it should be from /usr/include/asm-sparc
-  These two files define pt_regs structure differently
-*/
-#ifdef _LP64
-#include "asm-sparc64/ptrace.h"
-#else
-#include "asm-sparc/ptrace.h"
-#endif
-
-#endif //sparc or sparcv9
+#include <linux/ptrace.h>
 
 /************************************************************************************
 
diff -r 0fb5b60ab4a2 -r 7f77d17d0f13 src/cpu/sparc/vm/frame_sparc.hpp
--- a/src/cpu/sparc/vm/frame_sparc.hpp	Tue Apr 29 22:04:09 2014 -0700
+++ b/src/cpu/sparc/vm/frame_sparc.hpp	Tue Apr 29 22:05:10 2014 -0700
@@ -259,8 +259,8 @@
 
   // next two fns read and write Lmonitors value,
  private:
-  BasicObjectLock* interpreter_frame_monitors()           const  { return *interpreter_frame_monitors_addr(); }
-  void interpreter_frame_set_monitors(BasicObjectLock* monitors) {        *interpreter_frame_monitors_addr() = monitors; }
+  BasicObjectLock* interpreter_frame_monitors() const;
+  void interpreter_frame_set_monitors(BasicObjectLock* monitors);
 #else
  public:
   inline interpreterState get_interpreterState() const {
diff -r 0fb5b60ab4a2 -r 7f77d17d0f13 src/cpu/sparc/vm/frame_sparc.inline.hpp
--- a/src/cpu/sparc/vm/frame_sparc.inline.hpp	Tue Apr 29 22:04:09 2014 -0700
+++ b/src/cpu/sparc/vm/frame_sparc.inline.hpp	Tue Apr 29 22:05:10 2014 -0700
@@ -226,6 +226,13 @@
   return (Method**)sp_addr_at( Lmethod->sp_offset_in_saved_window());
 }
 
+inline BasicObjectLock* frame::interpreter_frame_monitors() const {
+  return *interpreter_frame_monitors_addr();
+}
+
+inline void frame::interpreter_frame_set_monitors(BasicObjectLock* monitors) {
+  *interpreter_frame_monitors_addr() = monitors;
+}
 
 // Constant pool cache
 
diff -r 0fb5b60ab4a2 -r 7f77d17d0f13 src/os_cpu/linux_sparc/vm/atomic_linux_sparc.inline.hpp
--- a/src/os_cpu/linux_sparc/vm/atomic_linux_sparc.inline.hpp	Tue Apr 29 22:04:09 2014 -0700
+++ b/src/os_cpu/linux_sparc/vm/atomic_linux_sparc.inline.hpp	Tue Apr 29 22:05:10 2014 -0700
@@ -78,12 +78,12 @@
   __asm__ volatile(
     "1: \n\t"
     " ldx    [%2], %%o2\n\t"
-    " add    %0, %%o2, %%o3\n\t"
+    " add    %1, %%o2, %%o3\n\t"
     " casx   [%2], %%o2, %%o3\n\t"
     " cmp    %%o2, %%o3\n\t"
     " bne    %%xcc, 1b\n\t"
     "  nop\n\t"
-    " add    %0, %%o2, %0\n\t"
+    " add    %1, %%o2, %0\n\t"
     : "=r" (rv)
     : "r" (add_value), "r" (dest)
     : "memory", "o2", "o3");
diff -r 0fb5b60ab4a2 -r 7f77d17d0f13 src/os_cpu/linux_sparc/vm/os_linux_sparc.cpp
--- a/src/os_cpu/linux_sparc/vm/os_linux_sparc.cpp	Tue Apr 29 22:04:09 2014 -0700
+++ b/src/os_cpu/linux_sparc/vm/os_linux_sparc.cpp	Tue Apr 29 22:05:10 2014 -0700
@@ -302,29 +302,30 @@
   if (context == NULL) return;
 
   ucontext_t *uc = (ucontext_t*)context;
+  sigcontext* sc = (sigcontext*)context;
   intptr_t *sp = (intptr_t *)os::Linux::ucontext_get_sp(uc);
 
   st->print_cr("Register to memory mapping:");
   st->cr();
 
   // this is only for the "general purpose" registers
-  st->print("G1="); print_location(st, SIG_REGS(sc).u_regs[CON__G1]);
-  st->print("G2="); print_location(st, SIG_REGS(sc).u_regs[CON__G2]);
-  st->print("G3="); print_location(st, SIG_REGS(sc).u_regs[CON__G3]);
-  st->print("G4="); print_location(st, SIG_REGS(sc).u_regs[CON__G4]);
-  st->print("G5="); print_location(st, SIG_REGS(sc).u_regs[CON__G5]);
-  st->print("G6="); print_location(st, SIG_REGS(sc).u_regs[CON__G6]);
-  st->print("G7="); print_location(st, SIG_REGS(sc).u_regs[CON__G7]);
+  st->print("G1="); print_location(st, SIG_REGS(sc).u_regs[CON_G1]);
+  st->print("G2="); print_location(st, SIG_REGS(sc).u_regs[CON_G2]);
+  st->print("G3="); print_location(st, SIG_REGS(sc).u_regs[CON_G3]);
+  st->print("G4="); print_location(st, SIG_REGS(sc).u_regs[CON_G4]);
+  st->print("G5="); print_location(st, SIG_REGS(sc).u_regs[CON_G5]);
+  st->print("G6="); print_location(st, SIG_REGS(sc).u_regs[CON_G6]);
+  st->print("G7="); print_location(st, SIG_REGS(sc).u_regs[CON_G7]);
   st->cr();
 
-  st->print("O0="); print_location(st, SIG_REGS(sc).u_regs[CON__O0]);
-  st->print("O1="); print_location(st, SIG_REGS(sc).u_regs[CON__O1]);
-  st->print("O2="); print_location(st, SIG_REGS(sc).u_regs[CON__O2]);
-  st->print("O3="); print_location(st, SIG_REGS(sc).u_regs[CON__O3]);
-  st->print("O4="); print_location(st, SIG_REGS(sc).u_regs[CON__O4]);
-  st->print("O5="); print_location(st, SIG_REGS(sc).u_regs[CON__O5]);
-  st->print("O6="); print_location(st, SIG_REGS(sc).u_regs[CON__O6]);
-  st->print("O7="); print_location(st, SIG_REGS(sc).u_regs[CON__O7]);
+  st->print("O0="); print_location(st, SIG_REGS(sc).u_regs[CON_O0]);
+  st->print("O1="); print_location(st, SIG_REGS(sc).u_regs[CON_O1]);
+  st->print("O2="); print_location(st, SIG_REGS(sc).u_regs[CON_O2]);
+  st->print("O3="); print_location(st, SIG_REGS(sc).u_regs[CON_O3]);
+  st->print("O4="); print_location(st, SIG_REGS(sc).u_regs[CON_O4]);
+  st->print("O5="); print_location(st, SIG_REGS(sc).u_regs[CON_O5]);
+  st->print("O6="); print_location(st, SIG_REGS(sc).u_regs[CON_O6]);
+  st->print("O7="); print_location(st, SIG_REGS(sc).u_regs[CON_O7]);
   st->cr();
 
   st->print("L0="); print_location(st, sp[L0->sp_offset_in_saved_window()]);
@@ -516,7 +517,7 @@
   if (nativeInstruction_at(*pc)->is_ic_miss_trap()) {
 #ifdef ASSERT
 #ifdef TIERED
-    CodeBlob* cb = CodeCache::find_blob_unsafe(pc);
+    CodeBlob* cb = CodeCache::find_blob_unsafe(*pc);
     assert(cb->is_compiled_by_c2(), "Wrong compiler");
 #endif // TIERED
 #endif // ASSERT